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DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

DS250DF810 25Gbps 多速率 8 通道重定时器

1 特性

2 应用

1

•

具有集成信号调节功能的八通道多速率重定时器

•

背板/中板长度延长

所有通道均可独立锁定在 20.2752 至 25.8Gbps 的

范围内（包括 10.3125Gbps、12.5Gbps 等子速

率）

针对前端口光学模块的抖动消除

IEEE802.3bj 100GbE、Infiniband EDR 和 OIF-

CEI-25G-LR/MR/SR/VSR 电气接口

•

超低延迟：25.78125Gbps 数据速率下的典型延迟

< 500ps

•

SFP28、QSFP28、CFP2/CFP4、CDFP

单电源，无需低抖动参考时钟，集成交流耦合电容

器以降低电路板布线复杂程度并节省物料清单

(BOM) 成本

3 说明

DS250DF810 是一款具有集成信号调节功能的八通道

多速率重定时器。该器件用于扩展有损且存在串扰的远

距离高速串行链路的延伸长度并提升稳定性，同时实现

不高于 10^-15的比特误码率 (BER)。

•

集成 2×2 交叉点

自适应性连续时间线性均衡器 (CTLE)

自适应判决反馈均衡器 (DFE)

DS250DF810 各通道的串行数据速率均可独立锁定在

20.6Gbps 至 25.8Gbps 的连续范围内或者支持的任意

子速率（速率的一半和四分之一），包括

带有 3 抽头有限脉冲响应 (FIR) 滤波器的低抖动发

射器

•

组合式均衡，在 12.9GHz 频率下支持 35dB 以上的

通道损耗

10.3125Gbps 和 12.5Gbps 等关键数据速率，从而允

许 DS280BR810 进行独立通道前向纠错 (FEC)。

可调节发送幅值：205mVppd 至 1225mVppd（典

型值）

器件信息⁽¹⁾

片上眼图张开度监视器 (EOM)，PRBS 模式校验器

/发生器小型 8mm × 13mm BGA 封装，可轻松实现

直通布线

器件型号

封装

封装尺寸（标称值）

135 引脚 FCBGA

(135)

DS250DF810

8.0mm x 13.0mm

•

独特引脚可实现在封装下方布置高速信号布线

支持兼容引脚的中继器

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

4 简化原理图

RX0P

TX0P

TX0N

RX0N

.

2.5V or

3.3V

RX7P

RX7N

TX7P

TX7N

To other open-

drain interrupt

pins

INT_N

VDD

SMBus

Slave mode

1 kΩ

SDA⁽¹⁾

SDC⁽¹⁾

EN_SMB

TEST

To system SMBus

Address straps

(pull-up, pull-

down, or float)

ADDR0

ADDR1

25 MHz

To next device‘s

CAL_CLK_IN

READ_EN_N

CAL_CLK_OUT

ALL_DONE_N

SMBus Slave

mode

Float for SMBus Slave

mode, or connect to next

device‘s READ_EN_N for

SMBus Master mode

2.5V

VDD

GND

1ꢀF

(2x)

0.1ꢀF

(4x)

(1) SMBus signals need to be pulled up elsewhere in the system.

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNLS513

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

www.ti.com.cn

1

2

3

4

5

6

7

8

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

简化原理图............................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 7

8.1 Absolute Maximum Ratings ...................................... 7

8.2 ESD Ratings.............................................................. 7

8.3 Recommended Operating Conditions....................... 7

8.4 Thermal Information.................................................. 8

8.5 Electrical Characteristics........................................... 8

9

Detailed Description ............................................ 16

9.1 Overview ................................................................. 16

9.2 Functional Block Diagram ....................................... 17

9.3 Feature Description................................................. 18

9.4 Device Functional Modes........................................ 29

9.5 Programming........................................................... 30

9.6 Register Maps......................................................... 32

10 Application and Implementation........................ 77

10.1 Application Information.......................................... 77

10.2 Typical Application ............................................... 77

11 Power Supply Recommendations ..................... 82

12 Layout................................................................... 82

12.1 Layout Guidelines ................................................. 82

12.2 Layout Example .................................................... 82

13 器件和文档支持 ..................................................... 84

13.1 器件支持 ............................................................... 84

13.2 文档支持................................................................ 84

13.3 接收文档更新通知 ................................................. 84

13.4 支持资源................................................................ 84

13.5 商标....................................................................... 84

13.6 静电放电警告......................................................... 84

13.7 Glossary................................................................ 84

14 机械、封装和可订购信息....................................... 84

8.6 Timing Requirements, Retimer Jitter

Specifications........................................................... 12

8.7 Timing Requirements, Retimer Specifications........ 13

8.8 Timing Requirements, Recommended Calibration

Clock Specifications................................................. 13

8.9 Recommended SMBus Switching Characteristics

(Slave Mode)............................................................ 13

8.10 Recommended SMBus Switching Characteristics

(Master Mode).......................................................... 14

8.11 Typical Characteristics ......................................... 15

5 修订历史记录

Changes from Revision B (June 2019) to Revision C

Page

•

首次公开发布 .......................................................................................................................................................................... 1

2

DS250DF810

www.ti.com.cn

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

6 说明（续）

印刷电路板 (PCB) 上集成了物理交流耦合电容（TX 与 RX），无需使用外部电容。DS250DF810 具备一个单电

源，能够最大限度地减少外部组件的数量。这些特性可降低 PCB 布线的复杂程度并节省 BOM 成本。

DS250DF230 的高级均衡特性包括：一个低抖动 3 抽头发送有限冲激响应 (FIR) 滤波器、一个自适应连续时间线

性均衡器 (CTLE) 以及一个自适应判决反馈均衡器 (DFE)。支持针对具有多个连接器且存在串扰的有损互连和背板

进行扩展。集成的时钟和数据恢复 (CDR) 功能可重置抖动预算并对高速串行数据进行重定时，非常适用于前端口

光学模块应用。DS250DF810 对每个通道对采用 2x2 交叉点，可为主机同时提供通道交叉和扇出选项。

DS250DF810 可通过 SMBus 或外部 EEPROM 进行配置。单个 EEPROM 最多可由 16 个器件共享。非破坏性片

上眼图监视器和 PRBS 发生器/校验器为系统内诊断提供支持。

3

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

www.ti.com.cn

7 Pin Configuration and Functions

135-pin fcBGA, 0.8mm BGA pin pitch

Top View

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Legend

Control/

status

J

H

G

F

GND

TX1N

GND

TX2N

GND

TX3N

GND

TX4N

GND

VDD

GND

TX5N

GND

TX6N

GND

J

H

G

F

TX0N

TX0P

GND

TX1P

GND

SDC

TX2P

GND

VDD

GND

TX3P

GND

VDD

GND

VDD

GND

TX4P

GND

VDD

TX5P

GND

TX6P

GND

TEST0

GND

TX7N

TX7P

GND

High-Speed

Ground

READ_

EN_N

GND

GND TEST4 INT_N

EN_SM

Power

CAL_C

LK_IN

TI Test pins

/ Reserved

E

D

C

B

A

LK_OU TEST1 ADDR1 SDA

T

VDD

TEST5

E

D

C

B

A

B

ALL_D

GND

RX0P

RX0N

GND ADDR0 TEST7 GND

GND

RX3P

GND

RX4P

GND TEST6

GND

RX7P

RX7N

ONE_N

GND

RX1P

RX2P

RX5P

RX6P

GND

15

GND

14

RX1N

13

GND

12

RX2N

11

GND

10

RX3N

9

GND

8

RX4N

7

GND

6

RX5N

5

GND

4

RX6N

3

GND

2

GND

1

Pin Functions

INTERNAL

TYPE

PULL-UP/

PULL-DOWN

DESCRIPTION

NAME

NO.

HIGH SPEED DIFFERENTIAL I/Os

RX0P

RX0N

C15

B15

Input

None

Inverting and non-inverting differential inputs to the equalizer. An

on-chip 100-Ω termination resistor connects RXP to RXN. These

inputs are AC coupled on-chip with physical 220nF capacitors.

RX1P

RX1N

B13

A13

Inverting and non-inverting differential inputs to the equalizer. An

on-chip 100-Ω termination resistor connects RXP to RXN. These

inputs are AC coupled on-chip with physical 220nF capacitors.

RX2P

RX2N

B11

A11

Inverting and non-inverting differential inputs to the equalizer. An

on-chip 100-Ω termination resistor connects RXP to RXN. These

inputs are AC coupled on-chip with physical 220nF capacitors.

RX3P

RX3N

B9

A9

Inverting and non-inverting differential inputs to the equalizer. An

on-chip 100-Ω termination resistor connects RXP to RXN. These

inputs are AC coupled on-chip with physical 220nF capacitors.

RX4P

RX4N

B7

A7

Inverting and non-inverting differential inputs to the equalizer. An

on-chip 100-Ω termination resistor connects RXP to RXN. These

inputs are AC coupled on-chip with physical 220nF capacitors.

RX5P

RX5N

B5

A5

Inverting and non-inverting differential inputs to the equalizer. An

on-chip 100-Ω termination resistor connects RXP to RXN. These

inputs are AC coupled on-chip with physical 220nF capacitors.

RX6P

RX6N

B3

A3

Inverting and non-inverting differential inputs to the equalizer. An

on-chip 100-Ω termination resistor connects RXP to RXN. These

inputs are AC coupled on-chip with physical 220nF capacitors.

RX7P

RX7N

C1

B1

Inverting and non-inverting differential inputs to the equalizer. An

on-chip 100-Ω termination resistor connects RXP to RXN. These

inputs are AC coupled on-chip with physical 220nF capacitors.

TX0P

TX0N

G15

H15

Output

None

Inverting and non-inverting 50Ω driver outputs. These outputs are

AC coupled on-chip with physical 220nF capacitors.

4

DS250DF810

www.ti.com.cn

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Pin Functions (continued)

INTERNAL

PULL-UP/

PULL-DOWN

TYPE

DESCRIPTION

NAME

NO.

TX1P

TX1N

TX2P

TX2N

TX3P

TX3N

TX4P

TX4N

TX5P

TX5N

TX6P

TX6N

TX7P

TX7N

H13

Output

None

Inverting and non-inverting 50Ω driver outputs. These outputs are

AC coupled on-chip with physical 220nF capacitors.

J13

H11

J11

H9

J9

Inverting and non-inverting 50Ω driver outputs. These outputs are

AC coupled on-chip with physical 220nF capacitors.

Inverting and non-inverting 50Ω driver outputs. These outputs are

AC coupled on-chip with physical 220nF capacitors.

H7

J7

Inverting and non-inverting 50Ω driver outputs. These outputs are

AC coupled on-chip with physical 220nF capacitors.

H5

J5

Inverting and non-inverting 50Ω driver outputs. These outputs are

AC coupled on-chip with physical 220nF capacitors.

H3

J3

Inverting and non-inverting 50Ω driver outputs. These outputs are

AC coupled on-chip with physical 220nF capacitors.

G1

H1

Inverting and non-inverting 50Ω driver outputs. These outputs are

AC coupled on-chip with physical 220nF capacitors.

CALIBRATION CLOCK PINS

25 MHz (±100 PPM) 2.5 V single-ended clock from external

oscillator. No stringent phase noise or jitter requirements on this

clock. Used to calibrate VCO frequency range. This clock is not

used to recover data.

Input, 2.5V

CMOS

CAL_CLK_IN

E1

None

Output, 2.5V

CMOS

2.5 V buffered replica of calibration clock input (pin E1) for

connecting multiple devices in a daisy-chained fashion.

CAL_CLK_OUT E15

SYSTEM MANAGEMENT BUS (SMBUS) PINS

ADDR0

D13

Input, 4-level

4-level strap pins used to set the SMBus address of the device.

The pin state is read on power-up. The multi-level nature of these

pins allows for 16 unique device addresses. The four strap options

include:

0: 1 kΩ to GND

R: 10 kΩ to GND

F: Float

ADDR1

E13

Input, 4-level

None

1: 1 kΩ to VDD

Four-level 2.5 V input used to select between SMBus master mode

(float) and SMBus slave mode (high). The four defined levels are:

0: 1 kΩ to GND - RESERVED

R: 10 kΩ to GND - RESERVED, TI test mode

F: Float - SMBus Master Mode

EN_SMB

E3

Input, 4-level

1: 1 kΩ to VDD - SMBus Slave Mode

I/O, 3.3V

LVCMOS, Open

Drain

SMBus data input / open drain output. External 2 kΩ to 5 kΩ pull-

up resistor is required as per SMBus interface standard. This pin is

3.3 V LVCMOS tolerant.

SDA

SDC

E12

F12

None

I/O, 3.3V

LVCMOS, Open

Drain

SMBus clock input / open drain clock output. External 2 kΩ to 5 kΩ

pull-up resistor is required as per SMBus interface standard. This

pin is 3.3 V LVCMOS tolerant.

SMBUS MASTER MODE PINS

SMBus Master Mode (EN_SMB=Float): When asserted low,

initiates the SMBus master mode EEPROM read function. Once

EEPROM read is complete (indicated by assertion of

ALL_DONE_N low), this pin can be held low for normal device

operation. This pin is 3.3 V tolerant.

SMBus Slave Mode (EN_SMB=1): When asserted low, this causes

the device to be held in reset (I2C state machine reset and register

reset). This pin should be pulled high or left floating for normal

operation in SMBus Slave Mode. This pin is 3.3 V tolerant.

Input, 3.3V

LVCMOS

READ_EN_N

F13

weak pull-up

5

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

www.ti.com.cn

Pin Functions (continued)

INTERNAL

PULL-UP/

PULL-DOWN

TYPE

DESCRIPTION

NAME

NO.

Indicates the completion of a valid EEPROM register load operation

when in SMBus Master Mode (EN_SMB=Float):

High = External EEPROM load failed or incomplete

Low = External EEPROM load successful and complete

When in SMBus slave mode (EN_SMB=1), this output will be high-

z until READ_EN_N is driven low, at which point ALL_DONE_N will

be driven low.

Output,

LVCMOS

ALL_DONE_N

D3

None

MISCELLANEOUS PINS

Open-drain 3.3 V tolerant active-low interrupt output. It pulls low

when an interrupt occurs. The events which trigger an interrupt are

programmable through SMBus registers. This pin can be

connected in a wired-OR fashion with other device's interrupt pin. A

single pull-up resistor in the 2 kΩ to 5 kΩ range is adequate for the

entire INT_N net.

Output,

LVCMOS,

Open-Drain

INT_N

F3

None

TEST0

TEST1

E2

Input, LVCMOS

weak pull-up

Reserved TI test pin. During normal (non-test-mode) operation,

these pins are configured as inputs and therefore are not affected

by the presence of a signal. These pins may be left floating, tied to

GND, or connected to a 2.5V (max) output.

E14

Reserved TI test pin. During normal (non-test-mode) operation, this

pin is configured as an input and therefore is not affected by the

presence of a signal. This pin should be tied to GND or left floating

to support both the Repeater and Retimer device.

TEST4

F4

Input, LVCMOS

None

TEST5

TEST6

TEST7

POWER

E4

Input, LVCMOS

None

Reserved TI test pin. During normal (non-test-mode) operation, this

pin is configured as an input and therefore is not affected by the

presence of a signal. This pin may be left floating, tied to GND, or

connected to a 2.5V (max) output.

D4

D12

Power supply, VDD = 2.5 V ±5%. TI recommends connecting at

least six de-coupling capacitors between the Retimer’s VDD plane

and GND as close to the Retimer as possible. For example, four

0.1 μF capacitors and two 1 μF capacitors directly beneath the

device or as close to the VDD pins as possible.

D6, D8, D10,

E5, E6, E7, E8,

E9, E10, F6,

F8, F10

VDD

Power

None

The VDD pins on this device should be connected through a low-

resistance path to the board VDD plane.

A1, A2, A4, A6,

A8, A10, A12,

A14, A15, B2,

B4, B6, B8,

B10, B12, B14,

C2, C3, C4, C5,

C6, C7, C8, C9,

C10, C11, C12,

C13, C14, D1,

D2, D5, D7, D9,

D11, D14, D15,

E11, F1, F2,

Ground reference. The GND pins on this device should be

connected through a low-resistance path to the board GND plane.

GND

Power

None

F5, F7, F9, F11,

F14, F15, G2,

G3, G4, G5,

G6, G7, G8,

G9, G10, G11,

G12, G13, G14,

H2, H4, H6, H8,

H10, H12, H14,

J1, J2, J4, J6,

J8, J10, J12,

J14, J15

6

DS250DF810

www.ti.com.cn

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

-0.5

MAX

2.75

4.0

UNIT

V

VDD_ABSMAX

VIO_2.5V,ABSMAX

VIO_3.3V,ABSMAX

VIN_ABSMAX

VOUT_ABSMAX

TJ_ABSMAX

Supply voltage (VDD)

2.5 V I/O voltage (LVCMOS, CMOS and Analog)

V

Open Drain Voltage (SDA, SDC, INT_N) and LVCMOS Input Voltage (READ_EN_N)

Signal input voltage (RXnP, RXnN)

V

2.75

150

V

Signal output voltage (TXnP, TXnN)

Junction temperature

V

ºC

Tstg

Storage temperature

-40

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2

kV

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1

kV

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2 kV may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1 kV may actually have higher performance.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX UNIT

2.625

VDD

Supply voltage, VDD to GND. DC plus AC power should not exceed these limits.

Supply noise, DC to < 50 Hz, sinusoidal⁽¹⁾

Supply noise, 50 Hz to 10 MHz, sinusoidal⁽¹⁾

Supply noise, >10 MHz, sinusoidal⁽¹⁾

2.375

V

NVDD

T_rampVDD

T_J

250 mVpp

20 mVpp

10 mVpp

μs

VDD supply ramp time, from 0V to 2.375V

Operating junction temperature

150

-40

110

85⁽²⁾

2.625

3.6

ºC

V

T_A

Operating ambient temperature

-40

VIO_2.5V

VIO_{3.3V,INT_N}

VIO_3.3V

2.5 V I/O voltage (LVCMOS, CMOS and Analog)

Open Drain LVCMOS I/O voltage (INT_N)

Open Drain LVCMOS I/O voltage (SDA, SDC)

2.375

V

2.375

3.6

V

(1) Steps must be taken to ensure the combined AC plus DC supply noise meets the specified VDD supply voltage limits.

(2) Steps must be taken to ensure the operating junction temperature range is met.

7

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

www.ti.com.cn

8.4 Thermal Information

CONDITIONS/ ASSUMPTIONS⁽²⁾

4-layer JEDEC 10-layer 8in x

THERMAL METRIC⁽¹⁾

UNIT

20-layer 8in x

6in Board

30-layer 8in x

6in Board

Board

6in Board

Junction-to-ambient thermal

resistance

R_θJA

26.4

9.3

8.5

-

8.2

-

Junction-to-case (top) thermal

resistance

R_θJC(top)

1.6

9.3

0.1

9.3

-

Junction-to-board thermal

resistance

R_θJB

-

°C/W

Junction-to-top characterization

parameter

Ψ_JT

0.1

5

0.1

4.9

0.1

4.6

Junction-to-board characterization

parameter

Ψ_JB

(1) For more information about traditional and new thermal metrics, see the IC Package-Thermal Metrics application report, SPRA953.

(2) No heat sink or airflow was assumed for these estimations. Depending on the application, a heat sink, faster airflow, and/or reduced

ambient temperature (<85 C) may be required in order to meet the maximum junction temperature specification per the Recommended

Operating Conditions section.

8.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Input data rate

TEST CONDITIONS

Full-rate

MIN

20.2752

10.1376

5.0688

TYP

MAX

25.8

12.9

6.45

UNIT

Gbps

Rbaud

Half-rate

Quarter-rate

Single device reading its

configuration from an EEPROM.

Common channel configuration. This

time scales with the number of

devices reading from the same

EEPROM.

t_EEPROM

t_POR

EEPROM configuration load time

Power-on reset assertion time

15⁽¹⁾

40⁽¹⁾

50

ms

Single device reading its

configuration from an EEPROM.

Unique channel configuration. This

time scales with the number of

devices reading from the same

EEPROM.

Internal power-on reset (PoR)

stretch between stable power supply

and de-assertion of internal PoR.

The SMBus address is latched on

the completion of the PoR stretch,

and SMBus accesses are permitted.

(1) From low assertion of READ_EN_N to low assertion of ALL_DONE_N. Does not include Power-On Reset time.

8

DS250DF810

www.ti.com.cn

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

POWER SUPPLY

TEST CONDITIONS

MIN

TYP

241

233

MAX

UNIT

mW

With CTLE, full DFE, Tx FIR,

Driver, and Crosspoint enabled. Idle

power consumption not included.

305

With CTLE, full DFE, Tx FIR, and

Driver enabled; Crosspoint disabled.

Idle power consumption not

included.

mW

With CTLE, partial DFE (taps 1-2

only), Tx FIR, and Driver enabled;

Crosspoint and DFE taps 3-5

disabled. Idle power consumption

not included.

220

mW

With CTLE, Tx FIR, Driver, and

Crosspoint enabled; DFE disabled.

Idle power consumption not

included.

211

365

290

430

mW

Power consumption per active

channel

W_channel

Assuming CDR acquiring lock with

CTLE, full DFE, Tx FIR, Driver, and

Crosspoint enabled. Idle power

consumption not included.

Assuming CDR acquiring lock with

CTLE, Tx FIR, Driver, and

Crosspoint enabled; DFE disabled.

Idle power consumption not

included.

318

393

mW

PRBS checker power consumption

only⁽²⁾

220

230

302

315

mW

PRBS generator power power

consumption only⁽²⁾

W_{static_total}

Total idle power consumption

Idle/static mode, power supplied, no

high-speed data present at inputs,

all channels automatically powered

down.

658

1050

1330

mW

With CTLE, full DFE, Tx FIR, Driver,

and Crosspoint enabled.

1036

1010

mA

With CTLE, full DFE, Tx FIR, and

Driver enabled; Crosspoint disabled.

Active mode total device supply

current consumption

With CTLE, partial DFE (taps 1-2

only), Tx FIR, and Driver enabled;

Crosspoint and DFE taps 3-5

disabled.

I_total

970

940

263

mA

With CTLE, Tx FIR, Driver, and

Crosspoint enabled. DFE disabled.

1278

400

Idle/static mode. Power supplied, no

Idle mode total device supply current high-speed data present at inputs,

I_{static_total}

consumption

all channels automatically powered

down.

LVCMOS DC SPECIFICATIONS

2.5 V LVCMOS pins

1.75

VDD

3.6

V

V_IH

V_IL

Input high level voltage

Input low level voltage

3.3 V LVCMOS pin (READ_EN_N)

2.5 V LVCMOS pins

GND

0.7

3.3 V LVCMOS pin (READ_EN_N)

0.8

(2) To ensure optimal performance, it is recommended to not enable more than two PRBS blocks (checker and/or generator) per channel

quad.

9

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_TH

High level (1) input voltage

4-level pins ADDR0, ADDR1, and

EN_SMB

0.95 *

VDD

V

Float level input voltage

10K to GND input voltage

Low level (0) input voltage

4-level pins ADDR0, ADDR1, and

EN_SMB

0.67 *

VDD

V

4-level pins ADDR0, ADDR1, and

EN_SMB

0.33 *

VDD

4-level pins ADDR0, ADDR1, and

EN_SMB

0.1

V_OH

V_OL

I_IH

High level output voltage

Low level output voltage

Input high leakage current

IOH = 4mA

2

V

IOL = -4mA

0.4

70

65

Vinput = VDD, Open drain pins

Vinput = VDD and CAL_CLK_IN pin

μA

I_IH

Vinput = VDD, ADDR[1:0] and

EN_SMB pins

I_IH

Input high leakage current

120

75

μA

I_IH

I_IL

Input high leakage current

Input low leakage current

Vinput = VDD, READ_EN_N

Vinput = 0V, Open drain pins

Vinput = 0V, CAL_CLK_IN pins

μA

-15

-45

Vinput = 0V, ADDR[1:0],

READ_EN_N, and EN_SMB pins

I_IL

Input low leakage current

-230

μA

RECEIVER INPUTS (RXnP, RXnN)

V_IDMax

Maximum input differential voltage

For normal operation

1225

<-16

<-12

mVppd

dB

RL_SDD11

Differential input return loss, SDD11 Between 50 MHz and 3.69 GHz

Differential input return loss, SDD11 Between 3.69 GHz and 12.9 GHz

dB

Differential to common-mode input

Between 50 MHz and 12.9 GHz

return loss, SDC11

RL_SDC11

RL_SCD11

RL_SCC11

<-23

<-24

<-10

dB

Differential to common-mode input

Between 50 MHz and 12.9 GHz

return loss, SCD11

Common-mode input return loss,

Between 150 MHz and 10 GHz

SCC11

Common-mode input return loss,

Between 10 GHz and 12.9 GHz

SCC11

Minimum input peak-to-peak

amplitude level at device pins

required to assert signal detect.

25.78125Gbps with PRBS7 pattern

AC signal detect assert (ON)

threshold level

V_SDAT

196

147

mVppd

and 20dB loss channel

Maximum input peak-to-peak

amplitude level at device pins which

causes signal detect to de-assert.

25.78125Gbps with PRBS7 pattern

AC signal detect de-assert (OFF)

threshold level

V_SDDT

and 20dB loss channel

TRANSMITTER OUTPUTS (TXnP, TXnN)

Measured with c(0)=7 setting

(Reg_0x3D[6:0]=0x07,

Reg_0x3E[6:0]=0x40,

REG_0x3F[6:0]=0x40). Differential

VOD

Output differential voltage amplitude measurement using an 8T pattern

(eight 1s followed by eight 0s) at

25.78125 Gbps with TXPn and

525

mVppd

TXNn terminated by 50 Ohms to

GND.

10

DS250DF810

www.ti.com.cn

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Measured with c(0)=31 setting

(Reg_0x3D[6:0]=0x1F,

Reg_0x3E[6:0]=0x40,

REG_0x3F[6:0]=0x40). Differential

VOD

Output differential voltage amplitude measurement using an 8T pattern

(eight 1s followed by eight 0s) at

25.78125 Gbps with TXPn and

1225

mVppd

TXNn terminated by 50 Ohms to

GND.

Differential output amplitude with TX

disabled

VOD_idle

VOD_res

< 11

< 50

mVppd

Difference in VOD between two

adjacent c(0) settings. Applies to

VOD in the 525mVppd to

Output VOD resolution

1225mVppd range [c(0)>4].

With respect to signal ground.

Measured with PRBS9 data pattern.

Common-mode AC output noise

V_cm-TX-AC

6.5

17

mV, RMS

Measured with a 33GHz (-3dB) low-

pass filter.

20%-to-80% rise time and 80%-to-

20% fall time on a clock-like {11111

00000} data pattern at 25.78125

t_r, t_f

Output transition time

Gbps. Measured for ~800 mVppd

output amplitude and no

ps

equalization: Reg_0x3D=+13,

Reg_0x3E=0, REG_0x3F=0

Differential output return loss,

SDD22

RL_SDD22

RL_SCD22

RL_SDC22

RL_SCC22

Between 50 MHz and 5 GHz

Between 5 GHz and 12.9 GHz

Between 50 MHz and 12.9 GHz

Between 50 MHz and 10 GHz

Between 10 GHz and 12.9 GHz

<-12

<-9

dB

Differential output return loss,

SDD22

Common-mode to differential output

return loss, SCD22

<-22

<-9

Differential-to-common-mode output

return loss, SDC22

Common-mode output return loss,

SCC22

Common-mode output return loss,

SCC22

<-9

SMBus ELECTRICAL CHARACTERISTICS (SLAVE MODE)

V_IH

V_IL

Input high level voltage

Input low level voltage

Input pin capacitance

Low level output voltage

SDA and SDC

1.75

3.6

0.8

V

GND

C_IN

V_OL

15

pF

V

SDA or SDC, IOL = 1.25 mA

0.4

15

SDA or SDC, VINPUT = VIN, VDD,

GND

I_IN

Input current

-15

μA

T_R

T_F

SDA rise time, read operation

SDA fall time, read operation

Pull-up resistor = 1 kΩ, Cb = 50pF

150

4.5

ns

11

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

www.ti.com.cn

8.6 Timing Requirements, Retimer Jitter Specifications

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Measured at 25.78125 Gbps to a

probability level of 1E-12 with

PRBS11 data pattern an evaluation

board traces de-embedded.

UIpp @

1E-12

J_TJ

Output Total jitter (TJ)

0.17

Measured at 25.78125 Gbps to a

probability level of 1E-12 with

PRBS11 data pattern an evaluation

board traces de-embedded

J_RJ

Output Random Jitter (RJ)

Output Duty Cycle Distortion (DCD)

Jitter peaking

6

4

mUI RMS

mUIpp

dB

Measured at 25.78125 Gbps to a

probability level of 1E-12 with

PRBS11 data pattern an evaluation

board traces de-embedded

J_DCD

J_PEAK

Measured at 10.3125 Gbps with

PRBS7 data pattern. Peaking

frequency in the range of 1 to 6

MHz.

0.8

0.4

Measured at 25.78125 Gbps with

PRBS7 data pattern. Peaking

frequency in the range of 1 to 17

MHz.

Jitter peaking

dB

Data rate of 10.3125Gbps with

PRBS7 pattern

BWPLL

PLL bandwidth

5.3

5.5

MHz

Data rate of 25.78125Gbps with

PRBS7 pattern

Measured at 25.78125 Gbps with SJ

frequency = 190 KHz, 30dB input

channel loss, PRBS31 data pattern,

800 mVppd launch amplitude, and

0.078 UIpp total uncorrelated output

jitter in addition to the applied SJ.

BER < 1E-12.

J_TOL

Input jitter tolerance

9

1

UIpp

Measured at 25.78125 Gbps with SJ

frequency = 940 KHz, 30dB input

channel loss, PRBS31 data pattern,

800 mVppd launch amplitude, and

0.078 UIpp total uncorrelated output

jitter in addition to the applied SJ.

BER < 1E-12.

Measured at 25.78125 Gbps with SJ

frequency > 15MHz, 30dB input

channel loss, PRBS31 data pattern,

800 mVppd launch amplitude, and

0.078 UIpp total uncorrelated output

jitter in addition to the applied SJ.

BER < 1E-12.

0.3

12

DS250DF810

www.ti.com.cn

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

8.7 Timing Requirements, Retimer Specifications

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input-to-output latency (propagation No crosspoint; CDR enabled and

3.5UI +

125ps

t_D

ps

delay) through a channel

Input-to-output latency (propagation Crosspoint enabled; CDR enabled

delay) through a channel and locked.

Input-to-output latency (propagation No crosspoint; CDR in raw mode.

locked.

3.5UI +

145ps

ps

< 145

delay) through a channel

25.78125 Gbps data rate.

Latency difference between

channels at full-rate. 25.78125 Gbps

data rate

t_SK

Channel-to-channel interpair skew

< 30

ps

Measured at 25.78125 Gbps, Adapt

Mode = 1 (Reg_0x31[6:5]=0x1),

EOM timer = 0x5

t_lock

CDR lock acquisition time

< 100

ms

(Reg_0x2A[7:4]=0x5).

Measured at 10.3125 Gbps, Adapt

Mode = 1 (Reg_0x31[6:5]=0x1),

EOM timer = 0x5

t_lock

ms

(Reg_0x2A[7:4]=0x5).

8.8 Timing Requirements, Recommended Calibration Clock Specifications

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MHz

PPM

CLK_f

Calibration clock frequency

Calibration clock PPM tolerance

25

CLK_PPM

-100

40%

100

Recommended/tolerable input duty

cycle

CLK_IDC

50%

60%

Intrinsic duty cycle distortion of chip

calibration clock output at the

CAL_CLK_OUT pin, assuming 50%

duty cycle on CAL_CLK_IN pin.

Intrinsic calibration clock duty cycle

distortion

CLK_ODC

45%

55%

Assumes worst-case 60%/40% input

duty cycle on the first device.

CAL_CLK_OUT from first devuce

connects to CAL_CLK_IN of second

device, and so on until the last

device.

Number of devices which can be

cascaded from CAL_CLK_OUT to

CAL_CLK_IN

CLKnum

20

N/A

8.9 Recommended SMBus Switching Characteristics (Slave Mode)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

SDC clock frequency

Data hold time

TEST CONDITIONS

MIN

TYP

100

0.75

100

MAX

UNIT

kHz

ns

f_SDC

10

400

t_HD-DAT

t_SU-DAT

Data setup time

ns

13

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

www.ti.com.cn

8.10 Recommended SMBus Switching Characteristics (Master Mode)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

SDC clock frequency

SDC low period

TEST CONDITIONS

MIN

260

TYP

303

1.90

1.40

0.6

MAX

UNIT

kHz

μs

f_SDC

346

2.21

1.63

T_LOW

1.66

1.22

T_HIGH

T_HD-STA

T_SU-STA

T_HD-DAT

T_SD-DAT

T_SU-STO

T_BUF

SDC high period

μs

Hold time start operation

Setup time start operation

Data hold time

μs

0.6

μs

0.9

μs

Data setup time

0.1

μs

Stop condition setup time

Bus free time between Stop-Start

SDC rise time

0.6

μs

1.3

μs

T_R

Pull-up resistor = 1 kΩ

Pull-up resistor = 1 kΩ

300

ns

T_F

SDC fall time

ns

14

DS250DF810

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ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

8.11 Typical Characteristics

1.6

1.4

1.2

1

c(0)=7

c(0)=16

c(0)=31

1.4

c(0)=31

1.2

1

0.8

0.6

0.4

0.8

0.6

0.4

2.325

2.395

2.465

2.535

2.605

2.675

-40

-15

10

35

60

85

VDD Supply Voltage (V)

Ambient Temperature (°C)

C001

C002

图 1. Typical VOD versus Supply Voltage

图 2. Typical VOD versus Temperature

0.25

0.2

0.15

0.1

0.05

0

0.25

0.2

0.15

0.1

0.05

0

TJ, VDD = 2.35 V

TJ, VDD = 2.65 V

DJ, VDD = 2.35 V

DJ, VDD = 2.65 V

TJ, VDD = 2.35 V

TJ, VDD = 2.65 V

DJ, VDD = 2.35 V

DJ, VDD = 2.65 V

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (°C)

C001

图 3. Typical VOD versus FIR Main-Cursor

图 4. Typical Output Jitter versus Temperature at

25.78125Gbps

45

40

35

30

25

20

15

10

5

3

2.8

2.6

2.4

2.2

2

VDD = 2.35V

VDD = 2.5V

VDD = 2.65V

VDD = 2.35V

VDD = 2.5V

VDD = 2.65V

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

0.1

1

10

100

0.5

1

2

4

8

16

32

64

Frequency (MHz)

C003

C004

图 5. Typical Sinusoidal Input Jitter Tolerance for 30dB

channel at 25.78125Gbps for 0.1MHz to 100MHz with Input

Random Jitter = 0.078UIpp, T = 25C

图 6. Typical Input Jitter Tolerance for 30dB channel at

25.78125Gbps for 0.5MHz to 100MHz with Input Random

Jitter = 0.078UIpp, T = 25C

15

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

www.ti.com.cn

9 Detailed Description

9.1 Overview

The DS250DF810 is an eight-channel multi-rate retimer with integrated signal conditioning. Each of the eight

channels operates independently. Each channel includes a continuous-time linear equalizer (CTLE) and a

Decision Feedback Equalizer (DFE), which together compensate for the presence of a dispersive transmission

channel between the source transmitter and the DS250DF810 receiver. The CTLE and DFE are self-adaptive.

Each channel includes an independent voltage-controlled oscillator (VCO) and phase-locked loop (PLL) which

produce a clean clock that is frequency-locked to the clock embedded in the input data stream. The high-

frequency jitter on the incoming data is attenuated by the PLL, producing a clean clock with substantially-reduced

jitter. This clean clock is used to re-time the incoming data, removing high-frequency jitter from the data stream

and reproducing the data on the output with significantly-reduced jitter.

Each channel of the DS250DF810 features an output driver with adjustable differential output voltage and output

equalization in the form of a three-tap finite impulse response (FIR) filter. The output FIR compensates for

dispersion in the transmission channel at the output of the DS250DF810.

All transmit and receive channels on the DS250DF810 are AC-coupled with physical AC-coupling capacitors (220

nF +/- 20%) on the package substrate. This ensures common mode voltage compatibility with all link partners

and eliminates the need for AC coupling capacitors on the system PCB, thereby saving cost and greatly reducing

PCB routing complexity.

Between each group of two adjacent channels (e.g. between channels 0 and 1, 2 and 3, 4 and 5, and 6 and 7) is

a full 2x2 cross-point switch. This allows multiplexing and de-multiplexing/fanout applications for fail-over

redundancy, as well as cross-over applications to aid PCB routing.

Each channel also includes diagnostic features such as a Pseudo Random Bit Sequence (PRBS) pattern

generator and checker, as well as a non-destructive eye opening monitor (EOM). The EOM can be used to plot

the post-equalized eye at the input to the decision slicer or simply to read the horizontal eye opening (HEO) and

vertical eye opening (VEO).

The DS250DF810 is configurable through a single SMBus port. The DS250DF810 can also act as an SMBus

master to configure itself from an EEPROM. Up to sixteen DS250DF810 devices can share a single SMBus.

The sections which follow describe the functionality of various circuits and features within the DS250DF810. For

more information about how to program or operate these features, consult the DS250DF810 Programming

Guide.

16

DS250DF810

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ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

9.2 Functional Block Diagram

One of Eight Channels

To adjacent

channel

DFE

Term

Raw

RXnP

RXnN

TXnP

Retimed

PRBS

Sampler

TX FIR

Driver

X-point

CTLE+VGA

220 nF

+

TXnN

PRBS

Gen

Voltage

Regulator

Signal

Detect

PRBS

Gen

PRBS

Checker

Voltage

Regulator

PFD, CDR,

And Divider

VCO

Channel Digital Core

Buffer

CAL

CAL_CLK_IN

ADDRn

SCL

Power-On

Reset

Shared Digital Core

Always-On 10 MHz

SDA

READ_EN_N

EN_SMB

ALL_

INT_

Shared Digital Core

17

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www.ti.com.cn

9.3 Feature Description

9.3.1 Device Data Path Operation

The DS250DF810 data path consists of several key blocks as shown in the functional block diagram. These key

circuits are:

•

AC-Coupled Receiver and Transmitter

Signal Detect

Continuous Time Linear Equalizer (CTLE)

Variable Gain Amplifier (VGA)

Cross-Point Switch

Decision Feedback Equalizer (DFE)

Clock and Data Recovery (CDR)

Calibration Clock

Differential Driver with FIR Filter

9.3.2 AC-Coupled Receiver and Transmitter

The differential receiver for each DS250DF810 channel contains on-chip AC coupling capacitors. The differential

transmitter for each DS250DF810 channel also implement on-chip AC coupling capacitors. Value is 220nF +/-

20% for all AC coupling capacitors.

9.3.3 Signal Detect

The DS250DF810 receiver contains a signal detect circuit. The signal detect circuit monitors the energy level on

the receiver inputs and powers on or off the rest of the high-speed data path if a signal is detected or not. By

default, each channel allows the signal detect circuit to automatically power on or off the rest of the high speed

data path depending on the presence of an input signal. The signal detect block can be manually controlled in

the SMBus channel registers. This can be useful if it is desired to manually force channels to be disabled. For

information on how to manually operate the signal detect circuit refer to the DS250DF810 Programming Guide.

9.3.4 Continuous Time Linear Equalizer (CTLE)

The CTLE in the DS250DF810 is a fully-adaptive equalizer. The CTLE adapts according to a Figure of Merit

(FOM) calculation during the lock acquisition process. The FOM calculation is based upon the horizontal eye

opening (HEO) and vertical eye opening (VEO). Once the CDR locks and the CTLE adapts, the CTLE boost

level is frozen until a manual re-adapt command is issued or until the CDR re-enters the lock acquisition state.

The CTLE can be re-adapted by resetting the CDR.

The CTLE consists of 4 stages, with each stage having 2-bit boost control. This allows for 256 different boost

combinations. The CTLE adaption algorithm allows the CTLE to adapt through 16 of these boost combinations.

These 16 boost combinations comprise the EQ Table in the channel registers. See channel registers 0x40

through 0x4F. This EQ Table can be reprogrammed to support up to 16 of the 256 boost settings.

The boost levels can be set between 8 dB and 25 dB (at 14GHz.)

9.3.5 Variable Gain Amplifier (VGA)

The DS250DF810 receiver implements a VGA. The VGA assists in the recovery of extremely small signals,

working in conjunction with the CTLE to equalize and scale amplitude. The VGA has 1-bit control via Register

0x8E[0], and the VGA is enabled by default. In addition to the VGA, the CTLE implements its own gain control

via register 0x13[5] to adjust the DC amplitude similar to the VGA. For more information on how to configure the

VGA refer to the DS250DF810 Programming Guide.

18

DS250DF810

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ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Feature Description (接下页)

9.3.6 Cross-Point Switch

Each group of two adjacent channels in the DS250DF810 has a 2×2 cross-point that may be enabled to

implement a 2-to-1 mux, a 1-to-2 fanout, or an A-to-B/B-to-A lane cross. A cross-point exists between the

following channel pairs:

•

Channel 0 and Channel 1

Channel 2 and Channel 3

Channel 4 and Channel 5

Channel 6 and Channel 7

9.3.7 Decision Feedback Equalizer (DFE)

A 5-tap DFE can be enabled within the data path of each channel to assist with reducing the effects of cross talk,

reflections, or post cursor inter-symbol interference (ISI). The DFE must be manually enabled, regardless of the

selected adapt mode. Once the DFE has been enabled it can be configured to adapt only during lock acquisition

or to adapt continuously. The DFE can also be manually configured to specified tap polarities and tap weights.

However, when the DFE is configured manually the DFE auto-adaption should be disabled. For many

applications with lower insertion loss (i.e. < 30 dB) lower crosstalk, and/or lower reflections, part or all of the DFE

can be disabled to reduce power consumption. The DFE can either be fully enabled (taps 1-5), partially enabled

(taps 1-2 only), or fully disabled (no taps).

The DFE taps are all feedback taps with 1UI spacing. Each tap has a specified boost weight range and polarity

bit.

表 1. DFE Tap Weights

DFE PARAMETER

Tap 1 Weight Range

Tap 2-5 Weight Range

Tap Weight Step Size

DECIMAL (REGISTER VALUE)

VALUE (mV) (TYP)

0 - 31

0 - 15

NA

0 – 217

0 – 105

7

0: (+) positive; feedback value creates a low-pass filter response, thus providing attenuation to

correct for negative-sign post-cursor ISI

Polarity

1: (-) negative; Feedback value creates a high-pass filter response, thus providing boost to correct

for positive-sign post-cursor ISI.

9.3.8 Clock and Data Recovery (CDR)

The CDR consists of a Phase Locked Loop (PLL), PPM counter, and Input and Output Data Multiplexers (mux)

allowing for retimed data, un-retimed data, PRBS generator and output muted modes.

By default, the equalized data is fed into the CDR for clock and data recovery. The recovered data is then output

to the FIR filter and differential driver together with the recovered clock which has been cleaned of any high-

frequency jitter outside the bandwidth of the CDR clock recovery loop. The bandwidth of the CDR defaults to 5.5

MHz (typ) in full-rate (divide-by-1) mode and 5.3 MHz (typ) in sub-rate mode. The CDR bandwidth is adjustable.

Refer to the DS250DF810 Programming Guide for more information on adjusting the CDR bandwidth. Users can

configure the CDR data to route the recovered clock and data to the PRBS checker. Users also have the option

of configuring the output of the CDR to send raw non-retimed data, or data from the pattern generator.

The CDR requires the following in order to be properly configured:

•

25 MHz calibration clock to run the PPM counter (CAL_CLK_IN).

Expected data rates must be programmed into the CDR either through the rate table or entered manually with

the corrected divider settings. Refer to the Programming Guide for more information on configuring the CDR

for different data rates.

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9.3.9 Calibration Clock

The calibration clock is not part of the CDR’s PLL and thus is not used for clock and data recovery. The

calibration clock is connected only to the PPM counter for each CDR. The PPM counter constrains the allowable

lock ranges of the CDR according to the programmed values in the rate table or the manually entered data rates.

The host should provide an input calibration clock signal of 25 MHz frequency. Because this clock is not used for

clock and data recovery, there are no stringent jitter requirements placed on this 25 MHz calibration clock.

9.3.10 Differential Driver with FIR Filter

The DS250DF810 output driver has a three-tap finite impulse response (FIR) filter which allows for pre- and post-

cursor equalization to compensate for a wide variety of output channel media. The filter consists of a weighted

sum of three consecutive retimed bits as shown in the following diagram. C[0] can take on values in the range [-

31, +31]. C[-1] and C[+1] can take on values in the range [-15, 15].

Retimed

Data

FIR filter

output

x

+

1 UI

Delay

C[-1]

Pre-cursor

x

+

1 UI

Delay

C[0]

Main-curosr

x

C[+1]

Post-cursor

图 7. FIR Filter Functional Model

When utilizing the FIR filter, it is important to abide by the following general rules:

•

|C[-1]|+|C[0]|+|C[+1]| ≤ 31; the FIR tap coefficients absolute sum must be less or equal to 31)

sgn(C[-1])=sgn(C[+1]) ≠ sgn(C[0]), for high-pass filter effect; the sign for the pre-cursor and/or post-cursor tap

must be different from main-cursor tap to realize boost effect

•

sgn(C[-1])=sgn(C[+1]) = sgn(C[0]), for low-pass filter effect; the sign for the pre-cursor and/or post-cursor tap

must be equal to the main-cursor tap to realize attenuation effect

The FIR filter is used to pre-distort the transmitted waveform in order to compensate for frequency-dependant

loss in the output channel. The most common way of pre-distorting the signal is to accentuate the transitions and

de-emphasize the non-transitions. The bit before a transition is accentuated via the pre-cursor tap, and the bit

after the transition is accentuated via the post-cursor tap. The figures below give a conceptual illustration of how

the FIR filter affects the output waveform. The following characteristics can be derived from the example

waveforms.

•

VOD_pk-pk=v₇- v₈

VOD_{low-frequency}= v₂- v₅

Rpre_dB= 20 * log₁₀(v₃⁄v₂)

Rpst_dB= 20 * log₁₀(v₁⁄v₂)

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Transmitted

Bits: 0

0

1

0

1

0

1

Differential

Voltage

v₇

v₁

v₃

v₂

0 V

Time [UI]

v₅

v₆

v₄

v₈

图 8. Conceptual FIR Waveform With Post-Cursor Only

Transmitted

Bits: 0

0

1

0

1

0

1

Differential

Voltage

v₃

v₇

v₁

v₂

0 V

Time [UI]

v₄

v₅

v₆

v₈

图 9. Conceptual FIR Waveform With Pre-Cursor Only

Transmitted

Bits: 0

0

1

0

1

0

1

Differential

Voltage

v₇

v₁

v₃

v₂

0 V

Time [UI]

v₅

v₆

v₄

v₈

图 10. Conceptual FIR Waveform With Both Pre- And Post-Cursor

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9.3.11 Setting the Output V_OD

The output differential voltage (V_OD) of the driver is controlled by manipulating the FIR tap settings. The main

cursor tap is the primary knob for amplitude adjustment. The pre and post cursor FIR tap settings can then be

adjusted to provide equalization. To maintain a constant peak-to-peak VOD, the user should adjust the main

cursor tap value relative to the pre/post tap changes so as to maintain a constant absolute sum of the FIR tap

values. The table below shows various settings for V_ODsettings ranging from 205 mVpp to 1225 mVpp (typical).

Note that the output peak-to-peak amplitude is a function of the sum of the absolute values of the taps, whereas

the low-frequency amplitude is purely a function of the main-cursor value.

表 2. Typical VOD and FIR Values

FIR SETTINGS

Peak-to Peak

RPRE(dB)

RPST(dB)

PRE-CURSOR:

REG_0x3E[6:0]

MAIN-CURSOR:

REG_0x3D[6:0]

POST-CURSOR:

REG_0x3F[6:0]

VOD(V)

0

-1

-2

-3

-4

-5

0.205

0.260

0.305

0.355

0.395

0.440

0.490

0.525

0.565

0.610

0.650

0.685

0.720

0.760

0.790

0.825

0.860

0.890

0.925

0.960

0.985

1.010

1.040

1.075

1.095

1.125

1.150

1.165

1.190

1.205

1.220

1.225

0.960

NA

2.1

2.5

3.1

3.8

4.7

+1

+2

+3

+4

+5

+6

+7

+8

+9

+10

+11

+12

+13

+14

+15

+16

+17

+18

+19

+20

+21

+22

+23

+24

+25

+26

+27

+28

+29

+30

+31

+18

+17

+16

+15

+14

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表 2. Typical VOD and FIR Values (接下页)

FIR SETTINGS

Peak-to Peak

VOD(V)

RPRE(dB)

RPST(dB)

PRE-CURSOR:

MAIN-CURSOR:

REG_0x3D[6:0]

POST-CURSOR:

REG_0x3F[6:0]

REG_0x3E[6:0]

0

+13

+12

+11

+10

18

17

16

15

26

25

24

23

22

21

20

19

18

17

16

15

26

25

24

23

22

21

20

-6

-7

-8

-9

0

0.960

1.165

NA

1.0

1.6

2.4

3.3

NA

0.7

1.2

1.5

2.0

2.6

3.2

4.0

5.8

7.2

9.0

11.6

NA

1.1

1.3

1.8

2.2

2.7

3.3

3.9

4.7

5.7

6.9

8.4

10.1

NA

0

-1

-2

-3

-4

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

0

-1

-2

-3

-4

-5

-6

-7

0

The recommended pre-cursor and post-cursor settings for a given channel will depend on the channel

characteristics (mainly insertion loss) as well as the equalization capabilities of the downstream receiver. The

DS250DF810 receiver, with its highly-capable CTLE and DFE, does not require a significant amount of pre- or

post-cursor. The figures below give general recommendations for pre- and post-cursor for different channel loss

conditions. The insertion loss (IL) in these plots refers to the total loss between the link partner transmitter and

the DS250DF810 receiver.

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图 11. Guideline for link partner FIR settings when IL ≤ 15dB

图 12. Guideline for link partner FIR settings when IL ≤ 25dB

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图 13. Guideline for link partner FIR settings when IL ≤ 35dB

9.3.12 Output Driver Polarity Inversion

In some applications, it may be necessary to invert the polarity of the data transmitted from the retimer. To invert

the polarity of the data, read back the FIR polarity settings for the pre, main and post cursor taps and then invert

these bits.

9.3.13 Debug Features

9.3.13.1 Pattern Generator

Each channel in the DS250DF810 can be configured to generate a 16-bit user-defined data pattern or a pseudo

random bit sequence (PRBS). The user defined pattern can also be set to automatically invert every other 16-bit

symbol for DC balancing purposes. The DS250DF810 pattern generator supports the following PRBS

sequences:

•

PRBS – 2⁷- 1

PRBS – 2⁹- 1

PRBS – 2¹¹- 1

PRBS – 2¹⁵- 1

PRBS – 2²³- 1

PRBS – 2³¹- 1

PRBS – 2⁵⁸- 1

PRBS – 2⁶³- 1

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9.3.13.2 Pattern Checker

The pattern checker can be manually set to look for specific PRBS sequences and polarities or it can be set to

automatically detect the incoming pattern and polarity. The PRBS checker supports the same set of PRBS

patterns as the PRBS generator.

The pattern checker consists of an 11-bit error counter. The pattern checker uses 32- bit words, but every bit in

the word is checked for error, so the error count represents the count of single bit errors.

In order to read out the bit and error counters, the pattern checker must first be frozen. Continuous operation with

simultaneous read out of the bit and error counters is not supported in this implementation. Once the bit and

error counter is read, they can be un-frozen to continue counting.

9.3.13.3 Eye Opening Monitor

The DS250DF810’s Eye Opening Monitor (EOM) measures the internal data eye at the input of the decision

slicer and can be used for 2 functions:

1. Horizontal Eye Opening (HEO) and Vertical Eye Opening (VEO) measurement

2. Full Eye Diagram Capture

The HEO measurement is made at the 0V crossing and is read in channel register 0x27. The VEO measurement

is made at the 0.5 UI mark and is read in channel register 0x28. The HEO and VEO registers can be read from

channel registers 0x27 and 0x28 at any time while the CDR is locked. The following equations are used to

convert the contents of channel registers 0x27 and 0x28 into their appropriate units:

•

HEO [UI] = ch reg 0x27 ÷ 32

VEO [mV] = ch reg 0x28 x 3.125

A full eye diagram capture can be performed when the CDR is locked. The eye diagram is constructed within a

64 x 64 array, where each cell in the matrix consists of an 16-bit word representing the total number of hits

recorded at that particular phase and voltage offset. Users can manually adjust the vertical scaling of the EOM or

allow the state machine to control the scaling which is the default option. The horizontal scaling controlled by the

state machine and is always directly proportional to the data rate.

When a full eye diagram plot is captured, the retimer will shift out four 16-bit words of junk data that should be

discarded followed by 4096 16-bit words that make up the 64 × 64 eye plot. The first actual word of the eye plot

from the retimer is for (X, Y) position (0,0), which is the earliest position in time and the most negative position in

voltage. Each time the eye plot data is read out the voltage position is incremented. Once the voltage position

has incremented to position 63 (the most positive voltage), the next read will cause the voltage position to reset

to 0 (the most negative voltage) and the phase position to increment. This process will continue until the entire

64 × 64 matrix is read out. 图 14 below shows the EOM read out sequence overlaid on top of a simple eye

opening plot. In this plot any hits are shown in green. This type of plot is helpful for quickly visualizing the HEO

and VEO. Users can apply different algorithms to the output data to plot density or color gradients to the output

data.

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63

127

4095

63

0

64

4032

63

Phase Position

图 14. EOM Full Eye Capture Readout

To manually control the EOM vertical range, remove scaling control from the state machine then select the

desired range:

Channel Reg 0x2C[6] → 0 (see 表 3).

表 3. Eye Opening Monitor Vertical Range Settings

CH REG 0x11[7:6] VALUE

EOM VERTICAL RANGE [mV]

2’b00

2'b01

2'b10

2'b11

±100

±200

±300

±400

The EOM operates as an under-sampled circuit. This allows the EOM to be useful in identifying over

equalization, ringing and other gross signal conditioning issues. However, the EOM cannot be correlated to a bit

error rate.

The EOM can be accessed in two ways to read out the entire eye plot:

•

Multi-byte reads can be used such that data is repeatedly latched out from channel register 0x25.

With single byte reads, the MSB are located in register 0x25 and the LSB are located in register 0x26. In this

mode, the device must be addressed each time a new byte is read.

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To perform a full eye capture with the EOM, follow these steps below within the desired channel register set:

表 4. Eye Opening Monitor Full Eye Capture Instructions

STEP

REGISTER [bits]

0x67[5]

OPERATION

Write

VALUE

DESCRIPTION

Disable lock EOM lock monitoring

1

0

0x2C[6]

Write

Set the desired EOM vertical range

2

0x11[7:6]

0x11[5]

Write

2'b--

0

3

4

Write

Power on the EOM

Enable fast EOM

0x24[7]

Write

1

Begin read out of the 64 x 64 array, discard first 4 words

Ch reg 0x24[0] is self-clearing.

0x24[0]

0x25

0x26

5

6

Read

1

0x25 is the MSB of the 16-bit word

0x26 is the LSB of the 16-bit word

0x25

0x26

Continue reading information until the 64 x 64 array is

complete.

Read

0x67[5]

0x2C[6]

0x11[5]

0x24[7,1]

Write

1

0

Return the EOM to its original state. Undo steps 1-4

7

9.3.14 Interrupt Signals

The DS250DF810 can be configured to report different events as interrupt signals. These interrupt signals do not

impact the operation of the device, but merely report that the selected event has occurred. The interrupt bits in

the register sets are all sticky bits. This means that when an event triggers an interrupt the status bit for that

interrupt is set to logic HIGH. This interrupt status bit will remain at logic HIGH until the bit has been read. Once

the bit has been read it will be automatically cleared, which allows for new interrupts to be detected. The

DS250DF810 will report the occurrence of an interrupt through the INT_N pin. The INT_N pin is an open drain

output that will pull the line low when an interrupt signal is triggered.

Note that all available interrupts are disabled by default. Users must activate the various interrupts before they

can be used.

The interrupts available in the DS250DF810 are:

•

CDR loss of lock

CDR locked

Signal detect loss

Signal detected

PRBS pattern checker bit error detected

HEO/VEO threshold violation

When an interrupt occurs, share register 0x08 reports which channel generated the interrupt request. Users can

then select the channel(s) that generated the interrupt request and service the interrupt by reading the

appropriate interrupt status bits in the corresponding channel registers. For more information on reading interrupt

status, refer to the DS250DF810 Programming Guide.

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9.4 Device Functional Modes

9.4.1 Supported Data Rates

The DS250DF810 supports a wide range of input data rates, including divide-by-2 and divide-by-4 sub-rates. The

supported data rates are listed in 表 5. Refer to the DS250DF810 Programming Guide for information on

configuring the DS250DF810 for different data rates.

表 5. Supported Data Rates

DATA RATE RANGE

DIVIDER

CDR MODE

COMMENT

MIN

MAX

≥ 20.2752 Gbps

≥ 10.1376 Gbps

> 6.45 Gbps

≤ 25.8 Gbps

≤ 12.9 Gbps

< 10.3 Gbps

1

2

Enabled

Disabled

N/A

Output jitter will be higher

with CDR disabled.

≥ 5.0688 Gbps

≥ 1.25 Gbps

≤ 6.45 Gbps

4

Enabled

Disabled

< 5.15 Gbps

N/A

Output jitter will be higher

with CDR disabled.

9.4.2 SMBus Master Mode

SMBus master mode allows the DS250DF810 to program itself by reading directly from an external EEPROM.

When using the SMBus master mode, the DS25DF810 will read directly from specific location in the external

EEPROM. When designing a system for using the external EEPROM, the user needs to follow these specific

guidelines:

•

Maximum EEPROM size is 2048 Bytes

Minimum EEPROM size for a single DS250DF810 with individual channel configuration is 595 Bytes (3 base

header bytes + 12 address map bytes + 8 x 72 channel register bytes + 2x2 share register bytes; bytes are

defined to be 8-bits)

•

Set ENSMB = Float, for SMBus master mode

The external EEPROM device address byte must be 0xA0

The external EEPROM device must support 400kHz operation at 2.5V or 3.3V supply

Set the SMBus address of the DS250DF810 by configuring the ADDR0 and ADDR1 pins

When loading multiple DS250DF810 devices from the same EEPROM, use these guidelines to configure the

devices:

•

Configure the SMBus addresses for each DS250DF810 to be sequential. The first device in the sequence

must have an address of 0x30

Daisy chain READ_EN_N and ALL_DONE_N from one device to the next device in the sequence so that they

do not compete for the EEPROM at the same time.

If all of the DS250DF810 devices share the same EEPROM channel and share register settings, configure

the common channel bit in the base header to 1. With common channel configuration enabled, each

DS250DF810 device will configure all 8 channels with the same settings.

When loading a single DS250DF810 from an EEPROM, use these guidelines to configure the device:

•

Set the common channel bit to 0 to allow for individual channel configuration, or set the common channel bit

to 1 to load the same configuration settings to all channels.

•

When configuring individual channels, a 1024 or 2048 Byte EEPROM must be used.

If there are more than three DS250DF810 devices on a PCB that require individual channel configuration,

then each device must have its own EEPROM.

9.4.3 Device SMBus Address

The DS250DF810’s SMBus slave address is strapped at power up using the ADDR[1:0] pins. The pin state is

read on power up, after the internal power-on reset signal is de-asserted. The ADDR[1:0] pins are four-level

LVCMOS IOs, which provides for 16 unique SMBus addresses. The four levels are achieved by pin strap options

as follows:

•

0: 1 kΩ to GND

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•

R: 10 kΩ to GND

F: Float

1: 1 kΩ to VDD

表 6. SMBus Address Map

REQUIRED ADDRESS PIN STRAP VALUE

8-BIT WRITE ADDRESS [HEX]

ADDR1

ADDR0

0x30

0x32

0x34

0x36

0x38

0x3A

0x3C

0x3E

0x40

0x42

0x44

0x46

0x48

0x4A

0x4C

0x4E

0

R

F

1

0

R

F

1

0

R

F

1

0

R

F

1

0

1

R

F

1

9.5 Programming

9.5.1 Bit Fields in the Register Set

Many of the registers in the DS250DF810 are divided into bit fields. This allows a single register to serve multiple

purposes which may be unrelated. Often, configuring the DS250DF810 requires writing a bit field that makes up

only part of a register value while leaving the remainder of the register value unchanged. The procedure for

accomplishing this task is to read in the current value of the register to be written, modify only the desired bits in

this value, and write the modified value back to the register. Of course, if the entire register is to be changed,

rather than just a bit field within the register, it is not necessary to read in the current value of the register first. In

all register configuration procedures described in the following sections, this procedure should be kept in mind. In

some cases, the entire register is to be modified. When only a part of the register is to be changed, however, the

procedure described above should be used.

Most register bits can be read or written to. However, some register bits are constrained to specific interface

instructions.

Register bits can have the following interface constraints:

•

R - Read only

RW - Read/Write

RWSC - Read/Write, self-clearing

9.5.2 Writing to and Reading from the Global/Shared/Channel Registers

The DS250DF810 has 3 types of registers:

1) Global Registers – These registers can be accessed at any time and are used to select individual channel

registers, the shared registers or to read back the TI ID and version information.

2) Shared Registers – These registers are used for device-level configuration, status read back or control.

3) Channel Registers – These registers are used to control and configure specific features for each individual

channel. All channels have the same channel register set and can be configured independent of each other.

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Programming (接下页)

The global registers can be accessed at any time, regardless of whether the shared or channel register set is

selected. The DS250DF1810 global registers are located on addresses 0xEF-0xFF. The function of the global

registers falls into the following categories:

•

Channel selection and share enabling – Registers 0xFC and 0xFF

Device and version information – Registers 0xEF-0xF3

Reserved/unused registers – all other addresses

Register 0xFF[5:4] is used to select the share registers of either Quad 0 (channels 0-3) or Quad 1 (channels 4-

7).

Register 0xFC is used to select the channel registers to be written to. To select a channel, write a 1 to its

corresponding bit in register 0xFC. Note that more than one channel may be written to by setting multiple bits in

register 0xFC. However, when performing an SMBus read transaction only one channel can be selected at a

time. If multiple channels are selected when attempting to perform an SMBus read, the device will return 0x00.

Register 0xFF bit 1 can be used to perform broadcast register writes to all channels. A single channel read-

modify broadcast write type commands can be accomplished by setting register 0xFF to 0x03 and selecting a

single channel in register 0xFC. This type of configuration allows for the reading of a single channel's register

information and then writing to all channels with the modified value. Register 0xFF bit 0 is used to select the

shared register page or the channel register page for the channels selected in register 0xFC.

TI repeaters/retimers have a vendor ID register (0xFE) which will always read back 0x03. In addition, there are

three device ID registers (0xF0, 0xF1, and 0xF3). These are useful to verify that there is a good SMBus

connection between the SMBus master and the DS250DF810.

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9.6 Register Maps

Table 7. Global Registers

DEFAULT

ADDRESS

(HEX)

BITS

VALUE

(HEX)

MODE

EEPROM

FIELD NAME

DESCRIPTION

EF

F0

F1

F3

FB

FC

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

0

1

0

1

0

1

0

1

0

1

0

R

N

SPARE

R

CHAN_CONFIG_ID[3]

CHAN_CONFIG_ID[2]

CHAN_CONFIG_ID[1]

CHAN_CONFIG_ID[0]

VERSION[7]

R

VERSION[6]

R

VERSION[5]

R

VERSION[4]

R

VERSION[3]

R

VERSION[2]

R

VERSION[1]

R

VERSION[0]

R

DEVICE_ID[7]

DEVICE_ID[6]

DEVICE_ID[5]

DEVICE_ID[4]

DEVICE_ID[3]

DEVICE_ID[2]

DEVICE_ID[1]

DEVICE_ID[0]

CHAN_VERSION[3]

CHAN_VERSION[2]

CHAN_VERSION[1]

CHAN_VERSION[0]

SHARE_VERSION[3]

SHARE_VERSION[2]

SHARE_VERSION[1]

SHARE_VERSION[0]

RESERVED

Full device ID

R

Digital Channel Version

Digital Share Version

R

RW

RESERVED

EN_CH7

Select channel 7

Select channel 6

Select channel 5

Select channel 4

EN_CH6

EN_CH5

EN_CH4

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Register Maps (continued)

Table 7. Global Registers (continued)

DEFAULT

ADDRESS

(HEX)

BITS

VALUE

(HEX)

MODE

EEPROM

FIELD NAME

DESCRIPTION

Select channel 3

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

0

1

0

RW

R

N

EN_CH3

EN_CH2

EN_CH1

EN_CH0

Select channel 2

Select channel 1

Select channel 0

FD

FE

FF

RESERVED

VENDOR_ID[7]

VENDOR_ID[6]

VENDOR_ID[5]

VENDOR_ID[4]

VENDOR_ID[3]

VENDOR_ID[2]

VENDOR_ID[1]

VENDOR_ID[0]

RESERVED

TI vendor ID

R

RW

RESERVED

EN_SHARE_Q1

EN_SHARE_Q0

RESERVED

Select shared registers for quad 1

Select shared registers for quad 0

RESERVED

WRITE_ALL_CH

Allows customer to write to all

channels as if they are the same, but

only allows read back from the

channel specified in 0xFC and 0xFD.

Note: en_ch_SMB must be = 1 or else

this function is invalid.

1

0

RW

N

EN_CH_SMB

1: Enables SMBUS access to the

channels specified in register 0xFC

0: The shared registers are selected,

see 0xFF[5:4]

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Table 8. Shared Registers

DEFAULT

ADDRESS

(HEX)

FIELD

BITS

VALUE

(HEX)

MODE

EEPROM

NAME

DESCRIPTION

SMBus Address

0

1

7

6

1

R

N

SMBus_Addr3

SMBus_Addr2

Strapped 7-bit addres is 0x18 +

SMBus_Addr[3:0]

1

5

4

0

1

0

1

0

1

0

1

0

1

R

N

SMBus_Addr1

SMBus_Addr0

RESERVED

RST_SMB_REGS

RST_SMB_MAS

rc_eeprm_rd

RESERVED

disab_eeprm_cfg

3:0

7

R

N

Y

N

6

5

R

4

R

3

R

2

R

1

R

0

R

2

3

4

7:0

7

RW

RWSC

RW

6

1: Resets share registers.

5

1: Reset for SMBus Master Mode

1: Force EEPROM Configuration

4

3

2

1

0

5

Disable Master Mode EEPROM

Configuration

7

6:5

4

0

1

RW

R

N

RESERVED

EEPROM_READ_DONE

This bit is set to 1 when read from

EEPROM is done

3

2

0

1

0

RW

R

N

Y

N

Y

RESERVED

int_q0c3

1

0

6

8

7:0

7

6

R

5

R

4

R

3

R

Interrupt from channel3 of quad0

Interrupt from channel2 of quad0

Interrupt from channel1 of quad0

Interrupt from channel0 of quad0

2

R

int_q0c2

1

R

int_q0c1

0

R

int_q0c0

A

7:1

R

RESERVED

dis_refclk_out

1: Disable REFCLK_OUT (high-Z)

0: Enable REFCLK_OUT

0

7

0

RW

Y

N

B

RESERVED

34

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ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 8. Shared Registers (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

FIELD

NAME

BITS

MODE

EEPROM

DESCRIPTION

refclk_det

High level when ref_clk has been

detected

6

0

R

N

5

4

0

1

0

RW

R

N

Y

N

RESERVED

3

mr_refclk_det_dis

RESERVED

eecfg_cmplt

eecfg_fail

2

1

0

C

D

E

7:0

7:2

1:0

7:0

7

RW

R

F

RW

R

10

6

5

4

3

2

1

0

11

7

11: Not valid 10: EEPROM load

completed successfully

01: EEPROM load failed after 64

attempts

6

0

R

N

00: EEPROM load in progress

5

4

3

2

1

0

R

N

eecfg_atmpt[5]

eecfg_atmpt[4]

eecfg_atmpt[3]

eecfg_atmpt[2]

eecfg_atmpt[1]

eecfg_atmpt[0]

reg_i2c_fast

Number of attempts made to load

EEPROM image

12

1: EEPROM load uses Fast I2C Mode

(400 kHz)

7

1

RW

N

0: EEPROM load uses Standard I2C

Mode (100 kHz)

6

5

4

3

2

1

0

1

0

1

RW

N

RESERVED

Table 9. Channel Select Global Register Definition

ADDRESS

(HEX)

BITS

DESCRIPTION

0xFC

7

Select register set for channel 7

35

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

www.ti.com.cn

Table 9. Channel Select Global Register Definition (continued)

ADDRESS

(HEX)

BITS

DESCRIPTION

6

5

4

3

2

1

0

Select register set for channel 6

Select register set for channel 5

Select register set for channel 4

Select register set for channel 3

Select register set for channel 2

Select register set for channel 1

Select register set for channel 0

Table 10. Device/Vendor ID Global Register Definition

ADDRESS

(HEX)

BITS

DESCRIPTION

0xF0

0xF1

0xF3

0xFE

TI Device ID. Contains 0x32.

TI Device ID. Contains 0x10.

TI Device ID. Contains 0x00.

TI Vendor ID. Read-only register. Contains value 0x03.

Table 11. Register Page Select Definition

ADDRESS

(HEX)

BITS

DESCRIPTION

0xFF

1: Selects shared registers for channels 4 -7

0: Normal operation

5

4

1: Selects shared registers for channels 0-3

0: Normal operation

1: Broadcast write to all channels, 0xFF[0] must be set to 1. Select a single channel in

0xFC.

0: Normal operation, select channel register as defined in 0xFC.

1

0

1: Select Channel Registers

0: Select Share Registers

36

DS250DF810

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ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 12. Channel Registers, 0 to 39

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

RESERVED

0

7

6

5

4

3

0

RW

N

RESERVED

RST_CORE

RESERVED

1: Reset the 10M core clock domain.

This is the main clock domain for all

the state machines

0: Normal operation

2

1

0

RW

N

RST_REGS

RST_VCO

1: Reset channel registers to power-

up defaults.

0: Normal operation

1: Resets the CDR S2P clock

domain, includes PPM counter,

EOM counter.

0: Normal operation

0

RW

N

RST_REFCLK

1: Resets the 25MHz reference

clock domain, includes PPM

counter. Does not work if 25MHz

clock is not present.

0: Normal operation

1

7

6

0

R

N

sigdet

Raw Signal Detect observation

pol_inv_det

Indicates PRBS checker detected

polarity inversion in the locked data

sequence.

5

4

0

R

N

CDR_LOCK_LOSS_INT

prbs_seq_det[3]

1: Indicates loss of CDR lock after

having acquired it. Bit clears on

read. Feature must be enabled with

reg_31[1]

Indicates the pattern detected on the

input serial stream

0xxx: No detect

3

2

1

0

R

N

prbs_seq_det[2]

prbs_seq_det[1]

prbs_seq_det[0]

1000: 7 bits PRBS sequence

1001: 9 bits PRBS sequence

1010: 11 bits PRBS sequence

1011: 15 bits PRBS sequence

1100: 23 bits PRBS sequence

1101: 31 bits PRBS sequence

1110: 58 bits PRBS sequence

1111: 63 bits PRBS sequence

0

7

0

R

N

SIG_DET_LOSS_INT

CDR_STATUS[7]

Loss of signal indicator, set once

signal is acquired and then lost.

Clears on read. Feature must be

enabled with reg_31[0]

2

"This register is used to read the

status of internal signal.

Select what is observable on this

bus using Reg_0x0C[7:4]"

6

5

4

3

2

1

0

R

N

CDR_STATUS[6]

CDR_STATUS[5]

CDR_STATUS[4]

CDR_STATUS[3]

CDR_STATUS[2]

CDR_STATUS[1]

CDR_STATUS[0]

37

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

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Table 12. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

3

4

5

6

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

RW

Y

N

EQ_BST0[1]

This register can be used to force an

EQ boost setting if used in

conjunction with channel register

0x2D[3].

EQ_BST0[0]

EQ_BST1[1]

EQ_BST1[0]

EQ_BST2[1]

EQ_BST2[0]

EQ_BST3[1]

EQ_BST3[0]

RESERVED

38

DS250DF810

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ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 12. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

RESERVED

8

7

6

5

4

3

2

1

0

7

0

1

0

1

0

RW

Y

RESERVED

REG_VCO_CAP_OV

RESERVED

9

Enable bit to override cap_cnt with

value in register and 0B[4:0]

6

5

0

RW

Y

REG_SET_CP_LVL_LPF_OV

REG_BYPASS_PFD_OV

Enable bit to override lpf_dac_val

with value in register 1F[4:0]

Enable bit to override

sel_retimedD_loopthru and

sel_rawD_loopthru with values in

reg1E[7:5]

4

3

2

0

RW

Y

REG_EN_FD_PD_VCO_PDIQ_OV

REG_EN_PD_CP_OV

Enable bit to override en_fd, pd_pd,

pd_vco, pd_pdiq with reg1E[0],

reg1E[2], reg1C[0], reg1C[1]

Enable bit to override pd_fd_cp and

pd_pd_cp with value in register

1B[1:0]

REG_DIVSEL_OV

Enable bit to override divsel with

value in register 18[6:4]

1

0

7

6

0

RW

Y

RESERVED

REG_PFD_LOCK_MODE_SM

RESERVED

Enable fd in lock state

RESERVED

A

REG_EN_IDAC_PD_CP_OV

AND_REG_EN_IDAC_FD_CP_OV

Enable bit to override phase

detector charge pump settings with

reg1C[7:5]

Enable bit to override frequency

detector charge pump settings with

reg1C[4:2]"

5

0

RW

Y

REG_DAC_LPF_HIGH_PHASE_OV Enable bit to loop filter comparator

_AND_REG_DAC_LPF_LOW_PHA trip voltages with reg16[7:0]

SE_OV

4

3

0

RW

Y

N

RESERVED

REG_CDR_RESET_OV

Enable CDR Reset override with

reg0A[2]

2

1

0

RW

N

REG_CDR_RESET_SM

REG_CDR_LOCK_OV

CDR Reset override bit

Enable CDR lock signal override

with reg0A[0]

0

7

6

5

4

3

2

1

0

1

0

1

RW

N

Y

REG_CDR_LOCK

RESERVED

CDR lock signal override bit

RESERVED

B

RESERVED

39

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

www.ti.com.cn

Table 12. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

RESERVED

C

7

6

5

4

3

2

1

0

7

0

1

RW

N

RESERVED

DES_PD

RESERVED

D

"1: De-serializer (for PRBS checker)

is powered down

0: De-serializer (for PRBS checker)

is enabled"

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

RW

N

Y

N

RESERVED

E

F

10

40

DS250DF810

www.ti.com.cn

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 12. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

11

7

6

0

RW

Y

EOM_SEL_VRANGE[1]

EOM_SEL_VRANGE[0]

Manually set the EOM vertical

range, used with channel register

0x2C[6]:

00: ±100 mV

01: ±200 mV

10: ±300 mV

11: ±400 mV

5

4

3

1

0

RW

Y

N

Y

EOM_PD

1: Normal operation

RESERVED

DFE_TAP2_POL

Bit forces DFE tap 2 polarity

1: Negative, boosts by the specified

tap weight

0: Positive, attenuates by the

specified tap weight

2

1

0

7

0

1

RW

Y

DFE_TAP3_POL

DFE_TAP4_POL

DFE_TAP5_POL

DFE_TAP1_POL

Bit forces DFE tap 3 polarity

1: Negative, boosts by the specified

tap weight

0: Positive, attenuates by the

specified tap weight

Bit forces DFE tap 4 polarity

1: Negative, boosts by the specified

tap weight

0: Positive, attenuates by the

specified tap weight

Bit forces DFE tap 5 polarity

1: Negative, boosts by the specified

tap weight

0: Positive, attenuates by the

specified tap weight

12

Bit forces DFE tap 1 polarity

1: Negative, boosts by the specified

tap weight

0: Positive, attenuates by the

specified tap weight

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

0

1

0

RW

N

Y

N

Y

RESERVED

DFE_WT1[4]

DFE_WT1[3]

DFE_WT1[2]

DFE_WT1[1]

DFE_WT1[0]

eq_PD_PeakDetect

eq_PD_SD

Bits force DFE tap 1 weight. Manual

DFE operation required to take

effect by setting 0x15[7]=1.

13

eq_hi_gain

eq_en_dc_off

RESERVED

eq_limit_en

1: Configures the final stage of the

equalizer to be a limiting stage.

0: Normal operation, final stage of

the equalizer is configured to be a

linear stage.

1

0

RW

Y

RESERVED

41

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

www.ti.com.cn

Table 12. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

EQ_SD_PRESET

DESCRIPTION

14

7

0

RW

Y

1: Forces signal detect HIGH, and

force enables the channel. Should

not be set if bit 6 is set.

0: Normal Operation.

6

0

RW

Y

EQ_SD_RESET

1: Forces signal detect LOW and

force disables the channel. Should

not be set if bit 7 is set.

0: Normal Operation.

5

4

3

2

1

0

7

0

1

0

RW

Y

N

Y

EQ_REFA_SEL1

EQ_REFA_SEL0

EQ_REFD_SEL1

EQ_REFD_SEL0

RESERVED

Controls the signal detect assert

levels.

Controls the signal detect de-assert

levels.

RESERVED

15

DFE_FORCE_EN

1: Enables manual DFE tap settings

0: Normal operation

6

5

4

3

0

1

0

RW

N

Y

RESERVED

DRV_PD

1: Powers down the high speed

driver

0: Normal operation

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

RW

Y

RESERVED

16

RESERVED

17

42

DS250DF810

www.ti.com.cn

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 12. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

18

7

6

5

4

0

1

0

RW

N

Y

RESERVED

PDIQ_SEL_DIV2

PDIQ_SEL_DIV1

PDIQ_SEL_DIV0

These bits will force the divider

setting if 0x09[2] is set.

000: Divide by 1

001: Divide by 2

010: Divide by 4

011: Divide by 8

100: Divide by 16

All other values are reserved.

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

RW

N

Y

N

Y

N

Y

RESERVED

CP_EN_CP_PD

19

1A

1B

RESERVED

1: Normal operation, phase detector

charge pump enabled

0

1

RW

Y

CP_EN_CP_FD

1: Normal operation, frequency

detector charge pump enabled

1C

7

6

5

4

3

2

1

0

1

0

1

0

RW

Y

EN_IDAC_PD_CP2

EN_IDAC_PD_CP1

EN_IDAC_PD_CP0

EN_IDAC_FD_CP2

EN_IDAC_FD_CP1

EN_IDAC_FD_CP0

RESERVED

Phase detector charge pump setting.

Override bit required for these bits to

take effect

Frequency detector charge pump

setting. Override bit required for

these bits to take effect

RESERVED

43

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

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Table 12. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

RESERVED

1D

7

6

5

4

3

2

1

0

7

6

5

0

1

RW

N

Y

RESERVED

1E

PFD_SEL_DATA_MUX2

PFD_SEL_DATA_MUX1

PFD_SEL_DATA_MUX0

For these values to take effect,

register 0x09[5] must be set to 1.

000: Raw Data*

001: Retimed Data

100: Pattern Generator

111: Mute

All other values are reserved.

4

3

0

1

RW

N

Y

SER_EN

DFE_PD

1: Enable PRBS Generator

This bit must be cleared for the DFE

to be functional in any adapt mode.

0: DFE enabled

1: DFE disabled

2

1

0

RW

Y

PFD_PD_PD

PFD phase detector power down

override

EN_PARTIAL_DFE

0: (Default) Disable DFE taps 3-5.

1: Enable DFE taps 3-5. DFE_PD

must also be set to 0.

0

1

RW

Y

PFD_EN_FD

PFD enable frequency detector

override

1F

7

6

5

4

3

0

1

RW

N

Y

RESERVED

MR_LPF_AUTO_ADJST_EN

"1: Allow LPF to tune to optimum

value during fast-cap search routine

0: Otherwise LPF value is

determined by the Reg_0x9D"

2

1

0

7

6

5

4

3

2

1

0

1

0

RW

Y

RESERVED

DFE_WT5[3]

DFE_WT5[2]

DFE_WT5[1]

DFE_WT5[0]

DFE_WT4[3]

DFE_WT4[2]

DFE_WT4[1]

DFE_WT4[0]

RESERVED

20

Bits force DFE tap 5 weight, manual

DFE operation required to take

effect by setting 0x15[7]=1.

Bits force DFE tap 4 weight, manual

DFE operation required to take

effect by setting 0x15[7]=1.

44

DS250DF810

www.ti.com.cn

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 12. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

21

7

6

5

4

3

2

1

0

7

0

RW

Y

N

DFE_WT3[3]

Bits force DFE tap 3 weight, manual

DFE operation required to take

effect by setting 0x15[7]=1.

DFE_WT3[2]

DFE_WT3[1]

DFE_WT3[0]

DFE_WT2[3]

DFE_WT2[2]

DFE_WT2[1]

DFE_WT2[0]

EOM_OV

Bits force DFE tap 2 weight, manual

DFE operation required to take

effect by setting 0x15[7]=1.

22

"1: Override enable for EOM manual

control

0: Normal operation"

6

0

RW

N

EOM_SEL_RATE_OV

"1: Override enable for EOM rate

selection

0: Normal operation"

5

4

3

2

1

0

7

0

RW

N

RESERVED

23

EOM_GET_HEO_VEO_OV

"1: Override enable for manual

control of the HEO/VEO trigger

0: Normal operation"

6

1

RW

Y

DFE_OV

1: Normal operation; DFE must be

enabled in Reg_0x1E[3]

5

4

3

2

1

0

RW

N

RESERVED

45

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

www.ti.com.cn

Table 12. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

FAST_EOM

DESCRIPTION

24

7

0

RW

N

1: Enables fast EOM for full eye

capture. In this mode the phase

DAC and voltage DAC or the EOM

are automatically incremented

through a 64 x 64 matrix. Values for

each point are stored in Reg_0x25

and Reg_0x26.

0: Normal operation

6

5

4

0

R

N

DFE_EQ_ERROR_NO_LOCK

DFE/CTLE SM quit due to loss of

lock

GET_HEO_VEO_ERROR_NO_HIT get_heo_veo sees no hits at zero

crossing

S

GET_HEO_VEO_ERROR_NO_OPE get_heo_veo cannot see a vertical

NING

eye opening

3

2

0

RW

N

RESERVED

DFE_ADAPT

RESERVED

RWSC

1: Manually start DFE adaption (self-

clearing)

0: Normal operation

1

0

R

N

EOM_GET_HEO_VEO

1: Manually triggers HEO/VEO

measurement; feature must be

enabled with Reg_0x23[7]; the

HEO/VEO values are read from

Reg_0x27, Reg_0x28

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

RWSC

R

N

EOM_START

EOM_COUNT15

EOM_COUNT14

EOM_COUNT13

EOM_COUNT12

EOM_COUNT11

EOM_COUNT10

EOM_COUNT9

EOM_COUNT8

EOM_COUNT7

EOM_COUNT6

EOM_COUNT5

EOM_COUNT4

EOM_COUNT3

EOM_COUNT2

EOM_COUNT1

EOM_COUNT0

HEO7

Starts EOM counter, self-clearing

MSBs of EOM counter

25

26

27

R

LSBs of EOM counter

R

HEO value, requires CDR to be

locked for valid measurement

R

HEO6

R

HEO5

R

HEO4

R

HEO3

R

HEO2

R

HEO1

R

HEO0

46

DS250DF810

www.ti.com.cn

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 12. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

28

7

6

5

4

3

2

1

0

7

6

0

R

N

VEO7

VEO6

VEO5

VEO4

VEO3

VEO2

VEO1

VEO0

VEO value, requires CDR to be

locked for valid measurement

R

29

RW

R

RESERVED

EOM_VRANGE_SETTING[1]

"Read the currently set Eye Monitor

Voltage Range:

11 - +/-400mV

10 - +/- 300mV

01 - +/- 200mV

00 - +/- 100mV"

5

4

3

2

1

0

7

6

5

4

0

1

0

1

R

N

Y

EOM_VRANGE_SETTING[0]

RESERVED

RW

R

RESERVED

VEO[8]

VEO MSB value

HEO MSB value

R

HEO[8]

2A

RW

EOM_TIMER_THR[3]

EOM_TIMER_THR[2]

EOM_TIMER_THR[1]

EOM_TIMER_THR[0]

The value of eom_timer_thr[7:0]

controls the amount of time the Eye

Monitor samples each point in the

eye for. The total counter bit width is

16b, this register representing the

upper 8b. Therefore, the count value

is equal to {eom_timer_thr[7:0],8'h0}.

The counter counts in 32b words.

Therefore, the total number of bits

counted is 32 times this value.

3

2

1

0

1

0

1

0

RW

Y

VEO_MIN_REQ_HITS[3]

VEO_MIN_REQ_HITS[2]

VEO_MIN_REQ_HITS[1]

VEO_MIN_REQ_HITS[0]

Whenever the Eye Monitor is used

to measure HEO and VEO, the data

is sampled for some number of bits,

set by Reg_0x2A[7:3]. This register

sets the number of hits within that

sample size that is required before

the EOM will indicate a hit has

occurred. This filtering only affects

the VEO measurement.

2B

7

6

5

4

3

2

1

0

1

0

1

0

RW

N

Y

RESERVED

EOM_MIN_REQ_HITS[3]

EOM_MIN_REQ_HITS[2]

EOM_MIN_REQ_HITS[1]

EOM_MIN_REQ_HITS[0]

Whenever the Eye Monitor is used

to measure HEO and VEO, the data

is sampled for some number of bits,

set by Reg_0x2A[7:3]. This register

sets the number of hits within that

sample size that is required before

the EOM will indicate a hit has

occured. This filtering only affects

the HEO measurement.

47

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Table 12. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

reload_dfe_taps

DESCRIPTION

2C

7

1

RW

N

Causes DFE taps to load from last

adapted values

6

5

4

1

RW

Y

VEO_SCALE

Scale VEO based on EOM vrange

DFE_SM_FOM1

DFE_SM_FOM0

This register defines the Figure of

Merit used when adapting the DFE:

00: not valid

01: SM uses only HEO

10: SM uses only VEO

11: SM uses both HEO and VEO

Additionally, if Register 0x6E[6] is

set to '1', the Alternate FOM is used.

This bit takes precedence over

DFE_SM_FOM

3

2

1

0

7

6

5

4

3

0

1

0

1

0

RW

Y

DFE_ADAPT_COUNTER3

DFE_ADAPT_COUNTER2

DFE_ADAPT_COUNTER1

DFE_ADAPT_COUNTER0

RESERVED

DFE look-beyond count.

2D

RESERVED

REG_EQ_BST_OV

Allow override control of the EQ

setting by writing to Reg_0x03

2

1

0

7

6

5

0

RW

R

Y

N

RESERVED

2E

RESERVED

EQ_BST3_2_TO_ANALOG

Read-back of eq_BST3[2] going to

analog

4

3

2

0

RW

N

RESERVED

PRBS_PATTERN_SEL[2]

MSB for the PRBS_PATTERN_SEL

field. Lower bits are found on

register 0x30[1:0]. Refer to the

register 0x30 description on this

table.

1

0

RW

N

RESERVED

48

DS250DF810

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ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 12. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

RESERVED

2F

7

6

0

1

RW

Y

RESERVED

RATE[2]

RATE[1]

RATE[0]

INDEX_OV

Configure PPM register and divider

for a standard data rate. Refer to

Programming Guide.

5

4

3

0

1

0

RW

Y

Configure PPM register and divider

for a standard data rate. Refer to

Programming Guide.

Configure PPM register and divider

for a standard data rate. Refer to

Programming Guide.

If this bit is 1, then Reg_0x39 is to

be used as 4-bit index to the [15:0]

array of EQ settings. The EQ setting

at that index is loaded to the EQ

boost registers going to the analog

and is used as the starting point for

adaption.

2

1

RW

Y

EN_PPM_CHECK

Enable the PPM to be used as a

qualifier when performing Lock

Detect

1

0

RW

Y

N

RESERVED

RWSC

CTLE_ADAPT

Starts CTLE adaptation, self-clearing

49

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Table 12. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

RW

EEPROM

FIELD NAME

FREEZE_PPM_CNT

DESCRIPTION

30

7

6

5

0

N

Y

N

Freeze the PPM counter to allow

safe read asynchronously

RW

EQ_SEARCH_OV_EN

EN_PATT_INV

Enables the EQ 'search" bit to be

forced by Reg_0x13[2]

RW

Enable automatic pattern inversion

of successive 16 bit words when

using the "Fixed Pattern" generator

option.

4

3

0

RW

N

RELOAD_PRBS_CHKR

PRBS_EN_DIG_CLK

Force reload of seed into PRBS

checker LFSR without holding the

checker in reset.

This bit enables the clock to operate

the PRBS generator and/or the

PRBS checher. Toggling this bit is

the primary method to reset the

PRBS pattern generator and PRBS

checker.

2

0

RW

N

PRBS_PROGPATT_EN

"Enable a fixed data pattern output.

Requires that serializer is enabled

with Reg_0x1E[4]. PRBS generator

and checker should be disabled,

Reg_0x30[3]. The fixed data pattern

is set by Reg_0x7C and Reg_0x97.

Enable inversion of the pattern every

16 bits with Reg_0x30[5]".

1

0

RW

N

PRBS_PATTERN_SEL[1]

PRBS_PATTERN_SEL[0]

"Selects the pattern output when

using the PRBS generator. Requires

the pattern generator to be

configured properly. The MSB for

the PRBS_PATTERN_SEL field is in

Reg_0x2E[2].

Use Reg_0x30[3] to enable the

PRBS generator.

000: 2^7-1 bits PRBS sequence

001: 2^9-1 bits PRBS sequence

010: 2^11-1 bits PRBS sequence

011: 2^15-1 bits PRBS sequence

100: 2^23-1 bits PRBS sequence

101: 2^31-1 bits PRBS sequence

110: 2^58-1 bits PRBS sequence

111: 2^63-1 bits PRBS sequence"

50

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ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 12. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

prbs_int_en

DESCRIPTION

31

7

0

RW

N

1: Enables interrupt for detection of

PRBS errors. The PRBS checker

must be properly configured for this

feature to work

6

5

0

1

RW

Y

ADAPT_MODE1

ADAPT_MODE0

00: no adaption

01: adapt CTLE only

10: adapt CTLE until optimal, then

DFE, then CTLE again

11: adapt CTLE until lock, then DFE,

then EQ until optimal

Note: for ADAPT_MODE=2 or 3, the

DFE must be enabled by setting

Reg_0x1E[3]=0 and Reg_0x1E[1]=1.

4

3

0

RW

Y

EQ_SM_FOM1

EQ_SM_FOM0

00: not valid

01: SM uses HEO only

10: SM uses VEO only

11: SM uses both HEO and VEO

2

1

0

RW

N

Y

RESERVED

cdr_lock_loss_int_en

Enable for CDR Lock Loss Interrupt.

Observable in reg_1[5]

0

RW

Y

signal_det_loss_int_en

Enable for Signal Detect Loss

Interrupt. Observable in reg_1[0]

32

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

RW

Y

HEO_INT_THRESH3

HEO_INT_THRESH2

HEO_INT_THRESH1

HEO_INT_THRESH0

VEO_INT_THRESH3

VEO_INT_THRESH2

VEO_INT_THRESH1

VEO_INT_THRESH0

HEO_THRESH3

These bits set the threshold for the

HEO and VEO interrupt. Each

threshold bit represents 8 counts of

HEO or VEO.

33

In adapt mode 3, the register sets

the minimum HEO and VEO

required for CTLE adaption, before

starting DFE adaption. This can be a

max of 15.

HEO_THRESH2

HEO_THRESH1

HEO_THRESH0

VEO_THRESH3

VEO_THRESH2

VEO_THRESH1

VEO_THRESH0

51

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Table 12. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

PPM_ERR_RDY

DESCRIPTION

34

7

0

R

N

1: Indicates that a PPM error count

is read to be read from channel

register 0x3B and 0x3C

6

0

RW

Y

LOW_POWER_MODE_DISABLE

By default, all blocks (except signal

detect) power down after 100 ms

after signal detect goes low.

After achieving lock, the CDR

continues to monitor the lock criteria.

If the lock criteria fail, the lock is

checked for a total of N number of

times before declaring an out of lock

condition, where N is set by this the

value in these registers, with a max

value of +3, for a total of 4. If during

the N lock checks, lock is regained,

then the lock condition is left HI, and

the counter is reset back to zero.

5

4

3

2

1

0

7

6

1

0

RW

Y

LOCK_COUNTER1

LOCK_COUNTER0

DFE_MAX_TAP2_5[3]

DFE_MAX_TAP2_5[2]

DFE_MAX_TAP2_5[1]

DFE_MAX_TAP2_5[0]

DATA_LOCK_PPM1

DATA_LOCK_PPM0

These four bits are used to set the

maximum value by which DFE taps

2-5 are able to adapt with each

subsequent adaptation. Same used

for both polarities.

35

Modifies the value of the ppm delta

tolerance from channel register

0x64:

00 - ppm_delta[7:0] =1 x

ppm_delta[7:0]

01 - ppm_delta[7:0] =1 x

ppm_delta[7:0] + ppm_delta[3:1]

10 - ppm_delta[7:0] =2 x

ppm_delta[7:0]

11 - ppm_delta[7:0] =2 x

ppm_delta[7:0] + ppm_delta[3:1]

5

4

3

2

1

0

7

6

0

1

0

RW

N

Y

N

Y

GET_PPM_ERROR

DFE_MAX_TAP1[4]

DFE_MAX_TAP1[3]

DFE_MAX_TAP1[2]

DFE_MAX_TAP1[1]

DFE_MAX_TAP1[0]

RESERVED

Get ppm error from ppm_count -

clears when done.

Normally updates continuously, but

can be manually triggered with read

value from channel register0x3B and

0x3C

Determines max tap limit for DFE

tap 1

36

HEO_VEO_INT_EN

1: Enable HEO/VEO interrupt

capability

5

4

3

2

1

0

1

0

RW

Y

N

Y

N

REF_MODE1

REF_MODE0

RESERVED

11: Normal Operation

52

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ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 12. Channel Registers, 0 to 39 (continued)

DEFAULT

VALUE

(HEX)

ADDRESS

(HEX)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

37

38

39

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

0

1

R

N

Y

CTLE_STATUS7

Feature is reserved for future use

CTLE_STATUS6

CTLE_STATUS5

CTLE_STATUS4

CTLE_STATUS3

CTLE_STATUS2

CTLE_STATUS1

CTLE_STATUS0

DFE_STATUS7

DFE_STATUS6

DFE_STATUS5

DFE_STATUS4

DFE_STATUS3

DFE_STATUS2

DFE_STATUS1

DFE_STATUS0

RESERVED

R

Feature is reserved for future use

R

RW

RESERVED

MR_EOM_RATE1

MR_EOM_RATE0

With eom_ov = 1, these bits control

the Eye Monitor Rate:

11: Use for full rate, fastest

10: Use for 1/2 Rate

All other values are reserved

4

3

2

1

0

RW

Y

RESERVED

START_INDEX[3]

START_INDEX[2]

START_INDEX[1]

START_INDEX[0]

Start index for EQ adaptation

53

DS250DF810

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Table 13. Channel Registers, 3A to A9

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

3A

3B

3C

3D

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

0

RW

R

Y

N

Y

FIXED_EQ_BST0[1]

During adaptation, if the divider

setting is >2, then a fixed EQ

setting from this register will be

used. However, if channel register

0x6F[7] is enabled, then an EQ

adaptation will be performed

instead

FIXED_EQ_BST0[0]

FIXED_EQ_BST1[1]

FIXED_EQ_BST1[0]

FIXED_EQ_BST2[1]

FIXED_EQ_BST2[0]

FIXED_EQ_BST3[1]

FIXED_EQ_BST3[0]

ppm_count[15]

ppm_count[14]

ppm_count[13]

ppm_count[12]

ppm_count[11]

ppm_count[10]

ppm_count[9]

PPM count MSB

R

ppm_count[8]

R

ppm_count[7]

PPM count LSB

R

ppm_count[6]

R

ppm_count[5]

R

ppm_count[4]

R

ppm_count[3]

R

ppm_count[2]

R

ppm_count[1]

R

ppm_count[0]

RW

EN_FIR_CURSOR

1: Enable Pre- and Post-cursor

FIR

0: Disable Pre- and Post-cursor

FIR (lower power)

6

0

RW

Y

FIR_C0_SGN

Main-cursor sign bit

0: positive

1: negative

5

4

3

2

1

0

7

6

0

1

0

1

0

1

RW

Y

RESERVED

FIR_C0[4]

RESERVED

Main-cursor magnitude

FIR_C0[3]

FIR_C0[2]

FIR_C0[1]

FIR_C0[0]

3E

FIR_PD_TX

FIR_CN1_SGN

Pre-cursor sign bit

1: negative

0: positive

5

4

3

2

1

0

RW

Y

RESERVED

FIR_CN1[3]

FIR_CN1[2]

FIR_CN1[1]

FIR_CN1[0]

RESERVED

Pre-cursor magnitude

54

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ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

3F

7

6

0

1

RW

Y

RESERVED

FIR_CP1_SGN

Post-cursor sign bit

1: negative

0: positive

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

RW

Y

RESERVED

FIR_CP1[3]

Post-cursor magnitude

FIR_CP1[2]

FIR_CP1[1]

FIR_CP1[0]

40

41

42

43

EQ_ARRAY_INDEX_0_BST0[1]

EQ_ARRAY_INDEX_0_BST0[0]

EQ_ARRAY_INDEX_0_BST1[1]

EQ_ARRAY_INDEX_0_BST1[0]

EQ_ARRAY_INDEX_0_BST2[1]

EQ_ARRAY_INDEX_0_BST2[0]

EQ_ARRAY_INDEX_0_BST3[1]

EQ_ARRAY_INDEX_0_BST3[0]

EQ_ARRAY_INDEX_1_BST0[1]

EQ_ARRAY_INDEX_1_BST0[0]

EQ_ARRAY_INDEX_1_BST1[1]

EQ_ARRAY_INDEX_1_BST1[0]

EQ_ARRAY_INDEX_1_BST2[1]

EQ_ARRAY_INDEX_1_BST2[0]

EQ_ARRAY_INDEX_1_BST3[1]

EQ_ARRAY_INDEX_1_BST3[0]

EQ_ARRAY_INDEX_2_BST0[1]

EQ_ARRAY_INDEX_2_BST0[0]

EQ_ARRAY_INDEX_2_BST1[1]

EQ_ARRAY_INDEX_2_BST1[0]

EQ_ARRAY_INDEX_2_BST2[1]

EQ_ARRAY_INDEX_2_BST2[0]

EQ_ARRAY_INDEX_2_BST3[1]

EQ_ARRAY_INDEX_2_BST3[0]

EQ_ARRAY_INDEX_3_BST0[1]

EQ_ARRAY_INDEX_3_BST0[0]

EQ_ARRAY_INDEX_3_BST1[1]

EQ_ARRAY_INDEX_3_BST1[0]

EQ_ARRAY_INDEX_3_BST2[1]

EQ_ARRAY_INDEX_3_BST2[0]

EQ_ARRAY_INDEX_3_BST3[1]

EQ_ARRAY_INDEX_3_BST3[0]

55

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Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

44

45

46

47

48

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

RW

Y

EQ_ARRAY_INDEX_4_BST0[1]

EQ_ARRAY_INDEX_4_BST0[0]

EQ_ARRAY_INDEX_4_BST1[1]

EQ_ARRAY_INDEX_4_BST1[0]

EQ_ARRAY_INDEX_4_BST2[1]

EQ_ARRAY_INDEX_4_BST2[0]

EQ_ARRAY_INDEX_4_BST3[1]

EQ_ARRAY_INDEX_4_BST3[0]

EQ_ARRAY_INDEX_5_BST0[1]

EQ_ARRAY_INDEX_5_BST0[0]

EQ_ARRAY_INDEX_5_BST1[1]

EQ_ARRAY_INDEX_5_BST1[0]

EQ_ARRAY_INDEX_5_BST2[1]

EQ_ARRAY_INDEX_5_BST2[0]

EQ_ARRAY_INDEX_5_BST3[1]

EQ_ARRAY_INDEX_5_BST3[0]

EQ_ARRAY_INDEX_6_BST0[1]

EQ_ARRAY_INDEX_6_BST0[0]

EQ_ARRAY_INDEX_6_BST1[1]

EQ_ARRAY_INDEX_6_BST1[0]

EQ_ARRAY_INDEX_6_BST2[1]

EQ_ARRAY_INDEX_6_BST2[0]

EQ_ARRAY_INDEX_6_BST3[1]

EQ_ARRAY_INDEX_6_BST3[0]

EQ_ARRAY_INDEX_7_BST0[1]

EQ_ARRAY_INDEX_7_BST0[0]

EQ_ARRAY_INDEX_7_BST1[1]

EQ_ARRAY_INDEX_7_BST1[0]

EQ_ARRAY_INDEX_7_BST2[1]

EQ_ARRAY_INDEX_7_BST2[0]

EQ_ARRAY_INDEX_7_BST3[1]

EQ_ARRAY_INDEX_7_BST3[0]

EQ_ARRAY_INDEX_8_BST0[1]

EQ_ARRAY_INDEX_8_BST0[0]

EQ_ARRAY_INDEX_8_BST1[1]

EQ_ARRAY_INDEX_8_BST1[0]

EQ_ARRAY_INDEX_8_BST2[1]

EQ_ARRAY_INDEX_8_BST2[0]

EQ_ARRAY_INDEX_8_BST3[1]

EQ_ARRAY_INDEX_8_BST3[0]

56

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ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

49

4A

4B

4C

4D

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

RW

Y

EQ_ARRAY_INDEX_9_BST0[1]

EQ_ARRAY_INDEX_9_BST0[0]

EQ_ARRAY_INDEX_9_BST1[1]

EQ_ARRAY_INDEX_9_BST1[0]

EQ_ARRAY_INDEX_9_BST2[1]

EQ_ARRAY_INDEX_9_BST2[0]

EQ_ARRAY_INDEX_9_BST3[1]

EQ_ARRAY_INDEX_9_BST3[0]

EQ_ARRAY_INDEX_10_BST0[1]

EQ_ARRAY_INDEX_10_BST0[0]

EQ_ARRAY_INDEX_10_BST1[1]

EQ_ARRAY_INDEX_10_BST1[0]

EQ_ARRAY_INDEX_10_BST2[1]

EQ_ARRAY_INDEX_10_BST2[0]

EQ_ARRAY_INDEX_10_BST3[1]

EQ_ARRAY_INDEX_10_BST3[0]

EQ_ARRAY_INDEX_11_BST0[1]

EQ_ARRAY_INDEX_11_BST0[0]

EQ_ARRAY_INDEX_11_BST1[1]

EQ_ARRAY_INDEX_11_BST1[0]

EQ_ARRAY_INDEX_11_BST2[1]

EQ_ARRAY_INDEX_11_BST2[0]

EQ_ARRAY_INDEX_11_BST3[1]

EQ_ARRAY_INDEX_11_BST3[0]

EQ_ARRAY_INDEX_12_BST0[1]

EQ_ARRAY_INDEX_12_BST0[0]

EQ_ARRAY_INDEX_12_BST1[1]

EQ_ARRAY_INDEX_12_BST1[0]

EQ_ARRAY_INDEX_12_BST2[1]

EQ_ARRAY_INDEX_12_BST2[0]

EQ_ARRAY_INDEX_12_BST3[1]

EQ_ARRAY_INDEX_12_BST3[0]

EQ_ARRAY_INDEX_13_BST0[1]

EQ_ARRAY_INDEX_13_BST0[0]

EQ_ARRAY_INDEX_13_BST1[1]

EQ_ARRAY_INDEX_13_BST1[0]

EQ_ARRAY_INDEX_13_BST2[1]

EQ_ARRAY_INDEX_13_BST2[0]

EQ_ARRAY_INDEX_13_BST3[1]

EQ_ARRAY_INDEX_13_BST3[0]

57

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Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

4E

4F

50

51

52

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

RW

Y

N

EQ_ARRAY_INDEX_14_BST0[1]

EQ_ARRAY_INDEX_14_BST0[0]

EQ_ARRAY_INDEX_14_BST1[1]

EQ_ARRAY_INDEX_14_BST1[0]

EQ_ARRAY_INDEX_14_BST2[1]

EQ_ARRAY_INDEX_14_BST2[0]

EQ_ARRAY_INDEX_14_BST3[1]

EQ_ARRAY_INDEX_14_BST3[0]

EQ_ARRAY_INDEX_15_BST0[1]

EQ_ARRAY_INDEX_15_BST0[0]

EQ_ARRAY_INDEX_15_BST1[1]

EQ_ARRAY_INDEX_15_BST1[0]

EQ_ARRAY_INDEX_15_BST2[1]

EQ_ARRAY_INDEX_15_BST2[0]

EQ_ARRAY_INDEX_15_BST3[1]

EQ_ARRAY_INDEX_15_BST3[0]

RESERVED

58

DS250DF810

www.ti.com.cn

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

53

54

55

56

57

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

RW

N

RESERVED

59

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

www.ti.com.cn

Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

58

59

5A

5B

5C

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

RW

N

RESERVED

60

DS250DF810

www.ti.com.cn

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

5D

5E

5F

60

61

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

RW

N

Y

RESERVED

GRP0_OV_CNT7

GRP0_OV_CNT6

GRP0_OV_CNT5

GRP0_OV_CNT4

GRP0_OV_CNT3

GRP0_OV_CNT2

GRP0_OV_CNT1

GRP0_OV_CNT0

CNT_DLTA_OV_0

Group 0 count LSB

Override enable for group 0

manual data rate selection

6

5

4

3

2

1

0

RW

Y

GRP0_OV_CNT14

GRP0_OV_CNT13

GRP0_OV_CNT12

GRP0_OV_CNT11

GRP0_OV_CNT10

GRP0_OV_CNT9

GRP0_OV_CNT8

Group 0 count MSB

61

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

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Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

Group 1 count LSB

62

7

6

5

4

3

2

1

0

7

0

RW

Y

GRP1_OV_CNT7

GRP1_OV_CNT6

GRP1_OV_CNT5

GRP1_OV_CNT4

GRP1_OV_CNT3

GRP1_OV_CNT2

GRP1_OV_CNT1

GRP1_OV_CNT0

CNT_DLTA_OV_1

63

Override enable for group 1

manual data rate selection

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

RW

Y

N

GRP1_OV_CNT14

GRP1_OV_CNT13

GRP1_OV_CNT12

GRP1_OV_CNT11

GRP1_OV_CNT10

GRP1_OV_CNT9

GRP1_OV_CNT8

GRP0_OV_DLTA3

GRP0_OV_DLTA2

GRP0_OV_DLTA1

GRP0_OV_DLTA0

GRP1_OV_DLTA3

GRP1_OV_DLTA2

GRP1_OV_DLTA1

GRP1_OV_DLTA0

RESERVED

Group 1 count MSB

64

65

66

Sets the PPM delta tolerance for

the PPM counter lock check for

group 0. Must also program

channel register 0x67[7].

Sets the PPM delta tolerance for

the PPM counter lock check for

group 1. Must also program

channel register 0x67[6].

RESERVED

62

DS250DF810

www.ti.com.cn

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

67

7

6

5

0

1

RW

Y

GRP0_OV_DLTA[4]

GRP1_OV_DLTA[4]

HV_LOCKMON_EN

1: Enable periodic monitoring of

HEO/VEO for lock qualification.

0: Disable periodic HEO/VEO

monitoring for lock qualification.

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

RW

N

Y

RESERVED

VEO_LCK_THRSH3

VEO_LCK_THRSH2

VEO_LCK_THRSH1

VEO_LCK_THRSH0

HEO_LCK_THRSH3

HEO_LCK_THRSH2

HEO_LCK_THRSH1

HEO_LCK_THRSH0

RESERVED

FOM_A6

RESERVED

68

69

6A

6B

VEO threshold to meet before lock

is established. The LSB step size

is 4 counts of VEO.

HEO threshold to meet before lock

is established. The LSB step size

is 4 counts of VEO.

RESERVED

Alternate Figure of Merit variable

A. Max value for this register is

128.

FOM_A5

FOM_A4

FOM_A3

FOM_A2

FOM_A1

FOM_A0

63

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

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Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

6C

6D

6E

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

0

RW

Y

FOM_B7

FOM_B6

FOM_B5

FOM_B4

FOM_B3

FOM_B2

FOM_B1

FOM_B0

FOM_C7

FOM_C6

FOM_C5

FOM_C4

FOM_C3

FOM_C2

FOM_C1

FOM_C0

HEO adjustment for Alternate

FoM, variable B

VEO adjustment for Alternate

FoM, variable C

EN_NEW_FOM_CTLE

1: CTLE adaption state machine

will use the alternate FoM

HEO_ALT = (HEO-

B)*A*2VEO_ALT = (VEO-C)*(1-

A)*2

The values of A,B,C are set in

channel register 0x6B, 0x6C, and

0x6D.

The value of A is equal to the

register value divided by 128.

The Alternate FoM = (HEOB)*A*2

+ (VEO-C)*(1-A)*2

6

0

RW

Y

EN_NEW_FOM_DFE

1: DFE adaption state machine will

use the alternate FoM.

HEO_ALT = (HEO-

B)*A*2VEO_ALT = (VEO-C)*(1-

A)*2

The values of A,B,C are set in

channel register 0x6B, 0x6C, and

0x6D.

The value of A is equal to the

register value divided by 128

The Alternate FoM = (HEOB)*A*2

+ (VEO-C)*(1-A)*2

5

4

3

2

1

0

RW

N

RESERVED

64

DS250DF810

www.ti.com.cn

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

6F

7

0

RW

Y

MR_EN_LOW_DIVSEL_EQ

Normally, during adaptation, if the

divider setting is >2, then a fixed

EQ setting, from Reg_0x3A will be

used. However, if Reg_0x6F[7]=1,

then an EQ adaptation will be

performed instead.

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

0

1

0

1

0

RW

R

Y

N

Y

N

RESERVED

EQ_LB_CNT[3]

EQ_LB_CNT[2]

EQ_LB_CNT[1]

EQ_LB_CNT[0]

PRBS_INT

RESERVED

70

CTLE look-beyond count for

adaptation

71

When enabled by Reg_0x31[7],

goes HI if a PRBS stream is

detected. Clears on reading.

PRBS checker must be enabled

with Reg_0x30[3].

Once cleared, if a PRBS error

occurs, then the interrupt will again

go HI. Clears on reading.

If signal detect is lost, this is

considered a PRBS error, and the

interrupt will go HI. Clears on

reading.

6

5

4

3

2

1

0

7

6

5

4

0

R

N

RESERVED

DFE_POL_1_OBS

DFE_WT1_OBS[4]

DFE_WT1_OBS[3]

DFE_WT1_OBS[2]

DFE_WT1_OBS[1]

DFE_WT1_OBS[0]

RESERVED

DFE tap 1 polarity observation

DFE tap 1 weight observation

72

RESERVED

DFE_POL_2_OBS

Primary observation point for DFE

tap 2 polarity

3

2

1

0

R

N

DFE_WT2_OBS3

DFE_WT2_OBS2

DFE_WT2_OBS1

DFE_WT2_OBS0

Primary observation point for DFE

tap 2 weight

65

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

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Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

RESERVED

73

74

75

7

6

5

4

0

R

N

RESERVED

DFE_POL_3_OBS

Primary observation point for DFE

tap 3 polarity

3

2

1

0

7

6

5

4

0

R

N

DFE_WT3_OBS3

DFE_WT3_OBS2

DFE_WT3_OBS1

DFE_WT3_OBS0

RESERVED

Primary observation point for DFE

tap 3 weight

RESERVED

DFE_POL_4_OBS

Primary observation point for DFE

tap 4 polarity

3

2

1

0

7

6

5

4

0

R

N

DFE_WT4_OBS3

DFE_WT4_OBS2

DFE_WT4_OBS1

DFE_WT4_OBS0

RESERVED

Primary observation point for DFE

tap 4 weight

RESERVED

DFE_POL_5_OBS

Primary observation point for DFE

tap 5 polarity

3

2

1

0

7

6

5

4

3

2

1

0

7

0

1

0

1

0

R

N

Y

N

DFE_WT5_OBS3

Primary observation point for DFE

tap 5 weight

R

DFE_WT5_OBS2

R

DFE_WT5_OBS1

R

DFE_WT5_OBS0

76

RW

post_lock_veo_thr[3]

post_lock_veo_thr[2]

post_lock_veo_thr[1]

post_lock_veo_thr[0]

post_lock_heo_thr[3]

post_lock_heo_thr[2]

post_lock_heo_thr[1]

post_lock_heo_thr[0]

PRBS_GEN_POL_EN

VEO threshold after LOCK is

established

HEO threshold after LOCK is

established

77

1: Force polarity inversion on

generated PRBS data

6

5

4

3

2

1

0

1

0

1

0

RW

Y

N

RESERVED

66

DS250DF810

www.ti.com.cn

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

78

7

6

5

0

R

N

RESERVED

SD_STATUS

Primary observation point forsignal

detect status

4

3

0

R

N

CDR_LOCK_STATUS

CDR_LOCK_INT

Primary observation point forCDR

lock status

Requires that channel register

0x79[1] be set.

1: Indicates CDR has achieved

lock, lock goes from LOW to

HIGH. This bit is cleared after

reading. This bit will stay set until it

has been cleared by reading.

2

0

R

N

SD_INT

Requires that channel register

0x79[0] be set.

1: Indicates signal detect status

has changed. This will trigger

when signal detect goes from

LOW to HIGH or HIGH to LOW.

This bit is cleared after reading.

This bit will stay set until it has

been cleared by reading.

1

0

R

N

EOM_VRANGE_LIMIT_ERROR

HEO_VEO_INT

Goes high if GET_HEO_VEO

indicates high during adaptation

Requires that channel register

0x36[6] be set.

1: Indicates that HEO/VEO

dropped below the limits set in

channel register 0x76 This bit is

cleared after reading. This bit will

stay set until it has been cleared

by reading.

79

7

6

0

RW

N

RESERVED

PRBS_CHKR_EN

1: Enable the PRBS checker.

0: Disable the PRBS checker

5

4

0

1

RW

N

PRBS_GEN_EN

1: Enable the pattern generator

0: Disable the pattern generator

PRBS_LCKUP_EXIT_EN

0: Turn off lock up detection in

PRBS checker/generator

Used for debug purposes only.

3

2

1

0

RW

N

Y

RESERVED

CDR_LOCK_INT_EN

1: Enable CDR lock interrupt,

observable in channel register

0x78[3]

0: Disable CDR lock interrupt

0

RW

Y

SD_INT_EN

1: Enable signal detect interrupt,

observable in channel register

0x78[3]

0: Disable signal detect interrupt

67

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

www.ti.com.cn

Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

7A

7B

7C

7D

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

0

RW

R

N

Y

RESERVED

PRBS_FIXED7

PRBS_FIXED6

PRBS_FIXED5

PRBS_FIXED4

PRBS_FIXED3

PRBS_FIXED2

PRBS_FIXED1

PRBS_FIXED0

Pattern generator user defined

pattern LSB. MSB located at

channel register 0x97.

R

RW

CONT_ADAPT_HEO_CHNG_THR Limit for HEO change before

S3

triggering a DFE adaption while

continuous DFE adaption is

enabled.

6

5

4

3

2

1

0

1

0

1

0

RW

Y

CONT_ADAPT_HEO_CHNG_THR

S2

CONT_ADAPT_HEO_CHNG_THR

S1

CONT_ADAPT_HEO_CHNG_THR

S0

CONT_ADAPT_VEO_CHNG_THR Limit for VEO change before

S3

triggering a DFE adaption while

continuous DFE adaption is

enabled

CONT_ADAPT_VEO_CHNG_THR

S2

CONT_ADAPT_VEO_CHNG_THR

S1

CONT_ADAPT_VEO_CHNG_THR

S0

68

DS250DF810

www.ti.com.cn

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

7E

7

6

5

4

3

0

1

0

RW

Y

CONT_ADPT_TAP_INCR3

CONT_ADPT_TAP_INCR2

CONT_ADPT_TAP_INCR1

CONT_ADPT_TAP_INCR0

Limit for allowable tap increase

from the previous base point

CONT_ADPT_FOM_CHNG_THRS Bits define by how much the FOM

3

can change before triggering DFE

adapt

2

1

0

7

0

1

0

RW

Y

N

CONT_ADPT_FOM_CHNG_THRS

2

CONT_ADPT_FOM_CHNG_THRS

1

CONT_ADPT_FOM_CHNG_THRS

0

7F

EN_OBS_ALT_FOM

1: Allows for alternate FoM

7Fcalculation to be shown in

channel registers 0x27, 0x28 and

0x29 instead of HEO and VEO

6

5

0

1

RW

N

Y

RESERVED

DIS_HV_CHK_FOR_CONT_ADAP 1: Ignore HEO/VEO lock condition

T

checks during continuous

adaption. Normal operation for

continuous DFE adaption

4

3

0

1

RW

Y

EN_DFE_CONT_ADAPT

1: Continuous DFE adaption is

enabled

0: DFE adapts only during lock

and then freezes

CONT_ADPT_CMP_BOTH

1: If continuous DFE adaption is

enabled, a DFE adaption will

trigger if either HEO orVEO

degrades

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

RW

R

Y

N

CONT_ADPT_COUNT2

CONT_ADPT_COUNT1

CONT_ADPT_COUNT0

RESERVED

Limit for number of weights the

DFE can look ahead in continuous

adaption

80

R

RESERVED

R

RESERVED

R

RESERVED

R

RESERVED

R

RESERVED

R

RESERVED

R

RESERVED

81

R

RESERVED

R

RESERVED

R

RESERVED

R

RESERVED

R

RESERVED

R

RESERVED

R

RESERVED

R

RESERVED

69

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

www.ti.com.cn

Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

82

7

0

RW

N

FREEZE_PRBS_CNTR

1: Freeze the PRBS error count to

allow for readback.

0: Normal operation. Error

counters is allowed to increment if

the PRBS checker is properly

configured

6

5

0

RW

N

RST_PRBS_CNTS

PRBS_PATT_OV

1: Reset the PRBS error counter.

0: Normal operation. Error counter

is released from reset.

1: Override PRBS pattern auto-

detection. Forces the pattern

checker to only lock onto the

pattern defined in Reg_0x82[4:2].

0: Normal operation. Pattern

checker will automatically detect

the PRBS pattern

4

3

2

0

RW

N

PRBS_PATT[2]

PRBS_PATT[1]

PRBS_PATT[0]

Used with the PRBS checker.

Usage is enabled with

Reg_0x82[5]. Select PRBS pattern

to be checked:

000 - PRBS7

001 - PRBS9

010 - PRBS11

011 - PRBS15

100 - PRBS23

101 - PRBS31

110 - PRBS58

111 - PRBS63

1

0

RW

N

PRBS_POL_OV

1: Override PRBS pattern auto

polarity detection. Forces the

pattern checker to only lock onto

the polarity defined in bit 0 of this

register.

0: Normal operation, pattern

checker will automatically detect

the PRBS pattern polarity

PRBS_POL

Usage is enabled with

Reg_0x82[1]=1

0: Forced polarity = true

1: Forced polarity = inverted

83

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

R

N

RESERVED

PRBS_ERR_CNT[10]

PRBS_ERR_CNT[9]

PRBS_ERR_CNT[8]

PRBS_ERR_CNT7

PRBS_ERR_CNT6

PRBS_ERR_CNT5

PRBS_ERR_CNT4

PRBS_ERR_CNT3

PRBS_ERR_CNT2

PRBS_ERR_CNT1

PRBS_ERR_CNT0

PRBS checker error count

84

70

DS250DF810

www.ti.com.cn

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

85

86

87

88

89

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

R

N

RESERVED

71

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

www.ti.com.cn

Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

8A

8B

8C

8D

8E

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

R

N

Y

RESERVED

R

RESERVED

R

RESERVED

R

RESERVED

R

RESERVED

R

RESERVED

R

RESERVED

R

RESERVED

RW

RESERVED

UNCORR_ERR_PATT7

UNCORR_ERR_PATT6

UNCORR_ERR_PATT5

UNCORR_ERR_PATT4

UNCORR_ERR_PATT3

UNCORR_ERR_PATT2

UNCORR_ERR_PATT1

UNCORR_ERR_PATT0

RESERVED

Used in conjunction with register

0x78[7]. This register, register

0x8B and register 0x8C set a 16-

bit pattern that is searched for

within the data stream. If this

pattern is found, the interrupt in

register 0x78[7] is set HI.

RESERVED

VGA_SEL_GAIN[0]

VGA selection bit (1: on, 0: off)

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Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

8F

90

91

7

6

0

1

R

N

Y

EQ_BST_TO_ANA7

Primary observation point for the

EQ boost setting.

R

EQ_BST_TO_ANA6

EQ_BST_TO_ANA5

EQ_BST_TO_ANA4

EQ_BST_TO_ANA3

EQ_BST_TO_ANA2

EQ_BST_TO_ANA1

EQ_BST_TO_ANA0

RESERVED

5

R

4

R

3

R

2

R

1

R

0

R

7

RW

6

RESERVED

5

RESERVED

4

RESERVED

3

RESERVED

2

RESERVED

1

RESERVED

0

RESERVED

7

RESERVED

6

RESERVED

5

RESERVED

4

RESERVED

3

RESERVED

2

RESERVED

1

RESERVED

0

RESERVED

92

93

94

95

96

7:0

7

RESERVED

6

RESERVED

5

RESERVED

4

RESERVED

3

EQ_EN_LOCAL

1: Enable the ebuf for the local

output. Can be set independently

of other controls.

2

1

0

RW

Y

EQ_EN_FANOUT

EQ_SEL_XPNT

XPNT_SLAVE

1: Enable the ebuf for the fanout.

Can be set independently of other

controls.

1: Indicates to a channel where it

is getting its data from. 0 indicates

local. 1-indicates from the cross.

1: Indicates to a channel if it needs

to wait for the other channel to

complete its lock/adaptation. The

need for this condition comes up

when input of one channel is

routed to the other channel or

multiple channels.

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Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

97

7

6

5

4

3

2

1

0

7:6

5:0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

R

N

Y

N

Y

PRBS_FIXED15

Pattern generator user defined

pattern MSB. LSB located at

channel register 0x7C.

R

PRBS_FIXED14

PRBS_FIXED13

PRBS_FIXED12

PRBS_FIXED11

PRBS_FIXED10

PRBS_FIXED9

PRBS_FIXED8

RESERVED

R

98

99

RW

9A

9B

9C

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Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

DESCRIPTION

9D

7

6

1

0

1

0

1

0

1

0

1

0

1

0

1

RW

R

N

Y

N

Y

N

Y

RESERVED

5

RESERVED

4

RESERVED

3

RESERVED

2

RESERVED

1

RESERVED

0

RESERVED

9E

7

cp_en_idac_pd[2]

cp_en_idac_pd[1]

cp_en_idac_pd[0]

cp_en_idac_fd[2]

cp_en_idac_fd[1]

cp_en_idac_fd[0]

RESERVED

Phase detector charge pump

setting, when override is enabled.

See reg_0C for other bits.

6

5

4

Frequency detector charge pump

setting, when override is enabled.

See reg_0C for other bits.

3

2

1

0

RESERVED

9F

A0

A1

A2

A3

A4

A5

7:0

7

NOT USED

R

NOT USED

R

NOT USED

R

NOT USED

R

NOT USED

R

NOT USED

RW

PFD_SEL_DATA_PSTLCK[2]

PFD_SEL_DATA_PSTLCK[1]

PFD_SEL_DATA_PSTLCK[0]

Post-lock PFD mux select

111 - Mute

110 - N/A

101 - 10M Clock

100 - PRBS Generator or Fixed

Pattern Generator Data

011 - N/A

6

5

010 - N/A

000 - Raw Data

4

3

2

1

0

RW

N

RESERVED

75

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Table 13. Channel Registers, 3A to A9 (continued)

DEFAULT

VALUE

(Hex)

ADDRESS

(Hex)

BITS

MODE

EEPROM

FIELD NAME

INCR_HIST_TMR

DESCRIPTION

A6

7

0

RW

N

Provides an option to increase

EOM timer given by 0x2A[7:4] for

histogram collection by +8 for

selection values < 8

6

1

RW

Y

EOM_TMR_ABRT_ON_HIT

Enables faster scan through the

eye-matrix by moving on to the

next matrix point as soon as hit is

observed

Note: This bit does not affect when

slope measurement are in

progress

5

0

RW

Y

SLP_MIN_REQ_HITS[1]

Minimum required hit count for

registering a hit during slope

measurements.

4

3

0

RW

Y

SLP_MIN_REQ_HITS[0]

LFT_SLP

0: allows slope measurement for

the right side of the eye

1: allows slope measurement for

the left side of the eye

2

0

RW

Y

TOP_SLP

0: allows slope measurement for

the bottom side of the eye

1: allows slope measurement for

the top side of the eye

1

0

1

RW

Y

DFE_BATHTUB_FOM

CTLE_BATHTUB_FOM

Enables slope-based bathtub FoM

for DFE adaptation

Enables slope-based bathtub FoM

for CTLE adaptation

A7

A8

A9

7:0

0

R

N

Y

RESERVED

RW

76

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ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

10 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The DS250DF810 is a high-speed retimer which extends the reach of differential channels and cleans jitter and

other signal impairments in the process. It can be deployed in a variety of different systems from backplanes to

front ports to active cable assemblies. The following sections outline typical applications and their associated

design considerations.

10.2 Typical Application

The DS250DF810 is typically used in the following main application scenarios:

1. Backplane and mid-plane reach extension

2. Front-port jitter cleaning / retiming for optical applications

图 15. Typical Uses for the DS250DF810 in a System

77

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www.ti.com.cn

Typical Application (接下页)

10.2.1 Backplane and Mid-Plane Applications

The DS250DF810 has strong equalization capabilities that allow it to recover data over channels up to 35 dB

insertion loss. As a result, the optimum placement for the DS250DF810 in a backplane/mid-plane application is

with the higher-loss channel segment at the input and the lower-loss channel segment at the output. This

reduces the equalization burden on the downstream ASIC/FPGA, as the DS250DF810 is equalizing a majority of

the overall channel. This type of asymmetric placement is not a requirement, but when an asymmetric placement

is required due to the presence of a passive backplane or mid-plane, then this becomes the recommended

placement.

图 16. Backplane/Mid-plane Application Block Diagram

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Typical Application (接下页)

Retimer

No AC coupling

capacitors needed

No AC coupling

capacitors needed

RX0P

RX0N

TX0P

TX0N

.

RX1P

RX1N

TX1P

TX1N

TX6P

TX6N

RX6P

RX6N

RX7P

RX7N

TX7P

TX7N

2.5 V or 3.3 V

VDD

To other

open-drain

interrupt pins

SMBus

Slave mode

1 kΩ

INT_N

SDA

To

system

SMBus⁽¹⁾

EN_SMB

TEST

SDC

25 MHz

Address

straps

(pull-up, pull-

down, or float)

ADDR0

ADDR1

CAL_CLK_IN

READ_EN_N

CAL_CLK_OUT

SMBus Slave

mode

Float for SMBus

Slave mode

ALL_DONE_N

GND

2.5 V

VDD

Minimum

recommended

decoupling

1 ꢀF

(2x)

0.1 ꢀF

(4x)

Backplane /

Mid-plane

Connector

ASIC / FPGA

Retimer

No AC coupling

capacitors needed

No AC coupling

capacitors needed

RX0P

RX0N

TX0P

TX0N

.

RX1P

RX1N

TX1P

TX1N

RX6P

RX6N

TX6P

TX6N

RX7P

RX7N

TX7P

TX7N

VDD

INT_N

SMBus

Slave mode

1 kΩ

SDA

SDC

EN_SMB

TEST

ADDR0

ADDR1

Address straps

(pull-up, pull-

down, or float)

CAL_CLK_IN

READ_EN_N

CAL_CLK_OUT

SMBus Slave

mode

ALL_DONE_N

GND

2.5 V

VDD

Minimum

recommended

decoupling

1 ꢀF

(2x)

0.1 ꢀF

(4x)

(1) SMBus signals need to be pulled up elsewhere in the system.

图 17. Backplane/Mid-plane Application Schematic

10.2.2 Design Requirements

For this design example, the following guidelines outlined in 表 14 apply.

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Typical Application (接下页)

表 14. Backplane/Mid-plane Application Design Guidelines

DESIGN PARAMETER

REQUIREMENT

Not required. AC coupling capacitors are included in the device

package.

AC coupling capacitors

Input channel insertion loss

Output channel insertion loss

≤ 35 dB at 25.78125 Gbps Nyquist frequency

Depends on downstream ASIC / FPGA capabilities. The

DS250DF810 has a low-jitter output driver with 3-tap FIR filter for

equalizing a portion of the output channel.

Link partner TX launch amplitude

Link partner TX FIR filter

800 mVppd to 1200 mVppd

Depends on channel loss

10.2.3 Detailed Design Procedure

The design procedure for backplane/mid-plane applications is as follows:

1. Determine the total number of channels on the board which require a DS250DF810 for signal conditioning.

This will dictate the total number of DS250DF810 devices required for the board. It is generally

recommended that channels with similar total insertion loss on the board be grouped together in the same

DS250DF810 device. This will simplify the device settings, as similar loss channels generally utilize similar

settings.

2. Determine the maximum current draw required for all DS250DF810 retimers. This may impact the selection

of the regulator for the 2.5 V supply rail. To calculate the maximum current draw, multiply the maximum

transient power supply current by the total number of DS250DF810 devices.

3. Determine the maximum operational power consumption for the purpose of thermal analysis. There are two

ways to approach this calculation:

a. Maximum mission-mode operational power consumption is when all channels are locked and

retransmitting the data which is received. PRBS pattern checkers/generators are not used in this mode

since normal traffic cannot be checked with a PRBS checker. For this calculation, multiply the worst-case

power consumption in mission mode by the total number of DS250DF810 devices.

b. Maximum debug-mode operational power consumption is when all channels are locked and

retransmitting the data which is received. At the same time, some channels’ PRBS checkers or

generators may be enabled. For this calculation, multiply the worst-case power consumption in debug

mode by the total number of DS250DF810 devices.

4. Determine the SMBus address scheme needed to uniquely address each DS250DF810 device on the board,

depending on the total number of devices identified in step 2. Each DS250DF810 can be strapped with one

of 16 unique SMBus addresses. If there are more DS250DF810 devices on the board than the number of

unique SMBus addresses which can be assigned, then use an I2C expander like the TCA/PCA family of

I2C/SMBus switches and multiplexers to split up the SMBus into multiple busses.

5. Determine if the device will be configured from EEPROM (SMBus Master Mode) or from the system I2C bus

(SMBus Slave Mode).

a. If SMBus Master Mode will be used, provisions should be made for an EEPROM on the board with 8-bit

SMBus address 0xA0.

b. If SMBus Slave Mode will be used for all device configurations, an EEPROM is not needed.

6. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD

supply and GND. Refer to the pin function description in Pin Configuration and Functions for more details.

7. Make provisions in the schematic and layout for a 25MHz (±100 ppm) single-ended CMOS clock. Each

DS250DF810 retimer buffers the clock on the CAL_CLK_IN pin and presents the buffered clock on the

CAL_CLK_OUT pin. This allows multiple (up to 20) retimers’ calibration clocks to be daisy chained to avoid

the need for multiple oscillators on the board. If the oscillator used on the board has a 2.5 V CMOS output,

then no AC coupling capacitor or resistor ladder is required at the input to CAL_CLK_IN. No AC coupling or

resistor ladder is needed between one retimer’s CAL_CLK_OUT output and the next retimer’s CAL_CLK_IN

input. The final retimer’s CAL_CLK_OUT output can be left floating.

8. Connect the INT_N open-drain output to an FPGA or CPU if interrupt monitoring is desired. Note that

multiple retimers’ INT_N outputs can be connected together since this is an open-drain output. The common

INT_N net should be pulled high.

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10.2.4 Application Curves

图 18. DS250DF810 Operating at 25.78125 Gbps

图 19. DS250DF810 FIR Transmit Equalization while

Operating at 25.78125 Gbps

图 18 shows a typical output eye diagram for the DS250DF810 operating at 25.78125 Gbps with PRBS9 pattern

using FIR main-cursor of +18, pre-cursor of -1 and post-cursor of +2. All other device settings are left at default.

图 19 shows an example of DS250DF810 FIR transmit equalization while operating at 25.78125 Gbps. In this

example, the Tx FIR filter main-cursor is set to +15, post-cursor to -3 and pre-cursor to -3. An 8T pattern is used

to evaluate the FIR filter, which consists of 0xFF00. All other device settings are left at default.

81

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11 Power Supply Recommendations

Follow these general guidelines when designing the power supply:

1. The power supply should be designed to provide the recommended operating conditions outlined in

Specifications in terms of DC voltage, AC noise, and start-up ramp time.

2. The maximum current draw for the DS250DF810 is provided in Specifications . This figure can be used to

calculate the maximum current the supply must provide. Typical mission-mode current draw can be inferred

from the typical power consumption in Specifications.

3. The DS250DF810 does not require any special power supply filtering (that is, ferrite bead), provided the

recommended operating conditions are met. Only standard supply decoupling is required. Refer to Pin

Configuration and Functions for details concerning the recommended supply decoupling.

12 Layout

12.1 Layout Guidelines

The following guidelines should be followed when designing the layout:

1. Decoupling capacitors should be placed as close to the VDD pins as possible. Placing them directly

underneath the device is one option if the board design permits.

2. High-speed differential signals TXnP/TXnN and RXnP/RXnN should be tightly coupled, skew matched, and

impedance controlled.

3. Vias should be avoided when possible on the high-speed differential signals. When vias must be used, care

should be taken to minimize the via stub, either by transitioning through most/all layers, or by back drilling.

4. GND relief can be used beneath the high-speed differential signal pads to improve signal integrity by

counteracting the pad capacitance.

5. GND vias should be placed directly beneath the device connecting the GND plane attached to the device to

the GND planes on other layers. This has the added benefit of improving thermal conductivity from the

device to the board

6. BGA landing pads for a 0.8 mm pitch flip-chip BGA are typically 0.4 mm in diameter (exposed). The actual

size of the copper pad will depend on whether solder-mask-defined (SMD) or non-solder-mask-defined

solder land pads are used. For more information, refer to TI’s Surface Mount Technology (SMT) References

at http://focus.ti.com/quality/docs under the "Quality & Lead (Pb)-Free Data" menu.

7. If vias are used for the high-speed signals, ground via should be implemented adjacent to the signal via to

provide return path and isolation. For differential pair, the typical via configuration is "ground-signal-signal-

ground".

12.2 Layout Example

The following example layout demonstrates how all signals can be escaped from the BGA array using stripline

routing on a generic 28-layer stackup. This example layout assumes the following:

•

Trace width: 0.127 mm (5 mil)

Trace edge-to-edge spacing: 0.152 mm (6 mil)

VIA finished hole size (diameter): 0.203 mm (8 mil)

VIA drilled hole size: 0.254 mm (10 mil)

VIA-to-VIA spacing: 1.0 mm (39 mil), to enhance PCB manufacturability

No VIA-in-pad used

Note that many other escape routing options exist using different trace width and spacing combinations. The

optimum trace width and spacing will depend on the PCB material, PCB routing density, and other factors.

82

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ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

Layout Example (接下页)

图 21. Internal Signal layer 1

图 20. Top Layer

图 23. Bottom Layer

图 22. Internal Signal Layer 2

83

DS250DF810

ZHCSKE9C –DECEMBER 2015–REVISED OCTOBER 2019

www.ti.com.cn

13 器件和文档支持

13.1 器件支持

13.1.1 开发支持

更多相关信息，请参阅 TI 表面贴装技术 (SMT) 参考资料（位于

http://focus.ti.com/quality/docs 页面的“质量和无铅 (Pb) 数据”菜单下）。

13.2 文档支持

13.2.1 相关文档

请参阅如下相关文档：

•

《DS2x0DF810、DS250DFx10、DS250DF230 编程人员指南》 (SNLU182)

单击此处，请求访问 DS250DF810 MySecure 文件夹中的 DS2X0DFX10 IBIS-AMI 模型和编程人员指南。

13.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

13.4 支持资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.5 商标

E2E is a trademark of Texas Instruments.

13.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

13.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

84

PACKAGE OUTLINE

ABV0135A

FCBGA - 2.51 mm max height

SCALE 1.300

BALL GRID ARRAY

13.2

12.9

B

A

(11)

BALL A1 CORNER

2X (1)

8.2

7.9

(6)

2X (2.8)

2X (2.6)

(0.5)

C

2.51 MAX

(0.58)

SEATING PLANE

0.2 C

BALL TYP

0.405

TYP

0.325

11.2 TYP

SYMM

(0.9) TYP

J

H

G

F

(0.8) TYP

SYMM

135X

6.4

E

D

C

TYP

0.51

0.41

0.2

C A

C

B

A

0.08

0.8 TYP

1

2

3

4

5

6

8

9

10 11 12 13 14 15

7

0.8 TYP

BALL A1 CORNER

4221740/B 02/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

ABV0135A

FCBGA - 2.51 mm max height

BALL GRID ARRAY

(0.8) TYP

135X ( 0.4)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

A

B

C

(0.8) TYP

D

SYMM

E

F

G

H

J

SYMM

LAND PATTERN EXAMPLE

SCALE:8X

(

0.4)

0.05 MAX

0.05 MIN

(

0.4)

SOLDER MASK

OPENING

METAL

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4221740/B 02/2016

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).

www.ti.com

EXAMPLE STENCIL DESIGN

ABV0135A

FCBGA - 2.51 mm max height

BALL GRID ARRAY

(

0.4) TYP

(0.8) TYP

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

A

B

C

(0.8) TYP

D

SYMM

E

F

G

H

J

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL

SCALE:8X

4221740/B 02/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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型号：	DS250DF810ABVT
厂家：	TEXAS INSTRUMENTS
描述：	25Gbps 多速率 8 通道重定时器 \| ABV \| 135 \| -10 to 85
文件：	总92页 (文件大小：2097K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS250DF810ABVT [TI]

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