DS16EV5110A [TI]
DS16EV5110A Video Equalizer (3DC) for DVI, HDMI Source/Repeater/Sink Applications; DS16EV5110A视频均衡器（ 3DC ）为DVI ， HDMI源/中继器/接收器应用
| 型号： | DS16EV5110A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DS16EV5110A Video Equalizer (3DC) for DVI, HDMI Source/Repeater/Sink Applications |
| 文件： | 总22页 (文件大小：1932K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS16EV5110A
DS16EV5110A Video Equalizer (3D+C) for DVI, HDMI Source/Repeater/Sink
Applications
Literature Number: SNLS301B
April 6, 2009
DS16EV5110A
Video Equalizer (3D+C) for DVI, HDMI Source/Repeater/
Sink Applications
General Description
Features
The DS16EV5110A is a multi-channel equalizer optimized for
video cable extension Source/Repeater/Sink Applications. It
operates between 250Mbps and 2.25Gbps with common ap-
plications at 1.65Gbps and 2.25Gbps (per data channel). It
contains three Transition-Minimized Differential Signaling
(TMDS) data channels and one clock channel as specified for
DVI and HDMI interfaces. It provides compensation for skin-
effect and dielectric losses, a common phenomenon when
transmitting video on commercially available high definition
video cables.
8 levels of equalization settable by 3 pins or through the
■
SMBus interface
DC-Coupled inputs and outputs
■
■
Optimized for operation from 250 Mbps to 2.25 Gbps in
support of UXGA, 480 I/P, 720 I/P, 1080 I, and 1080 P with
8, 10, and 12–bit Color Depth Resolutions
Two DS16EV5110A devices support DVI/HDMI Dual Link
■
■
■
■
DVI 1.0, and HDMI 1.3a Compatible TMDS Interface
Clock channel signal detect (LOS)
Enable for power savings standby mode
The inputs conform to DVI and HDMI requirements and fea-
tures programmable levels of input equalization. The pro-
grammable levels of equalization provide optimal signal boost
and reduces inter-symbol interference. Eight levels of boost
are selectable via a pin interface or by the optional System
Management Bus.
System Management Bus (SMBus) provides control of
boost, output amplitude, enable, and clock channel signal
detect threshold
■
Low power consumption: 475mW (Typical)
■
■
■
■
■
■
0.13 UI total jitter at 1.65 Gbps including cable
The clock channel is optimized for clock rates of up to 225
MHz and features a signal detect circuit. To maximize noise
immunity, the DS16EV5110A features a signal detector with
programmable thresholds. The threshold is adjustable
through a System Management Bus (SMBus) interface.
Single 3.3V power supply
Small 7mm x 7mm, 48-pin leadless LLP package
-40°C to +85°C operating temperature range
Extends TMDS cable reach over:
The DS16EV5110A may be used in Source Applications, Sink
Applications, or as a Repeater.
1. > 40 meters 24 AWG DVI Cable (1.65Gbps)
2. > 20 meters 28 AWG DVI Cable (1.65Gbps)
3. > 20 meters Cat5/Cat5e/Cat6 cables (1.65Gbps)
4. > 20 meters 28 AWG HDMI cables (2.25Gbps)
The DS16EV5110A also provides support for system power
management via output enable controls. Additional controls
are provided via the SMBus enabling customization and op-
timization for specific applications requirements. These con-
trols include programmable features such as output ampli-
tude and boost controls as well as system level diagnostics.
Applications
HDMI / DVI Cable Extenders
■
■
■
■
The DS16EV5110A is a pin-for-pin replacement to the
DS16EV5110. It features an enhanced CML output that
presents a high impedance when powered down.
HDMI / DVI Switches
Projectors
High Definition Displays
Typical Application
30064653
© 2009 National Semiconductor Corporation
300646
www.national.com
Pin Descriptions
Pin Name Pin Number I/O, Type
HIGH SPEED DIFFERENTIAL I/O
Description
C_IN−
C_IN+
1
2
I, CML
I, CML
I, CML
I, CML
O, CML
O, CML
O, CML
O, CML
Inverting and non-inverting TMDS Clock inputs to the equalizer. An on-chip 50Ω terminating
resistor connects C_IN+ to VDD and C_IN- to VDD.
D_IN0−
D_IN0+
4
5
Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating
resistor connects D_IN0+ to VDD and D_IN0- to VDD.
D_IN1−
D_IN1+
8
9
Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating
resistor connects D_IN1+ to VDD and D_IN1- to VDD.
D_IN2−
D_IN2+
11
12
Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating
resistor connects D_IN2+ to VDD and D_IN2- to VDD.
C_OUT-
C_OUT+
36
35
Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
D_OUT0−
D_OUT0+
33
32
D_OUT1–
D_OUT1+
29
28
D_OUT2−
D_OUT2+
26
25
Equalization Control
BST_0
BST_1
BST_2
23
14
37
I, LVCMOS BST_0, BST_1, and BST_2 select the equalizer boost level for EQ channels. BST_0,
BST_1, and BST_2 are internally pulled Low. See Table 2.
Device Control
EN
44
21
45
I, LVCMOS Enable Equalizer input. When held High, normal operation is selected. When held Low,
standby mode is selected. EN is internally pulled High. Signal is global to all Data and Clock
channels.
FEB
I, LVCMOS Force External Boost. When held High, the equalizer boost setting is controlled by the BST_
[0:2] pins. When held Low, the equalizer boost level is controlled through the SMBus (see
Table 1) control pins. FEB is internally pulled High.
SD
O, LVCMOS Equalizer Clock Channel Signal Detect Output. Produces a High when signal is detected.
POWER
VDD
3, 6, 7,
10, 13,
15, 46
Power
GND
GND
VDD pins should be tied to the VDD plane through a low inductance path. A 0.1µF bypass
capacitor should be connected between each VDD pin to the GND planes.
GND
22, 24,
27, 30,
31, 34
Ground reference. GND should be tied to a solid ground plane through a low impedance
path.
Exposed
Pad
DAP
The exposed pad at the center of the package must be connected to the ground plane.
System Management Bus (SMBus) Interface Control Pins
SDA
18
IO,
SMBus Data Input / Output. Internally pulled High to 3.3V with High-Z pull up.
LVCMOS
SDC
CS
17
16
I, LVCMOS SMBus Clock Input. Internally pulled High to 3.3V with High-Z pull up.
I, LVCMOS SMBus Chip select. When held High, the equalizer SMBus register is enabled. When held
Low, the equalizer SMBus register is disabled. CS is internally pulled Low. CS is internally
gated with SDC.
Other
Reserv
19, 20, 38,
39, 40,41,
42, 43, 47,
48
Reserved. Do not connect.
Note: I = Input, O = Output, IO =Input/Output,
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2
Connection Diagram
30064652
TOP VIEW — Not to Scale
Ordering Information
NSID
Tape & Reel Quantity
Package
SQA48D
SQA48D
DS16EV5110ASQ
DS16EV5110ASQX
250
2,500
3
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ESD Rating
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
>6 kV
HBM, 1.5 kΩ, 100 pF
Thermal Resistance
ꢀθJA, No Airflow
30°C/W
Supply Voltage (VDD
)
-0.5V to +4.0V
-0.5V + 4.0V
-0.5V to 4.0V
-0.5V to 4.0V
+150°C
Recommended Operating
LVCMOS Input Voltage
LVCMOS Output Voltage
CML Input/Output Voltage
Junction Temperature
Storage Temperature
Lead Temp. (Soldering, 5 sec.)
Conditions (Notes 2, 3)
Min
Typ
Max Units
Supply Voltage
(VDD to GND)
3.0
3.3
3.6
V
-65°C to +150°C
+260°C
Ambient Temperature
-40
25
+85
°C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified. (Notes 2, 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS
IIH-PU
IIH-PD
IIL-PU
IIL-PD
High Level Input Leakage Current LVCMOS pins with internal pull-up
resistors
-10
80
+10
105
-10
μA
μA
μA
μA
High Level Input Leakage Current LVCMOS pins with internal pull-
down resistors
Low Level Input Leakage Current LVCMOS pins with internal pull-up
resistors
-20
-10
Low Level Input Leakage Current LVCMOS pins with internal pull-
down resistors
+10
VIH
High Level Input Voltage
Low Level Input Voltage
2.0
0
VDD
0.8
V
V
V
V
VIL
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
SD Pin, IOH = -3mA
SD Pin, IOL = 3mA
2.4
0.4
POWER
PD
Power Dissipation
EN = High, Device Enabled
475
100
700
70
mW
mW
EN = Low, Power Down Mode
N
Supply Noise Tolerance (Note 4) DC to 50MHz
mVP-P
CML INPUTS
VTX
Input Voltage Swing (Launch
Amplitude)
Measured differentially at TPA
(Figure 2)
mVP-P
V
800
1200
VICMDC
VIN
Input Common-Mode Voltage
DC-Coupled Requirement
Measured at TPA (Figure 2)
VDD-0.3
VDD-0.2
Input Voltage Swing
Measured differentially at TPB
(Figure 2)
mVP-P
120
RLI
Differential Input Return Loss
Input Resistance
100 MHz– 825 MHz, with fixture's
effect de-embedded
10
50
dB
RIN
IN+ to VDD and IN− to VDD
45
55
Ω
CML OUTPUTS
VO
Output Voltage Swing
Measured differentially with OUT+
and OUT− terminated by 50Ω to
VDD
mVP-P
800
1200
VOCM
IOFF
Output common-mode Voltage
Output Leakage Current
Transition Time
Measured Single-ended
VDD-0.3
VDD-0.2
V
VOUT = 3.6V, VDD = open or 0V
±1
µA
tR, tF
20% to 80% of differential output
voltage, measured within 1" from
output pins.
75
240
ps
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4
Symbol
tCCSK
Parameter
Conditions
Min
Typ
25
Max
Units
ps
Inter Pair Channel-to-Channel
Skew (all 4 Channels)
Difference in 50% crossing
between shortest and longest
channels
tD
Latency
350
ps
OUTPUT JITTER
TJ1
Total Jitter at 1.65 Gbps
20m 28 AWG STP DVI Cable
Data Paths
UIP-P
0.13
0.2
0.17
EQ Setting 0x04 PRBS7
(Notes 5, 6, 7)
TJ2
Total Jitter at 2.25 Gbps
20m 28 AWG STP DVI Cable
Data Paths
EQ Setting 0x04 PRBS7
(Notes 5, 6, 7)
UIP-P
TJ3
TJ4
Total Jitter at 165 MHz
Total Jitter at 225 MHz
Random Jitter
Clock Paths
Clock Pattern
(Notes 5, 6, 7)
UIP-P
0.165
Clock Paths
Clock Pattern
(Notes 5, 6, 7)
UIP-P
psrms
0.165
3
RJ
(Notes 7, 8)
BIT RATE
FCLK
Clock Frequency
Bit Rate
Clock Path
(Note 5)
25
225
MHz
BR
Data Path
(Note 5)
0.25
2.25
Gbps
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of –40°C to +125°C. Models
are validated to Maximum Operating Voltages only.
Note 2: Typical values represent most likely parametric norms at VDD = 3.3V, TA = 25°C, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes.
Note 4: Allowed supply noise (mVP-P sine wave) under typical conditions.
Note 5: Specification is guaranteed by characterization and is not tested in production.
Note 6: Deterministic jitter is measured at the differential outputs (TPC of Figure 2), minus the deterministic jitter before the test channel (TPA of Figure 2). Random
jitter is removed through the use of averaging or similar means.
Note 7: Total Jitter is defined as peak-to-peak deterministic jitter from (Note 8) + 14.2 times random jitter in psrms
.
Note 8: Random jitter contributed by the equalizer is defined as sq rt (JOUT2 − JIN2). JOUT is the random jitter at equalizer outputs in psrms, see TPC of Figure 2;
JIN is the random jitter at the input of the equalizer in psrms, see TPA of Figure 2.
5
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Electrical Characteristics — System Management Bus Interface (Notes 2, 3)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
System Bus Interface — DC Specifications
VIL
Data, Clock Input Low Voltage
Data, Clock Input High Voltage
0.8
V
V
VIH
2.8
VDD
IPULLUP
Current through pull-up resistor or VOL = 0.4V
current source
10
mA
VDD
Nominal Bus Voltage
3.0
3.6
V
ILEAK-Bus
ILEAK-Pin
CI
Input Leakage per bus segment
Input Leakage per device pin
Capacitance for SDA and SDC
Termination Resistance
(Note 9)
+200
—200
µA
µA
pF
Ω
—15
1000
(Notes 9, 10)
10
RTERM
VDD3.3, (Notes 9, 10, 11)
System Bus Interface Timing Specification
FSMB
TBUF
Bus Operating Frequency
(Note 12)
10
100
kHz
µs
Bus Free Time Between Stop and
Start Condition
4.7
TSU:CS
TH:CS
Minimum time between SMB_CS (Note 5)
being active and start condition
30
ns
ns
Minimum time between stop
(Note 5)
100
condition and releasing SMB_CS
THD:STA
Hold Time After (Repeated) Start At IPULLUP, Max
Condition. First CLK generated
after this period.
4.0
4.7
µs
µs
TSU:STA
Repeated Start Condition Setup
Time
TSU:STO
THD:DAT
TSU:DAT
TTIMEOUT
TLOW
Stop Condition Setup Time
Data Hold Time
4.0
300
250
25
µs
ns
ns
ms
µs
µs
Data Setup Time
Detect Clock Low Timeout
Clock Low Period
(Note 12)
35
4.7
4.0
THIGH
Clock High Period
(Note 12)
(Note 12)
50
2
TLOW:SEXT
Cumulative Clock Low Extend
Time (Slave Device)
ms
tF
Clock/Data Fall Time
Clock/Data Rise Time
(Note 12)
(Note 12)
(Note 12)
300
ns
ns
tR
1000
tPOR
Time in which a device must be
operational after power-on reset
500
ms
Note 9: Recommended value. Parameter not tested in production.
Note 10: Recommended maximum capacitance load per bus segment is 400pF.
Note 11: Maximum termination voltage should be identical to the device supply voltage.
Note 12: Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common
AC specifications for details.
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6
Timing Diagrams
30064650
FIGURE 1. SMBus Timing Diagram
30064627
FIGURE 2. Test Setup Diagram for Jitter Measurement
7
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SMBus Transactions
System Management Bus (SMBus)
and Configuration Registers
The device supports WRITE and READ transactions. See
Register Description table for register address, type (Read/
Write, Read Only), default value and function information.
The System Management Bus interface is compatible to SM-
Bus 2.0 physical layer specification. The use of the Chip
Select signal is required. Holding the CS pin High enables
the SMBus port allowing access to the configuration registers.
Holding the CS pin Low disables the device's SMBus allowing
communication from the host to other slave devices on the
bus. In the STANDBY state, the System Management Bus
remains active. When communication to other devices on the
SMBus is active, the CS signal for the DS16EV5110As must
be driven Low.
Writing a Register
To write a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host (Master) selects the device by driving its
SMBus Chip Select (CS) signal High.
2. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
3. The Device (Slave) drives the ACK bit (“0”).
4. The Host drives the 8-bit Register Address.
5. The Device drives an ACK bit (“0”).
The address byte for all DS16EV5110As is AC'h. Based on
the SMBus 2.0 specification, the DS16EV5110A has a 7-bit
slave address of 1010110'b. The LSB is set to 0'b (for a
WRITE), thus the 8-bit value is 1010 1100 'b or AC'h.
6.
The Host drive the 8-bit data byte.
7. The Device drives an ACK bit (“0”).
8. The Host drives a STOP condition.
The SDC and SDA pins are 3.3V LVCMOS signaling and in-
clude high-Z internal pull up resistors. External low
impedance pull up resistors maybe required depending upon
SMBus loading and speed. Note, these pins are not 5V tol-
erant.
9. The Host de-selects the device by driving its SMBus CS
signal Low.
The WRITE transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable dur-
ing the time when SDC is High.
Reading a Register
To read a register, the following protocol is used (see SMBus
2.0 specification).
There are three unique states for the SMBus:
1. The Host (Master) selects the device by driving its
SMBus Chip Select (CS) signal High.
START: A High-to-Low transition on SDA while SDC is High
indicates a message START condition.
2. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
STOP: A Low-to-High transition on SDA while SDC is High
indicates a message STOP condition.
3. The Device (Slave) drives the ACK bit (“0”).
4. The Host drives the 8-bit Register Address.
5. The Device drives an ACK bit (“0”).
IDLE: If SDC and SDA are both High for a time exceeding
tBUF from the last detected STOP condition or if they are High
for a total exceeding the maximum specification for tHIGH then
the bus will transfer to the IDLE state.
6. The Host drives a START condition.
7. The Host drives the 7-bit SMBus Address, and a “1”
indicating a READ.
8. The Device drives an ACK bit “0”.
9. The Device drives the 8-bit data value (register contents).
10. The Host drives a NACK bit “1”indicating end of the
READ transfer.
11. The Host drives a STOP condition.
12. The Host de-selects the device by driving its SMBus CS
signal Low.
The READ transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
Please see Table 1 for more information.
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8
TABLE 1. SMBus Register Descriptions
Address Default Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Reserved Reserved Reserved SD
EN Reserved
Name
Status
Status
Status
Bit 1
Bit 0
0x00
0x01
0x02
0x03
0x00
0x00
0x00
0x77
RO ID Revision
RO Reserved Boost 1
RO Reserved Boost 3
Reserved Boost 2
Internal
Enable/
Individual
Channel
Boost
RW EN (Int.) Boost Control
EN (Int.) Reserved
0:Enable
0:Enable (BC for CH0)
1:Disable 000 (Min Boost)
1:Disable
(D_IN0±) 001
(C_IN±)
010
Control
for
011
100
C_IN±,
D_IN0±
101
110
111 (Max Boost)
Individual 0x04
Channel
Boost
0x77
RW EN (Int.) Boost Control
EN (Int.) Boost Control
0:Enable (BC for CH1)
1:Disable 000 (Min Boost)
0:Enable (BC for CH2)
1:Disable 000 (Min Boost)
Control
for
(D_IN2±) 001
(D_IN1±) 001
010
010
D_IN1±,
D_IN2±
011
100
011
100
101
101
110
110
111 (Max Boost)
111 (Max Boost)
Signal
Detect ON
(SD_ON)
0x05
0x06
0x00
0x00
RW Reserved
RW Reserved
Threshold (mV)
00: 70 (Default)
01: 55
10: 90
11: 75
Signal
Threshold (mV)
Detect OFF
(SD_OFF)
00: 40 (Default)
01: 30
10: 55
11: 45
SMBus or 0x07
CMOS
Control for
EN
0x00
0x78
RW Reserved
RW Reserved
SMBus
Enable
0: Disable
1: Enable
Output
Level
0x08
Output Level:
Reserved
00: 540 mVp-p
01: 770 mVp-p
10: 1000 mVp-p
11: 1200 mVp-p
Note: RO = Read Only, RW = Read/Write
9
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be controlled either via the Enable Pin (EN Pin) or via the
Enable Control Bit which is accessed through the SMBus port
(see Table 1 and Table 3). If Enable is activated, the data
channels and clock channel are placed in the ACTIVE state
and all device blocks function as described. The
DS16EV5110A can also be placed in STANDBY mode to
save power. In this mode only the control interface including
the SMBus port as well as the clock channel signal detection
circuit remain active.
DS16EV5110A Device Description
The DS16EV5110A video equalizer comprises three data
channels, a clock channel, and a control interface including a
Systeml Management Bus (SMBus) port.
DATA CHANNELS
The DS16EV5110A provides three data channels. Each data
channel consists of an equalizer stage, a limiting amplifier, a
DC offset correction block, and a TMDS driver as shown in
Figure 3.
TABLE 3. Enable and Device State Control
Register 07[0] EN Pin Register 03[3] Device State
EQUALIZER BOOST CONTROL
(SMBus)
(CMOS) (EN Control)
(SMBus)
The data channel equalizers support eight programmable lev-
els of equalization boost. The state of the FEB pin determines
how the boost settings are controlled. If the FEB pin is held
High, then the equalizer boost setting is controlled by the
Boost Set pins (BST_[0:2]) in accordance with Table 2. If this
programming method is chosen, then the boost setting se-
lected on the Boost Set pins is applied to all three data
channels. When the FEB pin is held Low, the equalizer boost
level is controlled through the SMBus. This programming
method is accessed via the appropriate SMBus registers (see
Table 1). Using this approach, equalizer boost settings can
be programmed for each channel individually. FEB is inter-
nally pulled High (default setting); therefore if left unconnect-
ed, the boost settings are controlled by the Boost Set pins
(BST_[0:2]). The range of boost settings provided enables the
DS16EV5110A to address a wide range of transmission line
path loss scenarios, enabling support for a variety of data
rates and formats.
0 : Disable
0 : Disable
1 : Enable
1 : Enable
1
0
X
X
0
1
ACTIVE
STANDBY
ACTIVE
X
X
STANDBY
CLOCK CHANNEL
The clock channel incorporates a limiting amplifier, a DC off-
set correction, and a TMDS driver as shown in Figure 4.
CLOCK CHANNEL SIGNAL DETECT
The DS16EV5110A features a signal detect circuit on the
clock channel. The status of the clock signal can be deter-
mined by either reading the Signal Detect bit (SD) in the
SMBus registers (see Table 1) or by the state of the SD pin.
A logic High indicates the presence of a signal that has ex-
ceeded a specified threshold value (called SD_ON). A logic
Low means that the clock signal has fallen below a threshold
value (called SD_OFF). These values are programmed via
the SMBus (Table 1). If not programmed via the SMBus, the
thresholds take on the default values for the SD_OFF and
SD_ON values as indicated in Table 4. The Signal Detect
threshold values can be changed through the SMBus. All
threshold values specified are DC peak-to-peak differential
signals (positive signal minus negative signal) at the input of
the device.
TABLE 2. EQ Boost Control Table
Control Via
SMBus
BC_2, BC_1,
BC_0
Control Via Pins EQ Boost Setting
BST_2, BST_1,
BST_0
at 825 MHz (dB)
(TYP)
(FEB = 1)
(FEB = 0)
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
9
14
18
21
24
26
28
30
TABLE 4. Clock Channel Signal Detect Threshold Values
Bit 1 Bit 0 SD_OFF Threshold
Register 06 (mV)
SD_ON Threshold
Register 05 (mV)
0
0
1
1
0
1
0
1
40 (Default)
70 (Default)
30
55
45
55
90
75
DEVICE STATE AND ENABLE CONTROL
The DS16EV5110A has an Enable feature which provides the
ability to control device power consumption. This feature can
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10
30064637
FIGURE 3. DS16EV5110A Data Channel
30064638
FIGURE 4. DS16EV5110A Clock Channel
OUTPUT LEVEL CONTROL
present. STANDBY mode can be implemented by connecting
the Signal Detect (SD) pin to the external (LVCMOS) Enable
(EN) pin. In order for this option to function properly,
REG07[0] should be set to a “0” (default value). If the clock
signal applied to the clock channel input swings above the
SD_ON threshold specified in the threshold register via the
SMBus, then the SD pin is asserted High. If the SD pin is
connected to the EN pin, this will enable the equalizer, limiting
amplifier, and output buffer on the data channels and the lim-
iting amplifier and output buffer on the clock channel; thus the
DS16EV5110A will automatically enter the ACTIVE state. If
the clock signal present falls below SD_OFF threshold spec-
ified in the threshold register, then the SD pin will be asserted
Low, causing the aforementioned blocks to be placed in the
STANDBY state.
The output amplitude of the TMDS drivers for both the data
channels and the clock channel can be controlled via the SM-
Bus (see Table 1). The default output level is 1000mV p-p.
The following Table presents the output level values support-
ed:
TABLE 5. Output Level Control Settings – REG 0x08[3:2]
Bit 3
Bit 2
Output Level (mV)
0
0
1
1
0
1
0
1
540
770
1000 (default)
1200
AUTOMATIC ENABLE FEATURE
It may be desired for the DS16EV5110A to be configured to
automatically enter STANDBY mode if no clock signal is
11
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In the Source Side application the DS16EV5110A is located
near the Serializer and conditions the signal for losses due to
internal cabling or FR4 losses (backplane). The signal is then
re-driven at full amplitude and reduced jitter over the external
cable interconnect.
Application Information
The DS16EV5110A is used to recondition DVI/HDMI video
signals or differential signals with similar characteristics for
signal loss and degradation due to transmission through a
length of shielded or unshielded cable. The DS16EV5110A
maybe used on the Source or Sink side of the application or
as a Repeater (Sink and Source).
30064654
FIGURE 5. DS16EV5110A Source-Side Application
In the Sink Side application the DS16EV5110A is located next
to the Deserializer and post-conditions the signal for losses
incurred over the cable interconnect.
30064639
FIGURE 6. DS16EV5110A Sink-Side Application
The DS16EV5110A may be used in repeater type application
as shown in Figure 7 . The cable on the output of the repeater
tends to be shorter and may be a dongle type application. The
input of the repeater recovers the signal after transmission
over a long cable interconnect.
30064624
FIGURE 7. DS16EV5110A Repeater Application with CAT 5 Cable
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12
In general, the use of multiple equalizers is not recommended
due to accumulation of random jitter.
configured by using two DS16EV5110A devices as shown in
Figure 8.
Note the recommended connections between LVCMOS con-
trol pins. This provides the Automatic Enable feature for both
devices based on the one active clock channel. In many ap-
plications the SMBus is not required (device is pin controlled),
for this application simply leave the three SMBus pins open.
SDC and SDA are internally pulled High, and CS is internally
pulled Low, thus the SMBus is in the disabled state.
DVI 1.0 AND HDMI V1.2a APPLICATIONS
A single DS16EV5110A can be used to implement cable ex-
tension solutions with various resolutions and screen refresh
rates. The range of digital serial rates supported is between
250 Mbps and 1.65 Gbps. For applications requiring ultra-
high resolution for DVI applications (e.g., QXGA and WQX-
GA), a “dual link” TMDS interface is required. This is easily
30064628
FIGURE 8. Connection in Dual Link Application
HDMI V1.3 APPLICATION
DC COUPLED DATA PATHS AND DVI/HDMI
COMPLIANCE
The DS16EV5110A can reliably extend operation to dis-
tances greater than 20 meters of 28 AWG HDMI cable at 2.25
Gbps, thereby supporting HDMI v1.3 for 1080p HDTV reso-
lution with 12-bit color depth. Please note that the Electrical
Characteristics specified in this document have not been test-
ed for and are not guaranteed for 2.25 Gbps operation.
The DS16EV5110A is designed to support TMDS differential
pairs with DC coupled transmission lines. It contains integrat-
ed termination resistors (50Ω), pulled up to VDD at the input
stage, and open collector outputs for DVI / HDMI for signal
swing.
13
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CABLE SELECTION
UTP (UNSHIELDED TWIST PAIRS) CABLES
At higher frequencies, longer cable lengths produce greater
losses due to the skin effect. The quality of the cable with
respect to conductor wire gauge and shielding heavily influ-
ences performance. Thicker conductors have lower signal
degradation per unit length. In nearly all applications, the
DS16EV5110A equalization can be set to 0x04, and equalize
up to 22 dB skin effect loss for all input cable configurations
at all data rates, without degrading signal integrity.
The DS16EV5110A can be used to extend the length of UTP
cables, such as Cat5, Cat5e and Cat6 to distances greater
than 20 meters at 1.65 Gbps with < 0.13 UI of jitter. Please
note that for non-standard DVI/HDMI cables, the user must
ensure the clock-to-data channel skew requirements are met.
Table 7 presents the recommended boost control settings for
various data rates and cable lengths for UTP configurations:
TABLE 7. Boost Control Setting for UTP Cables
28 AWG STP DVI / HDMI CABLES RECOMMENDED
BOOST SETTINGS
Setting
0x03
Data Rate
750 Mbps
750 Mbps
1.65 Gbps
Cat5 Cable
0–25m
The following table presents the recommended boost control
settings for various data rates and cable lengths for 28 AWG
DVI/HDMI compliant configurations. Boost setting maybe
done via the three BST[2:0] pins or via the respective register
values.
0x06
25–45m
0x03
Greater than 20m
Figure 10 shows the cable extension and jitter reduction ob-
tained with the use of the equalizer. Table 7 lists the various
gain settings used versus cable length recommendations.
TABLE 6. Boost Control Setting for STP Cables
Setting
0x04
0x04
0x06
0x06
0x03
0x06
Data Rate
750 Mbps
1.65 Gbps
750 Mbps
1.65 Gbps
2.25 Gbps
2.25 Gbps
28 AWG DVI / HDMI
0–25m
0–20m
25m to greater than 30m
20m to greater than 25m
0–15m
15m to greater than 20m
Figure 9 shows the cable extension and jitter reduction ob-
tained with the use of the equalizer. Table 6 lists the various
gain settings used versus cable length recommendations.
30064643
FIGURE 10. Equalized vs. Unequalized Jitter
Performance Over Cat5 Cable
30064642
FIGURE 9. Equalized vs. Unequalized Jitter Performance
Over 28 AWG DVI/HDMI Cable
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14
POWER SUPPLY BYPASSING
General Recommendations
Two approaches are recommended to ensure that the
DS16EV5110A is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be
connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the VDD and GND planes create
a low inductance supply with distributed capacitance. Sec-
ond, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.1µF bypass capac-
itor should be connected to each VDD pin such that the
capacitor is placed as close as possible to the
DS16EV5110A. Smaller body size capacitors can help facili-
tate proper component placement. Additionally, three capac-
itors with capacitance in the range of 2.2µF to 10µF should
be incorporated in the power supply bypassing design as well.
These capacitors can be either tantalum or an ultra-low ESR
ceramic and should be placed as close as possible to the
DS16EV5110A.
The DS16EV5110A is a high performance circuit capable of
delivering excellent performance. Careful attention must be
paid to the details associated with high-speed design as well
as providing a clean power supply. Refer to the LVDS
Owner’s Manual for more detailed information on high-speed
design tips as well as many other available resources avail-
able addressing signal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The TMDS differential inputs and outputs must have a con-
trolled differential impedance of 100Ω. It is preferable to route
TMDS lines exclusively on one layer of the board, particularly
for the input traces. The use of vias should be avoided if pos-
sible. If vias must be used, they should be used sparingly and
must be placed symmetrically for each side of a given differ-
ential pair. Route the TMDS signals away from other signals
and noise sources on the printed circuit board. All traces of
TMDS differential inputs and outputs must be equal in length
to minimize intra-pair skew.
EQUIVALENT I/O STRUCTURES
Figure 11 shows the DS16EV5110A CML output structure
and ESD protection circuitry.
LLP FOOTPRINT RECOMMENDATIONS
Figure 12 shows the DS16EV5110A CML input structure and
ESD protection circuitry.
See National application note: AN-1187 for additional infor-
mation on LLP packages footprint and soldering information.
30064640
FIGURE 11. Equivalent CML Output Structure
30064641
FIGURE 12. Equivalent CML Input Structure
15
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Typical Performance Characteristics
30064629
30064630
FIGURE 13. Un-Equalized vs. Equalized Signal after 25m of 28 AWG DVI Cable at 1.65 Gbps (0x06 Setting)
30064631
FIGURE 14. Output Signal after 20m of Cat5 Cable at 1.65 Gbps (0x06 Setting)
30064632
FIGURE 15. Output Signal after 30m of 28 AWG DVI Cable at 750 Mbps (0x06 Setting)
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16
30064633
FIGURE 16. Output Signal after 0.3m of 28 AWG DVI Cable at 1.65 Gbps (0x04 Setting)
30064634
FIGURE 17. Output Signal after 20m of 28 AWG HDMI Cable at 2.25 Gbps (0x06 Setting)
17
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Physical Dimensions inches (millimeters) unless otherwise noted
7mm x 7mm 48-pin LLP Package
Order Number DS16EV5110ASQ
Package Number SQA48D
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18
Notes
19
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