DRV2901 [TI]
具有宽电源电压、用于超声波清洗的单通道 PWM 输入压电换能器驱动器;
| 型号： | DRV2901 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有宽电源电压、用于超声波清洗的单通道 PWM 输入压电换能器驱动器 驱动 换能器 驱动器 |
| 文件： | 总23页 (文件大小：1193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV2901
ZHCSRG7 –JANUARY 2023
DRV2901 具有宽电源电压、用于超声波清洗的单通道PWM 输入压电传感器驱
动器
1 特性
3 说明
• 12V 至48V 宽电源电压工作范围
• 支持高达50W 的峰值功率
• 具有90mΩ 输出MOSFET 的高效功率级
• 用于加电保护的上电复位，无任何电源定序
• 集成式自保护电路，包括
DRV2901 是一款高性能镜头清洁器传感器驱动器。该
系统仅需一个简单的无源 LC 解调滤波器即可提供高质
量、高效的放大功能，并符合 EMI 标准。该器件需要
两个电源，一个为 12V，用于GVDD 和VDD，另外一
个为 12V 至 48V，用于 PVDD。由于内部上电复位，
DRV2901 不需要上电时序控制。
– 欠压保护
– 过热保护
– 过载保护
– 短路保护
DRV2901 具有一个片上集成创新保护系统，可保护器
件免受可能损坏系统的各种故障条件的影响。这些保护
是短路保护、过流保护、欠压保护和过热保护。
DRV2901 具有一个全新的专有限流电路，可降低在高
电平瞬态期间器件关断的可能性。
• 采用44 引脚HTSSOP 封装(DDV)
2 应用范围
器件信息(1)
• 热成像摄像机
• 交通监控摄像头
• 机器视觉摄像机
• 无线安防摄像头
• 无人机视觉
封装尺寸（标称值）
器件型号
DRV2901
封装
44 引脚散热薄型小外
形尺寸封装
(HTSSOP)
14.0mm x 6.1mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
OTW
SD
BST_A
Bootstrap
Capacitors
BST_B
RESET_AB
RESET_DRIVER
PWM_A
OUT_A
nd
2
-Order L-C
Output
Output Filter
for Each
Input
H-Bridge 1
Channel
Output
H-Bridge 1
OUT_B
PWM_B
Half-Bridge
1-Channel
H-Bridge
VAC
4
4
4
PVDD
Power
Supply
GVDD
VDD
VREG
PVDD
48 V
Hardwire
OC Limit
System
Power
Supply
Decoupling
Power Supply
Decoupling
GND
GND
12 V
GVDD (12 V)/VDD (12 V)
DRV2901 功能方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASF54
DRV2901
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Table of Contents
7 Detailed Description........................................................9
7.1 Block Diagrams...........................................................9
7.2 Feature Description...................................................10
8 Applications and Implementation................................13
8.1 Application Information............................................. 13
8.2 Typical Application.................................................... 14
9 Power Supply Recommendations................................15
9.1 System Power-up/power-down Sequence................15
9.2 System Design Recommendations...........................15
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用范围............................................................................ 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................8
Information.................................................................... 16
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
January 2023
*
Initial release.
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5 Pin Configuration and Functions
DDV PACKAGE
(TOP VIEW)
GVDD_A
OTW
GVDD_A
NC
NC
NC
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
NC
NC
SD
GND
3
4
5
GND
GND
6
RESET
PWM_A
OC_ADJ
GND
AGND
VREG
VREG
GND
VREG
PWM_B
RESET
GND
7
GND_A
OUT_A
PVDD_A
BST_A
BST_B
PVDD_B
OUT_B
GND_B
GND
GND
NC
NC
NC
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
VDD
GVDD_B
NC
GVDD_B
图5-1. DDV Package 44-Pin HTSSOP PowerPad Top View
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
AGND
BST_A
BST_B
GND
NO.
11
P
P
P
P
Analog ground
34
HS bootstrap supply (BST), external .033-μF capacitor to OUT_A required
HS bootstrap supply (BST), external .033-μF capacitor to OUT_B required
Ground.
33
6, 10, 14, 18, 28,
29, 38, 39
GND_A
GND_B
GVDD_A
GVDD_B
NC
37
30
P
P
P
P
Power ground for half-bridge A
Power ground for half-bridge B
1, 44
22, 23
Gate-drive voltage supply requires 0.1-μF capacitor to AGND
Gate-drive voltage supply requires 0.1-μF capacitor to AGND
Do not connect.
3, 4, 19, 20, 24,
25, 26, 27, 40, 41,
42, 43
—
OC_ADJ
OTW
9
O
O
O
O
P
Analog overcurrent programming pin requires resistor to ground
Overtemperature warning signal, open-drain, active-low
Output, half-bridge A
2
OUT_A
OUT_B
PVDD_A
36
31
35
Output, half-bridge B
Power supply input for half-bridge A requires close decoupling of 0.01-μF
capacitor in parallel with a 1.0-μF capacitor to GND_A.
PVDD_B
PWM_A
32
8
P
I
Power supply input for half-bridge B requires close decoupling of 0.01-μF
capacitor in parallel with a 1.0-μF capacitor to GND_B.
Input signal for half-bridge A
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表5-1. Pin Functions (continued)
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
16
PWM_B
RESET
SD
I
I
Input signal for half-bridge B
7, 17
5
Reset signal for half-bridge A and B, active-low
Shutdown signal, open-drain, active-low
O
P
VDD
21
Power supply for digital voltage regulator requires a 47-μF capacitor in parallel
with a 0.1-μF capacitor to GND for decoupling.
VREG
12, 13, 15
P
Digital regulator supply filter pin requires 0.1-μF capacitor to AGND.
(1) I = input, O = output, P = power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted (1)
VDD to AGND
–0.3 V to 13.2 V
GVDD_X to AGND
–0.3 V to 13.2 V
–0.3 V to 71 V
–0.3 V to 71V
–0.3 V to 79.7 V
–0.3 V to 4.2 V
–0.3 V to 0.3 V
–0.3 V to 0.3 V
–0.3 V to 0.3 V
–0.3 V to 4.2 V
–0.3 V to 7 V
9 mA
PVDD_X to GND_X (2)
OUT_X to GND_X (2)
BST_X to GND_X (2)
VREG to AGND
GND_X to GND
GND_X to AGND
GND to AGND
PWM_X, OC_ADJ, M1, M2, M3 to AGND
RESET_X, SD, OTW to AGND
Maximum continuous sink current ( SD, OTW)
Maximum operating junction temperature range, TJ
Storage temperature
0°C to 125°C
–40°C to 125°C
260°C
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds
Minimum pulse duration, low
50 ns
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
TYP
MAX UNIT
PVDD_X
GVDD_X
Half-bridge supply
DC supply voltage
DC supply voltage
DC supply voltage
0
50
52.5
13.2
13.2
V
V
Supply for logic regulators and gate-drive
circuitry
10.8
12
VDD
Digital regulator input
Output-filter inductance
10.8
5
12
10
V
LOutput
Minimum output inductance under
short-circuit condition
μH
FPWM
TJ
PWM frame rate
192
0
384
432
125
kHz
°C
Junction temperature
6.4 Thermal Information
DRV2901
DDV 44-PINS HTSSOP
THERMAL METRIC(1)
UNIT
JEDEC STANDARD 4 LAYER
PCB
RθJA
Junction-to-ambient thermal resistance
50.7
°C/W
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UNIT
DRV2901
DDV 44-PINS HTSSOP
THERMAL METRIC(1)
JEDEC STANDARD 4 LAYER
PCB
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
0.36
24.4
0.19
24.2
n/a
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
RL= 6 Ω, FPWM = 384 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions
unless otherwise specified.
DRV2900
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
Internal Voltage Regulator and Current Consumption
Voltage regulator, only used as a
reference node
VREG
VDD = 12 V
2.95
3.3
3.65
V
Operating, 50% duty cycle
Idle, reset mode
10
6
IVDD
VDD supply current
mA
50% duty cycle
8
IGVDD_X
IPVDD_X
Gate supply current per half-bridge
Half-bridge idle current
mA
Reset mode
0.3
15
500
50% duty cycle, without output filter or load
Reset mode, no switching
mA
μA
Output Stage MOSFETs
TJ = 25°C, includes metallization resistance,
GVDD = 12 V
RDSon,LS
Drain-to-source resistance, LS
90
90
mΩ
mΩ
TJ = 25°C, includes metallization resistance,
GVDD = 12 V
RDSon,HS
Drain-to-source resistance, HS
I/O Protection
Vuvp,G
Undervoltage protection limit,
GVDD_X
8.5
V
(1)
Vuvp,hyst
400
125
mV
°C
OTW(1)
Overtemperature warning
115
145
135
165
Temperature drop needed below
OTW temp. for OTW to be inactive
after the OTW event
(1)
OTWHYST
25
°C
OTE(1)
Overtemperature error
OTE-OTW differential
155
25
°C
°C
OTE-OTWdifferential
(1)
A reset needs to occur for SD for be
released following an OTE event.
(1)
OTEHYST
25
1.3
12
°C
ms
A
OLPC
IOC
Overload protection counter
Overcurrent limit protection
Overcurrent response time
FPWM = 384 kHz
Resistor—programmable, nominal,
ROCP = 22 kΩ
IOCT
Time from application of short condition to Hi-
Z of affected 1/2 bridge
250
ns
ROCP
OC programming resistor range
Resistor tolerance = 5%
22
69
kΩ
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RL= 6 Ω, FPWM = 384 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions
unless otherwise specified.
DRV2900
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
Connected when RESET is active to provide
bootstrap capacitor charge. Not used in SE
mode
Internal pulldown resistor at the
output of each half-bridge
RPD
1.0
kΩ
Static Digital Specifications
VIH
High-level input voltage
2
V
V
PWM_A, PWM_B, RESET_AB
VIL
Low-level input voltage
Input leakage current
0.8
Leakage
-100
100
μA
OTW/SHUTDOWN (SD)
Internal pullup resistance, OTW to
RINT_PU
20
26
35
kΩ
VREG, SD to VREG
Internal pullup resistor
External pullup of 4.7 kΩ to 5 V
IO = 4 mA
2.95
4.5
3.3
3.65
5
VOH
High-level output voltage
V
VOL
Low-level output voltage
Device fanout OTW, SD
0.2
30
0.4
V
FANOUT
No external pullup
Devices
(1) Specified by design
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6.6 Typical Characteristics
1.6
1.4
1.2
1.0
0.8
0.6
0.4
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.96
–40 –20
0
20 40 60 80 100 120 140
8.0
8.5
9.0
9.5 10.0 10.5 11.0 11.5 12
Gate Drive (V)
TJ – Junction Temperature – oC
GVDD = 12 V
TJ = 25°C
图6-2. Normalized RDS(on) vs Junction Temperature
图6-1. Normalized RDS(on) vs Gate Drive
6
5
4
3
2
1
0
100
90
80
70
60
50
40
30
20
10
0
–1
0
0.2
0.4
0.6
0.8
1
1.2
0
10 20 30 40 50 60 70 80 90 100
Input Duty Cycle (%)
Voltage (V)
TJ = 25°C
FS = 500 kHz; TC
=
25°C
图6-3. Drain To Source Diode Forward
On Characteristics
图6-4. Output Duty Cycle vs Input Duty Cycle
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7 Detailed Description
7.1 Block Diagrams
VDD
4
Under-
voltage
Protection
OTW
4
Internal Pullup
VREG
VREG
Resistors to VREG
SD
Power
On
Reset
AGND
GND
Protection
and
I/O Logic
Temp.
Sense
RESET_AB
Overload
I
OC_ADJ
sense
Protection
GVDD_B
BST_B
PVDD_B
OUT_B
PWM
Gate
PWM_B
Rcv.
Ctrl.
Timing
Drive
GND_B
GVDD_A
BST_A
PVDD_A
OUT_A
PWM
Gate
Drive
PWM_A
Rcv.
Ctrl.
Timing
GND_A
图7-1. System Block Diagram
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OTW
SD
BST_A
BST_B
Bootstrap
Capacitors
RESET_AB
RESET_DRIVER
PWM_A
PWM_B
OUT_A
nd
2
-Order L-C
Output
Output Filter
for Each
Input
H-Bridge 1
Channel
Output
H-Bridge 1
OUT_B
Half-Bridge
1-Channel
H-Bridge
VAC
4
4
4
PVDD
Power
Supply
GVDD
VDD
VREG
PVDD
48 V
Hardwire
OC Limit
System
Power
Supply
Decoupling
Power Supply
Decoupling
GND
GND
12 V
GVDD (12 V)/VDD (12 V)
图7-2. Functional Block Diagram
7.2 Feature Description
7.2.1 Error Reporting
The SD and OTW pins are both active-low, open-drain outputs. Their function is for protection-mode signaling to
a PWM controller or other system-control device.
Any fault resulting in device shutdown, such as overtemperatue shut down, overcurrent shut-down, or
undervoltage protection, is signaled by the SD pin going low. Likewise, OTW goes low when the device junction
temperature exceeds 125°C (see 表7-1).
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表7-1. Protection Mode Signal Descriptions
SD
OTW
DESCRIPTION
0
0
Overtemperature warning and (overtemperature shut down or overcurrent shut down or undervoltage
protection) occurred
0
1
1
1
0
1
Overcurrent shut-down or GVDD undervoltage protection occurred
Overtemperature warning
Device under normal operation
TI recommends monitoring the OTW signal using the system microcontroller and responding to an OTW signal
by reducing the load current to prevent further heating of the device resulting in device overtemperature
shutdown (OTSD).
To reduce external component count, an internal pullup resistor to internal VREG (3.3 V) is provided on both SD
and OTW outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see
the Electrical Characteristics section of this data sheet for further specifications).
7.2.2 Device Reset
Reset pin is provided for control of the H-bridge. When RESET_AB is asserted low, the power-stage FETs in H-
bridge are forced into a high-impedance (Hi-Z) state.
A rising-edge transition on reset input allows the device to resume operation after a shut-down fault and clears
the fault and SD pin.
7.2.3 Device Protection System
7.2.3.1 Overcurrent (OC) Protection With Current Limiting and Overload Detection
The device has independent, fast-reacting current detectors with programmable trip threshold (OC threshold) on
all high-side and low-side power-stage FETs. See the following table for OC-adjust resistor values. The detector
outputs are closely monitored by two protection systems. The first protection system controls the power stage in
order to prevent the output current from further increasing, i.e., it performs a current-limiting function rather than
prematurely shutting down during combinations of high-level transients and extreme load impedance drops. If
the high-current situation persists, i.e., the power stage is being overloaded, a second protection system triggers
a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state. Current limiting
and overload protection are independent for half-bridges A and B
• For the lowest-cost bill of materials in terms of component selection, the OC threshold measure should be
limited, considering the power output requirement and minimum load impedance. Higher-impedance loads
require a lower OC threshold.
• The demodulation-filter inductor must retain at least 5 μH of inductance at twice the OC threshold setting.
Unfortunately, most inductors have decreasing inductance with increasing temperature and increasing current
(saturation). To some degree, an increase in temperature naturally occurs when operating at high output
currents, due to core losses and the dc resistance of the inductor's copper winding. A thorough analysis of
inductor saturation and thermal properties is strongly recommended.
Setting the OC threshold too low might cause issues such as lack of enough output power and/or unexpected
shutdowns due to too-sensitive overload detection.
For added flexibility, the OC threshold is programmable within a limited range using a single external resistor
connected between the OC_ADJ pin and AGND. (See the Electrical Characteristics section of this data sheet for
information on the correlation between programming-resistor value and the OC threshold.) It should be noted
that a properly functioning overcurrent detector assumes the presence of a properly designed demodulation filter
at the power-stage output. Short-circuit protection is not provided directly at the output pins of the power stage
but only on the transducer terminals (after the demodulation filter). It is required to follow certain guidelines when
selecting the OC threshold and an appropriate demodulation inductor:
Max. Current Before OC Occurs (A)
OC-Adjust Resistor Values (kΩ)
22
12.2
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Max. Current Before OC Occurs (A)
OC-Adjust Resistor Values (kΩ)
27
47
10.5
6.4
4.0
3.0
68
100
7.2.3.2 Overtemperature Protection
The DRV2901 has a two-level temperature-protection system that asserts an active-low warning signal ( OTW)
when the device junction temperature exceeds 125°C (nominal) and, if the device junction temperature exceeds
155°C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the
high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case and RESET_AB must be
asserted low.
7.2.3.3 Undervoltage Protection (UVP) and Power-On
Reset (POR)
The UVP and POR circuits of the DRV2901 fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the GVDD_X and VDD supply voltages reach 9.8 V (typical). Although GVDD_X and VDD
are independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin
results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and SD being asserted
low. The device automatically resumes operation when all supply voltage on the bootstrap capacitors have
increased above the UVP threshold.
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8 Applications and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The DRV2901 is a high performance lens cleaner transducer driver. This device requires two power supplies, at
12 V for GVDD and VDD, and 12 V to 48 V for PVDD. The DRV2901 does not require power-up sequencing due
to internal power-on reset.
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8.2 Typical Application
图8-1. Typical System Diagram
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DRV2901
ZHCSRG7 –JANUARY 2023
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9 Power Supply Recommendations
9.1 System Power-up/power-down Sequence
9.1.1 Powering Up
The DRV2901 does not require a power-up sequence. The outputs of the H-bridges remain in a highimpedance
state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection
(UVP) voltage threshold (see the Electrical Characteristics section of this data sheet). Although not specifically
required, it is recommended to hold RESET_AB in a low state while powering up the device. This allows an
internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.
9.1.2 Powering Down
The DRV2901 does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics section of this data sheet). Although not specifically required, it is a
good practice to hold RESET_AB low during power down, thus preventing any artifacts.
9.2 System Design Recommendations
9.2.1 VDD Pin
The transient current in VDD pin could be significantly higher than average current through VDD pin. A low
resistive path to GVDD should be used. A 22-µF to 47-µF capacitor should be placed on VDD pin beside the
100-nF to 1-µF decoupling capacitor to provide a constant voltage during transient.
9.2.2 VREG Pin
The VREG pin is used for internal logic and should not be used as a voltage source for external circuitry. The
capacitor on VREG pin should be connected to AGND.
9.2.3 OTW Pin
OTW reporting indicates the device approaching high junction temperature. This signal can be used with MCU to
decrease system power when OTW is low in order to prevent OT shut down at a higher temperature.
No external pull up resistor or 3.3 V power supply is needed for 3.3 V logic. The OTW pin has an internal pullup
resistor connecting to an internal 3.3 V to reduce external component count. For 5 V logic, an external pull up
resistor to 5 V is needed.
Copyright © 2023 Texas Instruments Incorporated
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DRV2901
ZHCSRG7 –JANUARY 2023
www.ti.com.cn
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
16
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV2901DDVR
ACTIVE
HTSSOP
DDV
44
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV2901
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jan-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV2901DDVR
HTSSOP DDV
44
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jan-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP DDV 44
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
DRV2901DDVR
2000
Pack Materials-Page 2
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