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DLPA3000

ZHCSE87 –OCTOBER 2015

DLPA3000 电源管理集成电路 (PMIC) 和高电流 LED 驱动器 IC

1 特性

3 说明

1

•

高效、高电流红-绿-蓝三色 (RGB) LED 驱动器

集成降压转换器，支持高达 6A 的 LED 驱动器电流

DLPA3000 是一款高度集成的电源管理 IC，针对 DLP

Pico 投影仪系统进行了优化。该器件主要针对数百流

明的辅助照明应用。

RGB MOSFET 开关，支持通道选择，导通电阻极

低

DLPA3000 采用集成式高效降压转换器，可支持多个

LED 投影仪，并且能够使每个 LED 的电流高达 6A。

其顶部配有一个低电阻 RGB 开关，支持红色、绿色和

蓝色 LED 排序。 DLPA3000 包含五个降压转换器，其

中两个专用于 DLPC 低压电源。另有一个专用于稳压

电源，为 DMD 生成三个时序关键型直流电

•

每个通道具有 10 位可编程电流

提供用于选择颜色顺序 RGB LED 的输入

可生成数字微镜器件 (DMD) 高电压电源

配有两个高效降压转换器，用于生成 DLPC343x 和

DMD 电源

•

配有三个高效 8 位可编程降压转换器，用于 FAN

驱动器应用或常规电源（目前支持 PWR6，未来将

支持其他电源）

源：V_BIAS、V_RST和 V_OFS

。

DLPA3000 包含多个辅助块，可灵活使用。因此可以

量身定制 Pico 投影仪系统。三个 8 位可编程降压转

换器（尚未全部支持）可用于驱动投影仪 FAN 等或提

供辅助电源线。两个 LDO 可用于提供至多 200mA 的

低电流。这两个 LDO 预定义为 2.5V 和 3.3V。

•

两个 LDO，用于提供辅助电压

模拟 MUX，用于测量内部和外部节点（例如热敏

电阻和基准电平）

•

监视/保护：热关断、热模、电池低电量以及欠压锁

定

DLPA3000 的所有块均可通过 SPI 寻址。此外，该器

件还包含以下特性：生成系统复位，电源排序，用于顺

序选择活动 LED 的输入信号，IC 自我保护以及用于将

模拟信息传送到外部 ADC 的模拟 MUX。

2 应用

便携式 DLP^®Pico™ 投影仪的电源管理和 LED 驱

动器 IC

器件信息⁽¹⁾

部件号

封装

封装尺寸（标称值）

DLPA3000

HTQFP (100)

14.00mm x 14.00mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

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1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: DLPS052

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

1

2

3

4

5

6

特性.......................................................................... 1

8

9

Application and Implementation ........................ 57

8.1 Application Information............................................ 57

8.2 Typical Applications ................................................ 57

Power Supply Recommendations...................... 60

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 7

6.1 Absolute Maximum Ratings ...................................... 7

6.2 ESD Ratings.............................................................. 8

6.3 Recommended Operating Conditions....................... 8

6.4 Thermal Information.................................................. 8

6.5 Electrical Characteristics........................................... 9

6.6 SPI Timing Parameters........................................... 15

Detailed Description ............................................ 16

7.1 Overview ................................................................. 16

7.2 Functional Block Diagram ....................................... 16

7.3 Feature Description................................................. 16

7.4 Device Functional Modes........................................ 45

7.5 Register Maps......................................................... 48

10 Layout................................................................... 61

10.1 Layout Guidelines ................................................. 61

10.2 Layout Example .................................................... 61

10.3 SPI Connections ................................................... 62

10.4 R_LIMRouting.......................................................... 63

10.5 LED Connection.................................................... 63

10.6 Thermal Considerations........................................ 65

11 器件和文档支持 ..................................................... 68

11.1 器件支持................................................................ 68

11.2 相关链接................................................................ 68

11.3 社区资源................................................................ 68

11.4 商标....................................................................... 69

11.5 静电放电警告......................................................... 69

11.6 Glossary................................................................ 69

12 机械、封装和可订购信息....................................... 69

7

4 修订历史记录

日期

修订版本

注释

2015 年 10 月

*

首次发布。

2

DLPA3000

www.ti.com.cn

ZHCSE87 –OCTOBER 2015

5 Pin Configuration and Functions

PFD Package

100-Pin HTQFP

Top View

76

77

78

79

80

81

82

PWR7_BOOST

PWR2_BOOST

ACMPR_IN_1

ACMPR_IN_2

ACMPR_IN_3

ACMPR_IN_LABB

ACMPR_OUT

ACMPR_REF

PWR_VIN

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

SPI_MOSI

SPI_SS_Z

SPI_MISO

SPI_CLK

SPI_VIN

CW_SPEED_PWM_OUT

CLK_OUT

83

84

85

PWR_5P5V

VINA

THERMAL_PAD

ILLUM_B_COMP2

ILLUM_B_COMP1

ILLUM_A_COMP2

ILLUM_A_COMP1

ILLUM_B_PGND

ILLUM_B_SW

ILLUM_B_FB

AGND

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

PWR3_OUT

PWR3_VIN

DLPA3000

PWR4_OUT

PWR4_VIN

SUP_2P5V

SUP_5P0V

ILLUM_B_VIN

ILLUM_B_BOOST

ILLUM_A_PGND

ILLUM_A_SW

ILLUM_A_VIN

ILLUM_A_FB

PWR1_PGND

PWR1_FB

PWR1_SWITCH

PWR1_VIN

PWR1_BOOST

DMD_VOFFSET

DMD_VBIAS

DMD_VRESET

ILLUM_A_BOOST

ILLUM_LSIDE_DRIVE

ILLUM_HSIDE_DRIVE

3

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

Pin Functions

NAME

I/O

DESCRIPTION

NO.

1

N/C

–

I/O

O

No connect

Connection for the DMD SMPS-inductor (low-side switch).

DRST_LS_IND

DRST_5P5V

DRST_PGND

DRST_VIN

2

3

Filter pin for LDO DMD. Power supply for internal DMD reset regulator, typical 5.5 V.

Power ground for DMD SMPS. Connect to ground plane.

4

GND

5

POWER Power supply input for LDO DMD. Connect to system power.

DRST_HS_IND

ILLUM_5P5 V

ILLUM_VIN

6

I/O

O

Connection for the DMD SMPS-inductor (high-side switch).

7

Filter pin for LDO ILLUM. Power supply for internal ILLUM block, typical 5.5 V.

8

POWER Supply input of LDO ILLUM. Connect to system power.

CH1_SWITCH

RLIM_1

9

I

Low-side MOSFET switch for LED Cathode. Connect to RGB LED assembly.

Connection to LED current sense resistor for CH1 and CH2.

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

O

I

RLIM_BOT_K_2

RLIM_K_2

Kelvin sense connection to ground side of LED current sense resistor.

Kelvin sense connection to top side of current sense resistor.

Kelvin sense connection to ground side of LED current sense resistor.

Kelvin sense connection to top side of current sense resistor.

Connection to LED current sense resistor for CH1 and CH2.

I

RLIM_BOT_K_1

RLIM_K_1

I

RLIM_1

O

I

CH2_SWITCH

CH1_GATE_CTRL

CH2_GATE_CTRL

CH3_GATE_CTRL

RLIM_2

Low-side MOSFET switch for LED cathode. Connect to RGB LED assembly.

Gate control of CH1 external MOSFET switch for LED cathode.

Gate control of CH2 external MOSFET switch for LED cathode.

Gate control of CH3 external MOSFET switch for LED cathode.

Connection to LED current sense resistor for CH3.

I

O

I

RLIM_2

Connection to LED current sense resistor for CH3.

CH3_SWITCH

ILLUM_HSIDE_DRIVE

ILLUM_LSIDE_DRIVE

Low-side MOSFET switch for LED Cathode. Connect to RGB LED assembly.

Gate control for external high-side MOSFET for ILLUM Buck converter.

Gate control for external low-side MOSFET for ILLUM Buck converter.

I

O

Supply voltage for high-side N-channel MOSFET gate driver. A 100 nF capacitor (typical)

must be connected between this pin and ILLUM_A_SW.

ILLUM_A_BOOST

28

I

ILLUM_A_FB

ILLUM_A_VIN

29

30

Input to the buck converter loop controlling I_LED.

POWER Power input to the ILLUM Driver A.

Switch node connection between high-side NFET and low-side NFET. Serves as common

connection for the flying high side FET driver.

ILLUM_A_SW

31

I/O

ILLUM_A_PGND

ILLUM_B_BOOST

ILLUM_B_VIN

32

33

34

35

36

37

38

39

40

41

42

43

44

45

GND

I

Ground connection to the ILLUM Driver A.

Supply voltage for high-side N-channel MOSFET gate driver.

POWER Power input to the ILLUM driver B.

ILLUM_B_FB

I

I/O

GND

I/O

GND

O

Input to the buck converter loop controlling I_LED.

ILLUM_B_SW

Switch node connection between high-side NFET and low-side NFET.

Ground connection to the ILLUM driver B.

Connection node for feedback loop components

Thermal pad. Connect to clean system ground.

Color wheel clock output

ILLUM_B_PGND

ILLUM_A_COMP1

ILLUM_A_COMP2

ILLUM_B_COMP1

ILLUM_B_COMP2

THERMAL_PAD

CLK_OUT

CW_SPEED_PWM_OUT

SPI_VIN

O

Color wheel PWM output

I

Supply for SPI interface

4

DLPA3000

www.ti.com.cn

ZHCSE87 –OCTOBER 2015

Pin Functions (continued)

NAME

I/O

DESCRIPTION

NO.

46

SPI_CLK

I

O

I

SPI clock input

SPI_MISO

SPI_SS_Z

SPI_MOSI

47

SPI data output

48

SPI chip select (active low)

SPI data input

49

I

Charge-pump-supply input for the high-side FET gate drive circuit. Connect 100 nF

capacitor between PWR7_BOOST and PWR7_SWITCH pins.

PWR7_BOOST

50

I

PWR7_FB

51

52

53

54

55

56

57

58

59

60

61

62

63

64

Converter feedback input. Connect to converter output voltage.

PWR7_VIN

PWR7_SWITCH

PWR7_PGND

ACMPR_LABB_SAMPLE

PROJ_ON

POWER Power supply input for converter.

I/O

Switch node connection between high-side NFET and low-side NFET.

GND

Ground pin. Power ground return for switching circuit.

Control signal to sample voltage at ACMPR_IN_LABB.

Input signal to enable/disable the IC and DLP projector.

Reset output to the DLP system (active low). Pin is held low to reset DLP system.

Interrupt output signal (open drain, active low). Connect to pull-up resistor.

Digital ground. Connect to ground plane.

I

O

RESET_Z

INT_Z

O

DGND

GND

I

CH_SEL_0

Control signal to enable either of CH1,2,3.

CH_SEL_1

I

Control signal to enable either of CH1,2,3.

PWR6_PGND

PWR6_SWITCH

PWR6_VIN

GND

I/O

Ground pin. Power ground return for switching circuit.

Switch node connection between high-side NFET and low-side NFET.

POWER Power supply input for converter.

Charge-pump-supply input for the high-side FET gate drive circuit. Connect 100 nF

capacitor between PWR6_BOOST and PWR6_SWITCH pins.

PWR6_BOOST

65

I

PWR6_FB

66

67

68

I

Converter feedback input. Connect to output voltage.

PWR5_VIN

POWER Power supply input for converter.

PWR5_SWITCH

I/O

Switch node connection between high-side NFET and low-side NFET.

Charge-pump-supply input for the high-side FET gate drive circuit. Connect 100nF

capacitor between PWR5_BOOST and PWR5_SWITCH pins.

PWR5_BOOST

69

I

PWR5_PGND

PWR5_FB

70

71

72

73

74

75

GND

Ground pin. Power ground return for switching circuit.

Converter feedback input. Connect to output voltage.

Ground pin. Power ground return for switching circuit.

Switch node connection between high-side NFET and low-side NFET.

I

PWR2_FB

PWR2_PGND

PWR2_SWITCH

PWR2_VIN

GND

I/O

POWER Power supply input for converter.

Charge-pump-supply input for the high-side FET gate drive circuit. Connect 100 nF

capacitor between PWR2_BOOST and PWR2_SWITCH pins.

PWR2_BOOST

76

I

ACMPR_IN_1

ACMPR_IN_2

ACMPR_IN_3

ACMPR_IN_LABB

ACMPR_OUT

ACMPR_REF

PWR_VIN

77

78

79

80

81

82

83

84

85

86

87

88

I

Input for analog sensor signal.

I

Input for analog sensor signal.

I

Input for ambient light sensor, sampled input

Analog comparator out

O

I

Reference voltage input for analog comparator

POWER Power supply input for LDO_Bucks. Connect to system power.

Filter pin for LDO_BUCKS. Internal analog supply for buck converters, typical 5.5 V.

POWER Input voltage supply pin for Reference system.

PWR_5P5V

VINA

O

AGND

GND

O

Analog ground pin.

PWR3_OUT

PWR3_VIN

Filter pin for LDO_2 DMD/DLPC/AUX, typical 2.5 V.

POWER Power supply input for LDO_2. Connect to system power.

5

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

Pin Functions (continued)

NAME

I/O

DESCRIPTION

NO.

89

90

91

92

93

94

95

96

PWR4_OUT

PWR4_VIN

SUP_2P5V

SUP_5P0V

PWR1_PGND

PWR1_FB

O

Filter pin for LDO_1 DMD/DLPC/AUX, typical 3.3 V.

POWER Power supply input for LDO_1. Connect to system power.

O

Filter pin for LDO_V2V5. Internal supply voltage, typical 2.5 V.

Filter pin for LDO_V5V. Internal supply voltage, typical 5 V.

Ground pin. Power ground return for switching circuit.

GND

I

Converter feedback input. Connect to output voltage.

PWR1_SWITCH

PWR1_VIN

I/O

Switch node connection between high-side NFET and low-side NFET.

POWER Power supply input for converter.

Charge-pump-supply input for the high-side FET gate drive circuit. Connect 100nF

PWR1_BOOST

97

I

capacitor between PWR1_BOOST and PWR1_SWITCH pins.

VOFS output rail. Connect to ceramic capacitor.

VBIAS output rail. Connect to ceramic capacitor.

VRESET output rail. Connect to ceramic capacitor.

DMD_VOFFSET

DMD_VBIAS

98

99

O

DMD_VRESET

100

6

DLPA3000

www.ti.com.cn

ZHCSE87 –OCTOBER 2015

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)

(1)

MIN

–0.3

–2

MAX

28

30

7

UNIT

ILLUM_A,B_BOOST

ILLUM_A,B_BOOST (10 ns transient)

ILLUM_A,B_BOOST vs ILLUM_A,B_SWITCH

ILLUM_LSIDE_DRIVE

7

ILLUM_HSIDE_DRIVE

28

7

ILLUM_A_BOOST vs ILLUM_HSIDE_DRIVE

ILLUM_A,B_SW

-0.3

–2

22

27

ILLUM_A,B_SW (10 ns transient)

–3

PWR_VIN, PWR1,2,3,4,5,6,7_VIN, VINA, ILLUM_VIN, ILLUM_A,B_VIN,

DRST_VIN

–0.3

22

PWR1,2,5,6,7_BOOST

–0.3

–2

28

30

22

27

6.5

20

7

PWR1,2,5,6,7_BOOST (10 ns transient)

PWR1,2,5,6,7_SWITCH

PWR1,2,5,6,7_SWITCH (10 ns transient)

PWR1,2,5,6,7_FB

–3

–0.3

–18

PWR1,2,5,6,7_BOOST vs PWR1,2,5,6,7_SWITCH

CH1,2,3_SWITCH, DRST_LS_IND, ILLUM_A,B_FB

ILLUM_A,B_COMP1,2, INT_Z, PROJ_ON

DRST_HS_IND

Voltage

V

7

ACMPR_IN_1,2,3, ACMPR_REF, ACMPR_IN_LABB,

ACMPR_LABB_SAMPLE, ACMPR_OUT

–0.3

3.6

SPI_VIN, SPI_CLK, SPI_MOSI, SPI_SS_Z, SPI_MISO, CH_SEL_0,1,

RESET_Z

–0.3

3.6

0.3

RLIM_K_1,2, RLIM_1,2

DGND, AGND, DRST_PGND, ILLUM_A,B_PGND, PWR1,2,5,6,7_PGND,

RLIM_BOT_K_1,2

DRST_5P5V, ILLUM_5P5V, PWR_5P5, PWR3,4_OUT, SUP_5P0V

–0.3

–18

7

CH1,2,3_GATE_CTRL

CLK_OUT

3.6

7

CW_SPEED_PWM

SUP_2P5V

3.6

12

20

7

DMD_VOFFSET

DMD_VBIAS

DMD_VRESET

RESET_Z, ACMPR_OUT

SPI_DOUT

1

Source current

mA

5.5

1

RESET_Z, ACMPR_OUT

SPI_DOUT, INT_Z

Storage temperature

Sink current

T_stg

mA

ºC

5.5

150

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽²⁾

±2000

(1)

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101,

all pins⁽³⁾

±500

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in

to the device.

(2) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

PWR_VIN, PWR1,2,3,4,5,6,7_VIN, VINA, ILLUM_VIN,

ILLUM_A,B_VIN, DRST_VIN

6

20

CH1,2,3_SWITCH, ILLUM_A,B_FB,

INT_Z, PROJ_ON

–0.1

6.3

6

PWR1,2,5,6,7_FB

5

ACMPR_REF, CH_SEL_0,1, SPI_CLK, SPI_MOSI,

SPI_SS_Z

–0.1

3.6

V_I

Input voltage

V

RLIM_BOT_K_1,2

ACMPR_IN_1,2,3, LABB_IN_LABB

SPI_VIN

–0.1

1.7

–0.1

0

0.1

1.5

3.6

RLIM_K_1,2

0.25

5.7

ILLUM_A,B_COMP1,2

T_A

T_J

Ambient temperature

70

°C

Operating junction temperature

0

120

6.4 Thermal Information

DLPA3000

THERMAL METRIC⁽¹⁾

HTQFP (PFD)

UNIT

100 PINS

7.0

(2)

(3)

R_θJA

R_θJC(top)

ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

0.7

(4)

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.6

(5)

ψ_JB

3.4

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, but

since the device is intended to be cooled with a heatsink from the top case of the package, the simulation includes a fan and heatsink

attached to the DLPA3000. The heatsink is a 22 mm × 22 mm × 12 mm aluminum pin fin heatsink with a 12 × 12 × 3 mm stud. Base

thickness is 2 mm and pin diameter is 1.5 mm with an array of 6 × 6 pins. The heatsink is attached to the DLPA3000 with 100 um thick

thermal grease with 3 W/m-K thermal conductivity. The fan is 20 × 20 × 8 mm with 1.6 cfm open volume flow rate and 0.22 in. water

pressure at stagnation.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard

test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining Rθ_JA, using a procedure described in JESD51-2a (sections 6 and 7), but modified to include the

fan and heatsink described in note 2.

(5) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining Rθ_JA, using a procedure described in JESD51-2a (sections 6 and 7), but modified to include the

fan and heatsink described in note 2.

8

DLPA3000

www.ti.com.cn

ZHCSE87 –OCTOBER 2015

6.5 Electrical Characteristics

over operating free-air temperature range. V_IN= 12 V, T_A= 0 to +70°C, typical values are at T_A= 25°C, configuration

according to Typical Applications (V_IN=12 V, I_OUT= 6 A, LED, internal FETs) (unless otherwise noted).

PARAMETER

TEST CONDITIONS

SUPPLIES

MIN

TYP

MAX UNIT

INPUT VOLTAGE

V_IN

Input voltage range

VINA – pin

6⁽¹⁾

3.9

12

20

V

Low battery warning

threshold

VINA falling (via 5 bit trim function)

18.4

V_{LOW_BAT}

Hysteresis

VINA rising

90

mV

V

UVLO threshold

Hysteresis

VINA falling (via 5 bit trim function)

VINA rising

3.9

6

18.4

V_UVLO

mV

DMD_VBIAS, DMD_VOFFSET,

DMD_VRESET loaded with 10 mA

V_STARTUP

Startup voltage

V

INPUT CURRENT

I_IDLE

Idle current

IDLE mode, all VIN pins combined

15

µA

STANDBY mode, analog, internal supplies

and LDOs enabled, DMD, ILLUMINATION

and BUCK CONVERTERS disabled.

I_STD

Standby current

3.7

mA

Quiescent current DMD block (in addtion to

I_STD) with DMD type TRP, VINA + DRST_VIN

I_{Q_DMD}

Quiescent current (DMD)

Quiescent current (ILLUM)

0.49

21

mA

Quiescent current ILLUM block (in addtion to

I_STD) in 6 A LED configuration, internal FETs,

V_openloop= 3 V (0x18, ILLUM_OLV_SEL),

VINA + ILLUM_VIN + ILLUM_A_VIN +

ILLUM_B_VIN

I_{Q_ILLUM}

Quiescent current per BUCK converter (in

addtion to I_STD), Normal mode, VINA +

PWR_VIN + PWR1,2,5,6,7_VIN,

PWR1,2,5,6,7_VOUT = 1 V

4.3

15

Quiescent current per BUCK converter (in

addtion to I_STD), Normal mode, VINA +

PWR_VIN + PWR1,2,5,6,7_VIN,

PWR1,2,5,6,7_VOUT = 5 V

Quiescent current

(per BUCK)

I_{Q_BUCK}

mA

Quiescent current per BUCK converter (in

addtion to I_STD), Cycle-skipping mode, VINA +

PWR_VIN + PWR1,2,5,6,7_VIN = 1 V

0.41

0.46

Quiescent current per BUCK converter (in

addtion to I_STD), Cycle-skipping mode, VINA +

PWR_VIN + PWR1,2,5,6,7_VIN = 5 V

Typical Application: 6 A LED, Internal FETs,

DMD type TRP. ACTIVE mode, all VIN pins

combined, DMD, ILLUMINATION and

I_{Q_TOTAL}

Quiescent current (Total)

38

mA

PWR1,2 enabled, PWR3,4,5,6,7 disabled.

INTERNAL SUPPLIES

V_{SUP_5P0V}Internal supply, analog

V_{SUP_2P5V}Internal supply, logic

5

V

2.5

(1) V_INmust be higher than the UVLO voltage setting, including after accounting for AC noise on V_IN, for the DLPA3000 to fully operate.

While 6.0 V is the min V_INvoltage supported, TI recommends that the UVLO is never set below 6.21 V. 6.21 V gives margin above 6.0 V

to protect against the case where someone suddenly removes V_IN’s power supply which causes the V_INvoltage to drop rapidly. Failure

to keep V_INabove 6.0 V before the mirrors are parked and V_OFS, V_RST, and V_BIASsupplies are properly shut down can result in

permanent damage to the DMD. Since 6.21 V is 0.21 V above 6.0 V, when UVLO trips there is time for the DLPA3000 and DLPC343x

to park the DMD mirrors and do a fast shut down of supplies V_OFS, V_RST, and V_BIAS. For whatever UVLO setting is used, if V_IN’s power

supply is suddenly removed enough bulk capacitance should be included on V_INinside the projector to keep V_INabove 6.0 V for at least

100us after UVLO trips.

9

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range. V_IN= 12 V, T_A= 0 to +70°C, typical values are at T_A= 25°C, configuration

according to Typical Applications (V_IN=12 V, I_OUT= 6 A, LED, internal FETs) (unless otherwise noted).

PARAMETER

TEST CONDITIONS

DMD - LDO DMD

MIN

TYP

MAX UNIT

V_{DRST_VIN}

6

12

5.5

20

V

V_{DRST_5P5V}

Rising

Falling

80%

60%

PGOOD

OVP

Power good DRST_5P5V

Overvoltage protection

DRST_5P5V

7.2

V

Regulator dropout

Regulator current limit⁽²⁾

At 25 mA, VDRST_VIN= 5.5 V

56

mV

mA

300

340

400

DMD - REGULATOR

Switch A (from DRST_5P5V to

DRST_HS_IND)

920

450

R_DS(ON)

MOSFET ON-resistance

Forward voltage drop

mΩ

Switch B (from DRST_LS_IND to

DRST_PGND)

Switch C (from DRST_LS_IND to

DRST_VBIAS⁽²⁾), VDRST_LS_IND = 2 V, I_F

100 mA

=

1.21

1.22

V_FW

V

Switch D (from DRST_LS_IND to

DRST_VOFFSET⁽²⁾), VDRST_LS_IND = 2 V,

I_F= 100 mA

t_DIS

Rail Discharge time

Power-good timeout

Switch current limit

C_OUT= 1 µF

40

µs

ms

mA

t_PG

Not tested in production

DMD type TRP

15

I_LIMIT

610

VOFFSET REGULATOR

V_OFFSET

Output voltage

DMD type TRP

10

V

DC output voltage accuracy

DC Load regulation

DMD type TRP, I_OUT= 10 mA

DMD type TRP, I_OUT= 0 to 10 mA

-0.3

0.3

10

–10

–5

V/A

DMD type TRP, I_OUT= 10 mA, DRST_VIN = 8

V to 20 V

DC Line regulation

mV/V

V_RIPPLE

I_OUT

Output ripple

DMD type TRP, I_OUT= 10 mA, C_OUT= 1 µF

DMD type TRP

200

mVpp

mA

Output current

0.1

1

Power-good threshold

(fraction of nominal output

voltage)

VOFFSET rising

86%

66%

PGOOD

C

VOFFSET falling

DMD type TRP, recommended value (use

same value as output capacitor on VRESET)

Output capacitor

µF

t_DISCHARGE<40 µs at VIN = 8 V

1

VBIAS REGULATOR

V_BIAS

Output voltage

DMD type TRP

18

V

DC output voltage accuracy

DC Load regulation

DMD type TRP, I_OUT= 10 mA

DMD type TRP, I_OUT= 0 to 10 mA

–0.3

0.1

0.3

–18

–3

V/A

DMD type TRP, I_OUT= 10 mA, DRST_VIN = 8

V to 20 V

DC Line regulation

mV/V

V_RIPPLE

I_OUT

Output ripple

DMD type TRP, I_OUT= 10 mA, C_OUT= 470 nF

DMD type TRP

200

mVpp

mA

Output current

10

Power-good threshold

(fraction of nominal output

voltage)

VBIAS rising

86%

66%

PGOOD

VBIAS falling

(2) Including rectifying diode.

10

DLPA3000

www.ti.com.cn

ZHCSE87 –OCTOBER 2015

Electrical Characteristics (continued)

over operating free-air temperature range. V_IN= 12 V, T_A= 0 to +70°C, typical values are at T_A= 25°C, configuration

according to Typical Applications (V_IN=12 V, I_OUT= 6 A, LED, internal FETs) (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DMD type TRP, recommended value (use

same or smaller value as output capacitors

VOFFSET / VRESET)

470

C

Output capacitor

nF

t_DISCHARGE<40 µs at VIN = 8 V

470

VRESET REGULATOR

V_RST

Output voltage

DMD type TRP

–14

V

DC output voltage accuracy

DC Load regulation

DMD type TRP, I_OUT= 10 mA

DMD type TRP, I_OUT= 0 to 10 mA

-0.3

0.3

V

–4

–2

V/A

DMD type TRP, I_OUT= 10 mA, DRST_VIN = 8

to 20 V

DC Line regulation

mV/V

V_RIPPLE

I_OUT

Output ripple

DMD type TRP, I_OUT= 10 mA, C_OUT= 1 µF

DMD type TRP

120

mVpp

mA

Output current

0.1

1

10

1

PGOOD

Power-good threshold

90%

DMD type TRP, recommended value (use

same value as output capacitor on VOFFSET)

C

Output capacitor

µF

t_DISCHARGE<40 µs at VIN = 8 V

DMD - BUCK CONVERTERS

OUTPUT VOLTAGE

V_{PWR_1_VOUT}Output Voltage

V_{PWR_2_VOUT}

DMD type TRP

1.1

1.8

V

Output Voltage

DMD type TRP

DC output voltage accuracy

DMD type TRP, I_OUT= 0 mA

–3%

3%

MOSFET

R_ON,H

High side switch resistance

Low side switch resistance⁽³⁾25°C

25°C, V_{PWR_1,2_Boost}– V_{PWR1,2_SWITCH}= 5.5 V

150

85

mΩ

R_ON,L

LOAD CURRENT

Allowed load current⁽⁴⁾

Current limit⁽³⁾

.

3

A

I_OCL

L_OUT= 3.3 μH

3.2

3.6

4.2

ON-TIME TIMER CONTROL

t_ON

On time

Minimum off time⁽³⁾

V_IN= 12 V, V_O= 5 V

T_A= 25°C, V_FB= 0 V

120

270

ns

t_OFF(MIN)

START-UP

Soft start

1

2.5

4

ms

PGOOD

Ratio_OV

Ratio_PG

Overvoltage protection

120%

72%

Relative power good level

Low to High

ILLUMINATION - LDO ILLUM

V_{ILLUM_VIN}

6

12

5.5

20

V

V_{ILLUM_5P5V}

Rising

Falling

80%

60%

PGOOD

OVP

Power good ILLUM_5P5V

Overvoltage protection

ILLUM_5P5V

7.2

V

Regulator dropout

Regulator current limit⁽³⁾

At 25 mA, V_{ILLUM_VIN}= 5.5 V

53

mV

mA

300

340

400

(3) Not production tested.

(4) Care should be taken not to exceed the max power dissipation. Please refer to Thermal Considerations.

11

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range. V_IN= 12 V, T_A= 0 to +70°C, typical values are at T_A= 25°C, configuration

according to Typical Applications (V_IN=12 V, I_OUT= 6 A, LED, internal FETs) (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

ILLUMINATION - DRIVER A,B

V_{ILLUM_A,B_IN}

PWM

Input supply voltage range

Oscillator frequency

Output driver dead time

6

12

20

V

ƒ_SW

3 V < V_IN< 20 V

600

28

kHz

ns

HDRV off to LDRV on, TRDLY = 0

HDRV off to LDRV on, TRDLY = 1

LDRV off to HDRV on, TRDLY = 0

t_DEAD

40

35

MAXIMUM CURRENTS

Internal switches, I_DSthreshold, single buck

(6 A use case).

HSD OC

High-side drive over current

9.5

A

Both directions In or Out. Internal switches,

I_DSthreshold, single buck

(6 A use case)

Low-side drive maximum

allowed current

LSD MC

BOOT DIODE

Bootstrap diode forward

voltage

V_DFWD

I_BOOT= 5 mA

0.75

89%

V

PGOOD

RatioUV

Undervoltage protection

Power FETs

POWER FETs

High-Side,T_A= 25°C, V_{ILLUM_A,B_BOOST –}

_{ILLUM_A,B_SW}= 5.5 V

150

85

R_ON

mΩ

Low-side, T_A= 25°C

RGB STROBE CONTROLLER SWITCHES

R_ON

ON-resistance

CH1,2,3_SWITCH

V_DS= 5.0 V

30

45

mΩ

I_LEAK

OFF-state leakage current

0.1

µA

LED CURRENT CONTROL

Ratio with respect to V_{ILLUM_A,B_VIN}

(Duty cycle limitation).

0.85x

V_{LED_ANODE}

LED anode voltage⁽³⁾

6.3

V

V_{ILLUM_A,B_VIN}≥ 8 V. See register

SWx_IDAC[9:0] for settings.

I_LED

LED currents

300

–75

6000

mA

DC current offset,

CH1,2,3_SWITCH

R_LIM= 25 mΩ

0

0.67

8

75

mA

A

20% higher than I_LED. Min-setting,

R_LIM= 25 mΩ.

Transient LED current limit

range (programmable)

20% higher than I_LED. Max-setting,

R_LIM= 25 mΩ.

I_LEDfrom 5% to 95%, I_LED= 300 mA, transient

t_RISE

Current rise time

50

20

µs

current limit disabled⁽³⁾

.

BUCK CONVERTERS - LDO_BUCKS

Input voltage range

PWR1,2,5,6,7_VIN

V_{PWR_VIN}

6

12

V

V_{PWR_5P5V}

PWR_5P5V

5.5

80%

60%

Rising

Falling

PGOOD

OVP

Power good PWR_5P5V

Overvoltage Protection

PWR_5P5V

7.2

V

Regulator dropout

Regulator current limit⁽²⁾

At 25 mA, V_{PWR_VIN}= 5.5 V

41

mV

mA

300

340

400

12

DLPA3000

www.ti.com.cn

ZHCSE87 –OCTOBER 2015

Electrical Characteristics (continued)

over operating free-air temperature range. V_IN= 12 V, T_A= 0 to +70°C, typical values are at T_A= 25°C, configuration

according to Typical Applications (V_IN=12 V, I_OUT= 6 A, LED, internal FETs) (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

(5)

BUCK CONVERTERS - GENERAL PURPOSE BUCK CONVERTERS

OUTPUT VOLTAGE

Output voltage (General

purpose buck1,2,3)

V_{PWR_5,6,7_VOUT}

8-bit programmable

I_OUT= 0 mA

1

5

V

DC output voltage accuracy

–3.5%

3.5%

MOSFET

R_ON,H

25°C, V_{PWR5,6,7_Boost}– V_{PWR5,6,7_SWITCH}= 5.5

V

Low side switch resistance⁽³⁾25°C

High side switch resistance

150

85

mΩ

R_ON,L

LOAD

CURRENT

Allowed load current

2

A

PWR6⁽⁴⁾

.

Allowed load current PWR5, Buck converters should not be used at this

A

PWR7⁽⁴⁾

Current limit⁽³⁾⁽⁴⁾

.

time, they will become available in the future.

I_OCL

L_OUT= 3.3 μH

3.2

3.6

4.2

ON-TIME TIMER CONTROL

t_ON

On time

Minimum off time⁽³⁾

V_IN= 12 V, V_O= 5 V

T_A= 25°C, V_FB= 0 V

120

270

ns

t_OFF(MIN)

START-UP

310

4

Soft start

1

2.5

ms

PGOOD

Ratio_OV

Ratio_PG

Overvoltage protection

120%

72%

Relative power good level

Low to high

AUXILIARY LDOs

LDO1 (PWR4), LDO2 (PWR3)

V_{PWR3,4_VIN}

PGOOD

Input voltage range

3.3

12

80%

60%

20

V

Power good PWR3,4_VOUT PWR3,4_VOUT rising

PWR3,4_VOUT falling

Overvoltage protection

PWR3,4_VOUT

OVP

7

DC output voltage accuracy

I_OUT= 0 mA

–3%

300

3%

PWR3,4_VOUT

Regulator current limit⁽³⁾

340

40

400

mA

µs

t_ON

Turn-on time

to 80% of V_OUT= PWR3 and PWR4, C= 1 µF

LDO2 (PWR3)

V_{PWR3_VOUT}

Output voltage PWR3_VOUT

Load current capability

2.5

V

200

mA

DC load regulation

PWR3_VOUT

V_OUT= 2.5 V, I_OUT= 5 to 200 mA

–70

30

mV/A

µV/V

DC line regulation

PWR3_VOUT

V_OUT= 2.5 V, I_OUT= 5 mA, PWR3_VIN = 3.3 to

20 V

LDO1 (PWR4)

V_{PWR4_VOUT}

Output voltage PWR4_VOUT

Load current capability

3.3

V

200

mA

DC load regulation

PWR4_VOUT

V_OUT= 3.3 V, I_OUT= 5 to 200 mA

–70

30

mV/A

µV/V

DC line regulation

PWR4_VOUT

V_OUT= 3.3V, I_OUT= 5 mA, PWR4_VIN= 4 to 20

V

(5) General Purpose Buck2 (PWR6) currently supported, others will be available in the future.

13

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range. V_IN= 12 V, T_A= 0 to +70°C, typical values are at T_A= 25°C, configuration

according to Typical Applications (V_IN=12 V, I_OUT= 6 A, LED, internal FETs) (unless otherwise noted).

PARAMETER

TEST CONDITIONS

At 25 mA, V_OUT= 3.3 V, V_{PWR4_VIN}= 3.3 V

MEASUREMENT SYSTEM

MIN

TYP

MAX UNIT

Regulator dropout

48

mV

AFE

AFE_GAIN[1:0] = 01

AFE_GAIN[1:0] = 10

AFE_GAIN[1:0] = 11

PGA, AFE_CAL_DIS = 1⁽³⁾

Comparator⁽³⁾

1

9.5

18

G

Amplifier gain (PGA)

V/V

–1

1

mV

V_OFS

Input referred offset voltage

Settling time

–1.5

+1.5

To 1% of final value⁽³⁾

To 0.1% of final value⁽³⁾

.

46

69

67

µs

τ_RC

.

100

Input voltage Range

ACMPR_IN_1,2,3

V_{ACMPR_IN_1,2,3}

0

1.5

V

LABB

To 1% of final value⁽³⁾

To 0.1% of final value⁽³⁾

.

4.6

7

6.6

10

τ_RC

Settling time

µs

.

Input voltage range

ACMPR_IN_LABB

V_{ACMPR_IN_LABB}

0

7

1.5

28

V

Sampling window

ACMPR_IN_LABB

Programmable per 7 µs

µs

COLOR WHEEL PWM

CLK_OUT

Clock output frequency

2.25

MHz

V

V_{CW_SPEED_PWM}Voltage range

_OUT

Average value programmable in 16 bits

0

5

CW_SPEED_PWM_OUT

DIGITAL CONTROL - LOGIC LEVELS AND TIMING CHARACTERISTICS

V_SPI

SPI supply voltage range

SPI_VIN

1.7

3.6

0.3

V

RESETZ, CMP_OUT, CLK_OUT. I_O= 0.3 mA

sink current

0

0.3 ×

V_SPI

V_OL

Output low-level

SPI_DOUT. I_O= 5 mA sink current

INTZ. I_O= 1.5 mA sink current

0.3 ×

V_SPI

0

RESETZ, CMP_OUT, CLK_OUT. I_O= 0.3 mA

source current

1.3

2.5

V_OH

Output high-level

Input low-level

V

SPI_DOUT. I_O= 5 mA source current

PROJ_ON, LED_SEL0, LED_SEL1

0.7 × V_SPI

0

V_SPI

0.4

V_IL

0.3 ×

V_SPI

SPI_CSZ, SPI_CLK, SPI_DIN

0

PROJ_ON, LED_SEL0, LED_SEL1

SPI_CSZ, SPI_CLK, SPI_DIN

V_IO= 3.3 V, any digital input pin

1.2

V_IH

Input high-level

V

0.7 × V_SPI

V_SPI

0.1

I_BIAS

Input bias current

µA

Normal SPI mode, DIG_SPI_FAST_SEL = 0,

ƒ_OSC= 9 MHz

0

36

40

SPI_CLK

SPI clock frequency⁽⁶⁾

Deglitch time

MHz

Fast SPI mode, DIG_SPI_FAST_SEL = 1,

V_SPI> 2.3 V, ƒ_OSC= 9 MHz

20

t_DEGLITCH

LED_SEL0, LED_SEL1⁽³⁾

INTERNAL OSCILLATOR

.

300

9

ns

ƒ_OSC

Oscillator frequency

Frequency accuracy

MHz

T_A= 0 to 70°C

–5%

5%

(6) Maximum depends linearly on oscillator frequency ƒ_OSC

.

14

DLPA3000

www.ti.com.cn

ZHCSE87 –OCTOBER 2015

Electrical Characteristics (continued)

over operating free-air temperature range. V_IN= 12 V, T_A= 0 to +70°C, typical values are at T_A= 25°C, configuration

according to Typical Applications (V_IN=12 V, I_OUT= 6 A, LED, internal FETs) (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

THERMAL SHUTDOWN

Thermal warning (HOT

threshold)

120

10

T_WARN

°C

Hysteresis

Thermal shutdown (TSD

threshold)

150

15

T_SHTDWN

Hysteresis

The timing parameters (SPI Timing Parameters) and the SPI timing diagram (Figure 1) are given.

6.6 SPI Timing Parameters

SPI_VIN = 3.6 V ± 5%, T_A= 0 to 70ºC, C_L= 10 pF (unless otherwise noted).

PARAMETER

Serial clock frequency

MIN

0

MAX

UNIT

MHz

ns

f_CLK

t_CLKL

t_CLKH

t_t

40

Pulse width low, SPI_CLK, 50% level

Pulse width high, SPI_CLK, 50% level

Transition time, 20% to 80% level, all signals

SPI_SS_Z falling to SPI_CLK rising, 50% level

SPI_CLK falling to SPI_CSZ rising, 50% level

SPI_MOSI data setup time, 50% level

SPI_MOSI data hold time, 50% level

10

0.2

8

ns

4

1

ns

t_CSCR

t_CFCS

t_CDS

t_CDH

t_iS

ns

7

6

ns

SPI_MISO data setup time, 50% level

SPI_MISO data hold time, 50% level

10

0

ns

t_iH

ns

t_CFDO

t_CSZ

SPI_CLK falling to SPI_MISO data valid, 50% level

SPI_CSZ rising to SPI_MISO HiZ

13

6

ns

SPI_SS_Z

SPI_CLK

t

CFCS

CSCR

CLKL

CLKH

t

CDH

CDS

SPI_MOSI

SPI_MISO

t

iH

t

CSZ

CFDO

t

iS

Ii-ù

Figure 1. SPI Timing Diagram

15

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

7 Detailed Description

7.1 Overview

The DLPA3000 is a highly integrated power management IC optimized for DLP Pico Projector systems. It is

targeting accessory applications up to several hundreds of lumen and is designed to support a wide variety of

high-current LEDs. The Projector system supports the TRP type of digital mirror device (DMD). Functional Block

Diagram shows a typical DLP Pico Projector implementation using the DLPA3000.

Part of the projector is the projector module which is an optimized combination of components consisting of for

instance DLPA3000, LEDs, DMD, DLPC chip, memory and optional sensors/fans. The front-end chip controls the

projector module. More information about the system and projector module configuration can be found in a

separate application note.

Within the DLPA3000 several blocks can be distinguished. The blocks are listed below and subsequently

discussed in detail:

1. Supply and monitoring: Creates internal supply and reference voltages and has functions such as thermal

protection and low battery warning.

2. Illumination: Block to control the light. Contains drivers, strobe decoder for the LEDs and power conversion

3. DMD: Generates voltages and their specific timing for the DMD. Contains regulators and DMD/DLPC buck

converters.

4. Buck converters: General purpose buck converters

5. Auxilairy LDOs: Fixed voltage LDOs for customer usage.

6. Measurement system: Analog front end to measure internal and external signals

7. Digital control: SPI, digital control

7.2 Functional Block Diagram

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DLPA3000

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7.3 Feature Description

7.3.1 Supply and Monitoring

This block takes care of creating several internal supply voltages and monitors correct behavior of the device.

16

DLPA3000

www.ti.com.cn

ZHCSE87 –OCTOBER 2015

Feature Description (continued)

7.3.1.1 Supply

SYSPWR is the main supply of the DLPA3000. It can range from 6V to 20V, where the typical is 12 V. At power-

up, several (internal) power supplies are started one after the other in order to make the system work correctly

(Figure 2). A sequential startup ensures that all the different blocks start in a certain order and prevent excessive

startup currents. The main control to start the DLPA3000 is the control pin “PROJ_ON”. Once set high the basic

analog circuitry is started that is needed to operate the digital and SPI interface. This circuitry is supplied by two

LDO regulators that generate 2.5 V (SUP_2P5V) and 5 V (SUP_5P0V). These regulator voltages are for internal

use only and should not be loaded by an external application. The output capacitors of those LDOs should be 2.2

µF for the 2.5 V LDO and 4.7 µF for the 5 V LDO, pin 91 and 92, respectively. Once these are up the digital core

is started, and the DLPA3000 Digital State Machine (DSM) takes over.

Subsequently, the 5.5 V LDOs for various blocks are started: PWR_5V5V, DRST_5P5V and ILLUM_5P5V. Next,

the buck converters and DMD LDOs are started (PWR_1 to PWR_4). The DLPA3000 is now awake and ready to

be controlled by the DLPC (indicated by RESET_Z going high).

Lastly, the general purpose buck converters (PWR_5 to 7) can be started (if used) as well as the regulator that

supplies the DMD. The DMD regulator generates the timing critical VOFFSET, VBIAS and VRESET supplies.

17

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

Feature Description (continued)

{ò{tíw

Lniꢂiꢁꢂed ꢃy ꢀ[t/

twhW_hb

{Üt_5t0ë

{Üt_2t5ë

ꢀ_/hw9_9b

(LbÇ9wb![ {LDb![)

tíw_5t5ë

ꢀw{Ç_5t5ë

L[[Üa_5t5ë

tíw_1

tíw_2

tíw_3

tíw_4

tíw_5

tíw_6

tíw_7

LbÇ_ù

w9{9Ç_ù

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(LbÇ9wb![ {LDb![)

ꢀaꢀ_ëhCC{9Ç

ꢀaꢀ_ë.L!{

ꢀaꢀ_ëw9{9Ç

1 to

320ms

0 to

320ms

>10ms

>5ms

Analog start

Digital state machine control only

Digital state machine & SPI control

(1)

Figure 2. Powerup Timing

(1) Arrows indicate sequence of events automatically controlled by digital state machine. Other events are initiated under SPI control.

18

DLPA3000

www.ti.com.cn

ZHCSE87 –OCTOBER 2015

Feature Description (continued)

7.3.1.2 Monitoring

Several possible faults are monitored by the DLPA3000. If a fault has occurred and what kind of fault it is can be

read in register 0x0C. Subsequently, an interrupt can be generated if such a fault occurs. The fault conditions for

which an interrupt is generated can be configured individually in register 0x0D.

7.3.1.2.1 Block Faults

Fault conditions for several supplies can be observed such as the low voltage supplies (SUPPLY_FAULT).

ILLUM_FAULT monitors correct supply and voltage levels in the illumination block and DMD_FAULT monitors a

correct functioning DMD block. The PROJ_ON_INT bit indicates if PROJ_ON was asserted.

7.3.1.2.2 Low Battery and UVLO

Monitoring is also done on the battery voltage (input supply) by the low battery warning (BAT_LOW_WARN) and

battery low shutdown (BAT_LOW_SHUT) (see Figure 3). They warn for a low V_INsupply voltage or automatically

shutdown the DLPA3000 when the V_INsupply drops below a predefined level, respectively. The threshold levels

for these fault conditions can be set from 3.9 V to 18.4 V by writing to registers 0x10<4:0> (LOWBATT) and

0x11<4:0> (BAT_LOW_SHUT_UVLO). These threshold levels have hysteresis. This hysteresis depends on the

selected threshold voltage and is depicted in Figure 4. It is recommended to set the low battery voltage higher

than the under voltage lock out such that a warning is generated before the device goes into shutdown.

ëLb!

8ꢀ

ëw9C

{ò{tíw

1µ

16ë

0x0/<3>

.!Ç_[hí_{IÜÇ

0x11<4:0>

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0x0/<2>

.!Ç_[hí_í!wb

0x10<4:0>

[hí.!ÇÇ_{9[

!Db5

86

Figure 3. Battery Voltage Monitoring

0.14

0.12

0.1

0.08

0.06

0.04

0.02

0

4

6

8

10

12

14

16

18

20

TRIM SETTING (V)

D002

Figure 4. Hysteresis on V_{LOW_BAT}and V_UVLO

19

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

Feature Description (continued)

7.3.1.2.3 Auto LED Turn Off Functionality

The PAD devices can be supplied from either a battery pack or an adapter. The PAD devices use several

warning and detection levels, as indicated in the previous paragraphs, to prevent system damage in case the

supply voltage becomes too low or even interrupted.

Interruption of the supply voltage occurs when, for instance, the adapter is switched to another mains outlet. In

case a battery pack is installed, the system power control should switch at that moment to the battery pack. A

change of supply voltage from, for instance, 20 V to 8 V can occur, and thus the OVP level (which is ratio-metric;

see Ratio Metric Overvoltage Protection) could become lower than V_LED. An OVP fault will be triggered and the

system will switch off.

The Auto_LED_Turn_Off functionality can be used to prevent the system from turning off in these circumstances.

This function disables the LEDs when the supply voltage drops below LED_AUTO_OFF_LEVEL (reg 0x18h). It is

advisable to have this level the same as the BAT_LOW_WARN level. When the Auto_LED_Turn_Off functionality

is enabled (reg 0x01h), once a supply voltage drop is detected to below LED_AUTO_OFF_LEVEL, the LEDs will

be switched off and the system should start sending lower current levels to have a lower V_LED. After start using

lower currents, the LEDs can be switched on again by disabling AUTO_LED_TURN_OFF function. As a result,

the system can continue working at the lower supply voltage using a lower intensity. The system has to monitor

the BAT_LOW_WARN status, and once the mains adapter is plugged in again (seen by BAT_LOW_WARN

being low), the Auto_LED_Turn_Off functionality can be enabled again. Now the LED currents can be restored to

their original levels from before the supply voltage drop.

7.3.1.2.4 Thermal Protection

The chip temperature is constantly monitored to prevent overheating of the device. There are two levels of fault

condition (register 0x0C). The first is to warn for overheating (TS_WARN). This is an indication that the chip

temperature raises to a critical temperature. The next level of warning is TS_SHUT. This occurs at a higher

temperature than TS_WARN and will shutdown the chip to prevent permanent damage. Both temperature faults

have hysteresis on their levels to prevent rapid switching around the temperature threshold.

7.3.2 Illumination

The illumination function includes all blocks needed to generate light for the DLP system. In order to set

accurately the current through the LEDs a control loop is used (Figure 5). The intended LED current is set via

IDAC[9:0]. The Illumination driver controls the LED anode voltage V_LEDand as a result a current will flow through

one of the LEDs. The LED current is measured via the voltage across sense resistor R_LIM. Based on the

difference between the actual and intended current, the loop controls the output of the buck converter (V_LED

)

higher or lower. Which LED conducts the current is controlled by switches P, Q, and R. The Openloop feedback

circuitry ensures that the control loop can be closed for cases when there is no path via the LED, for instance

when I_LED= 0.

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DLPA3000

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ZHCSE87 –OCTOBER 2015

Feature Description (continued)

SYSPWR

LDO

ILLUM

[

ILLUMINATION

DRIVER

100n

16V

A (B)

L_OUT

a

C_OUT

V_LED

—Openloop“

feedback

circuitry

t

wD.

{Çwh.9

59/h59w

v

w

w_[La

IDAC[0:9]

Figure 5. Illumination Control Loop

Within the illumination block, the following blocks can be distinguished:

•

Programmable gain block

LDO illum: analog supply voltage for internal illumination blocks.

Illumination driver A: primary driver using internal FETs.

Illumination driver B: secondary driver – for future purpose; will not be discussed.

RGB stobe decoder: controls the on-off rhythm of the LEDs and measures the LED current.

7.3.2.1 Programmable Gain Block

The current through the LEDs is determined by a digital number stored in the respective IDAC registers 0x03h to

0x08h. These registers determine the LED current which is measured through the sense resistor R_LIM. The

voltage across R_LIMis compared with the current setting from the IDAC registers and the loop regulates the

current to its set value.

21

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

Feature Description (continued)

L_OUT

V_LED

ILLUMINATION

Buck Converter

Gain

C_OUT

r_LED

R_WIRE

R_ON

V_RLIM

R_LIM

Figure 6. Programmable Gain Block in the Illumination Control Loop

When current is flowing through an LED, a forward voltage is built up over the LED. The LED also represents a

(low) differential resistance, which is part of the load circuit for V_LED. Together with the wire resistance (R_WIRE

and the R_ONresistance of the FET switch, a voltage divider is created with R_LIMthat is a factor in the loop gain of

the ILED control. Under normal conditions, the loop is able to produce a well-regulated LED current of up to 6 A.

)

Since this voltage divider is part of the control loop, care must be taken while designing the system.

When, for instance, two LEDs in series are connected, or when a relatively high wiring resistance is present in

the loop, the loop gain will reduce due to the extra attenuation caused by the increased series resistances of r_LED

+ R_WIRE+R_ON. As a result, the loop response time lowers. To compensate for this increased attenuation, the loop

gain can be increased by selecting a higher gain for the programmable gain block. The gain increase can be set

through register 0x25h [3:0].

Under normal circumstances, the default gain setting (00h) is sufficient. In case of a series, connection of two

LEDs setting 01h or 02h might suffice.

As discussed before, wiring resistance also impacts the control-loop performance. It is advisable to prevent

unnecessary large-wire length in the loop. Keeping wiring resistance as low as possible is good for efficiency

reasons. In case wiring resistance still impacts the response time of the loop, an appropriate setting of the gain

block can be selected. The same goes for connector resistance and PCB tracks. Keep in mind that basically

every mΩ counts. Following these precautions will help get a proper functioning of the I_LEDcurrent loop.

7.3.2.2 LDO Illum

This regulator is dedicated to the illumination block and provides an analog supply of 5.5 V to the internal

circuitry. It is recommended to use 1-µF capacitors on both the input and output of the LDO.

7.3.2.3 Illumination Driver A

The illumination driver of the DLPA3000 is a buck converter with two internal low-ohmic N-channel FETs (see

Figure 7). The theory of operation of a buck converter is explained in Understanding Buck Power Stages in

Switchmode Power Supplies (SLVA057). For proper operation, selection of the external components is very

important, especially the inductor L_OUTand the output capacitor C_OUT. For best efficiency and ripple performance,

an inductor and capacitor should be chosen with low equivalent series resistance (ESR).

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DLPA3000

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ZHCSE87 –OCTOBER 2015

Feature Description (continued)

29

ILLUM_A_FB

30 ILLUM_A_VIN

SYSPWR

ILLUM_A_BOOST

28

2x22µ

16V

L

100n

16V

ILLUMINATION

31

32

ILLUM_A_SW

DRIVER

A

V_LED

L_OUT

M

2.7µH

9A

C_OUT

2x22µ

6.3V

Low_ESR

ILLUM_A_PGND

Figure 7. Typical Illumination Driver Configuration

Several factors determine the component selection of the buck converter, such as input voltage (SYSPWR),

desired output voltage (V_LED) and the allowed output current ripple. Configuration starts with selecting the

inductor L_OUT

.

The value of the inductance of a buck power stage is selected such that the peak-to-peak ripple current flowing

in the inductor stays within a certain range. Here, the target is set to have an inductor current ripple, k_{I_RIPPLE}

,

less than 0.3 (30%). The minimum inductor value can be calculated given the input and output voltage, output

current, switching frequency of the buck converter (ƒ_SWITCH= 600 kHz) and inductor ripple of 0.3 (30%):

V_OUT

∂ (V_IN- V_OUT

)

V_IN

k_{I _ RIPPLE}∂I_OUT∂ f_SWITCH

L_OUT

=

(1)

Example: V_IN= 12 V, V_OUT= 4.3 V, I_OUT= 6 A results in an inductor value of L_OUT= 2.7 µH

Once the inductor is selected, the output capacitor C_OUTcan be determined. The value is calculated using the

fact that the frequency compensation of the illumination loop has been designed for an LC-tank resonance

frequency of 15 kHz:

1

f_RES

=

= 15kHz

2∂ p∂ L_OUT∂C_OUT

(2)

Example: C_OUT= 41.7 µF given that L_OUT= 2.7 µH. A practical value is 2 × 22 µF. Here a parallel connection of

two capacitors is chosen to lower the ESR even further.

The selected inductor and capacitor determine the output voltage ripple. The resulting output voltage ripple

V_{LED_RIPPLE}is a function of the inductor ripple k_{I_RIPPLE}, output current I_OUT, switching frequency ƒ_SWITCHand the

capacitor value C_OUT

:

k_{I_RIPPLE}∂I_OUT

V_{LED _RIPPLE}

=

8∂ f_SWITCH∂C_OUT

(3)

Example: k_{I_RIPPLE}= 0.3, I_OUT= 6 A, ƒ_SWITCH= 600 kHz and C_OUT= 44 µF results in an output voltage ripple of

V_{LED_RIPPLE}= 8.5 mVpp

As can be seen, this is a relative small ripple.

It is strongly advised to keep the capacitance value low. The larger the capacitor value the more energy is

stored. In case of a V_LEDgoing down, stored energy needs to be dissipated. This might result in a large

discharge current. For a V_LEDstep down from V₁to V₂, while the LED current was I₁. The theoretical peak

reverse current is:

23

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

Feature Description (continued)

C_OUT

2

I_2,MAX

=

´ V ²- V₂+ I ²

(

)

1

L_OUT

(4)

For the single-LED case, it is advised to keep C_OUTat maximum 44µF.

Two other components need to be selected in the buck converter. The value of the input-capacitor (pin

ILLUM_A_VIN) should be equal to or greater than the selected output capacitance C_OUT, in this case >44 µF.

The capacitor between ILLUM_A_SWITCH and ILLUM_A_BOOST is a charge pump capacitor to drive the high

side FET. The recommended value is 100 nF.

7.3.2.4 RGB Strobe Decoder

The DLPA3000 contains circuitry to sequentially control the three color-LEDs (red, green and blue). This circuitry

consists of three NMOS switches, the actual strobe decoder, and the LED current control (Figure 8). The NMOS

switches are connected to the cathode terminals of the external LED package and turn the currents through the

LEDs on and off.

From ILLUM_A_FB

From LDO_ILLUM

(V_LED

)

CH1_GATE_CTRL

CH2_GATE_CTRL

1ꢁ

20

21 CH3_GATE_CTRL

ꢁ,10

/I1_{íLÇ/I

/I2_{íLÇ/I

17,18

24,2ꢀ

t

/I3_{íLÇ/I

v

wD.

w

{Çwh.9

59/h59w

11,16 RLIM_1

RLIM_2

22,23

1ꢀ

14

RLIM_K_1

RLIM_BOT_K_1

25mꢀ

1W

13 RLIM_K_2

12 RLIM_BOT_K_2

CH_SEL_0

CH_SEL_1

60

61

From host

Figure 8. Switch Connection for a Common-Anode LED assembly

The NMOS FET’s P, Q and R are controlled by the CH_SEL_0 and CH_SEL_1 pins. CH_SEL[1:0] typically

receive a rotating code switching from RED to GREEN to BLUE and then back to RED. The relation between

CH_SEL[0:1] and which switch is closed is indicated in Table 1.

24

DLPA3000

www.ti.com.cn

ZHCSE87 –OCTOBER 2015

Feature Description (continued)

Table 1. Switch Positions for Common Anode RGB LEDs

SWITCH

Q

PINS CH_SEL[1:0

IDAC REGISTER

P

R

00

01

10

11

Open

Closed

Open

Closed

Open

Closed

N/A

0x03 and 0x04 SW1_IDAC[9:0]

0x05 and 0x06 SW2_IDAC[9:0]

0x07 and 0x08 SW3_IDAC[9:0]

Besides enabling one of the switches, CH_SEL[1:0] also selects a 10-bit current setting for the control IDAC that

is used as the set current for the LED. This set current together with the measured current through R_LIMis used

to control the illumination driver to the appropriate V_LED. The current through the 3 LEDs can be set

independently by registers 0x03 to 0x08 (Table 1).

Each current level can be set from off to 150mV/R_LIMin 1023 steps:

Led current(A) = 0 for bit value = 0

Bit value +1 150mV

Led current(A) =

∂

for bit value = 1to 1023

1024

R_LIM

(5)

The maximum current for R_LIM= 25 mΩ is thus 6 A.

7.3.2.4.1 Break Before Make (BBM)

The switching of the three LED NMOS switches (P, Q, and R) is controlled such that a switch is returned to the

OPEN position first before the subsequent switch is set to the CLOSED position (BBM). (See Figure 9.) The

dead time between opening and closing switches is controlled through the BBM register (0x0E). Switches that

already are in the CLOSED position and are to remain in the CLOSED state are not opened during the BBM

delay time.

..a deꢀd ꢁime (0x09)

t

v

w

t

Figure 9. BBM Timing

7.3.2.4.2 Openloop Voltage

Several situations exist in which the control loop for the buck converter via the LED is not present. In order to

prevent the output voltage of the buck converter to run-away, the loop is closed by means of an internal resistive

divider (see Figure 5 - Openloop feedback circuitry). Situations in which the openloop voltage control is active:

•

During the BBM period. Transitions from one LED to another implies that during the BBM time all LEDs are

off.

•

Current setting for all three LEDs is 0.

It is advised to set the openloop voltage to about the lowest LED forward voltage. The openloop voltage can be

set between 3 V and 18 V in steps of 1 V through register 0x18.

25

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

7.3.2.4.3 Transient Current Limit

Typically the forward voltages of the GREEN and BLUE diodes are close to each other (about 3 V to 5 V)

however the forward voltage of the red diode is significantly lower (2 V to 4 V). This can lead to a current spike in

the RED diode when the strobe controller switches from green or blue to red. This happens because V_LEDis

initially at a higher voltage than required to drive the red diode. DLPA3000 provides transient current limiting for

each switch to limit the current in the LEDs during the transition. The transient current limit value is controlled

through register 0x02 (ILLUM_ILIM). In a typical application it is required only for the RED diode. The value for

ILLUM_ILIM should be set at least 20% higher than the DC regulation current. Register 0x02

(ILLUM_SW_ILIM_EN) contains three bits to select which switch employs the transient current limiting feature.

The effect of the transient current limit on the LED current is shown in Figure 10.

Çrꢀnsient current

limit ꢀctive

/urrent

overshoot

L[[Üa_L[La

{í_L5!/

ÇLa9

{í_L5!/

ÇLa9

Figure 10. LED Current Without (Left) and With (Right) Transient Current Limit

7.3.2.5 Illumination Monitoring

The illumination block is continuously monitored for system failures to prevent damage to the DLPA3000 and

LEDs. Several possible failures are monitored, such as a broken control loop and a too high or too low output

voltage V_LED. The overall illumination fault bit is in register 0x0C (ILLUM_FAULT). If any of the below failures

occur, the ILLUM_FAULT bit may be set high:

•

ILLUM_BC1_PG_FAULT

ILLUM_BC1_OV_FAULT

Where PG is power good and OV is overvoltage.

7.3.2.5.1 Power Good

Both the Illumination driver and the Illumination LDO have a power good indication. The power good for the

driver indicates if the output voltage (V_LED) is within a defined window indicating that the LED current has

reached the set point. If, for some reason, the LED current cannot be controlled to the intended value, this fault

occurs. Subsequently, bit ILLUM_BC1_PG_FAULT in register 0x27 is set high. The illumination LDO output

voltage is also monitored. When the power good of the LDO is asserted, it implies that the LDO voltage is below

a pre-defined minimum of 80% (rising) or 60% (falling) edge. The power good indication for the LDO is in register

0x27 (V5V5_LDO_ILLUM_PG_FAULT).

7.3.2.5.2 Ratio Metric Overvoltage Protection

The DLPA3000 illumination driver LED outputs are protected against open circuit use. In case no LED is

connected and the PAD device is instructed to set the LED current to a specific level, the LED voltage

(ILLUM_A_FB) will quickly rise and potentially rail to VIN. This should be prevented. The OVP protection circuit

triggers once V_LEDcrosses a predefined level. As a result the DLPA3000 will be switched off.

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DLPA3000

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ZHCSE87 –OCTOBER 2015

The same protection circuit is triggered in case the supply voltage (VINA) will become too low to have the

DLPA3000 work properly given the V_LEDlevel. This protection circuit is constructed around a comparator that will

sense both the LED voltage and the V_INAsupply voltage. The fraction of the V_INAis connected to the minus input

of the comparator while the fraction of the V_LEDvoltage is connected to the plus input. Triggering occurs when

the plus input rises above the minus input and an OVP fault is set. The fraction of the VINA must be set between

1 V and 4 V to ensure proper operation of the comparator.

ILLUM_A_FB

(V_LED

VINA

)

Settings:

reg 0x19h [4:0]

reg 0x0Bh [4:0]

V_LED/ V_{LED_RATIO}

OVP_trigger

+

V_INA/ V_{INA_RATIO}

1V< V_IN-<4V

Figure 11. Ratio Metric OVP

The fraction of the ILLUM_A_FB voltage is set by the register 0x19h bits [4:0], while the setting of the fraction of

the VINA voltage is done by register 0x0Bh bits [4:0]. In general an OVP fault is set when

V_LED/V_{LED_RATIO}≥ V_INA/V_{INA_RATIO}

thus when:

V

_LED≥ V_INA× V_{LED_RATIO}/V_{INA_RATIO}

Clearly, the OVP level is ratio-metric, i.e. can be set to a fixed fraction of V_INA

For example: V_LEDshould stay below 85% of V_INA. The settings for the respective registers are:

.

•

reg 0x19h [4:0] = 01h (4.98)

reg 0x0Bh [4:0] = 07h (5.85)

The result is as follows: OVP triggers if V_LED≥ V_INA× 4.98/5.85 = 0.85 V_INA

.

Additionally, for V_{IN_RATIO}= 5.85, the V_IN-input voltage for the comparator is between 1 V and 3.4 V for a supply

voltage between 6 V and 20 V.

7.3.2.6 Load Current and Supply Voltage

The DLPA3000 is designed to be able to deliver a current up to 6 Amps to a LED light source. This maximum

current depends on the V_LEDthat is built up over the LED including all series resistances like R_ON, R_WIREand

R_LIM(see Figure 6) . The Illum Buck Converter needs some headroom to work properly. This paragraph shows

two typical situations for a fixed LED voltage and the accompanying supply voltage range for which a current of

4A or 6A can be delivered. Figure 12 shows the relation between the LED current and the supply voltage for a

fixed LED voltage of 5 V, while Figure 13 shows this relation for a LED voltage of 6.3 V. While varying the Supply

Voltage the curve shows a constant load current for a given LED voltage above the point where the control loop

can maintain a constant current, but the load current drops below the point where the loop is no longer able to

keep the current on its value set by the register. This knee-point shifts to higher supply voltage with rising

temperature.

27

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

4.5

4

6.5

6

5.5

5

3.5

V_LED=5V

4.5

4

I-LED (A) 85C

I-LED (A) 25C

I-LED (A) -30C

I-LED (A) 85C

3

2.5

2

I-LED (A) 25C

I-LED (A) -30C

3.5

3

2.5

2

V_LED=6.3V

1.5

1

1.5

1

6

6.2

6.4

SUPPLY VOLTAGE (V)

Figure 12. 4-A Led Current at V_LED= 5 V

6.6

6.8

7

7.2 7.4 7.6 7.8

8

8.2 8.4 8.6 8.8

9

SUPPLY VOLTAGE (V)

C001

C002

Figure 13. 6-A Led Current at V_LED= 6.3 V

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DLPA3000

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ZHCSE87 –OCTOBER 2015

7.3.2.7 Illumination Driver Plus Power FETS Efficiency

Figure 14 is an overview of the efficiency of the illumination driver plus power FETS for an input voltage of 12 V.

The efficiency is shown for several output voltage levels (V_LED) where the load current is swept.

Figure 15 displays the efficiency versus input voltage (V_{ILLUM_A_VIN}) at various output voltage levels (V_LED).

96

94

92

90

88

86

84

82

80

78

76

92

91

90

89

88

87

86

85

84

83

82

81

80

V_LED= 3.0V

V_LED= 4.0V

V_LED= 5.0V

V_LED= 6.0V

V_LED= 6.3V

V_LED= 3V

V_LED= 4V

V_LED= 5V

V_LED= 6V

0

0.5

1

1.5

2

2.5

I_OUT[A]

3

3.5

4

4.5

5

5.5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

ILLUM_A_VIN (V)

D001

D003

Figure 14. Illumination Driver Plus Power FETS Efficiency

(V_{ILLUM_A_IN}= 12 V)

Figure 15. Illumination Driver Plus Power FETS Efficiency

vs V_{ILLUM_A_IN}

29

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

7.3.3 DMD Supplies

This block contains all the supplies needed for the DMD and DLPC (see Figure 16). The block comprises:

•

LDO_DMD: for internal supply

DMD_HV: regulator generates high voltage supplies

Two buck converters: for DLPC/DMD voltages

ë.L!{: Çwt=18ë

ëhC{: Çwt=10ë

ëw{Ç: Çwt=-14ë

5a5 Ië

[5h 5a5

w9DÜ[!Çhw

.Ü/Y1: 5a5ꢀ5[t/ (tíw1)

.Ü/Y2: 5a5ꢀ5[t/ (tíw2)

Çwt= 1ꢁ1ë (5[t/)

Çwt= 1ꢁ8ë (5[t/ꢀ5a5)

Figure 16. DMD Supplies Blocks

The DMD supplies block is designed to work with the TRP-type DMD and the related DLPC. The TRP-type DMD

has its own set of supply voltage requirements. Besides the three high voltages, two supplies are needed for the

DMD and the related DLPC (DLPC343x-family for instance). These supplies are made by two buck converters.

The EEPROM of the DLPA3000 is factory programmed for a certain configuration, such as which buck

converters are used. Which configuration is programmed in EEPROM can be read in the capability register 0x26.

It concerns the following bits:

•

DMD_BUCK1_USE

DMD_BUCK2_USE

A description of the function of these capability bits can be found in the register map, register 0x26.

7.3.3.1 LDO DMD

This regulator is dedicated to the DMD supplies block and provides an analog supply voltage of 5.5 V to the

internal circuitry. It is recommended to use a 1-µF/16-V capacitor on the input and a 10-µF/6.3-V capacitor on the

output of the LDO assuming a battery voltage of 12 V.

7.3.3.2 DMD HV Regulator

The DMD HV regulator generates three high voltage supplies: DMD_VRESET, DMD_VBIAS and

DMD_VOFFSET (see Figure 17). The DMD HV regulator uses a switching regulator (switch A-D), where the

inductor is time shared between all three supplies. The inductor is charged up to a certain current value (current

limit) and then discharged into one of the three supplies. If not all supplies need charging, the time available will

be equally shared between those that do need charging. The recommended value for the capacitors is 1 µF for

V_RSTand V_OFS, and 470 nF for V_BIAS. The inductor value is 10 µH.

30

DLPA3000

www.ti.com.cn

ZHCSE87 –OCTOBER 2015

LDO DMD

(DRST_5P5V)

A

MBR0540T1

6 DRST_HS_IND

VRST

1µ/50V

2 DRST_LS_IND

10µH/0.7A

100 DMD_VRESET

D

C

G

DMD

HIGH VOLTAGE

REGULATOR

B

F

470n/50V

1µ/50V

4 DRST_PGND

99 DMD_VBIAS

98 DMD_VOFFSET

VBIAS

VOFS

E

Figure 17. DMD High Voltage Regulator

7.3.3.2.1 Power-Up and Power-Down Timing

The power-up and power-down sequence is important to ensure a correct operation of the DLPA3000 and to

prevent damage to the DMD. The DLPA3000 controls the correct sequencing of the DMD_VRESET,

DMD_VBIAS and DMD_VOFFSET to ensure a reliable operation of the DMD.

The general startup sequence of the supplies was described previously in Supply and Monitoring. The power-up

sequence of the high-voltage DMD lines is especially important to prevent damaging the DMD. Damage could

include, for example, that DMD mirrors get stuck or collide. A too-large delta voltage between DMD_VBIAS and

DMD_VOFFSET could cause the damage and should therefore be prevented.

After PROJ_ON is pulled high, the DMD buck converters and LDOs are powered (PWR1-4) the DMD high

voltage lines (HV) are sequentially enabled. First, DMD_VOFFSET is enabled. After

a

delay,

VOFS_STATE_DURATION (register 0x10) DMD_VBIAS is enabled. Finally, after another delay,

VBIAS_STATE_DURATION (register 0x11) DMD_VRESET is enabled. The DLPA3000 is now fully powered and

ready for starting projection.

For power down, there are two sequences: normal power down (Figure 18) and a fault fast powerdown used in

case a fault occurs (Figure 19).

In normal power-down mode, the power down is initiated after pulling PROJ_ON pin low. 25 ms after PROJ_ON

is pulled low, DMD_VBIAS and DMD_VRESET will stop regulating. 10 ms later, DMD_OFFSET will stop

regulating. When DMD_OFFSET stops regulating, RESET_Z is pulled low. 1 ms after the DMD_OFFSET stops

regulating, all three voltages are discharged. Finally, all other supplies are turned off. INT_Z remains high during

the power-down sequence since no fault occurred. During power down, it is guaranteed that the HV levels do not

violate the DMD specifications on these three lines. For this, it is important to select the capacitors such that

C_VOFFSETis equal to C_VRESETand C_VBIASis ≤ C_VOFFSET, C_VBIAS

.

The fast power-down mode (Figure 19) is started in case a fault occurs (INT_Z will be pulled low), for instance

due to overheating. The fast power-down mode can be enabled or disabled through register 0x01,

FAST_SHUTDOWN_EN. The mode is enabled by default. After the fault occurs, regulation of DMD_VBIAS and

DMD_VRESET is stopped. The time (delay) between fault and stop of regulation can be controlled through

register 0x0F (VBIAS/VRST_DELAY). The delay can be selected between 4 µs and ≈1.1 ms, where the default is

≈540 µs. A defined delay-time after the regulation stopped, all three high voltages lines are discharged and

RESET_Z is pulled low. The delay can be controlled through register 0x0F (VOFS/VRESETZ_DELAY). Delay

can be selected between 4 µs and ≈1.1ms. The default is ≈4 µs. Finally, the internal DMD_EN signal is pulled

low.

31

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

Now the DLPA3000 is in a standby state. It remains in standby state until the fault resolves. In case the fault

resolves, a restart is initiated. It starts then by powering up PWR_3 and follows the regular power up as depicted

in Figure 19. Again, for proper discharge timing and levels, the capacitors should be selected such that C_VOFFSET

is equal to C_VRESETand C_VBIASis ≤ C_VOFFSET, C_VBIAS

.

32

DLPA3000

www.ti.com.cn

ZHCSE87 –OCTOBER 2015

{ò{tíw

twhW_hb

{Üt_5t0ë

{Üt_2t5ë

Lniꢂiꢁꢂed ꢄy ꢀ[t/

ꢀ_/hw9_9b

(LbÇ9wb![ {LDb![)

tíw_5t5ë

ꢀw{Ç_5t5ë

L[[Üa_5t5ë

tíw_1

tíw_2

tíw_3

tíw_4

tíw_5

tíw_6

tíw_7

LbÇ_ù

w9{9Ç_ù

Lniꢂiꢁꢂed ꢄy

ꢀ[t/ viꢁ {tL

ꢀaꢀ_9b

(LbÇ9wb![ {LDb![)

{ꢂop

wegulꢁꢂing

ꢀaꢀ_ëhCC{9Ç

{ꢂop

wegulꢁꢂing

ꢀaꢀ_ë.L!{

ꢀaꢀ_ëw9{9Ç

{ꢂop

wegulꢁꢂing

>10ms

>5ms

25ms 10ms

1ms

ëhC{

{Ç!Ç9

ë.L!{

{Ç!Ç9

10ms 120µs

ꢀÜw!ÇLhb ꢀÜw!ÇLhb

0x10ꢃ7:5] 0x11ꢃ7:5]

Analog start

Digital state machine control only

Digital state machine & SPI control

(1) Arrows indicate sequence of events automatically controlled by digital state machine. Other events are initiated under

SPI control.

Figure 18. Power Sequence Normal Shutdown Mode

33

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

{ò{tíw

Lniꢂiꢁꢂed ꢆy ꢀ[t/

twhW_hb

{Üt_5t0ë

{Üt_2t5ë

tíw_5t5ë

ꢀw{Ç_5t5ë

L[[Üa_5t5ë

tíw_1

{upplies ꢁre noꢂ ꢂurned off,

Ünless twhW_hb is seꢂ [oꢅ

tíw_2

tíw_3

tíw_4

tíw_5

tíw_6

tíw_7

Lniꢂiꢁꢂed ꢆy

C!Ü[Ç

LbÇ_ù

w9{9Ç_ù

Lniꢂiꢁꢂed ꢆy

ꢀ[t/ viꢁ {tL

ꢀaꢀ_9b

(LbÇ9wb![ {LDb![)

ꢀaꢀ_ëhCC{9Ç

ꢀaꢀ_ë.L!{

ꢀaꢀ_ëw9{9Ç

>10ms

>5ms

ëhC{ ëhC{ ëhC{

ꢀelꢁy ꢀelꢁy ꢀelꢁy

ë.L!{

ꢀelꢁy

0x0C

ëhC{

{Ç!Ç9

ꢀÜw!ÇLhb ꢀÜw!ÇLhb

0x10ꢃ7:5] 0x11ꢃ7:5]

ë.L!{

{Ç!Ç9

120µs

0x0C

ꢃ7:4]

0x0C

ꢃ7:4]

0x0C

ꢃ7:4]

ꢃ3:0]

Analog start

Digital state machine control only

Digital state machine & SPI control

Ln cꢁse fꢁulꢂ resolves

(LbÇ_ù remꢁins loꢅ unꢂil cleꢁred)

A. Arrows indicate sequence of events automatically controlled by digital state machine. Other events are initiated under

SPI control.

Figure 19. Power Sequence Fault Fast Shutdown Mode

34

DLPA3000

www.ti.com.cn

ZHCSE87 –OCTOBER 2015

7.3.3.3 DMD/DLPC Buck Converters

Each of the two DMD buck converters creates a supply voltage for the DMD and/or the DLPC. The values of the

voltages for the TRP-type of DMD and DLPC used, for instance:

•

TRP DMD+DLPC3438: 1.1 V (DLPC) and 1.8 V (DLPC/DMD)

The topology of the buck converters is the same as the general purpose buck converters discussed later in this

document. To configure the inductor and capacitor, see Buck Converters.

A typical configuration is 3.3 µH for the inductor and 2 × 22 µF for the output capacitor.

97 PWR1_BOOST

100n

6.3V

96

95

PWR1_VIN

SYSPWR

H

I

2x10µ

16V

R_SN1

C_SN1

PWR1_SWITCH

DMD/DLPC

PWR1

3.3µH

3A

PWR1_PGND

PWR1_FB

93

94

V_DMD-DLPC-1

2x22µ

6.3V

Low_ESR

76 PWR2_BOOST

100n

6.3V

75

74

PWR2_VIN

SYSPWR

J

2x10µ

16V

R_SN2

C_SN2

PWR2_SWITCH

DMD/DLPC

PWR2

K

3.3µH

3A

PWR2_PGND

PWR2_FB

73

72

V_DMD-DLPC-2

2x22µ

6.3V

Low_ESR

Figure 20. DMD/DLPC Buck Converters

35

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

7.3.3.4 DMD Monitoring

The DMD block is continuously monitored for failures to prevent damage to the DLPA3000 and/or the DMD.

Several possible failures are monitored such that the DMD voltages can be guaranteed. Failures could be, for

instance, a broken control loop or a too-high or too-low converter output voltage. The overall DMD fault bit is in

register 0x0C, DMD_FAULT. If any of the failures in Table 2 occur, the DMD_FAULT bit will be set high.

Table 2. DMD FAULT Indication

POWER GOOD (REGISTER 0x29)

BLOCK

HV Regulator

REGISTER BIT

THRESHOLD

DMD_RESET: 90%,

DMD_PG_FAULT

DMD_OFFSET and DMD_VBIAS: 86% rising, 66% falling

PWR1

PWR2

BUCK_DMD1_PG_FAULT

BUCK_DMD2_PG_FAULT

Ratio: 72%

LDO_GP2_PG_FAULT /

LDO_DMD1_PG_ FAULT

PWR3 (LDO_2)

PWR4 (LDO_1)

80% rising, 60% falling

LDO_GP1_PG_FAULT /

LDO_DMD1_PG_ FAULT

OVER-VOLTAGE (REGISTER 0x2A)

BLOCK

REGISTER BIT

BUCK_DMD1_OV_FAULT

BUCK_DMD2_OV_FAULT

THRESHOLD (V)

PWR1

PWR2

Ratio: 120%

LDO_GP2_OV_FAULT /

LDO_DMD1_OV_FAULT

PWR3 (LDO_2)

PWR4 (LDO_1)

7

LDO_GP1_OV_FAULT /

LDO_DMD1_OV_FAULT

7.3.3.4.1 Power Good

The DMD HV regulator, DMD buck converters, DMD LDOs and the LDO_DMD that supports the HV regulator, all

have a power good indication.

The DMD HV regulator is continuously monitored to check if the output rails DMD_RESET, DMD_VOFFSET and

DMD_VBIAS are in regulation. If either one of the output rails drops out of regulation (for example, due to a

shorted output or overloading), the DMD_ PG_FAULT bit in register 0x29 is set. The threshold for DMD_RESET

is 90% and the thresholds for DMD_OFFSET and DMD_VBIAS are 86% (rising edge) and 66% (falling edge).

The power good signal for the two DMD buck converters indicate if their output voltage (PWR1_FB and

PWR2_FB) are within a defined window. The relative power good ratio is 72%. This means that if the output

voltage is below 72% of the set output voltage, the power good bit is asserted. The power good bits are in

register 0x29, BUCK_DMD1_PG_FAULT and BUCK_DMD2_PG_FAULT.

DMD_LDO1 and DMD_LDO2 output voltages are also monitored. When the power good fault of the LDO is

asserted, it implies that the LDO voltage is below 80% (rising edge) or 60% (falling edge) of its intended value.

The power good indication for the LDOs is in register 0x29, LDO_GP1_PG_FAULT / LDO_DMD1_PG_FAULT

and LDO_GP2_PG_FAULT / LDO_DMD2_PG_FAULT.

The LDO_DMD used for the DMD HV regulator has its own power good signaling. The power good fault of the

LDO_DMD is asserted if the LDO voltage is below 80% (rising edge) or 60% (falling edge) of its intended value.

The power good indication for this LDO is in register 0x29, V5V5_LDO_DMD_PG_FAULT.

7.3.3.4.2 Overvoltage Fault

An overvoltage fault occurs when an output voltage rises above a pre-defined threshold. Overvoltage faults are

indicated for the DMD buck converters, DMD LDOs and the LDO_DMD supporting the DMD HV regulator. The

overvoltage fault of LDO1 and LDO2 are not incorporated in the overall DMD_FAULT when the LDOs are used

as general purpose LDOs. Table 2 provides an overview of the possible DMD overvoltage faults and their

threshold levels.

36

DLPA3000

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ZHCSE87 –OCTOBER 2015

7.3.4 Buck Converters

The DLPA3000 contains three general purpose buck converters and a supporting LDO (LDO_BUCKS). The

three programmable 8-bit buck converters can generate a voltage between 1 V and 5 V and have an output

current limit of 3 A. One of the buck converters and the LDO_BUCKS is depicted in Figure 21.

The two DMD/DLPC buck converters discussed earlier in the DMD section have the same architecture as these

three buck converters and can be configured in the same way.

1µ/16V

PWR_VIN

83

84

SYSPWR

LDO

BUCKS

PWR_5P5V

1µ/6.3V

PWRx_BOOST

PWRx_VIN

100n

6.3V

SYSPWR

2x10µ

16V

R_SNx

C_SNx

PWRx_SWITCH

General Purpose

BUCKx

L_OUT

3.3µH

3A

PWRx_PGND

PWRx_FB

V_OUT

C_OUT

2x22µ

6.3V

Low_ESR

Figure 21. Buck Converter

7.3.4.1 LDO Bucks

This regulator supports the 3 general purpose buck converters and the two DMD/DLPC buck converters and

provides an analog voltage of 5.5 V to the internal circuitry. It is recommended to use a 1 µF/16 V capacitor on

the input and a 1 µF/6.3 V capacitor on the output of the LDO.

7.3.4.2 General Purpose Buck Converters

The three buck converters are for general purpose usage (Figure 21). Each of the converters can be enabled or

disabled through register 0x01 bit:

•

BUCK_GP1_EN

BUCK_GP2_EN

BUCK_GP3_EN

The output voltages of the converters are configurable between 1 V and 5 V with an 8-bit resolution. This can be

done through registers 0x13, 0x14, and 0x15.

General Purpose Buck2 (PWR6) has a current capability of 2 A. Other General Purpose Buck converters (PWR5,

7) are not supported at this time; they will become available in the future.

37

DLPA3000

ZHCSE87 –OCTOBER 2015

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The buck converters can operate in two switching modes: normal (600-kHz switching frequency) mode and the

skip mode. The skip mode is designed to increase light load efficiency. As the output current decreases from

heavy load condition, the inductor current is also reduced and eventually comes to point that its rippled valley

touches zero level, which is the boundary between continuous conduction and discontinuous conduction modes.

The rectifying MOSFET is turned off when its zero inductor current is detected. As the load current further

decreases, the converter runs into discontinuous conduction mode. The on-time is kept almost the same as it

was in the continuous conduction mode so that it takes longer time to discharge the output capacitor with smaller

load current to the level of the reference voltage. The skip mode can be enabled or disabled per buck converter

in register 0x16.

The theory of operation of a buck converter is explained in Understanding Buck Power Stages in Switchmode

Power Supplies (SLVA057). This section will therefore be limited to the component selection. For proper

operation, selection of the external components is very important, especially the inductor L_OUTand the output

capacitor C_OUT. For best efficiency and ripple performance, an inductor and capacitor should be chosen with low

equivalent series resistance (ESR).

The component selection of the buck converter is mainly determined by the output voltage. Table 3 shows the

recommended value for inductor L_OUTand capacitor C_OUTfor a given output voltage.

Table 3. Recommended Buck Converter L_OUTand C_OUT

L_OUT(µH)

TYP

C_OUT(µF)

V_OUT(V)

MIN

1.5

2.2

3.3

MAX

4.7

MIN

22

MAX

68

1 - 1.5

1.5 - 3.3

3.3 - 5

2.2

3.3

4.7

22

68

4.7

22

68

The inductor peak-to-peak ripple current, peak current, and RMS current can be calculated using Equation 6,

Equation 7, and Equation 8 respectively. The inductor saturation current rating must be greater than the

calculated peak current. Likewise, the RMS or heating current rating of the inductor must be greater than the

calculated RMS current. The switching frequency of the buck converter is approximately 600 kHz (ƒ_SWITCH).

V_OUT

∂(V_{IN _MAX}- V_OUT

)

V

IN _MAX

I_{L _OUT _RIPPLE _P-P}

=

L_OUT∂ f_SWITCH

(6)

(7)

I_{L _ OUT _RIPPLE _P-P}

I_{L _ OUT _PEAK}= I_{L _ OUT}

+

2

1

2

I_{L _OUT(RMS)}= I_{L _OUT}

+

∂I_{L _OUT _RIPPLE_P-P}

12

(8)

The capacitor value and ESR determines the level of output voltage ripple. The buck converter is intended for

use with ceramic or other low ESR capacitors. Recommended values range from 22 to 68 μF. Equation 9 can be

used to determine the required RMS current rating for the output capacitor.

V_OUT∂(V_IN- V_OUT

12 ∂ V_IN∂L_OUT∂ f_SWITCH

Two other components need to be selected in the buck converter configuration. The value of the input-capacitor

(pin PWRx_VIN) should be equal or greater than halve the selected output capacitance C_OUT. In this case C_IN

)

I_{C_OUT(RMS)}

=

(9)

2

× 10 µF is sufficient. The capacitor between PWRx_SWITCH and PWRx_BOOST is a charge pump capacitor to

drive the high side FET. The recommended value is 100 nF.

Since the switching edges of the buck converter are relatively fast, voltage overshoot and ringing can become a

problem. To overcome this problem a snubber network is used. The snubber circuit consists of a resistor and

capacitor that are connected in series from the switch node to ground. The snubber circuit is used to damp the

parasitic inductances and capacitances during the switching transitions. This circuit reduces the ringing voltage

and also reduces the number of ringing cycles. The snubber network is formed by RSNx and CSNx. More

information on controlling switch-node ringing in synchronous buck converters and configuring the snubber can

be found in Analog Application Journal 2Q 2012 (SLYT464).

38

DLPA3000

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ZHCSE87 –OCTOBER 2015

7.3.4.3 Buck Converter Monitoring

The buck converter block is continuously monitored for system failures to prevent damage to the DLPA3000 and

peripherals. Several possible failures are monitored such as a too-high or too-low output voltage. The possible

faults are summarized in Table 4.

Table 4. Buck Converter Fault Indication

POWER GOOD (REGISTER 0X27)

BLOCK

REGISTER BIT

BUCK_GP1_PG_FAULT

BUCK_GP2_PG_FAULT

BUCK_GP3_PG_FAULT

THRESHOLD (RISING EDGE)

Gen.Buck1

Gen.Buck2

Gen.Buck3

Ratio 72%

OVERVOLTAGE (REGISTER 0X28)

Gen.Buck1

Gen.Buck2

Gen.Buck3

BUCK_GP1_OV_FAULT

Ratio 120%

BUCK_GP2_OV_FAULT

BUCK_GP3_OV_FAULT

7.3.4.3.1 Power Good

The buck converters as well as the supporting LDO_BUCK have a power good indication. Each buck converter

has a separate indication.

The power good for the three buck converters indicate if their output voltage (PWR5,6,7_FB) is within a defined

window. The relative power good ratio is 72%. This means that if the output voltage is below 72% of the set

voltage the PG_fault bit is set high. The power good bits of the buck converters are in register 0x27 bit:

•

BUCK_GP1_PG_FAULT for BUCK1 (PWR5)

BUCK_GP2_PG_FAULT for BUCK2 (PWR6)

BUCK_GP3_PG_FAULT for BUCK3 (PWR7)

The LDO_BUCKS that supports the buck converters has its own power good indication. The power good of the

LDO_BUCKS is asserted if the LDO voltage is below 80% (rising edge) or 60% (falling edge) of its intended

value. The power good indication for the LDO_BUCKS is in register 0x29, V5V5_LDO_BUCK_PG_FAULT.

7.3.4.3.2 Overvoltage Fault

An overvoltage fault occurs when an output voltage rises above a pre-defined threshold. Overvoltage faults are

indicated for the buck converters, and LDO_BUCKS. The overvoltage fault of the LDO_BUCKS is asserted if the

LDO voltage is above 7.2 V and can be found in register 0x2A, V5V5_LDO_BUCK_OV_FAULT. The overvoltage

of the general purpose buck converters is 120% of the set value and can be read through register 0x28,

BUCK_GP1,2,3_OV_FAULT.

39

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

7.3.4.4 Buck Converter Efficiency

An overview of the efficiency of the buck converter for an input voltage of 12 V is provided in Figure 22. The

efficiency is shown for several output voltage levels where the load current is swept.

Figure 23 depicts the buck converter efficiency versus input voltage (V_IN) for a load current (I_OUT) of 1 A for

various output voltage levels (V_OUT).

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

V_OUT= 1V

V_OUT= 2V

V_OUT= 3V

V_OUT= 4V

V_OUT= 5V

V_OUT= 1V

V_OUT= 2V

V_OUT= 3V

V_OUT= 4V

V_OUT= 5V

0

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7

I_OUT(A)

3

3.3

6

8

10

12

14

16

18

20

V_IN(V)

D001

Figure 22. Buck Converter Efficiency vs I_OUT(V_IN= 12 V)

Figure 23. Buck Converter Efficiency vs V_IN(I_OUT= 1 A)

40

DLPA3000

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ZHCSE87 –OCTOBER 2015

7.3.5 Auxiliary LDOs

LDO_1 and LDO_2 are the two auxiliary LDOs that can freely be used by an additional external application. All

other LDOs are for internal usage only and should not be loaded. LDO1 (PWR4) is a fixed voltage of 3.3 V, while

LDO2 (PWR3) is a fixed voltage of 2.5 V. Both LDOs are capable to deliver 200 mA.

7.3.6 Measurement System

The measurement system (Figure 24) is designed to sense internal and external nodes and convert them to

digital by the implemented AFE comparator. The AFE can be enabled through register 0x0A, AFE_EN. The

reference signal for this comparator, ACMPR_REF, is a low pass filtered PWM signal coming from the DLPC. To

be able to cover a wide range of input signals, a variable gain amplifier (VGA) is added with 3 gain settings (1x,

9.5x, and 18x). The gain of the VGA can be set through register 0x0A, AFE_GAIN. The maximum input voltage

of the VGA is 1.5 V. However, some of the internal voltages are too large to be handled by the VGA and are

divided down first.

ACMPR_REF

82

From host

SYSPWR/xx

ILLUM_A_FB/xx

ILLUM_B_FB/xx

CH1_SWITCH

CH2_SWITCH

CH3_SWITCH

RLIM_K1

RLIM_K2

VREF_1V2

MUX

81 ACMPR_OUT

VOTS

VPROG1/12

VPROG2/12

V_LABB

To host

ACMPR_IN_LABB

80

55

S/H

ACMPR_IN_1

ACMPR_IN_2

ACMPR_IN_3

ACMPR_LABB_SAMPLE

AFE

AFE_SEL[3:0] AFE_GAIN [1:0]

ACMPR_IN_1

77

From light sensor

ACMPR_IN_2 78

ACMPR_IN_3 79

From temperature sensor

Figure 24. Measurement System

The multiplexer (MUX) connects to a wide range of nodes. Selection of the MUX input can be done through

register 0x0A, AFE_SEL. Signals that can be selected:

•

System input voltage, SYSPWR

LED anode cathode voltage, ILLUM_A_FB

LED cathode voltage, CHx_SWITCH

V_R_LIMto measure LED current

Internal reference, VREF_1V2

Die temperature represented by voltage VOTS

EEPROM programming voltage, VPROG1,2/12

LABB sensor, V_LABB

External sense pins, ACMPR_IN_1,2,3

The system input voltage SYSPWR can be measured by selecting the SYSPWR/xx input of the MUX. Before the

system input voltage is supplied to the MUX, the voltage needs to be divided. This is because the variable gain

amplifier (VGA) can handle voltages up to 1.5 V, whereas the system voltage can be as high as 20 V. The

division is done internally in the DLPA3000. The division factor selection (VI_Ndivision factor) is combined with the

AUTO_LED_TURN_OFF functionality of the illumination driver and can be set through register 0x18,

ILLUM_LED_AUTO_OFF_SEL.

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The LED voltages can be monitored by measuring both the common anode of the LEDs as well as the cathode

of each LED individually. The LED anode voltage (V_LED) is measured by sensing the feedback pin of the

illumination driver (ILLUM_A_FB). Like the SYSPWR, the LED anode voltage needs to be divided before feeding

it to the MUX. The division factor is combined with the overvoltage fault level of the illumination driver and can be

set through register 0x19, VLED_OVP_VLED_RATIO. The cathode voltages CH1,2,3_SWITCH are fed directly

to the MUX without division factor.

The LED current can be determined by knowing the value of sense resistor R_LIMand the voltage across the

resistor. The voltage at the top-side of the sense resistor can be measured by selecting MUX-input RLIM_K1.

The bottom-side of the resistor is connected to GND.

VOTS is connected to an on-chip temperature sensor. The voltage is a measure for the junction temperature of

the chip: Temperature (°C) = 300 × VOTS (V) –270

For storage of trim bits, but also for the USER EEPROM bytes (0x30 to 0x35), the DLPA3000 has two EEPROM

blocks. The programming voltage of EEPROM block 1 and 2 can be measured through MUX input VPROG1/12

and VPROGR2/12, respectively. The EEPROM programming voltage is divided by 12 before it is supplied to the

MUX to prevent a too-large voltage on the MUX input. The EEPROM programming voltage is ≈12 V.

LABB is a feature that stands for Local Area Brightness Boost. LABB locally increases the brightness while

maintaining good contrast and saturation. The sensor needed for this feature should be connected to pin

ACMPR_IN_LABB. The light sensor signal is sampled and held such that it can be read independently of the

sensor timing. To use this feature, it should be ensured that:

•

The AFE block is enabled (0x0A, AFE_EN = 1)

The LABB input is selected (0x0A, AFE_SEL<3:0>=3h)

The AFE gain is set appropriately to have AFE_Gain x VLABB < 1.5 V (0x0A, AFE_GAIN<1:0>)

Sampling of the signal can be done through one of the following methods:

1. Writing to register 0x0B by specifying the sample time window (TSAMPLE_SEL) and set bit

SAMPLE_LABB=1 to start sampling. The SAMPLE_LABB bit in register 0x0B is automatically reset to 0 at

the end of the sample period to be ready for a next sample request.

2. Use the input ACMPR_LABB_SAMPLE-pin as a sample signal. As long as this signal is high, the signal on

ACMPR_IN_LABB is tracked. Once the ACMP_LABB_SAMPLE is set low again, the value at that moment

will be held.

ACMPR_IN_1,2,3 can measure external signals from for instance a light sensor or a temperature sensor. It

should be ensured that the voltage on the input does not exceed 1.5 V.

7.3.7 Digital Control

This section discusses the serial protocol interface (SPI) of the DLPA3000, as well as the interrupt handling,

device shutdown, and register protection.

7.3.7.1 SPI

The DLPA3000 provides a 4-wire SPI port that supports two SPI clock frequency modes: 0 MHz to 36 MHz, and

20 MHz to 40MHz. The clock frequency mode can be set in register 0x17, DIG_SPI_FAST_SEL. The interface

supports both read and write operations. The SPI_SS_Z input serves as the active low chip select for the SPI

port. The SPI_SS_Z input must be forced low for writing to or reading from registers. When SPI_SS_Z is forced

high, the data at the SPI_MOSI input is ignored, and the SPI_MISO output is forced to a high-impedance state.

The SPI_MOSI input serves as the serial data input for the port; the SPI_MISO output serves as the serial data

output. The SPI_CLK input serves as the serial data clock for both the input and output data. Data at the

SPI_MOSI input is latched on the rising edge of SPI_CLK, while data is clocked out of the SPI_MISO output on

the falling edge of SPI_CLK. Figure 25 illustrates the SPI port protocol. Byte 0 is referred to as the command

byte, where the most significant bit is the write/not-read bit. For the W/nR bit, a 1 indicates a write operation,

while a 0 indicates a read operation. The remaining seven bits of the command byte are the register address

targeted by the write or read operation. The SPI port supports write and read operations for multiple sequential

register addresses through the implementation of an auto-increment mode. As shown in Figure 25, the auto-

increment mode is invoked by simply holding the SPI_SS_Z input low for multiple data bytes. The register

address is automatically incremented after each data byte transferred, starting with the address specified by the

command byte. After reaching address 0x7Fh, the address pointer jumps back to 0x00h.

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Set SPI_CS_Z=1 here to write/read one register location

Hold SPI_CS_Z=0 to enable auto-increment mode

SPI_SS_Z

Header

Register Data (write)

SPI_MOSI

SPI_MISO

SPI_CLK

Byte0

Byte1

Byte2

Byte3

ByteN

Register Data (read)

Data for A[6:0]

Data for A[6:0]+1

Data for A[6:0]+(N-2)

Byte0

Set high for write, low for read

Byte1 <un-used address space>

SPI_MOSI

SPI_CLK

W/nR

A6

A5

A4

A3

A2

A1

A0

N7

N6

N5

N4

N3

N2

N1

N0

Register Address

Figure 25. SPI Protocol

7.3.7.2 Interrupt

The DLPA3000 has the capability to flag for several faults in the system, such as overheating, low battery, power

good, and overvoltage faults. If a certain fault condition occurs, one or more bits in the interrupt register (0x0C)

will be set. The setting of a bit in register 0x0C will trigger an interrupt event, which will pulldown the INT_Z pin.

Interrupts can be masked by setting the respective MASK bits in register 0x0D. Setting a MASK bit will prevent

that the INT_Z is pulled low for the particular fault condition. Some high-level faults are composed of multiple

low-level faults. The high-level faults can be read in register 0x0C, while the lower-level faults can be read in

registers 0x027 through 0x2A. An overview of the faults and how they are related is given in Table 5.

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Table 5. Interrupt Registers

HIGH-LEVEL

MID-LEVEL

LOW-LEVEL

DMD_PG_FAULT

BUCK_DMD1_PG_FAULT

BUCK_DMD1_OV_FAULT

BUCK_DMD2_PG_FAULT

BUCK_DMD2_OV_FAULT

DMD_FAULT

LDO_GP1_PG_FAULT / LDO_DMD1_PG_FAULT

LDO_GP1_OV_FAULT / LDO_DMD1_OV_FAULT

LDO_GP2_PG_FAULT / LDO_DMD2_PG_FAULT

LDO_GP2_OV_FAULT / LDO_DMD2_OV_FAULT

SUPPLY_FAULT

BUCK_GP1_PG_FAULT

BUCK_GP1_OV_FAULT

BUCK_GP2_PG_FAULT

BUCK_GP2_OV_FAULT

BUCK_GP3_PG_FAULT

BUCK_GP3_OV_FAULT

ILLUM_BC1_PG_FAULT

ILLUM_BC1_OV_FAULT

ILLUM_BC2_PG_FAULT

ILLUM_BC2_OV_FAULT

ILLUM_FAULT

PROJ_ON_INT

BAT_LOW_SHUT

BAT_LOW_WARN

TS_SHUT

TS_WARN

7.3.7.3 Fast-Shutdown in Case of Fault

The DLPA3000 has two shutdown modes: a normal shutdown initiated after pulling PROJ_ON level low, and a

fast power-down mode. The fast power-down feature can be enabled or disabled through register 0x01,

FAST_SHUTDOWN_EN. By default, the mode is enabled.

When the fast power-down feature is enabled, a fast shutdown is initiated for specific faults. This shutdown

happens autonomously from the DLPC. The DLPA3000 enters the fast shutdown mode only for specific faults,

thus not for all the faults flagged by the DLPA3000. The faults for which the DLPA3000 goes into fast-shutdown

are listed in Table 6.

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Table 6. Faults hat Trigger a Fast-Shutdown

HIGH-LEVEL

LOW-LEVEL

BAT_LOW_SHUT

TS_SHUT

DMD_PG_FAULT

BUCK_DMD1_PG_FAULT

BUCK_DMD1_OV_FAULT

BUCK_DMD2_PG_FAULT

DMD_FAULT

BUCK_DMD2_OV_FAULT

LDO_GP1_PG_FAULT / LDO_DMD1_PG_FAULT

LDO_GP1_OV_FAULT / LDO_DMD1_OV_FAULT

LDO_GP2_PG_FAULT / LDO_DMD2_PG_FAULT

LDO_GP2_OV_FAULT / LDO_DMD2_OV_FAULT

ILLUM_BC1_OV_FAULT

ILLUM_FAULT

ILLUM_BC2_OV_FAULT

7.3.7.4 Protected Registers

By default, all regular USER registers are writable, except for the READ ONLY registers. Registers can be

protected though to prevent accidental write operations. By enabling the protecting, only USER registers 0x02

through 0x09 are writable. Protection can be enabled/ disabled through register 0x2F, PROTECT_USER_REG.

7.3.7.5 Writing to EEPROM

The DLPA3000 has an EEPROM mainly intended for default settings and factory trimming parameters. Registers

0x30 through 0x35 can freely be used for customer convenience, though, to write a serial number or version

information for instance. Writing to EEPROM requires a couple of steps. First, the EEPROM needs to be

unlocked. Unlock the EEPROM by writing 0xBAh to register 0x2E followed by writing 0xBE to the same register.

Both writes must be consecutive; in other words, there must be no other read or write operation in between

sending these two bytes. Once the password has been successfully written, registers 0x30h through 0x35h are

unlocked and can be write-accessed using the regular SPI protocol. They remain unlocked until any byte other

than 0xBABE is written to PASSWORD register 0x2E or the part is power-cycled. To permanently store the

written data in EEPROM, write a 1 to register 0x2F, EEPROM_PROGRAM, more than 250 ms later, followed by

writing a 0 to the same register.

To check if the registers are unlocked, read back the PASSWORD register 0x2E. If the data returned is 0x00h,

the registers are locked. If the PASSWORD register returns 0x01h, the registers are unlocked.

7.4 Device Functional Modes

Table 7. Modes of Operation

MODE

DESCRIPTION

This is the lowest-power mode of operation. All power functions are turned off, registers are reset to their default values, and

the IC does not respond to SPI commands. RESET_Z pin is pulled low. The IC will enter OFF mode whenever the PROJ_ON

pin is low.

OFF

The DMD regulators and LED power (V_LED) are turned off, but the IC does respond to the SPI. The device enters WAIT mode

whenever PROJ_ON is set high, DMD_EN⁽¹⁾bit is set to 0 or a FAULT is resolved.

WAIT

The device also enters STANDBY mode when a fault condition is detected. ⁽²⁾(See Interrupt). Once the fault condition is

resolved, WAIT mode is entered.

STANDBY

ACTIVE1

ACTIVE2

The DMD supplies are enabled but LED power (V_LED) is disabled. PROJ_ON pin must be high, DMD_EN bit must be set to 1,

and ILLUM_EN⁽³⁾bit is set to 0.

DMD supplies and LED power are enabled. PROJ_ON pin must be high and DMD_EN and ILLUM_EN bits must both be set

to 1.

(1) Settings can be done through register 0x01

(2) Power-good faults, overvoltage, over-temperature shutdown, and undervoltage lockout

(3) Settings can be done through register 0x01, bit is named ILLUM_EN

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Table 8. Device State as a Function of Control-Pin Status

PROJ_ON Pin

STATE

LOW

OFF

WAIT

STANDBY

ACTIVE1

ACTIVE2

HIGH

(Device state depends on DMD_EN and ILLUM_EN bits and whether there are any fault

conditions.)

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POWERDOWN

VRESET = OFF

VBIAS = OFF

VOFFSET = OFF

VLED = OFF

Valid power source connected

PROJ_ON = low

OFF

SPI interface disabled

D_CORE_EN = low

RESET_Z = low

All registers set to default values

PROJ_ON = high

VRESET = OFF

VBIAS = OFF

VOFFSET = OFF

VLED = OFF

SPI interface enabled

D_CORE_EN = high

RESET_Z = high

DMD_EN = 0

||

PROJ_ON = low

FAULT = 0

WAIT

VRESET = OFF

VBIAS = OFF

VOFFSET = OFF

VLED = OFF

SPI interface enabled

D_CORE_EN = high

RESET_Z = low

DMD_EN = 1

FAULT = 0

STANDBY

&

DMD_EN = 0

||

VRESET = ON

VBIAS = ON

VOFFSET = ON

VLED = OFF

PROJ_ON = low

FAULT = 1

ACTIVE 1

SPI interface enabled

D_CORE_EN = high

RESET_Z = high

VLED_EN = 1

VLED_EN = 0

VRESET = ON

VBIAS = ON

VOFFSET = ON

VLED = ON

DMD_EN = 0

||

PROJ_ON = low

FAULT = 1

ACTIVE 2

SPI interface enabled

D_CORE_EN = high

RESET_Z = high

A. || = OR, & = AND

B. FAULT = Undervoltage on any supply, thermal shutdown, or UVLO detection

C. UVLO detection, per the diagram, causes the DLPA3000 to go into the standby state. This is not the lowest power

state. If lower power is desired, PROJ_ON should be set low.

D. DMD_EN register bit can be reset or set by SPI writes. DMD_EN defaults to 0 when PROJ_ON goes from low to high

and then the DPP ASIC software automatically sets it to 1. Also, FAULT = 1 causes the DMD_EN register bit to be

reset.

E. D_CORE_EN is a signal internal to the DLPA3000. This signal turns on the VCORE regulator.

Figure 26. State Diagram

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7.5 Register Maps

Register Address, Default, R/W, Register name. Boldface settings are the hardwired defaults.

Table 9. Register Map

NAME

0x00, D3, R/W, Chip Identification

CHIPID

BITS

DESCRIPTION

[7:4] Chip identification number: D (hex)

[3:0] Revision number, 3 (hex)

REVID

0x01, 82, R/W, Enable Register

0: Fast shutdown disabled

[7]

FAST_SHUTDOWN_EN

CW_EN

1: Fast shutdown enabled

0: Color wheel circuitry disabled

[6]

1: Color wheel circuitry enabled

0: General purpose buck3 disabled

1: Generale purpose buck3 enabled

BUCK_GP3_EN

BUCK_GP2_EN

BUCK_GP1_EN

ILLUM_LED_AUTO_OFF_EN

ILLUM_EN

[5]

0: General purpose buck2 disabled

1: General purpose buck2 enabled

[4]

0: General purpose buck1 disabled

1: General purpose buck1 enabled

[3]

0: Illum_led_auto_off_en disabled

1: Illum_led_auto_off_en enabled

[2]

0: Illum regulators disabled

[1]

1: Illum regulators enabled

0: DMD regulators disabled

[0]

DMD_EN

1: DMD regulators enabled

0x02, 70, R/W, IREG Switch Control

TBD

[7]

Reserved, value does not matter.

Rlim voltage top-side (mV). Illum current limit = Rlim voltage / Rlim

0000: 17

0001: 20

0010: 23

1000: 73

1001: 88

1010: 102

1011: 117

1100: 133

1101: 154

1110: 176

1111: 197

ILLUM_ILIM

[6:3] 0011: 25

0100: 29

0101: 37

0110: 44

0111: 59

Bit2: CH3, MOSFET R transient current limit (0:disabled, 1:enabled)

[2:0] Bit1: CH2, MOSFET Q transient current limit (0:disabled, 1:enabled)

Bit0: CH1, MOSFET P transient current limit (0:disabled, 1:enabled)

ILLUM_SW_ILIM_EN

0x03, 00, R/W, SW1_IDAC(1)

TBD

[7:2] Reserved, value does not matter.

Led current of CH1(A) = ((Bit value + 1)/1024) × (150 mV / Rlim), Most significant bits of 10

bits register (register 0x03 and 0x04).

00 0000 0000 [OFF]

00 0011 0011 [(52/1024) × (150mV/Rlim)], Minimum code.

….

SW1_IDAC<9:8>

[1:0]

[7:0]

11 1111 1111 [150mV/Rlim]

0x04, 00, R/W, SW1_IDAC(2)

SW1_IDAC<7:0>

Led current of CH1(A) = ((Bit value + 1)/1024) × (150 mV / Rlim), Least significant bits of 10

bits register (register 0x03 and 0x04).

00 0000 0000 [OFF]

00 0011 0011 [(52/1024) × (150mV/Rlim)], Minimum code.

….

11 1111 1111 [150mV/Rlim]

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Register Maps (continued)

Table 9. Register Map (continued)

NAME

0x05, 00, R/W, SW2_IDAC(1)

TBD

BITS

DESCRIPTION

[7:2] Reserved, value does not matter.

Led current of CH2(A) = ((Bit value + 1)/1024) × (150 mV / Rlim), Most significant bits of 10

bits register (register 0x05 and 0x06).

00 0000 0000 [OFF]

00 0011 0011 [(52/1024) × (150mV/Rlim)], Minimum code.

….

SW2_IDAC<9:8>

[1:0]

[7:0]

11 1111 1111 [150mV/Rlim]

0x06, 00, R/W, SW2_IDAC(2)

SW2_IDAC<7:0>

Led current of CH2(A) = ((Bit value + 1)/1024) × (150 mV / Rlim), Least significant bits of 10

bits register (register 0x05 and 0x06).

00 0000 0000 [OFF]

00 0011 0011 [(52/1024) × (150mV/Rlim)], Minimum code.

….

11 1111 1111 [150mV/Rlim]

0x07, 00, R/W, SW3_IDAC(1)

TBD

[7:2] Reserved, value does not matter.

Led current of CH3(A) = ((Bit value + 1)/1024) × (150 mV / Rlim), Most significant bits of 10

bits register (register 0x07 and 0x08).

00 0000 0000 [OFF]

00 0011 0011 [(52/1024) × (150mV/Rlim)], Minimum code.

SW3_IDAC<9:8>

[1:0]

….

11 1111 1111 [150mV/Rlim]

0x08, 00, R/W, SW3_IDAC(2)

SW3_IDAC<7:0>

Led current of CH3(A) = ((Bit value + 1)/1024) × (150 mV / Rlim), Least significant bits of 10

bits register (register 0x07 and 0x08).

00 0000 0000 [OFF]

[7:0]

00 0011 0011 [(52/1024) × (150mV/Rlim)], Minimum code.

….

11 1111 1111 [150mV/Rlim]

0x09, 00, R/W, Switch ON/OFF Control

Only used if DIRECT MODE is enabled (see register 0x2F)

SW3

SW2

SW1

[7]

0: SW3 disabled

1: SW3 enabled

Only used if DIRECT MODE is enabled (see register 0x2F)

0: SW2 disabled

1: SW2 enabled

[6]

[5]

Only used if DIRECT MODE is enabled (see register 0x2F)

0: SW1 disabled

1: SW1 enabled

TBD

[4:0] Reserved, value does not matter.

0x0A, 00, R/W, Analog Front End (1)

0: Analog front end disabled

[7]

AFE_EN

1: Analog front end enabled

0: Calibrated 18x AFE_VGA

[6]

AFE_CAL_DIS

1: Uncalibrated 18x AFE_VGA

Gain analog front end gain

00: Off

[5:4] 01: 1x

10: 9.5x

AFE_GAIN

11: 18x

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Register Maps (continued)

Table 9. Register Map (continued)

NAME

BITS

DESCRIPTION

Selected analog multiplexer input

0000: ILLUM_A_FB/xx, where xx is controlled by VLED_OVP_VLED_RATIO<4:0>

(reg0x19)

0001: ILLUM_B_FB/xx, where xx is controlled by VLED_OVP_VLED_RATIO<4:0> (reg0x19)

0010: VIN/xx, where xx is controlled by ILLUM_LED_AUTO_OFF_SEL<3:0> (reg0x18)

0011: V_LABB

0100: RLIM_K1

0101: RLIM_K2

0110: CH1_SWITCH

0111: CH2_SWITCH

AFE_SEL

[3:0]

1000: CH3_SWITCH

1001: VREF_1V2

1010: VOTS (Main temperature sense block output voltage)

1011: VPROG1/12 (EEPROM block1 programming voltage divided by 12)

1100: VPROG2/12 (EEPROM block2 programming voltage divided by 12)

1101: ACMPR_IN_1

1110: ACMPR_IN_2

1111: ACMPR_IN_3

0x0B, 00, R/W, Analog Front End (2)

Samples time LABB Sensor (µs)

00: 7

TSAMPLE_SEL

[7:6] 01: 14

10: 21

11: 28

0: LABB SAMPLING disabled

1: START LABB SAMPLING (auto reset to 0 after TSAMPLE_SEL time).

SAMPLE_LABB

[5]

OVP_VIN Division factor.

00000: 3.33

00001: 4.98

00010: 5.23

01000: 6.10

01001: 6.23

01010: 6.67

01011: 7.11

01100: 7.50

01101: 7.96

01110: 8.34

01111: 8.77

10000: 9.16

10001: 9.60

10010: 9.99

10011: 10.41

10100: 10.88

10101: 11.26

10110: 11.67

10111: 12.11

11000: 12.51

11001: 12.94

11010: 13.31

11011: 13.70

11100: 14.11

11101: 14.56

11110: 15.04

11111: 15.41

VLED_OVP_VIN_RATIO

[4:0] 00011: 5.32

00100: 5.42

00101: 5.52

00110: 5.62

00111: 5.85

0x0C, 00, R, Main Status Register

0: No PG or OV failures for any of the LV Supplies

1: PG failures for a LV Supplies

SUPPLY_FAULT

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

0: ILLUM_FAULT = LOW

1: ILLUM_FAULT = HIGH

ILLUM_FAULT

PROJ_ON_INT

DMD_FAULT

BAT_LOW_SHUT

BAT_LOW_WARN

TS_SHUT

0: PROJ_ON = HIGH

1: PROJ_ON = LOW

0: DMD_FAULT = LOW

1: DMD_FAULT = HIGH

0: VIN > UVLO_SEL<4:0>

1: VIN < UVLO_SEL<4:0>

0: VIN > LOWBATT_SEL<4:0>

1: VIN < LOWBATT_SEL<4:0>

0: Chip temperature < 132.5°C and no violation in V5V0

1: Chip temperature > 156.5°C, or violation in V5V0

0: Chip temperature < 121.4°C

1: Chip temperature > 123.4°C

TS_WARN

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Register Maps (continued)

Table 9. Register Map (continued)

NAME

BITS

DESCRIPTION

0x0D, F5, Interrupt Mask Register

0: Not masked for SUPPLY_FAULT interrupt

1: Masked for SUPPLY_FAULT interrupt

SUPPLY_FAULT_MASK

ILLUM_FAULT_MASK

PROJ_ON_INT_MASK

DMD_FAULT_MASK

BAT_LOW_SHUT_MASK

BAT_LOW_WARN_MASK

TS_SHUT_MASK

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

0: Not masked for ILLUM_FAULT interrupt

1: Masked for ILLUM_FAULT interrupt

0: Not masked for PROJ_ON_INT interrupt

1: Masked for PROJ_ON_INT interrupt

0: Not masked for DMD_FAULT interrupt

1: Masked for DMD_FAULT interrupt

0: Not masked for BAT_LOW_SHUT interrupt

1: Masked for BAT_LOW_SHUT interrupt

0: Not masked for BAT_LOW_WARN interrupt

1: Masked for BAT_LOW_WARN interrupt

0: Not masked for TS_SHUT interrupt

1: Masked for TS_SHUT interrupt

0: Not masked for TS_WARN interrupt

1: Masked for TS_WARN interrupt

TS_WARN_MASK

0x0E, 00, R/W, Break-Before-Make Delay

Break before make delay register (ns), step size is 111 ns

0000 0000: 0

0000 0001: 333

0000 0010: 444

BBM_DELAY

[7:0] 0000 0011: 555

….

1111 1101: 28305

1111 1110: 28416

1111 1111: 28527

0x0F, 07, R/W, Fast Shutdown Timing

VOFS/RESETZ_DELAY (µs)

0000: 4.000 – 4.445

0001: 8.010 – 8.900

0010: 16.02 – 17.80

0011: 32.00 – 35.55

0100: 63.99 – 71.10

0101: 128.0 – 142.2

0110: 256.0 – 284.5

1000: 6.230 – 7.120

1001: 12.46 – 14.24

1010: 24.89 – 28.44

1011: 49.77 – 56.88

1100: 99.5 – 113.8

1101: 199.1 – 227.6

1110: 398.3 – 455.2

VOFS/RESETZ_DELAY

[7:4]

1111: 1024.2 –

1138.0

0111: 512.1 – 569.0

VBIAS/VRST_DELAY (µs)

0000: 4.000 – 4.445

0001: 8.010 – 8.900

0010: 16.02 – 17.80

0011: 32.00 – 35.55

0100: 63.99 – 71.10

0101: 128.0 – 142.2

0110: 256.0 – 284.5

1000: 6.230 – 7.120

1001: 12.46 – 14.24

1010: 24.89 – 28.44

1011: 49.77 – 56.88

1100: 99.5 – 113.8

1101: 199.1 – 227.6

1110: 398.3 – 455.2

VBIAS/VRST_DELAY

[3:0]

1111: 1024.2 –

1138.0

0111: 512.1 – 569.0

51

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

Register Maps (continued)

Table 9. Register Map (continued)

NAME

BITS

DESCRIPTION

0x10, C0, R/W, VOFS State Duration

Duration of VOFS state (ms)

000: 1

001: 5

010: 10

VOFS_STATE_DURATION

[7:5] 011: 20

100: 40

101: 80

110: 160

111: 320

Low battery level selection

00000: 3.93

00001: 5.92

01000: 7.27

01001: 7.43

01010: 7.95

01011: 8.46

01100: 8.93

01101: 9.47

01110: 9.92

01111: 10.42

10000: 10.94

10001: 11.46

10010: 11.92

10011: 12.42

10100: 12.97

10101: 13.42

10110: 13.91

10111: 14.43

11000: 14.96

11001: 15.47

11010: 15.91

11011: 16.37

11100: 16.87

11101: 17.40

11110: 17.96

11111: 18.41

00010: 6.21

LOWBATT_SEL

[4:0] 00011: 6.32

00100: 6.43

00101: 6.55

00110: 6.67

00111: 6.93

0x11, 00, R/W, VBIAS State Duration

Duration of VBIAS state (ms)

000: bypass

001: 5

010: 10

VBIAS_STATE_DURATION

[7:5] 011: 20

100: 40

101: 80

110: 160

111: 320

Undervoltage lockout level selection

00000: 3.93

00001: 5.92

01000: 7.27

01001: 7.43

01010: 7.95

01011: 8.46

01100: 8.93

01101: 9.47

01110: 9.92

01111: 10.42

10000: 10.94

10001: 11.46

10010: 11.92

10011: 12.42

10100: 12.97

10101: 13.42

10110: 13.91

10111: 14.43

11000: 14.96

11001: 15.47

11010: 15.91

11011: 16.37

11100: 16.87

11101: 17.40

11110: 17.96

11111: 18.41

00010: 6.21

UVLO_SEL

[4:0] 00011: 6.32

00100: 6.43

00101: 6.55

00110: 6.67

00111: 6.93

0x13, 00, R/W, GP1 Buck Converter Voltage Selection

General purpose1 buck output voltage = 1+ bit value * 15.69 (stepsize = 15.69 mV)

00000000 1 V

….

BUCK_GP1_TRIM

[7:0]

11111111 5 V

0x14, 00, R/W, GP2 Buck Converter voltage Selection

General purpose2 buck output voltage = 1+ bit value * 15.69 (stepsize = 15.69 mV)

00000000 1 V

….

BUCK_GP2_TRIM

[7:0]

11111111 5 V

0x15, 00, R/W, GP3 Buck Converter Voltage Selection

General purpose3 driver output voltage = 1+ bit value * 15.69 (stepsize = 15.69 mV)

00000000 1 V

….

BUCK_GP3_TRIM

[7:0]

11111111 5 V

52

DLPA3000

www.ti.com.cn

ZHCSE87 –OCTOBER 2015

Register Maps (continued)

Table 9. Register Map (continued)

NAME

0x16, 00, R/W, Buck Skip Mode

TBD

BITS

DESCRIPTION

[7:5] Reserved, value does not matter.

Skip Mode:

Bit4: Buck_GP3 (0:disabled, 1:enabled)

Bit3: Buck_GP1 (0:disabled, 1:enabled)

Bit2: Buck_GP2 (0:disabled, 1:enabled)

BUCK_SKIP_ON

[4:0]

Bit1: Buck_DMD1 (0:disabled, 1:enabled)

Bit0: Buck_DMD2 (0:disabled, 1:enabled)

0x17, 02, R/W, User Configuration Selection Register

0: SPI Clock from 0 to 36 MHz

1: SPI Clock from 20 to 40 MHz

DIG_SPI_FAST_SEL

TBD

[7]

[6]

[5]

Reserved, value does not matter.

0: Current limiting disabled (External FETs mode)

1: Current limiting enabled (External FETs mode)

ILLUM_EXT_LSD_CUR_LIM_EN

Reserved

[4]

[3]

ILLUM_3A_INT_SWITCH_SEL

Illum Configuration: most significant bit is ILLUM_EXT_SWITCH_CAP<6> (Reg0x26). Other

4 bits are <3:0> of this register. “x” is don’t care.

x xx00: Off

x x110: 2 x 3 A Internal FETs

x 0010: 1 x 6 A Internal FETs

x 1010: 1 x 3 A Internal FETs

ILLUM_DUAL_OUTPUT_CNTR_SE

L

[2]

[1]

ILLUM_INT_SWITCH_SEL

0 xx0x: Off

0 x11x: 2 x 3 A Internal FETs

0 001x: 1 x 6 A Internal FETs

ILLUM_EXT_SWITCH_SEL

[0]

0 101x: 1 x 3 A Internal FETs

1 xxx1: External FETs

0x18, 00, R/W, OLV -ILLUM_LED_AUTO_OFF_SEL

Illum openloop voltage (V) = 3 + bit value * 1 (stepsize = 1 V)

0000: 3 V

0001: 4 V

...

ILLUM_OLV_SEL

[7:4]

1110: 17 V

1111: 18 V

Led Auto Off Level

(V)

Bit value

VIN division factor

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

3.93

5.92

6.21

6.32

6.43

6.55

6.67

6.93

7.27

7.95

8.93

9.92

10.94

11.92

12.97

13.91

3.33

4.98

5.23

5.32

5.42

5.52

5.62

5.85

6.10

6.67

7.50

8.34

9.16

9.99

10.88

11.67

ILLUM_LED_AUTO_OFF_SEL

[3:0]

53

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

Register Maps (continued)

Table 9. Register Map (continued)

NAME

BITS

DESCRIPTION

0x19, 1F, R/W, Illumination Buck Converter Overvoltage Fault Level

Reserved

[7:5]

Bit value / OVP VLED division factor

00000: 3.33

00001: 4.98

00010: 5.23

01000: 6.10

10000: 9.16

10001: 9.60

10010: 9.99

10011: 10.41

10100: 10.88

10101: 11.26

10110: 11.67

10111: 12.11

11000: 12.51

01001: 6.23

01010: 6.67

01011: 7.11

01100: 7.50

01101: 7.96

01110: 8.34

01111: 8.77

11001: 12.94

11010: 13.31

11011: 13.70

11100: 14.11

11101: 14.56

11110: 15.04

11111: 15.41

VLED_OVP_VLED_RATIO

[4:0] 00011: 5.32

00100: 5.42

00101: 5.52

00110: 5.62

00111: 5.85

0x1B, 00, R/W, Color Wheel PWM Voltage(1)

Least significant 8 bits of 16 bits register (register 0x1B and 0x1C) Average color wheel PWM

voltage (V), step size = 76.295 µV

CW_PWM <7:0>

[7:0] 0x0000 0 V

....

0xFFFF 5 V

0x1C, 00, R/W, Color Wheel PWM Voltage(2)

Most significant 8 bits of 16 bits register (register 0x1B and 0x1C) Average color wheel PWM

voltage (V), step size = 76.295 µV

CW_PWM <15:8>

[7:0] 0x0000 0 V

....

0xFFFF 5 V

0x25, 00, R/W, ILLUM BUCK CONVERTER BANDWIDTH SELECTION

reserved

[7:4]

ILED CONTROL LOOP BANDWIDTH INCREASE (dB)

00: 0

ILLUM_BW_BC1

[3,2] 01: 1.9

10: 4.7

11: 9.3

ILED CONTROL LOOP BANDWIDTH INCREASE (dB)

00: 0

[1,0] 01: 1.9

10: 4.7

ILLUM_BW_BC2

11: 9.3

0x26, 9F, R, Capability register

0: LED_AUTO_TURN_OFF_CAP disabled

1: LED_AUTO_TURN_OFF_CAP enabled

LED_AUTO_TURN_OFF_CAP

[7]

[6]

[5]

[4]

[3]

[2]

[1]

0: No external switch control capability

1: External switch control capability included

ILLUM_EXT_SWITCH_CAP

CW_CAP

0: No color wheel capability

1: Color wheel capability included

0: VSP

1: TRP

DMD type

0: LDO1 not used for DMD, voltage set by user register

1: LDO1 used for DMD, voltage set by EEPROM

DMD_LDO1_USE

DMD_LDO2 _USE

DMD_BUCK1 _USE

0: LDO2 not used for DMD, voltage set by user register

1: LDO2 used for DMD, voltage set by EEPROM

0: DMD Buck1 disabled

1: DMD Buck1 used

54

DLPA3000

www.ti.com.cn

ZHCSE87 –OCTOBER 2015

Register Maps (continued)

Table 9. Register Map (continued)

NAME

BITS

DESCRIPTION

0: DMD Buck2 disabled

1: DMD Buck2 used

DMD_BUCK2 _USE

[0]

0x27, 00, R, Detailed status register1 (Power good failures for general purpose and illumination blocks)

0: No fault

BUCK_GP3_PG_FAULT

[7]

1: Focus motor buck power good failure. Does not initiate a fast shutdown.

0: No fault

BUCK_GP1_PG_FAULT

[6]

1: General purpose buck1 power good failure. Does not initiate a fast shutdown.

0: No fault

BUCK_GP2_PG_FAULT

Reserved

[5]

[4]

[3]

1: General purpose buck2 power good failure. Does not initiate a fast shutdown.

0: No fault

ILLUM_BC1_PG_FAULT

1: Illum buck converter1 power good failure. Does not initiate a fast shutdown.

0: No fault

ILLUM_BC2_PG_FAULT

[2]

1: Illum buck converter2 power good failure. Does not initiate a fast shutdown.

TBD

[1]

[0]

Reserved, value always 0

0x28, 00, R, Detailed status register2 (Overvoltage failures for general purpose and illum blocks)

0: No fault

BUCK_GP3_OV_FAULT

BUCK_GP1_OV_FAULT

[7]

[6]

1: Focus motor buck overvoltage failure. Does not initiate a fast shutdown.

0: No fault

1: General purpose buck1 overvoltage failure. Does not initiate a fast shutdown.

0: No fault

BUCK_GP2_OV_FAULT

TBD

[5]

[4]

[3]

1: General purpose buck2 overvoltage failure. Does not initiate a fast shutdown.

Reserved, value always 0

0: No fault

ILLUM_BC1_OV_FAULT

1: Illum buck converter1 overvoltage failure. Does not initiate a fast shutdown.

0: No fault

ILLUM_BC2_OV_FAULT

[2]

1: Illum buck converter2 overvoltage failure. Does not initiate a fast shutdown.

TBD

[1]

[0]

Reserved, value always 0

0x29, 00, R, Detailed status register3 (Power good failure for DMD related blocks)

TBD

[7]

Reserved, value always 0

0: No fault

DMD_PG_FAULT

[6]

1: VBIAS, VOFS and/or VRST power good failure. Initiates a fast shutdown.

0: No fault

BUCK_DMD1_PG_FAULT

BUCK_DMD2_PG_FAULT

[5]

[4]

1: Buck1 (used to create DMD voltages) power good failure. Initiates a fast shutdown.

0: No fault

1: Buck2 (used to create DMD voltages) power good failure. Initiates a fast shutdown.

TBD

[3]

[2]

Reserved, value always 0

0: No fault

LDO_GP1_PG_FAULT /

LDO_DMD1_PG_FAULT

[1]

[0]

1: LDO1 (used as general purpose or DMD specific LDO) power good failure. Initiates a fast

shutdown.

0: No fault

LDO_GP2_PG_FAULT /

LDO_DMD2_PG_FAULT

1: LDO2 (used as general purpose or DMD specific LDO) power good failure. Initiates a fast

shutdown.

0x2A, 00, R, Detailed status register4 (Overvoltage failures for DMD related blocks and Color Wheel)

TBD

[7]

[6]

Reserved, value always 0

0: No fault

BUCK_DMD1_OV_FAULT

[5]

1: Buck1 (used to create DMD voltage) overvoltage failure

55

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

Register Maps (continued)

Table 9. Register Map (continued)

NAME

BITS

DESCRIPTION

0: No fault

BUCK_DMD2_OV_FAULT

[4]

1: Buck2 (used to create DMD voltage) overvoltage failure

TBD

[3]

[2]

Reserved, value always 0

LDO_GP1_OV_FAULT /

LDO_DMD1_OV_FAULT

0: No fault

[1]

[0]

1: LDO1 (used as general purpose or DMD specific LDO) overvoltage failure

LDO_GP2_OV_FAULT /

LDO_DMD2_OV_FAULT

0: No fault

1: LDO2 (used as general purpose or DMD specific LDO) overvoltage failure

0x2B, 00, R, Chip ID extension

CHIP_ID_EXTENTION

[7:0] ID extension to distinguish between various configuration options.

0x2C, 00, R/W, ILLUM_LED_AUTO_TURN_OFF_DELAY SETTINGS

Reserved

[7:4] TBD

ILLUM_LED_AUTO_TURN_OFF_DELAY (µsec)

0000: 4.000-4.445

0100: 63.99-71.10

0101: 128.0-142.2

0110: 256.0-284.5

0111: 512.1-569.0

1000: 6.230-7.120

1001: 12.46-14.24

1010: 24.89-28.44

1011: 49.77-56.88

1100: 99.5-113.8

ILLUM_LED_AUTO_TURN_OFF_D

ELAY

[3:0] 0001: 8.010-8.900

0010: 16.02-17.80

1101: 199.1-227.6

1110: 398.3-455.2

1111: 1024.2-1138.0

0011: 32.00-35.55

0x2E, 00, R/W, User Password

USER PASSWORD (0xBABE)

[7:0] Write Consecutively 0xBA and 0xBE to unlock.

0x2F, 00, R/W, User Protection Register

TBD

[7:3] Reserved, value does not matter.

0: EEPROM programming disabled

1: Shadow register values programmed to EEPROM

EEPROM_PROGRAM

[2]

[1]

0: Direct mode disabled

1: Direct mode enabled (register 0x09 to control switched)

DIRECT_MODE

0: ALL regular USER registers are WRITABLE, except for READ ONLY registers

1: ONLY USER registers 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, and 0x09 are

WRITABLE

PROTECT_USER_REG

[0]

0x30, 00, R/W, User EEPROM

Register

USER_REGISTER1

[7:0] User EEPROM Register1

0x31, 00, R/W, User EEPROM Register

USER_REGISTER2

[7:0] User EEPROM Register2

0x32, 00, R/W, User EEPROM Register

USER_REGISTER3

[7:0] User EEPROM Register3

0x33, 00, R/W, User EEPROM Register

USER_REGISTER4

[7:0] User EEPROM Register4

0x34, 00, R/W, User EEPROM Register

USER_REGISTER5

[7:0] User EEPROM Register5

0x35, 00, R/W, User EEPROM Register

USER_REGISTER6

[7:0] User EEPROM Register6

56

DLPA3000

www.ti.com.cn

ZHCSE87 –OCTOBER 2015

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

In display applications, using the DLPA3000 provides all needed analog functions including all analog power

supplies and the RGB LED driver (up to 6 A per LED) to provide a robust and efficient display solution. Each

DLP application is derived primarily from the optical architecture of the system and the format of the data coming

into the DLPC343x DLP controller chip.

8.2 Typical Applications

8.2.1 Typical Application Setup Using DLPA3000

A common application when using DLPA3000 is to use it with a DLP3010 DMD and DLPC3433/DLPC3438

controller for creating a small, ultra-portable projector. The DLPC3433/DLPC3438 in the projector typically

receives images from a PC or video player using HDMI or VGA analog, as shown in Figure 27. Card readers and

Wi-Fi can also be used to receive images if the appropriate peripheral chips are added. The DLPA3000 provides

power supply sequencing and control of the RGB LED currents as required by the application.

+

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DLPA3000

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Figure 27. Typical Setup Using DLPA3000

8.2.1.1 Design Requirements

An ultra-portable projector can be created by using a DLP chip set comprised of a DLP3010 (.3 720) DMD, a

DLPC3433 or DLPC3438 controller, and the DLPA3000 PMIC/LED Driver. The DLPC3433 or DLPC3438 does

the digital image processing, the DLPA3000 provides the needed analog functions for the projector, and DMD is

the display device for producing the projected image. In addition to the three DLP chips in the chipset, other

chips may be needed. At a minimum, a Flash part is needed to store the software and firmware to control the

DLPC3433 or DLPC3438. The illumination light that is applied to the DMD is typically from red, green, and blue

LEDs. These are often contained in three separate packages, but sometimes more than one color of LED die

may be in the same package to reduce the overall size of the projector. For connecting the DLPC3433 or

DLPC3438 to the front-end chip for receiving images, the parallel interface is typically used. While using the

parallel interface, I²C should be connected to the front-end chip for inputting commands to the DLPC3433 or

DLPC3438.

57

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

Typical Applications (continued)

The DLPA3000 has five built-in buck switching regulators to serve as projector system power supplies. Two of

the regulators are fixed to 1.1 V and 1.8 V for powering the DLP chipset. The remaining three buck regulators

are available for general purpose use and their voltages are programmable. These three programmable

regulators can be used to drive variable-speed fans or to power other projector chips, such as the front-end chip.

The only power supply needed at the DLPA3000 input is SYSPWR from an external DC power supply or internal

battery. The entire projector can be turned on and off by using a single signal called PROJ_ON. When

PROJ_ON is high, the projector turns on and begins displaying images. When PROJ_ON is set low, the projector

turns off and draws just microamps of current on SYSPWR.

8.2.1.2 Detailed Design Procedure

For connecting the DLP3010, DLPC3433 or DLPC3438 and DLPA3000 together, see the reference design

schematic. When a circuit board layout is created from this schematic, a very small circuit board is possible. An

example small-board layout is included in the reference design database. Layout guidelines should be followed

to achieve reliable projector operation. The optical engine that has the LED packages and the DMD mounted to it

is typically supplied by an optical OEM who specializes in designing optics for DLP projectors.

8.2.1.3 Application Curve

As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the

brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white-

screen lumens changes with LED currents, as shown in Figure 28. For the LED currents shown, it is assumed

that the same current amplitude is applied to the red, green, and blue LEDs. The thermal solution used to

heatsink the red, green, and blue LEDs can significantly alter the curve shape shown.

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

LED CURRENT (A)

D001

Figure 28. Luminance vs LED Current

58

DLPA3000

www.ti.com.cn

ZHCSE87 –OCTOBER 2015

Typical Applications (continued)

8.2.2 Typical Application with DLPA3000 Internal Block Diagram

91 SUP_2P5V

92 SUP_5P0V

LDO_V2V5

2.2µ/4V

N/C

1

4.7µ/6.3V

1µ/16V

LDO_V5V

THERMAL_PAD 42

8

7

ILLUM_VIN

SYSPWR

LDO

ILLUM

ILLUM_5P5V

VINA 85

1µ/6.3V

SYSPWR

VREF

0x0/<3>

.!Ç_[hí_{IÜÇ

V_LED

29 ILLUM_A_FB

1µ/16V

0x11<4:0>

30 ILLUM_A_VIN

28 ILLUM_A_BOOST

Üë[h_{9[

0x0/<2>

.!Ç_[hí_í!wb

SYSPWR

0x10<4:0>

[hí.!ÇÇ_{9[

2x10µ

16V

L

100n

16V

26 ILLUM_HSIDE_DRIVE

AGND

86

NC

31

27

ILLUM_A_SW

ILLUMINATION

DRIVER

A

2.7µH

9A

M

AFE_GAIN [1:0]

AFE_SEL[3:0]

ILLUM_LSIDE_DRIVE

2x22µ

6.3V

Low_ESR

32 ILLUM_A_PGND

R_SNA

AFE

ACMPR_REF 82

ACMPR_OUT 81

From host

To host

38 ILLUM_A_COMP1

39 ILLUM_A_COMP2

C_SNA

10p

MUX

35

ILLUM_B_FB

NC

34 ILLUM_B_VIN

SYSPWR

33 ILLUM_B_BOOST

ACMPR_IN_LABB

80

55

V_LABB

S/H

2x10µ

16V

ACMPR_LABB_SAMPLE

N

O

36

ILLUM_B_SW

ACMPR_IN_1

77

ILLUMINATION

DRIVER

B

From light sensor

ACMPR_IN_2 78

ACMPR_IN_3 79

From temperature sensor

37 ILLUM_B_PGND

40 ILLUM_B_COMP1

41 ILLUM_B_COMP2

NC

DRST_5P5V

10µ/6.3V

3

5

LDO

DMD

DRST_VIN

SYSPWR

19 CH1_GATE_CTRL

20 CH2_GATE_CTRL

NC

1µ/16V

21 CH3_GATE_CTRL

A

MBR0540T1

1µ/50V

DRST_HS_IND

DRST_LS_IND

6

2

V_LED

9,10 CH1_SWITCH

17,18

24,25

CH2_SWITCH

CH3_SWITCH

10µ/0.7A

DMD_VRESET 100

P

D

Q

VRST

C

RGB

STROBE

DECODER

R

B

DMD

HIGH VOLTAGE

REGULATOR

11,16 RLIM_1

RLIM_2

22,23

470n/50V

DRST_PGND

4

DMD_VBIAS 99

VBIAS

VOFS

DMD_VOFFSET 98

15 RLIM_K_1

1µ/50V

14 RLIM_BOT_K_1

G

25mꢀ

1W

13 RLIM_K_2

F

12 RLIM_BOT_K_2

E

PWR1_BOOST 97

PWR1_VIN 96

69

PWR5_BOOST

100n

6.3V

100n

6.3V

67 PWR5_VIN

SYSPWR

General

Purpose

H

I

2x10µ

16V

S

T

2x10µ

16V

R_SN5C_SN5

C_SN1R_SN1

PWR1_SWITCH 95

68

PWR5_SWITCH

DMD/DLPC

PWR1

3.3µH

3A

BUCK1

3.3µH

3A

PWR1_PGND 93

PWR1_FB 94

70 PWR5_PGND

71

1-5V / 8bit

PWR5_FB

V_DMD-DLPC-1

2x22µ

6.3V

Low_ESR

PWR2_BOOST 76

PWR2_VIN 75

65

PWR6_BOOST

100n

6.3V

100n

6.3V

64 PWR6_VIN

SYSPWR

General

Purpose

J

2x10µ

16V

U

V

2x10µ

16V

C_SN2

R_SN2

R_SN6

C_SN6

PWR2_SWITCH 74

63 PWR6_SWITCH

DMD/DLPC

PWR2

K

3.3µH

3A

BUCK2

3.3µH

3A

PWR2_PGND 73

PWR2_FB 72

62 PWR6_PGND

66 PWR6_FB

1-5V / 8bit

V_DMD-DLPC-2

2x22µ

6.3V

Low_ESR

PWR4_VIN

90

50

PWR7_BOOST

3.3V-20V

100n

6.3V

1µ/16V

LDO_1

DMD/DLPC/AUX

52 PWR7_VIN

SYSPWR

PWR4_OUT 89

PWR3_VIN 88

General

Purpose

W

X

2x10µ

16V

R_SN7C_SN7

1µ/6.3V

1µ/16V

53 PWR7_SWITCH

BUCK3

3.3µH

3A

54 PWR7_PGND

51 PWR7_FB

LDO_2

DMD/DLPC/AUX

1-5V / 8bit

2x22µ

PWR3_OUT 87

6.3V

Low_ESR

1µ/6.3V

1µ/16V

PWR_VIN

83

SYSPWR

CW_SPEED_PWM_OUT 44

CLK_OUT 43

NC

LDO

BUCKS

Color Wheel

PWM

84 PWR_5P5V

57 RESET_Z

1µ/6.3V

PROJ_ON 56

CH_SEL_0 60

CH_SEL_1 61

From host

To system

0.1µ/6.3V

SPI_VIN

5.1k

DIGITAL

CORE

SPI_VIN 45

SPI_SS_Z 48

SPI_CLK 46

SPI_MISO 47

SPI_MOSI 49

From host

58 INT_Z

To DLPC

(optional)

From host

To host

SPI

Y

59 DGND

From host

Figure 29. Typical Application: V_IN= 12 V, I_OUT= 6 A, LED, Internal FETs

59

DLPA3000

ZHCSE87 –OCTOBER 2015

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9 Power Supply Recommendations

The DLPA3000 is designed to operate from a 6 V to 20 V input voltage supply or battery. To avoid insufficient

supply current due to line drop, ringing due to trace inductance at the VIN terminals, or supply peak current

limitations, additional bulk capacitance may be required. In the case of ringing that is caused by the interaction

with the ceramic input capacitors, an electrolytic or tantalum type capacitor may be needed for damping.

The amount of bulk capacitance required should be evaluated such that the input voltage can remain in spec

long enough for a proper fast shutdown to occur for the V_OFFSET, V_RESET, and V_BIASsupplies. The shutdown

begins when the input voltage drops below the programmable UVLO threshold, such as when the external power

supply or battery supply is suddenly removed from the system.

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10 Layout

10.1 Layout Guidelines

For switching power supplies, the layout is an important step in the design process, especially when it concerns

high-peak currents and high-switching frequencies. If the layout is not carefully done, the regulator could show

stability issues and/or EMI problems. Therefore, it is recommended to use wide- and short-traces for high-current

paths and for their return power ground paths. The input capacitor, output capacitor, and inductor should be

placed as near as possible to the IC. In order to minimize ground noise coupling between different buck

converters, it is advised to separate their grounds and connect them together at a central point under the part.

The high currents of the buck converters concentrate around pins V_IN, SWITCH and P_GND(Figure 30). The

voltage at the pins V_IN, P_GND, and FB are DC voltages while the pin SWITCH has a switching voltage between

V_INand P_GND. In case the FET between pins 52 and 53 is closed, the red line indicates the current flow while the

blue line indicates the current flow when the FET between pins 53 and 54 is closed. These paths carry the

highest currents and must be kept as short as possible.

50

PWR7_BOOST

100n

6.3V

52 PWR7_VIN

SYSPWR

General

Purpose

2x10µ

16V

R_SN7

C_SN7

53 PWR7_SWITCH

BUCK3

3.3µH

3A

PWR7_FB

51

54

Regulated Output

Voltage

2x22µ

6.3V

Low_ESR

PWR7_PGND

Figure 30. High AC Current Paths in a Buck Converter

The trace to the V_INpin carries high AC currents. Therefore, the trace should be low-resistive to prevent voltage

drop across the trace. Additionally, the decoupling capacitors should be placed as near to the V_INpin as possible.

The SWITCH pin is connected alternatingly to the V_INor GND. This means a square wave voltage is present on

the SWITCH pin with an amplitude of V_INand containing high frequencies. This can lead to EMI problems if not

properly handled. To reduce EMI problems, a snubber network (RSN7 & CSN7) is placed at the SWITCH pin to

prevent and/or suppress unwanted high-frequency ringing at the moment of switching.

The P_GNDpin sinks high current and should be connected to a star ground point such that it does not interfere

with other ground connections.

The FB pin is the sense connection for the regulated output voltage, which is a DC voltage; no current is flowing

through this pin. The voltage on the FB pin is compared with the internal reference voltage in order to control the

loop. The FB connection should be made at the load such that I•R drop is not affecting the sensed voltage.

10.2 Layout Example

As an example of a proper layout, one of the buck converters layout is shown in Figure 31. It shows the routing

and placing of the components around the DLPA3000 for optimal performance. The output voltage of the

converters used by the DLPA3000 is set through a register. The DLPA3000 uses the feedback pin to compare

the output voltage with an internal setpoint.

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ZHCSE87 –OCTOBER 2015

www.ti.com.cn

Layout Example (continued)

Figure 31. Practical Layout

For a proper layout, short traces are required and power grounds should be separated from each other. This

avoids ground shift problems, which can occur due to interference of the ground currents of different buck

converters. High currents are flowing through the inductor (L9) and the output capacitors (C46, C47). Therefore,

it is important to keep the traces to and from inductor and capacitors as short as possible to avoid losses due to

trace resistance. It is strongly recommended to use high quality capacitors with a low ESR value to keep the

losses in the capacitors as low as possible, and to keep the voltage ripple on the output acceptable.

In order to prevent problems with switching high currents at high frequencies, the layout is very critical and

snubber networks are advisable. The switching frequency can vary from several hundreds of kHz to frequencies

in the MHz range. Keep in mind that it takes only nanoseconds to switch currents from zero to several amperes,

which is equivalent to even much higher frequencies. Those switching moments will cause EMI problems if not

properly handled, especially when ringing occurs on the edges, which can have higher amplitude and frequency

as the switching voltage itself. To prevent this ringing, the DLPA3000 buck converters all need a snubber

network consisting of a resistor and a capacitor in series implemented on the board to reduce this unwanted

behavior. In this case, the snubber network is placed on the bottom-side of the PCB (thus not visible here) and

connected to the trace of L9 routing to the switch node.

In order to clarify what plays a role when laying out a buck converter, this paragraph explains the connections

and placing of the parts around the buck converter connected to the pins 50 through 54. The supply voltage is

connected to pin 52, which is laid out on a mid-layer (purple-colored) and is connected to this pin using 3 vias to

ensure a stable and low-resistance connection is made. The decoupling is done by capacitor C43 and C44,

visible on the bottom-right of Figure 31, and the connection to the supply and the ground layer is done using

multiple vias. The ground connection on pin 54 is also done using multiple vias to the ground layer, which is

visible as the blue areas in Figure 31. By using different layers, it is possible to create low-resistive paths. Ideally,

the ground connection of the output capacitors and the ground connection of the part (pin 54) should be close

together. The layout connects both points together using a wide trace on the bottom layer (blue colored area)

which is also suitable to bring both connections together. All buck converters in the layout have the same layout

structure and use a separated ground trace to their respective ground connection on the part. All these ground

connections are connected together on the ground plane below the DLPA3000 itself. Figure 31 shows the

position of the converter inductor and its accompanying capacitors (L9 & C46, C47) positioned as near as

possible to the pins 51 and 53 using traces as thick as possible. The ground connections of these capacitors is

done using multiple vias to the ground layer to ensure a low resistance path.

10.3 SPI Connections

The SPI interface consists of several digital lines and the SPI supply. If routing of the interface lines is not done

properly, communication errors can occur. It should be prevented that SPI lines can pickup noise and possible

interfering sources should be kept away from the interface.

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ZHCSE87 –OCTOBER 2015

SPI Connections (continued)

Pickup of noise can be prevented by ensuring that the SPI ground line is routed together with the digital lines as

much as possible to the respective pins. The SPI interface should be connected by a separate own ground

connection to the DGND of the DLPA3000 (Figure 32). This prevents ground noise between SPI ground

references of DLPA3000 and DLPC due to the high current in the system.

CLK

MISO

MOSI

5[t/

SS_Z

{tL

Lnꢀerface

SPI_GND

DLPA3000

DGND

GND

VIN

-

V_GND-DROP+

I

DLPA3000 PCB

Figure 32. SPI Connections

Interfering sources should be kept away from the interface lines as much as possible. High-current lines, such as

neighboring PWR_7, should especially be routed carefully. If PWR 7 is routed too close to SPI_CLK, for

example, it could lead to false clock pulses and thus communication errors.

10.4 R_LIMRouting

R_LIMis used to sense the LED current. To accurately measure the LED current, the RLIM _K_1,2 lines should be

connected close to the top-side of measurement resistor R_LIM, while RLIM_BOT_K_1,2 should be connected

close to the bottom-side of R_LIM

.

The switched LED current is running through R_LIM. Therefore, a low-ohmic ground connection for R_LIMis strongly

advised.

10.5 LED Connection

Switched large currents are running through the wiring from the DLPA3000 to the LEDs. Therefore, special

attention needs to be paid here. Two perspectives apply to the LED-to-DLPA3000 wiring:

1. The resistance of the wiring, R_series

2. The inductance of the wiring, L_series

The location of the parasitic series impedances are depicted in Figure 33.

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DLPA3000

ZHCSE87 –OCTOBER 2015

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LED Connection (continued)

V_LED

R_SERIES

L_SERIES

SW_P,Q,R

V_RLIM

R_LIM

Figure 33. Parasitic Inductance (L_series) and Resistance (R_series) in Series with LED

Currents up to 6 A can run through the wires connecting the LEDs to the DLPA3000. Some noticeable

dissipation can easily be caused. Every 10 mΩ of series resistances implies for 6 A average LED current a

parasitic power dissipation of 0.36 W. This might cause PCB heating, but more importantly, the overall system

efficiency is deteriorated.

Additionally, the resistance of the wiring might impact the control dynamics of the LED current. It should be noted

that the routing resistance is part of the LED current control loop. The LED current is controlled by V_LED. For a

small change in V_LED(ΔV_LED) the resulting LED current variation (ΔI_LED) is given by the total differential

resistance in that path:

DV_LED

DI_LED

=

r_LED+ R_series+ R_{on _ SW _ P,Q,R}+ R_LIM

(10)

in which r_LEDis the differential resistance of the LED and Ron_SW_P,Q,R the on resistance of the strobe

decoder switch. In this expression, L_seriesis ignored since realistic values are usually sufficiently low to cause any

noticeable impact on the dynamics.

All the comprising differential resistances are in the range of 25 mΩ to several 100s mΩ. Without paying special

attention, a series resistance of 100 mΩ can easily be obtained. It is advised to keep this series resistance

sufficiently low (for example, <50 mΩ).

The series inductance plays an important role when considering the switched nature of the LED current. While

cycling through R, G, and B LEDs, the current through these branches is turned-on and turned-off in short-time

duration. Specifically, turning-off is fast. A current of 6 A goes to 0 A in a matter of 50 ns. This implies a voltage

spike of about 1 V for every 10 nH of parasitic inductance. It is recommended to minimize the series inductance

of the LED wiring by:

•

Short wires

Thick wires / multiple parallel wires

Small enclosed area of the forward and return current path

If the inductance cannot be made sufficiently low, a zener diode needs to be used to clamp the drain voltage of

the RGB switch, such it does not surpass the absolute maximum rating. The clamping voltage needs to be

chosen between the maximum expected V_LEDand the absolute maximum rating. Take care of sufficient margin

of the clamping voltage relative to the mentioned minimum and maximum voltage.

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ZHCSE87 –OCTOBER 2015

10.6 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires

special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added

heat sinks and convection surfaces, and the presence of other heat-generating components affect the power

dissipation limits of a given component. In general three basic approaches for enhancing thermal performance

can be used; these are listed below:

•

Improving the heat sinking capability of the PCB

Reducing the thermal resistance to the environment of the chip by adding / increasing heat sink capability on

top of the package

•

Adding or increasing airflow in the system

The DLPA3000 is a device with efficient power converters. Nevertheless, since the power delivered to the LEDs

can be quite large (more than 30 W in some cases), the power dissipated in the DLPA3000 device can still be

considerable. In order to have proper operation of the DLPA3000, guidance is given below on the thermal

dimensioning of the DLPA3000 application.

The target of the dimensioning is to keep the junction temperature below the maximum recommendation of

120°C during operation. In order to determine the junction temperature of the DLPA3000, a summation of all

power dissipation terms, P_diss, needs to be made. The junction temperature, T_junction, is then given by:

T_junction= T_ambient+ P_diss∂R_qJA

(11)

in which T_ambientis the ambient temperature and R_θJAis the thermal resistance from junction to ambient.

Depending on the application of the DLPA3000, the total power dissipation can vary. The main contributors in the

DLPA3000 will typically be the:

•

Buck converters

RGB strobe decoder switches

LDOs

The calculation of the dissipation for these blocks is shown below.

For a buck converter, the dissipated power is given by:

≈

∆

«

’

1

÷

-1

P_{diss _buck}= P -P_out= P_out

in

÷

h_buck

◊

(12)

where η_buckis the efficiency of the buck converter, P_inis the power delivered at the input of the buck converter,

and P_outis the power delivered to the load of the buck converter. For buck converter PWR1,2,5,6,7, the efficiency

can be determined using the curves in Figure 22.

Similarly, for the buck converter in the illumination block the dissipated power, P_{diss_illum_buck}, can be calculated

using the expression for P_{diss_buck}. For the illumination block, however, an extra term needs to be added to the

dissipation, i.e. the dissipation of the LED switch. So, the dissipation for the illumination block, P_{diss_illum}, can be

described by:

≈

∆

«

’

1

2

÷

P_{diss _illum}= P_{out _LEDs}

-1 + I_{LED _ avg}∂R_{sw _PQR}

÷

h_{illum _buck}

◊

(13)

where P_OUTrepresents the total power supplied to the LEDs, I_{LED_avg}is the average LED current, and R_{sw_P,Q,R}

the on-resistance of the RGB strobe controller switches. It should be noted here that the sense resistor, R_LIM

,

also carries the average LED current, but is not added to this dissipation term. Since the R_LIMis external to the

DLPA3000, it does not contribute to the heating of the DLPA3000, at least not directly, although potentially it

does through increasing the ambient temperature. For total system dissipation, R_LIMshould of course be

included.

These discussed buck converters potentially handle the highest power levels, which is why they need to be

power efficient. In contrast, linear regulators, such as LDOs, handle less power. However, since the efficiency of

an LDO can be relative low, the related power dissipation can be significant. To calculate the power dissipation

of an LDO, P_{diss_LDO}, the following equation can be used:

65

DLPA3000

ZHCSE87 –OCTOBER 2015

www.ti.com.cn

Thermal Considerations (continued)

P_{diss_LDO}

=

(

V - V_out∂I_load

)

in

(14)

where V_inis the input supply voltage, V_outis the output voltage of the LDO, and I_loadis the load current of the

LDO. Since the voltage drop over the LDO (V_in–V_out) can be relative large, a relatively small load current can

yield significant DLPA3000 dissipation. If this situation occurs, one might consider using one of the general

purpose bucks to have a more power-efficient (less dissipation) solution.

One LDO, the LDO DMD, needs special attention, since it is used as the power supply of a boost power

converter. The boost converter is used to supply the high voltages for the DMD (such as V_BIAS, V_OFS, and V_RST).

The loading on these lines can be up to I_load,max=10 mA simultaneously. Thus, the maximum related power level

is moderate. Assuming an efficiency on the order of 80% for the boost converter, η_boost, this implies a maximum

boost converter dissipation, P_{diss_DMD_boost,max}of:

≈

∆

«

’

÷

◊

1

÷

P_{diss _DMD _ boost ,max}= I_load,max

(

V_BIAS+ V_OFS+ V_RST

)

∂

-1 ö 0.1W

h_boost

(15)

In perspective of the dissipation of the illumination buck converter, this is likely negligible. The term that might

count to the total power dissipation is P_{diss_LDO_DMD}. The input current of the DMD boost converter is supplied by

this LDO. In case of a high-supply voltage, a non-negligible dissipation term is obtained. The worst-case load

current for the LDO is given by:

(

V_BIAS+ V_OFS+ V_RST

)

I_load,maxö 100mA

1

I_{load_LDO,max}

=

h_boost

V_{DRST _ 5P5V}

(16)

where the output voltage of the LDO is V_{DRST_5P5V}= 5.5 V.

Thus, the worst-case dissipation of the LDO, can be on the order of 1.5 W for an input supply voltage of 19.5 V.

However, this is a worst-case scenario. In most cases, the load current of the LDO DMD is significantly less. It is

advised to check this LDO current level for the specific application.

Finally, the DLPA3000 will draw a quiescent current. This quiescent current is relatively independent of the power

supply voltage. For the buck converters, the quiescent current is comprised in the efficiency numbers. For the

LDOs, a quiescent current on the order of 0.5 mA can be used. For the rest of the DLPA3000 circuitry, not

included in the buck converters or LDOs, a quiescent current on the order of 3 mA applies. So, overall, when the

power dissipation of the buck converters, illumination block (illumination buck + P,Q,R switches) and the LDOs

are summed, a good estimate of the DLPA3000 dissipation, P_{diss_DLPA3000}, is obtained. Given as an equation:

P_diss

=

P_buck

+

P_{illu min ation}

+

P_LDOs

_ DLPA 3000

_ converters

ƒ

(17)

Once this total power dissipation is know, the thermal design can be done. A few examples are given. Assume

the total P_{diss_DLPA3000}= 7.5 W and the heatsink and airflow is as given in Thermal Information. What is the

maximum ambient temperature that can be allowed?

Know parameters: T_junction,max= 120 °C, R_θJA= 7 °C/W, Pdiss_DLPA3000 = 7.5 W.

Using Equation 11 the maximum ambient temperature can be calculated as:

T_ambient,max= T_junction,max- P_diss∂ R_qJA= 120èC - 7.5W ∂ 7èC/ W = 67.5èC

(18)

In the same way, the junction temperature of the DLPA3000 can be calculated once the dissipated power and

the ambient temperature is known. For instance:

T_ambient= 50 °C, R_θJA= 7 °C/W, P_{diss_DLPA3000}= 8.5 W.

For the heat sink configuration and airflow as indicated in Thermal Information, the junction temperature can be

calculated to be:

T_junction= T_ambient+P_diss∂R_qJA= 50èC+7.5W∂7èC/W =102.5èC

(19)

In case the combination of ambient temperature and DLPA3000 power dissipation does not yield an acceptable

junction temperature (such as <120°C), two approaches can be used:

1. Using larger heatsink or more airflow to reduce R_θJA

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www.ti.com.cn

ZHCSE87 –OCTOBER 2015

Thermal Considerations (continued)

2. Reduce power dissipation in DLPA3000 by for instance not using an internal general purpose buck

converter, but an external one. Or lowering maximum LED current.

As a final example, it is shown below how to determine a de-rating of the maximum I_LEDin case the junction

temperature at I_LED= 6 A exceeds the maximum allowed temperature. Assume the following parameters:

P_{buck_converters}= 1 W, P_LDOs= 0.5 W, T_ambient= 75°C, R_θJA= 7°C/W, V_LED= 3.5 V and T_junction,max= 120°C.

In order to find the maximum acceptable LED current, a few steps are required. First, the total maximum allowed

dissipation for the DLPA3000 needs to be determined

120^oC - 75^oC

T_junction,max- T_ambient

P_diss,max

=

= 6.4W

7^oC / W

R_qJA

(20)

Since the buck converters and LDOs do dissipate in total 2.5 W, for the illumination block the dissipation budget

is 4.9 W. The dissipation of the illumination block comprises two terms: the illumination buck converter

dissipation and the P,Q,R-switches. Note that the dissipation of R_LIMis not included here since this calculation is

about the junction temperature. For overall system dissipation, of course R_LIMshould be included.

Information needed to calculate I_LEDare the illumination buck converter efficiency and the on-resistance of the

P,Q,R-switches.

The efficiency of the converter can be derived from Figure 14. For V_LED= 3.5 V and I_LEDis between 4 A and 6 A,

the efficiency is on average 80%. The on resistance of switch P,Q,R is given in the tables and is typically 30

mOhm. Assuming V_LEDto be independent of I_LED, the dissipation of the illumination block is given by:

≈

∆

’

÷

◊

1

2

÷

P_{diss_illum}= V_LED∂I_LED

∂

-1 +I_LED∂R_{on_ sw _PQR}

∆

«

h

illum_buck

(21)

Rewriting this expression for I_LEDyields:

2

≈

∆

«

’

≈

∆

«

’

1

2

÷

-1

V_LED

-1

V_LED

÷

h_{illum_buck}

4R_o²_{n_sw _PQR}

h_{illum_buck}

P_{diss_illum}

◊

I_LED

=

+

-

= 4.8 A

R_{on_sw _PQR}

2R_{on_sw _PQR}

(22)

Thus, to meet the maximum junction temperature requirement, the LED current should stay below 4.8 A. Once

the maximum current selected, it is advised to redo the thermal calculations based on the LED current. It might

be that the assumed efficiency is too high for the first calculated LED current. That would require the calculations

to be redone, but now with a better estimate for the efficiency. The same goes for the LED voltage. At lower

current, a lower LED voltage is to be expected. That implies a lower power delivered to the LED and less power

dissipated in the buck converter.

Once the system is dimensioned and built, the actual junction temperature can be derived from measuring the

internal VOTS using the AFE. This is described in Measurement System.

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ZHCSE87 –OCTOBER 2015

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11 器件和文档支持

11.1 器件支持

11.1.1 器件命名规则

75

51

76

50

YMLLLLSG4

YM = YEAR / MONTH

LLLL = LOT TRACE CODE

S

= ASSEMBLY SITE CODE

= pin 1 Marking (White Dot)

DLPA3000D

100

26

1

25

图 34. 封装标记 DLPA3000（顶视图）

11.2 相关链接

下面的表格列出了快速访问链接。范围包括技术文档、支持和社区资源、工具和软件，以及样片或购买的快速访

问。

表 10. 相关链接

器件

产品文件夹

单击此处

样片与购买

单击此处

技术文档

单击此处

工具与软件

单击此处

支持与社区

单击此处

DLPA3000

DLPC3433

DLPC3438

11.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

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ZHCSE87 –OCTOBER 2015

11.4 商标

Pico, E2E are trademarks of Texas Instruments.

DLP is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不

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69

重要声明和免责声明

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型号：	DLPA3000DPFDR
厂家：	TEXAS INSTRUMENTS
描述：	DLP® PMIC/LED driver for DLP3010 (0.3 720p) DMD \| PFD \| 100 \| 0 to 70 集成电源管理电路
文件：	总75页 (文件大小：1295K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLPA3000DPFDR [TI]

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