DLPC120ZXSRQ1_技术文档

DLPC120-Q1

ZHCSHX7B –NOVEMBER 2017 –REVISED MAY 2022

DLPC120-Q1 汽车DMD 控制器

1 特性

3 说明

• 符合面向汽车应用的AEC-Q100 标准：

– 温度等级2：–40°C 至105°C（环境温度）

• 与三个DMD 器件兼容：

– DLP3030-Q1：0.3 WVGA S450

– DLP3020-Q1：0.3 WVGA S247

– DLP3021-Q1：0.3 WVGA S247

• 视频输入接口：

DLPC120-Q1 适用于汽车应用的 DMD 显示控制器是

与三个数字微镜器件 (DMD) 之一（DLP3030-Q1、

DLP3020-Q1 或 DLP3021-Q1）兼容的芯片组的一部

分。DLPC120-Q1 的核心逻辑负责接受视频输入并对

数据进行格式化以便在 DMD 上显示，同时还控制

RGB LED 来形成实时图像。DLPC120-Q1 还负责根据

外部系统控制或 DMD 温度输入来控制 DMD 的上电和

断电事件。通过与外部调光电路和微控制器结合，

DLPC120-Q1 支持的宽调光范围 > 5000:1，适合于

HUD 应用。通常情况下，DLPC120-Q1 是主机处理器

I²C 接口的外围器件。

– 24 位并行（RGB888、RGB666 或RGB565）

– 60Hz 帧速率

– 从QVGA 至WVGA 的输入分辨率

– 像素时钟高达40MHz

• 视频处理：

– 图像缩放

器件信息

器件型号⁽¹⁾

封装尺寸（标称值）

封装

– 可编程去伽玛曲线

– 边框调整

– 水平和垂直图像翻转

• DMD 接口：

DLPC120-Q1

NFBGA (216)

17.00mm × 17.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– 78MHz DDR DMD 接口

– 一致的DMD 数据加载和复位控制过热工作范围

– 断电时自动停止DMD

– DMD 温度管理

Color & Dimming control

Flash

SPI

I²C

• 外部存储器支持

TMS320

F28023

Color

LEDs

Controller

& Driver

Host

SPI

DLPC120-Q1

– DDR2：312MHz 时钟（624MHz 数据速率）

– 串行闪存39MHz 时钟

• 系统控制

Illumination

Control

& Feedback

Video

Processing &

DMD

real-time

optical

24-bit RGB

& Syncs

Formatting

feedback

loop

– I²C 通讯接口

– 可编程启动界面

– DMD 电源和复位驱动器控制

– 基于闪存的可编程配置

• 测试支持

photo diode

LED Enable

Timing Control

Data & Control

DLP3030-Q1

Reset

.3" WLP(H) s450

DVSP DMD

Power Good

I²C

TMP411

-Q1

Data &

Address

DMD Power

– 内置测试图形发生器

– JTAG：支持边界扫描

• 采用216 引脚1.0mm 间距BGA 封装

DDR-2 DRAM

frame buffer

TPS65100

-Q1

Power Enable

2 应用

典型系统图

• 宽视场和增强现实抬头显示(HUD)

• 车内投影显示和照明

• 数字仪表组、导航和信息娱乐系统挡风玻璃显示

• 汽车小灯

• 动态地面投影

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS096

DLPC120-Q1

ZHCSHX7B –NOVEMBER 2017 –REVISED MAY 2022

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Table of Contents

6.13 JTAG Interface Timing Requirements ....................19

6.14 I²C Interface Timing Requirements ........................20

7 Parameter Measurement Information..........................21

7.1 Parallel Interface Input Source Timing......................21

7.2 Design for Test Functions......................................... 21

8 Detailed Description......................................................22

8.1 Overview...................................................................22

8.2 Functional Block Diagram.........................................22

8.3 Feature Description...................................................23

8.4 Device Functional Modes..........................................26

9 Application and Implementation..................................26

9.1 Application Information............................................. 26

9.2 Typical Application.................................................... 27

10 Power Supply Recommendations..............................29

10.1 Power Supply Filtering............................................29

11 Layout...........................................................................30

11.1 Layout Guidelines................................................... 30

12 Device and Documentation Support..........................33

12.1 第三方产品免责声明................................................33

12.2 Device Support....................................................... 33

12.3 Documentation Support.......................................... 34

12.4 接收文档更新通知................................................... 34

12.5 支持资源..................................................................34

12.6 Trademarks.............................................................34

12.7 Electrostatic Discharge Caution..............................34

12.8 术语表..................................................................... 34

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

5.1 LED Driver Interface................................................... 5

5.2 DMD Temperature Interface........................................5

General Purpose I/O.........................................................6

5.3 Main Video and Data Control Interface.......................6

5.4 DMD Interface.............................................................7

5.5 Memory Interface........................................................8

Board Level Test and Debug.............................................9

Manufacturing Test Support..............................................9

Test Point Interface........................................................... 9

Power and Ground..........................................................10

6 Specifications................................................................ 12

6.1 Absolute Maximum Ratings...................................... 12

6.2 ESD Ratings............................................................. 12

6.3 Recommended Operating Conditions.......................12

6.4 Thermal Information..................................................12

6.5 Electrical Characteristics...........................................13

6.6 Electrical Characteristics for I/O ...............................13

6.7 Power Supply and Reset Timing Requirements....... 13

6.8 Reference Clock PLL Timing Requirements.............15

6.9 Parallel Interface General Timing Requirements...... 16

6.10 Parallel Interface Frame Timing Requirements ......16

6.11 Flash Memory Interface Timing Requirements ...... 17

6.12 DMD Interface Timing Requirements .....................18

Information.................................................................... 35

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (March 2018) to Revision B (April 2022)

Page

• 添加了DLP3020-Q1 和DLP3021-Q1 作为支持的器件删除了DLP3000-Q1..................................................... 1

• 包括数字仪表组、导航和信息娱乐挡风玻璃显示、汽车小灯和动态地面投影应用。.......................................... 1

• 根据最新的德州仪器(TI) 和行业数据表标准对本文档进行了更新。...................................................................1

• 将封装尺寸从16mm × 16mm 更新为17mm × 17mm，并添加了DLP3020-Q1 和DLP3021-Q1 器件作为支持

的器件删除了DLP3000...................................................................................................................................... 1

• This document is updated per the latest Texas Instruments and industry inclusive terminologies. All

occurrences of MISO are now POCI; all occurrences of MOSI are now PICO.................................................. 3

• Updated LED Driver Interface ............................................................................................................................5

• Updated Design Requirements ........................................................................................................................27

• Updated General PCB Recommendations ......................................................................................................31

Changes from Revision * (November 2017) to Revision A (March 2018)

Page

• 将器件状态从预告信息更改为量产数据.............................................................................................................1

• Changed case-to-junction thermal coefficient from 0.77°C/W : to 0.28°C/W in Thermal Information table......12

• Updated Temperature Monitor Function .......................................................................................................... 25

• Updated Application Information ......................................................................................................................26

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5 Pin Configuration and Functions

图5-1. ZXS Package 216-Pin BGA Top View

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表5-1. DLPC120-Q1 Device Initialization and Programming Pin Descriptions

I/O

CLOCK

NAME

NO.

POWER

TYPE

SYSTEM

DESCRIPTION

Functional Reset (Active Low). Resets internal logic and causes

PLL startup and PLL locking. Assertion is required after power

supplies are within limits. See 节6.7 for timing requirements.

RESETZ

H13

I₂

Async

N/A

System Power Good indicator. Should be held low until all

DLPC120-Q1 power has been within operating limits. See 节6.7

for timing requirements. Must be set high to enable normal

operation. When set low, the DLPC120-Q1 begins the parking

routine for the DMD. Together with pin E14 (LED_R_PWM /

PWRGOOD_CNTRL), this signal is critical for DLP30xx-Q1

parking as part of the Pre-Conditioning Sequence and subsequent

un-parking. See DLPC120-Q1 Programmer's Guide for

implementation details.

PWRGOOD

G13

G15

Reference Clock Input (16 MHz). Can be driven by crystal across

this pin and PLL_REFCLK_O or by external oscillator. See 节6.7

for timing requirements.

PLL_REFCLK_I

PLL_REFCLK_O

HUD_INTR

G14

A14

O₆

N/A

Crystal output. Used with PLL_REFCLK_I.

Interrupt signal. This active high signal indicates one of the

interrupt sources in the controller has been triggered.

3.30 V

I²C Clock for Device configuration and control. Requires external

pull-up. Port 1 peripheral command/control interface.

IIC_SCL_1

IIC_SDA_1

IIC_SCL_2

IIC_SDA_2

P16

N15

M15

N16

B₈

N/A

I²C Data for Device configuration and control. Requires external

pull-up. Port 1 peripheral command/control interface.

I²C Clock Debug Port. Requires external pull-up. Port 2 peripheral

command/control interface.

I²C Data Debug Port. Requires external pull-up. Port 2 peripheral

command/control interface.

Serial Data input from the external SPI Flash device. This

provides device logical programming data as well as functional

configuration parameter data.

FLASH_POCI

F14

I₂

FLASH_SCLK

FLASH_CSZ

F15

E16

O₆

FLASH_SCLK

N/A

Chip Select output for the external SPI Flash device. Active low.

Clock for the external SPI Flash device.

FLASH_SCLK

Serial Data output to the external SPI Flash device. This pin

sends address and control information as well as data when

programming.

FLASH_PICO

E15

O₆

FLASH_SCLK

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5.1 LED Driver Interface

I/O

CLOCK

SYSTEM

N/A

DESCRIPTION

NAME

NO.

POWER TYPE

LED_B_PWM

D16

O₆

Function reserved for future use.

Repurposed for power good control. Together with pin G13

(PWRGOOD), this signal is used for DLP30xx-Q1 parking as part of

the preconditioning sequence and subsequent unparking. See the

DLPC120-Q1 Programmer's Guide for implementation details.

LED_R_PWM

(PWRGOOD_CNTRL)

E14

O₆

N/A

LED_G_PWM

LED_B_EN

F13

C15

O₆

N/A

Function reserved for future use.

Blue LED enable strobe. Controlled by programmable DMD

sequence timing (active high)

Red LED enable strobe. Controlled by programmable DMD

sequence timing (active high)

LED_R_EN

LED_G_EN

LED_S_EN

LED_D_EN

LEDDRV_ON

C16

D14

B16

E13

D15

O₆

N/A

Green LED enable strobe. Controlled by programmable DMD

sequence timing (active high)

LED shunt enable. Controlled by programmable DMD sequence

timing (active high)

N/A

LED drive enable. Controlled by programmable DMD sequence

timing (active high)

N/A

3.30 V

O₆

LED driver enable. Active high output control to external LED drive

logic

Async

LED enable (active high input). A logic low on this signal forces

LEDDRV_ON low and RGB strobes low. These signals are enabled

100 ms after LED_EN transitions to a high (assuming

corresponding SW parameters are also set to enable LED

operation).

LED_EN

F16

I₂

Async

LED threshold compare (active low input). A logic low on this signal

indicates a threshold is reached, and in discontinuous mode

controls shunt enable (LED_S_EN).

LED_COMPZ

D13

I₂

Async

AST_CLR0

AST_HLD0

AST_INTR0

AST_CLR1

AST_HLD1

AST_INTR1

L12

M13

L13

O₆

N/A

Function reserved for future use

Sequence timer interrupt port

Function reserved for future use

M12

R16

M14

5.2 DMD Temperature Interface

I/O

CLOCK

NAME

NO.

POWER TYPE

SYSTEM

DESCRIPTION

Temperature control serial data. This signal is used to

communicate with the TMP411 to read the temperature values.

Follows I²C protocol as required by TMP411.

TMP_SDA

K13

B₈

Async

Temperature control serial clock. This signal is used to

communicate with the TMP411 to read the temperature values.

Follows I²C protocol as required by TMP411.

3.30 V

B₈

TMP_SCL

M16

C14

Async

HTR_ENABLE

O₆

Reserved pin

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General Purpose I/O

I/O

CLOCK

NAME

NO.

POWER TYPE

SYSTEM

DESCRIPTION

This pin is configured by default to be asserted at the lowest

brightness mode to activate flicker reduction logic in the LED

driver circuit. It is deasserted, otherwise, to deactivate the flicker

reduction logic for normal operation. Contact a TI Applications

Engineer for implementation details.

AUXBIT_0

(FLICKER_SELECT)

C13

O₆

Async

DMD sequencer reset AUX Bit 1. Intended for system debug.

Can be routed to a testpoint or left unconnected

AUXBIT_1

AUXBIT_2

AUXBIT_6

AUXBIT_7

B14

A15

D11

B13

O₆

Async

3.30 V

DMD sequencer reset AUX Bit 2. Intended for system debug.

Can be routed to a testpoint or left unconnected

O₆

DMD sequencer reset AUX Bit 6. Intended for system debug.

Can be routed to a testpoint or left unconnected

DMD sequencer reset AUX Bit 7. Intended for system debug.

Can be routed to a testpoint or left unconnected

5.3 Main Video and Data Control Interface

I/O

TYPE

I₂

CLOCK

SYSTEM

N/A

NAME

NO.

T8

POWER

DESCRIPTION

Pixel clock⁽¹⁾

PCLK

P_VSYNC

P_HSYNC

P_DATAEN

PDATA[0]

PDATA[1]

PDATA[2]

PDATA[3]

PDATA[4]

PDATA[5]

PDATA[6]

PDATA[7]

PDATA[8]

PDATA[9]

PDATA[10]

PDATA[11]

PDATA[12]

PDATA[13]

PDATA[14]

PDATA[15]

PDATA[16]

PDATA[17]

PDATA[18]

PDATA[19]

PDATA[20]

PDATA[21]

PDATA[22]

PDATA[23]

P7

I₂

Vertical sync⁽²⁾

Horizontal sync⁽²⁾

Data valid⁽²⁾

P8

I₂

N8

I₂

R8

I₂

T9

I₂

R9

I₂

T10

N9

I₂

R10

T11

P10

R11

T12

P11

R12

T13

P12

N11

R13

T14

T15

R14

N12

R15

N13

P14

P15

I₂

3.30 V

I₂

PCLK

I₂

Data⁽³⁾

I₂

(1) Pixel clock capture edge is software programmable.

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(2) VSYNC, HSYNC, and data valid polarity are software programmable.

(3) The 24-bit PDATA bus can be mapped based on pixel format. By default PDATA[23-16]=Red[7-0], PDATA[15-8]=Green[7-0], and

PDATA[7-0]=Blue[7-0]. See the DLPC120-Q1 Programmer's Guide for more information.

5.4 DMD Interface

I/O

CLOCK

NAME

NO.

B12

A13

A12

B11

C10

A11

D9

POWER TYPE

SYSTEM

DESCRIPTION

DMD_D0

DMD_D1

DMD_D2

DMD_D3

DMD_D4

DMD_D5

DMD_D6

DMD_D7

DMD_D8

DMD_D9

DMD_D10

DMD_D11

DMD_D12

DMD_D13

DMD_D14

DMD_DCLK

DMD_LOADB

DMD_SCTRL

DMD_TRC

DMD data pins. DMD data pins are DDR (Double Data Rate)

signals that are clocked on both edges of DMD_DCLK.

B10

A10

B9

O₅

DMD_DCLK

A9

A8

B8

C8

A7

A6

O₅

N/A

DMD data clock (DDR)

C7

DMD_DCLK

DMD data load signal (active low)

DMD data serial control signal

DMD data toggle rate control

B6

O₅

1.80 V

B7

O₅

DMD DAD output enable (active low). A pullup (10 kΩto 100

kΩ) to the 1.8-V rail for the DMD interface is needed to keep

this signal inactive when tristated.

DMD_DAD_OEZ

A5

O₅

Async

DMD_DAD_BUS

DMD_DAD_STRB

DMD_SAC_BUS

DMD_SAC_CLK

B5

D7

A4

A3

O₅

DMD_SAC_CLK

DMD_DCLK

DMD_SAC_CLK

N/A

DMD DAD bus data

DMD DAD bus strobe.

DMD SAC bus data

DMD SAC bus clock

DMD interface test clock. Signal connected to DMD JTAG

interface to allow the verification of the interface. The

interface is tristated when not active.

DMD_JTCK

DMD_JTMS

B4

C5

O₄

N/A

DMD interface test mode. Signal connected to DMD JTAG

interface to allow the verification of the interface. The

interface is tristated when not active.

DMD interface test data output. Signal connected to DMD

JTAG interface to allow the verification of the interface. This

signal connects to the DMD JTAG TDI. The interface is

tristated when not active.

DMD_JTDI

D5

O₄

N/A

DMD interface test data input. Signal connected to DMD

JTAG interface to allow the verification of the interface. This

signal connects to the DMD JTAG TDO. Internal pulldown.

DMD_JTDO

C4

I₁

O₆

N/A

DMD_PWR_EN

C11

3.30 V

Async

DMD power regulator enable (active high)

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5.5 Memory Interface

I/O

CLOCK

NAME

NO.

F2

F1

H1

C1

F4

D2

H2

G1

G2

G3

F3

E1

B1

D1

E2

J1

POWER

TYPE

SYSTEM

DESCRIPTION

MEM_CLK

MEM_CLKZ

MEM_A0

MEM_A1

MEM_A2

MEM_A3

MEM_A4

MEM_A5

MEM_A6

MEM_A7

MEM_A8

MEM_A9

MEM_A10

MEM_A11

MEM_A12

MEM_BA0

MEM_BA1

MEM_RASZ

MEM_CASZ

MEM_WEZ

MEM_CSZ

MEM_CKE

O_s

N/A

DDR memory, Differential Memory Clock.

MEM_CLK

DDR memory, Multiplexed Row and Column Address.

MEM_CLK

DDR memory, Bank Select.

J2

D3

J3

O_s

MEM_CLK

DDR memory, Row Address Strobe (Active low).

DDR memory, Column Address Strobe (Active low).

DDR memory, Write Enable (Active low).

DDR memory, Chip Select (Active low).

1.80 V

C2

K2

K1

DDR memory, Clock Enable (Active high).

DDR memory, On die termination (ODT). ODT is not verified

and supported operational mode. This pin should be left open

or connected to corresponding DDR2 pin.

MEM_ODT

MEM_RST

MEM_ZQ

E4

C3

J4

O_s

MEM_CLK

DDR memory, Reset. Do Not connect.

DDR memory, External pad where to connect the external

impedance calibration resistor. The user connects the PAD

pin through an external 240 Ω± 1% resistor to ground.

MEM_DQS0

MEM_DQSZ0

MEM_DQ0

MEM_DQ1

MEM_DQ2

MEM_DQ3

MEM_DQ4

MEM_DQ5

MEM_DQ6

MEM_DQ7

N1

N2

P2

R1

P1

M2

L3

B_SD

N/A

DDR memory, Lower Byte, R/W Data Strobe.

DDR memory, Lower Byte, R/W Data Strobe, inverted.

B_s

MEM_DQS0

DDR memory, Lower Byte, Bidirectional R/W Data.

M1

L2

L1

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I/O

TYPE

B_s

CLOCK

SYSTEM

N/A

NAME

NO.

R4

T4

T6

R6

T5

R5

P5

T3

T2

R3

POWER

DESCRIPTION

MEM_DQS1

MEM_DQSZ1

MEM_DQ8

MEM_DQ9

MEM_DQ10

MEM_DQ11

MEM_DQ12

MEM_DQ13

MEM_DQ14

MEM_DQ15

DDR memory, Upper Byte, R/W Data Strobe.

B_SD

N/A

DDR memory, Upper Byte, R/W Data Strobe, inverted.

1.80 V

B_s

MEM_DQS1

DDR memory, Upper Byte, Bidirectional R/W Data.

Board Level Test and Debug

I/O

CLOCK

NAME

NO.

POWER

TYPE

SYSTEM

DESCRIPTION

JTAG, Reset. Includes weak internal pull-up. Holds TAP controller

and associated JTAG logic in idle state under normal operation.

This pin should be pulled down with a 5 kΩor smaller

resistor for normal operation.

JTAGRSTZ

J13

I₂

Async

3.30 V

JTAGTDI

JTAGTCK

JTAGTMS

JTAGTDO

K15

L15

L16

K14

I₂

JTAGTCK

N/A

JTAG, Serial Data In. Includes weak internal pull-up.

JTAG, Serial Data Clock. Includes weak internal pull-up.

JTAG, Test Mode Select. Includes weak internal pull-up.

JTAG, Serial Data Out.

I₂

JTAGTCK

O₆

Manufacturing Test Support

I/O

CLOCK

NAME

NO.

POWER

TYPE

SYSTEM

DESCRIPTION

Manufacturing Test Enable signal. Should be connected directly to

ground on the PCB for normal operation. Weak Internal Pulldown.

HWTEST_EN

G16

3.30 V

I₂

O

N/A

Memory Controller Analog Test Output. Factory Test purposes

only, should be left unconnected in system.

MEM_ATO

MEM_DTO0

MEM_DTO1

K3

M4

N4

N/A

Memory Controller Digital Test Output #1. Factory Test purposes

only, should be left unconnected in system.

3.30 V

O_s

Memory Controller Digital Test Output #2. Factory Test purposes

only, should be left unconnected in system.

Test Point Interface

NAME

I/O

CLOCK

NO.

K16

J14

J15

J16

H16

H15

H12

POWER

TYPE

SYSTEM DESCRIPTION

TSTPT_0

TSTPT_1

TSTPT_2

TSTPT_3

TSTPT_4

TSTPT_5

TSTPT_6

Reserved for Test Outputs. These test I/O should be left open or

unconnected for normal operation in final product design. (DO

NOT tie to GND), Internal Pullup on all signals. TSTPT_4

should be pulled up using external 10 kΩresistor to ensure

proper initialization.

3.30 V

B₈

Async

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I/O

CLOCK

NAME

NO.

POWER

TYPE

SYSTEM DESCRIPTION

This pin is configured by default to indicate whether the system

is in Continuous Mode (High) or Discontinuous Mode (Low).

Contact a TI Applications Engineer for implementation details. It

can also be reserved as a Test Output.

TSTPT_7 (CM_DM)

H14

3.30 V

B₈

Async

Power and Ground

I/O

NAME

NO.

DESCRIPTION

VCCIO_1

VCCIO_2

VCCIO_3

B2, D4, G4, K4, M3, N5, P3, R7

BA2, D10, D12, D6, D8

PWR

1.8 V (DDR2 MEM).

1.8 V (DMD I/F).

3.3 V (MISC IO).

B15, E12, L14, N10, P13

Voltage Referenced Input

(50% of DDR Memory Voltage).

MEM_VREF0

MEM_VREF1

H4

N6

Voltage Referenced Input

(50% of DDR Memory Voltage).

VCCA

VSSA

VDD

G12

F12

PWR

PLL Power Input.

PLL R-C Return Path (NOT a GND).

1.2-V core logic power supply.

G8, G9, H7, H10, J7, J10, K8, K9

PWR

GND

EFUSE Programming voltage (Used in Manufacturing Test

VDDQ

GND

J12

only.)

Should be tied to GND.

A1, A16, B3, C6, C9, C12, E3, G7,

G10, H3, H8, H9, J8, J9, K7, K10,

K12, L4, N3, N7, N14, P4, P6, P9,

R2, T1, T7, T16

GND

Common Ground (I/O Ground).

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表5-2. I/O Type Subscript Definition

I/O

SUPPLY REFERENCE

SUBSCRIPT

DESCRIPTION

1.8 V

1

VDD

2

3.3 V

VCCIO_3

VDD

4

8 mA

5

6

6, 10, or 12 mA

8 mA

VCCIO_2

VCCA

S

SSTL_18

8 mA

VCCIO_1

VCCIO_3

VCCIO_1

8

SD

TYPE

I

SSTL_18 Differential

Input

O

Output

B

Bidirectional

Power

N/A

PWR

GND

Ground return

表5-3. Internal Pullup and Pulldown Characteristics

INTERNAL PULL-UP AND PULL-DOWN

RESISTOR CHARACTERISTICS

VCCIO

MIN

TYP

MAX

UNIT

Weak pull-up resistance

3.3 V

1.8 V

27

32

52

39

46

91

61

79

kΩ

Weak pull-down resistance

180

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) ⁽¹⁾

MIN

MAX

UNIT

SUPPLY VOLTAGE⁽²⁾

VCCIO_1

0

1.98

3.6

V

VCCIO_2

VCCIO_3

3.6

VCCA (PLL)

VDD

1.32

GENERAL

T_J

Operating junction temperature

Storage temperature

125

150

°C

–40

T_stg

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and

this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values are with respect to GND.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

All pins

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per AEC

Q100-011

Corner pins (A1, A16, T1,

and T16)

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.14

1.71

3.135

0.0

NOM

1.2

1.8

3.3

0.0

MAX

1.26

1.89

3.465

0.0

UNIT

V

VDD

1.2-V supply voltage, core logic

Analog voltage for PLL

VCCA

VCCIO_0

VCCIO_1

VCCIO_2

VDDQ

T_J

V

DDR2 memory interface

V

1.8-V supply voltage for DMD

Pixel interface supply voltage

EFuse programming voltage

Operating junction temperature

Operating ambient temperature⁽¹⁾

V

125

°C

–40

T_A

105

(1) Operating ambient temperature is dependent on system thermal design. Operating junction temperature may not exceed its specified

range across ambient temperature conditions.

6.4 Thermal Information

DLPC120-Q1

THERMAL METRIC⁽¹⁾

ZXS (BGA)

216 PINS

0.28

UNIT

Case-to-junction thermal coefficient

°C/W

ψ_JT

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6.4 Thermal Information (continued)

DLPC120-Q1

THERMAL METRIC⁽¹⁾

ZXS (BGA)

216 PINS

26.32

UNIT

T_JA

Junction-to-ambient thermal coefficient

°C/W

(1) For more information about traditional and new thermal metrics, see the , Semiconductor and IC Package Thermal Metrics Application

Report (SPRA953).

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

140

3

MAX UNIT

I_VDD

Logic core power (1.2 V)

PLL power (1.2 V)

186

10

mA

I_VCCA

DDR2 memory and DMD interface I/O

power (1.8 V)

I_{VCCIO_0/1}

I_{VCCIO_2}

180

245

mA

Pixel data input power (3.3 V)

Total power

4

10

mA

469

724

mW

6.6 Electrical Characteristics for I/O

PARAMETER

TEST CONDITIONS

MIN

1.17

2.0

TYP

MAX UNIT

VCCIO + 0.3

High-level

input

threshold

voltage

1.8-V LVCMOS (I/O Type 1)

3.3-V LVCMOS (I/O Type 2, 8)

SSTL_18 (I/O Type S, SD)

1.8-V LVCMOS (I/O Type 1)

3.3-V LVCMOS (I/O Type 2, 8)

SSTL_18 (I/O Type S, SD)

VCCIO + 0.3

0.63

V_IH

V

1.08

Low-level

input

threshold

voltage

–0.3

V_IL

0.8

V

0.73

1.8-V LVCMOS fixed current (I/O Type

4)

1.35

1.8-V LVCMOS variable current (I/O

Type 5)

High-level

output

V_OH

V

voltage

3.3-V LVCMOS fixed current (I/O Type

6, 8)

2.4

SSTL_18 (I/O Type S, SD)

VCCIO –0.28

1.8-V LVCMOS fixed current (I/O Type

4)

0.45

1.8-V LVCMOS variable current (I/O

Type 5)

Low-level

output

V_OL

V

voltage

3.3-V LVCMOS fixed current (I/O Type

6, 8)

0.4

SSTL_18 (I/O Type S, SD)

0.28

6.7 Power Supply and Reset Timing Requirements

MIN

MAX

UNIT

Power supplies can be applied in any order if they

occur within this maximum timing. Otherwise,

Time for all DLPC120-Q1 power rails to be

applied

t_ramp

10

ms

refer to Note ⁽¹⁾

.

PWRGOOD shall be controlled by

LED_R_PWM / PWRGOOD_CNTRL signal,

which is an output of the DLPC120-Q1 and will

automatically be asserted after the device

releases from reset.

RESETZ rising edge (or PWRGOOD

rising edge—whichever comes second) to

DMD_PWR_EN rising edge

t_{pwr_en}

150

µs

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6.7 Power Supply and Reset Timing Requirements (continued)

MIN

MAX

UNIT

ms

External delay between DMD_PWR_EN

and DMD mirror supply voltages

t_dly

This delay is not required for supported devices.

t_oez

DMD_PWR_EN rising edge to falling edge of DMD_OEZ

5

ms

It is required that the DMD executes a Pre-

Conditioning Sequence prior to parking. The final

action of this sequence is the de-assertion of the

LED_R_PWM / PWRGOOD_CNTRL signal,

which shall drive the PWRGOOD signal low. See

the DLPC120-Q1 Programmer's Guide for

instructions on how to execute the Pre-

Conditioning Sequence.

t_preconditionDMD preconditioning timeI

800

200

µs

t_park

DMD park time (approximate)

PWRGOOD low to falling edge of DMD_PWR_EN

Power supplies can be removed in any order if

200

500

µs

t_{pd_dmd}

they occur within this maximum timing.

Otherwise, they shall be removed in the reverse

order they were applied, per the t_ramp

Time for DLPC120-Q1 power supplies to

be removed

t_fall

10

ms

specification and Note ⁽¹⁾

.

(1) If the DLPC120-Q1 supplies cannot be applied according to this timing specification, then they must be applied in the following order,

spanning no longer than 100 ms (shall be removed in the reverse order for power down):

a. Apply VCCIO_2 (3.3 V)

b. Apply VCCIO_0, VCCIO_1 (1.8 V) DDR Memory and DMD, in any order

c. Apply VDD (1.2 V) DLPC120-Q1 core supply voltage

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t_ramp

t_fall

Power Supplies

t_precondition

DMD VCC rail must not

go low until after

DLPC120 reset

PWRGOOD

(ASIC input)

PLL_REFCLK

PLL_REFCLK must

be stable before

reset de-asserted

RESETZ

(ASIC input)

t_{pwr_en}

RESETZ must not go low

until after DMD MIRROR

SUPPLIES are within 4V

of ground

t_{pd_dmd}

DMD_PWR_EN

(ASIC output)

t_oez

t_park

DMD_OEZ

(ASIC output)

t_dly

DMD MIRROR SUPPLIES

(VBIAS, VOFFSET, VRESET)

图6-1. Power Supply and RESETZ Timing

6.8 Reference Clock PLL Timing Requirements

MIN

NOM

16.00

MAX UNIT

Clock frequency

Cycle time

MHz

ns

ƒ_clock

No clock spreading⁽¹⁾

62.5

t_c

With clock spreading⁽¹⁾

1.02 × t_c

ns

t_w(H)

t_w(L)

t_jp

Pulse duration, high

50% to 50% reference points

0.4 x t_c

–250

ns

Pulse duration, low

ns

Period jitter, PLL_REFCLK_I

250

ps

(1) PLL clock spreading is configurable. See DLPC120-Q1 Programmer's Guide for a description of how to select spread spectrum

options.

t_c

t_w(H)

t_w(L)

50%

PLL_REFCLK_I

50%

图6-2. PLL Reference Clock Timing

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6.9 Parallel Interface General Timing Requirements

MIN

3.1

MAX

UNIT

MHz

ns

Clock frequency, PCLK⁽¹⁾

40.0

ƒ_clock

t_{p_clkper}

t_{p_wh}

Clock period, PCLK

VIH/VIL

25.0

6.0

320.0

Pulse width low, PCLK

Pulse width high, PCLK

ns

t_{p_wl}

6.0

ns

Setup time - HSYNC, DATEN, PDATA(23:0)

valid before the active edge of PCLK⁽²⁾

t_{p_su}

VIH/VIL

2.0

ns

Hold time - HSYNC, DATEN, PDATA(23:0)

valid after the active edge of PCLK⁽²⁾

t_{p_h}

t_t

VIH/VIL

2.0

0.2

ns

Transition time - PCLK

10% to 90% reference points

6

(1) This range includes the 200 ppm of the external oscillator.

(2) The active (capture) edge of PCLK for HSYNC, DATEN, and PDATA(23:0) is software programmable, but defaults to rising edge.

t_{p_clkper}

t_{p_wh}

t_{p_wl}

PCLK

t_{p_h}

t_{p_su}

PDATA(23:0),

DATAEN,

HSYNC, VSYNC,

图6-3. Parallel Video Interface General Timing

6.10 Parallel Interface Frame Timing Requirements

MIN

1

MAX

UNIT

Lines

t_{p_vsw}

t_{p_vbp}

t_vfp

Vertical sync width

Vertical back porch

Vertical front porch

Horizontal sync width

Horizontal back porch

Horizontal front porch

50% reference points

6

Lines

4⁽¹⁾

Lines

t_hsw

t_hbp

5

PCLKs

4

t_hfp

40⁽¹⁾

(1) Values depend on many factors and may need to be higher depending on scaling ratio and other factors. See resolution table for

typical values that have been verified.

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1 Frame

t_{p_vsw}

VSYNC

(This diagram assumes the VSYNC

active edge is the Rising edge)

t_{p_vbp}

t_{p_vfp}

HSYNC

DATAEN

1 Line

t_{p_hsw}

HSYNC

(This diagram assumes the HSYNC

active edge is the Rising edge)

t_{p_hfp}

t_{p_hbp}

DATAEN

PDATA(23:0)

PCLK

P

n-2

P

n-1

P0

P1

P2

P3

Pn

图6-4. Parallel Interface Frame Timing

6.11 Flash Memory Interface Timing Requirements

MIN

NOM

MAX UNIT

Clock frequency, FLASH_SCLK⁽¹⁾

39.00

25.64

MHz

ns

ƒ_clock

t_clkper

t_wh

Clock period, FLASH_SCLK

Pulse width high, FLASH_SCLK

Pulse width low, FLASH_SCLK

50% reference points

10

ns

t_wl

ns

20% to 80% reference points,

C_load= 20 pF

t_t

Transition time, all signals

1

3

ns

Flash POCI valid data max delay after

FLASH_SCLK falling edge

t_{valid_POCI}

t_{valid_PICO_b}

t_{valid_PICO_a}

50% reference points

10

PICO valid before rising edge of

FLASH_SCLK

2.2

5.2

PICO valid after rising edge of

FLASH_SCLK

(1) Spread Spectrum clock modulation, when enabled, will affect the nominal frequency of the FLASH_SCLK.

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t_clkper

t_wl

FLASH_SCLK

(DLPC120 Output)

t_wh

t_{valid_POCI}

FLASH_POCI

(DLPC120 Input)

t_{valid_PICO_b}

t_{valid_PICO_a}

FLASH_PICO

(DLPC120 Outputs)

图6-5. Flash Interface Timing

6.12 DMD Interface Timing Requirements

MIN

75.00

12.5

NOM

MAX

UNIT

MHz

ns

Clock frequency, DMD_DCLK and DMD_SAC_CLK⁽¹⁾

78.00

80.00

15.0

200

ƒ_clock

t_{p_clkper}

t_{p_clkjit}

Clock period, DMD_DCLK and DMD_SAC_CLK

Clock jitter, DMD_DCLK and DMD_SAC_CLK

50% reference points

Maximum f_clock

ps

Pulse width high, DMD_DCLK and

DMD_SAC_CLK

t_{p_wh}

50% reference points

6.2

ns

Pulse width low, DMD_DCLK and

DMD_SAC_CLK

t_{p_wl}

t_t

50% reference points

6.2

0.5

ns

Transition time, all signals

20% to 80% reference points

1.5

Output setup time –DMD_D(14:0),

DMD_SCTRL, DMD_LOADB and DMD_TRC

relative to both rising and falling edges of

DMD_DCLK⁽²⁾

t_{p_su}

50% reference points

ns

Output hold time –DMD_D(14:0), DMD_SCTRL,

DMD_LOADB and DMD_TRC signals relative to

both rising and falling edges of DMD_DCLK⁽²⁾

t_{p_h}

50% reference points

1.5

0.20

1.65

ns

DMD data skew –DMD_D(14:0), DMD_SCTRL,

DMD_LOADB and DMD_TRC signals relative to

each other

t_{p_d1_skew}

DAD/ SAC data skew - DMD_SAC_BUS,

DMD_DAD_OEZ and DMD_DAD_BUS signals

relative to DMD_SAC_CLK

t_{p_d2_skew}

t_{p_d3_skew}

t_{p_clk_skew}

DMD_DAD_STRB signal relative to DMD_DCLK 50% reference points

1.65

0.25

ns

Clock skew – DMD_DCLK and DMD_SAC_CLK

50% reference points

relative to each other

(1) This range includes the 200 PPM of the external oscillator.

(2) Output setup and hold numbers already account for ASIC clock jitter. Only routing skew and DMD setup/ hold need be considered in

system timing analysis.

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t_{p_d1_skew}

DMD_D(14:0)

DMD_SCTRL

DMD_TRC

DMD_LOADB

t_{p_h}

t_{p_su}

DMD_DCLK

t_{p_wl}

t_{p_wh}

t_{clk_skew}

DMD_SAC_CLK

t_{p_d2_skew}

DMD_SAC_BUS

DMD_DAD_OEZ

DMD_DAD_BUS

t_{p_d3_skew}

DMD_DAD_STRB

图6-6. DMD Interface Timing

6.13 JTAG Interface Timing Requirements

MIN

MAX

UNIT

MHz

ns

Clock frequency, JTAGTCK

Cycle time, JTAGTCK

Pulse duration high

10

ƒ_clock

t_c

100

40

t_w(H)

t_w(L)

t_t

50% to 50% reference points

20% to 80% reference points

ns

Pulse duration low

40

ns

Transition time, t_t= t_f= t_r

5

ns

Setup time, JTAGTDI valid before JTAGTCK rising edge, and JTAGTMS valid before

JTAGTCK rising edge

t_su

10

ns

t_h

Hold time, JTAGTDI valid after JTAGTCK, and JTAGTMS valid after JTAGTCK

Output propagation, clock to Q. JTAGTCK falling edge to JTAGTDO

10

3

ns

t_pd

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t_t

t_c

t_w(H)

t_w(L)

80%

20%

JTAGTCK

(input)

50%

t_su

t_h

JTAGTDI

JTAGTMS

(inputs)

Valid

t_pd(max)

JTAGTDO

(outputs)

Valid

图6-7. JTAG Interface Timing

6.14 I²C Interface Timing Requirements

MIN

20

MAX

UNIT

Clock frequency

400

kHz

ƒ_scl

t_sch

t_scl

t_sp

Clock duration high

0.6

μs

ns

Clock duration low

1.3

Spike time

0

400

t_sds

t_sdh

t_icr

Setup time

100⁽³⁾

ns

Hold time

0⁽¹⁾

0.9⁽²⁾

300

μs

ns

(4)

Input rise time

20 + 0.1 x C_b

(4)

t_ocf

t_buf

t_sts

t_sth

t_sph

Output fall time

1 + 0.1 x C_b

300

ns

Bus free time between stop and start conditions

Start or repeated start condition setup

Start or repeated start condition hold

Stop condition hold

1.3

0.6

μs

(1) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

(2) The maximum t_{HD_DAT}has only to be met if the device does not stretch the LOW period (t_LOW) of the SCL signal.

(3) A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement t_{SU_DAT}250 ns must then be met.

This is automatically the case since the device does not stretch the LOW period of the SCL signal.

(4) C_b= total capacitance of one bus line in pF.

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7 Parameter Measurement Information

7.1 Parallel Interface Input Source Timing

The supported sources with typical timings are shown in 表7-1.

表7-1. Parallel Interface Supported Resolutions (Typical Timing)

RESOLUTION

HORIZONTAL

VERTICAL

CLOCK

MHz

SYNC

WIDTH

SYNC

WIDTH

HORIZONTAL

VERTICAL

FP

BP

FP

BP

320

400

480

500

640

800

852

853

854

864

960

608

120

160

240

250

160

240

480

240

480

160

240

250

480

684⁽¹⁾

40

42

32

50

24

41

50

70

50

74

72

70

40

6

4

7

1

3.1

4.2

42

15

16

8

7

6.3

48

6

7.8

96

14

15

19

8

9.4

50

36

11

14

35

14

35

5

10.2

8.3

41

104

84

12.6

25.2

31.5

15.8

31.5

12.6

18.9

19.7

37.8

33.33

9

144

68

9

67

9

68

9

68

9

60

9

164

46

9

13

14

35

104

9

30

(1) Optical Bypass Mode.

7.2 Design for Test Functions

The DLPC120-Q1 has several built-in test features. These tests can be run to verify ASIC functionality on startup

or during normal operation. Refer to DLPC120-Q1 Programmer's Guide for more detail regarding test usage. 表

7-2 defines the execution time of each test.

表7-2. Test Execution Times

TEST NAME

LENGTH (ms) SUMMARY

The Short DDR2 BIST implements a memory check using a March13 Algorithm to verify the

external DDR2 SDRAM frame buffer space. It runs at power-up or also can be executed on

demand, but it is recommended to run only at power-up, since the image will flash if executed

on demand. The short version runs a portion of the long test.

DDR2 BIST (Short)

DDR2 BIST (Long)

FLASH BIST (1 MByte)

145

470

215

The Long DDR2 BIST is the same as the Short DDR2 BIST, but it runs the test multiple times.

The Flash BIST calculates configuration memory checksum (32 bits) for data integrity of the

Flash data and interface. Flash checksum is recommended to be done at power-up to verify

configuration settings. The Flash BIST memory range to perform checksum is programmable to

up to 32M.

The System BIST validates the DLPC120-Q1 internal logic. It sends a known test pattern image

through the ASIC to verify the checksum at the last stage before the data reaches the DMD.

When enabled, the checksum for each frame of data is calculated and stored in an I²C register.

System BIST⁽²⁾

See⁽¹⁾

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表7-2. Test Execution Times (continued)

TEST NAME

LENGTH (ms) SUMMARY

The DMD JTAG BIST validates the connection between the ASIC and DMD. It uses the DMD

JTAG interface to sample the ASIC pins and compare against expected values, and it also tries

to detect shorts between signals. The BIST is run on demand.

DMD Interface Test

6.93

The Front End Video Checksum is used to verify that the video is received correctly at the front

end on the specified region of the frame. When enabled, it calculates the checksum for the

specified region of the video frame and stored in an I²C register.

Front End Video

Checksum

See⁽¹⁾

The Video Detect test shall be used to monitor external video VSYNC. If external video is not

valid, the DMD must be put into a safe state (e.g. switched to an internal black test

pattern).

Video Detect Test

(1) The length of these tests will vary depending on frame rate but will not exceed 2 frames.

(2) Some processing options must be turned off for this test.

8 Detailed Description

8.1 Overview

The DLPC120-Q1 is compatible with three DMD components:

• DLP3030-Q1 - 0.3 WVGA S450 DMD

• DLP3020-Q1 - 0.3 WVGA FQR DMD

• DLP3021-Q1 - 0.3 WVGA FQR DMD

The DLPC120-Q1 formats incoming video data from a parallel interface and drives the DMD timing to display the

video. It also controls illumination enables to strobe illuminators synchronously with the DMD mirror movement.

The DLPC120-Q1 is designed for automotive applications with a wide operating temperature range and

diagnostic features to identify certain failure modes.

8.2 Functional Block Diagram

PIXEL

DATA

DLPC120

24

16

FRAME

MEMORY

CONTROLLER

FRONT END

PROCESSING

DDR

DRAM

DDR

VIDEO-GRAPHICS

PROCESSING

CONFIGURATION

CONTROL

DISPLAY

CONTROL

DMD

FORMATTING

CLOCKS

& RESETS

PLL

I2C

SPI

DDR

SERIAL

FLASH

LED

DRIVER

OSC

0.3 WVGA

DMD

HOST

CONTROLLER

图8-1. Functional Block Diagram

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8.3 Feature Description

8.3.1 Serial Flash Interface

The DLPC120-Q1 utilizes an external SPI serial flash memory device for configuration support. The minimum

required size is dependent on the desired minimum number of Sequences, CMT tables, and Splash options,

while the maximum supported size is 64 Mb. The DLPC120-Q1 can be used to Read, Erase, and program the

serial flash. Refer to DLPC120-Q1 Programmer's Guide for details of Flash configuration information.

The DLPC120-Q1 utilizes a single SPI interface, employing SPI mode 0 protocol, operating at a frequency of

39.0 MHz. All read operations assume the Flash supports address auto-incrementing. The DLPC120-Q1 should

support any flash device that meets these criteria plus the criteria listed in 表8-1.

表8-1. SPI Flash Instruction Op Code Compatibility Requirements

FLASH COMMAND

Fast Read (Single Output)

Read Electronic Signature

Others

OPCODE

0x0B

0xAB

May vary

The DLPC120-Q1 does not have any specific Page, Block or Sector size requirements. If the user would like to

use a portion of the serial flash for storing external data (such as calibration data) via the I²C interface, then the

minimum sector size needs to be considered as it will drive minimum erase size. Note that use of serial flash for

storing external data may impact the number of features that can be supported.

The DLPC120-Q1 does not drive the /HOLD (active low Hold) or /WP (active low Write Protect) pins on the flash

device and thus these pins should be tied to a logic high on the PCB via an external pull-up.

表8-2. DLPC120-Q1 Compatible SPI Flash Device Options

VENDOR

ISSI

PART NUMBER

IS25LP064A-JMLE

W25Q64CVSFAG

DENSITY (Mb)

SUPPLY VOLTAGE SUPPORTED⁽¹⁾

64

3.3 V

Winbond

Spansion

Micron

S25FL064P0XMFV000

M25P64-VMF3TPB

(1) The Flash supply voltage must match VCCIO_2 on the DLPC120-Q1. Multiple voltage options are often available under the same base

part number.

8.3.2 Serial Flash Programming

The external serial flash may also be programmed via the same SPI interface which is connected to the

DLPC120-Q1. In order to avoid conflicting data on this interface, the DLPC120-Q1 must be held in reset while

the flash memory is programmed. See flash specification for details of the programming configuration.

8.3.3 DDR2 Memory Interface

The DLPC120-Q1 ASIC DDR2 Memory interface consists of a 16-bit wide, 312-MHz (nominal) DDR2 interface

with standard signaling. The DLPC120-Q1 only support DDR2 interface with external termination. The DDR2

interface is a very high speed signaling interface.

A DDR2 memory should be selected that supports the 312-MHz clock frequency and compliant to the JEDEC

standard for DDR2 memories (JESD79-2A).

表8-3. Compatible JEDEC DDR2 Devices

PARAMETER

MIN

DDR2-800

X16

MAX

UNITS

JEDEC DDR2 device speed grade⁽¹⁾

JEDEC DDR2 device bit width

JEDEC DDR2 device count

JEDEC DDR2 Memory size

Bits

1

Device(s)

MByte

512

1024

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表8-3. Compatible JEDEC DDR2 Devices (continued)

PARAMETER

MIN

MAX

UNITS

CAS Latency

5

(1) The DDR2 interface operates with a clock frequency of 312 MHz, higher DDR2 speed grades are supported due to inherent JEDEC

DDR2 backwards compatibility.

表8-4. DLPC120-Q1 Compatible DDR2 Device Options

VENDOR

ISSI

PART NUMBER

SIZE

512 Mb

1 Gb

ORGANIZATION

SPEED GRADE

C_L

5

IS46DR16320C-25DBLA2

MT47H64M16HR-25E AAT

MT47H32M16HR-25E AAT

32Mx16

DDR2-800

Micron

32Mx16

DDR2-800

5

512 Mb

32Mx16

DDR2-800

5

8.3.4 JTAG and DMD Interface Test

The DLPC120-Q1 has two test interfaces using JTAG protocol:

• A standard JTAG (IEEE-1149) function of the ASIC is provided. The TI-provided BSDL file contains the

details of the DLPC120-Q1 boundary scan chain. This JTAG interface is provided to enable system level

validation of proper assembly of the DLPC120-Q1 onto a PCB.

• The DLPC120-Q1's DMD interface is designed to be the controller for an in-system DMD interface test. The

DMD interface should be connected directly to the DMD's JTAG pins. This interface is exclusively designed

and verified to support the DLP3030-Q1, DLP3020-Q1 and DLP3021-Q1.

DLPC120

DMD

Boundary Scan Register

JTAGRSTZ

JTAGTCK

JTAGTMS

JTAGTDI

DMD_JTCK

DMD_JTMS

DMD_JTDI

DMD_JTDO

JTAG

TAP

Controller

JTAG

TAP

Controller

DMD

I/F

Tester

State Machine

JTAGTDO

DMD Interface

(data and control)

Boundary Scan Register

CORE LOGIC

图8-2. JTAG and DMD Interface Test

Using the DMD JTAG function, the DMD interface signals are toggled, and the connection at the DMD is verified

by using the DMD JTAG signals to sample the inputs, and then toggled back to the DLPC120-Q1 for comparison

to expected values. All DMD logic signals, except DAD OEZ, are tested individually for stuck high or low

independently. Alternating data pattern for adjacent pins, as well as "walking 1’s" and "walking 0’s" patterns

are used during the test. The DAD_OEZ is only tested in the high state as asserting this signal and toggling the

inputs could cause damage to the DMD. Refer to 图 8-3 for recommended connections for the DLPC120-Q1

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boundary scan test configuration. Refer to 图 8-4 for recommended connections of the DLPC120-Q1 to DMD

interface test. For additional information about the DMD Boundary scan function refer to the specific DMD device

datasheet.

test

connector

JTAGRSTZ

JTAGTCK

JTAGTMS

JTAGTDO

JTAGTDI

JTAGRSTZ

JTAGTCK

JTAGTMS

JTAGTDI

JTAGTDO

DLPC120

3.3 V

DLPC120 standard JTAG I/F

图8-3. DLPC120-Q1 JTAG Boundary Scan Connection Example

DMD_JTCK

DMD interface test I/F

DMD_JTMS

1.8 V

DMD_JTDO

DLPC120

DMD_JTDI

DMD (Data & control signals)

location of optional board

to board connection

DMD (Data & control signals)

DMD_JTCK

DMD input pins and

input boundary JTAG

pins available for test

when disconnected from

DLPC120 via board to

board connection

DMD

DMD input boundary scan JTAG I/F

DMD_JTMS

DMD_JTDI

DMD_JTDO

1.8 V

图8-4. DLPC120-Q1 JTAG to DMD Interface Connection Example

8.3.5 Temperature Monitor Function

The DLPC120-Q1 connects with the TMP411 through a standard I²C bus protocol using the TMP_SDA and

TMP_SCL pins. The internal temperature controller initializes the TMP411 to read the temperature of the DMD.

The TMP controller issues a set of read commands at eight times per second through the I²C interface to read

the remote temperature (DMD) and local temperature from the TMP411.

The TMP411 monitors the DMD temperature and controls the DMD park operation when the DMD is operated

beyond the required specification. See the DLP3030-Q1, DLP3020-Q1 and DLP3021-Q1 Data Sheet for the

DMD operating temperature. If the DMD park operation is used, then a 1-degree hysteresis is applied. See the

DLPC120-Q1 Programmer's Guide for description of this function.

8.3.6 Host Command Interface

The DLPC120-Q1 provides two I²C interface port for host commands. Only one of these ports is intended to be

used at a time. The unused port is meant for system debug or development purposes. The I²C protocol and

register definitions are defined in the DLPC120-Q1 Programmer's Guide.

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8.4 Device Functional Modes

The DLPC120-Q1 has three operational display modes, which are selected with command list execution via the

Host control interface. These display modes are External Video, Splash Screen, and Test Pattern.

8.4.1 External Video Mode

Upon the release of reset and initialization, the DLPC120-Q1 will automatically enter in External Video mode.

This mode will process the video source on the parallel RGB input interface at a given resolution and frame rate.

The system supports multiple input video resolutions, and the resolution expected by the DLPC120-Q1 can be

configured via command list execution. See 表 7-1 for the different external video resolutions supported by the

system.

8.4.2 Splash Screen Mode

This mode displays a custom, static image, which is stored in the DLPC120-Q1 Application Serial Flash memory.

The content of the splash image is configurable. The Flash memory can store multiple Splash Screens, where

the quantity is limited by the size of the splash images, size of the memory chip, and capacity of the remaining

memory contents. Splash Screens are displayed via command list execution. Contact a TI Applications Engineer

in order to change the splash images stored in the Flash memory.

8.4.3 Test Pattern Mode

This mode displays a fixed, static image, which is stored in the DLPC120-Q1 Application Serial Flash memory.

The content of the test patterns are pre-defined, limited by the design of the DLPC120-Q1. Test Patterns are

displayed via command list execution. See DLPC120-Q1 Programmer's Guide for a list and image of the

supported Test Patterns.

9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The DLPC120-Q1 is a DLP display processor that supports automotive head-up display (HUD) applications. It

accepts data from a variety of video input resolutions and provides the digital image processing and control

necessary to drive an LED based DLP display system. This document reflects the operation, pinout, and timing

associated with the DLPC120-Q1 device only.

The DLPC120-Q1 is compatible with three DMD components:

• DLP3030-Q1 –0.3 WVGA S-450 DMD

• DLP3020-Q1 –0.3 WVGA FQR DMD

• DLP3021-Q1 –0.3 WVGA FQR DMD

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9.2 Typical Application

color & dimming control bus

FLASH

_LSMF_LUL_TA_daS_taH

SEQ/CMT data

ICP code

TMP411 data

- Devices included in HUD reference design

- Devices available in TI catalog portfolio

SPI

TMS320

F28023

Color

Controller

& Driver

LED_COMPZ

RGBSD_EN(5)

I2C2(2)

SPI (4)

HUD

Display

Graphics &

Control

Processor

LEDs

(parallel RGB)

CLK

HUD_INTR

AST_INTR0

Optional

LVDS

transmit/

receiver

chipset

real-time

optical

feedback

loop

CAN

XCVR

CTL(4)

OPA354 -Q1

LED Sensor

DATA(24)

DLPC120

JTAG(4)

DMD JTAG(4)

DLP3030-Q1

debug port

I2C1(2)

DCLK, CTL(4), DATA(15)

SAC_CLK, SAC, DAD(2)

.3" WLP(H) s450

DVSP DMD

RESETZ

PWRGOOD

TMP(2)

(2)

automotive

power

conditioning/

protection

Discrete DC

Supplies &

Power Mgmt

battery

12V net

TMP411

-Q1

DMD remote die

temperature

sensor

DATA(16)

ADDR

CTL(9)

(12)

TPS65140

-Q1

DDR-2 DRAM

Frame Buffer

DMD_PWR_EN

DC Supply

Voltages

图9-1. DLPC120-Q1 System Block Diagram

9.2.1 Design Requirements

The 图 9-1 shows a typical projector application. For this application, the DLPC120-Q1 is controlled by a

separate control processor, and the image data is received through the parallel RGB interface.

As with prior DLP^®electronics solutions, image data is 100% digital from the DLPC120-Q1 input port to the

image projected on to the display screen. The image stays in digital form and is never converted into an analog

signal. The DLPC120-Q1 processes the digital input image and converts the data into a bit-plane format, as

needed by the DMD. The DMD then reflects light to the screen using binary pulse-width-modulation (PWM) for

each pixel mirror. The viewer’s eyes integrate this light to form brilliant, crisp images.

The DLPC120-Q1 provides signals that enable red, green, and blue LEDs to synchronize to the DMD PWM bit

planes. These signals combined with an external MCU (TMS320F28023) can be used to create a very high

dynamic dimming range necessary for automotive heads-up display (HUD) applications.

The DLPC120-Q1 also features temperature monitoring of the DMD in order to automatically park the

micromirrors when the DMD temperature is beyond the operating range.

The DLPC120-Q1 uses the DDR2 SDRAM as a frame buffer to convert RGB video data into the necessary bit

plane format required by the DMD. The DLPC120-Q1 also supports multiple input resolutions and scales them to

match the native .3" WVGA DMD format. These images can also be electronically bezel-adjusted on the DMD,

which could allow the displayed image to be electronically adjusted for mechanical misalignment. The DLPC120-

Q1 is configured at power up with data stored in the Flash memory via SPI. The Flash interface is the primary

method to configure the controller.

The DLPC120-Q1 supports system diagnostic and self-check features, such as video detection, DDR2 memory

Built-in Self Test (BIST), System BIST, Flash BIST, and JTAG (in system and DMD interface).

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Due to the mechanical nature of the micromirrors, the latency of the DMD and DLPC120-Q1 chipset is fixed

across all temperature and operating conditions. The observed video latency is one frame, or 16.67 ms at an

input frame rate of 60 Hz. However, please note that the use of the DLPC120-Q1 bezel adjustment feature, if

enabled, requires an additional frame of processing.

Contact a TI Applications Engineer in order to gain access to a fully functional reference design based on the

DLP30xx-Q1 chipset.

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10 Power Supply Recommendations

10.1 Power Supply Filtering

The following filtering circuits are recommended for the various supply inputs.

68 Ohm 1 A

1.8 V

VCC18

VDD18_B

VDD

2.2 µF

0.1 µF

0.1 µF 0.01 µF 0.01 µF 0.01 µF 0.01 µF

2.2 µF

图10-1. VCC18 Recommended Filter

68 Ohm 1 A

1.8 V

2.2 µF

0.1 µF

0.1 µF 0.01 µF 0.01 µF 0.01 µF 0.01 µF

2.2 µF

图10-2. VDD18_B Recommended Filter

68 Ohm 1 A

1.2 V

2.2 µF

0.1 µF

0.1 µF 0.01 µF 0.01 µF

2.2 µF

图10-3. VDD Recommended Filter

68 Ohm 1 A

3.3 V

VDD33

2.2 µF

0.1 µF

0.1 µF 0.01 µF 0.01 µF 0.01 µF

2.2 µF

图10-4. VDD33 Recommended Filter

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11 Layout

11.1 Layout Guidelines

11.1.1 PCB layout guidelines for internal ASIC PLL power

The PLL’s two analog supplies, VCCA and VSSA, shall be filtered with two series ferrite beads and two shunt

0.1-µF and 0.01-µF capacitors. The ferrite on VSSA is preferred but optional.

Ferrite

VDD

VCCA

0.1 µF

0.01 µ F

Ferrite

VSSA

VSS

图11-1. PLL Power Guidelines

表11-1. Recommended PLL Filter Components

COMPONENT

Shunt Capacitor

PARAMETER

RECOMMENDED VALUE

UNIT

µF

Ω

Capacitance

0.1

Capacitance

0.01

Impedance at 10 MHz

Impedance at 100 MHz

DC Resistance

>= 180

>= 600

< 0.40

Series Ferrite

Ω

Example ferrite bead recommendations are listed in 表11-2.

表11-2. PLL Power Ferrite Bead Recommendations

PART NUMBER

BLM18EG601SN1

BLM15AX601SN1

R @ DC

Z @ 10 MHz

Z @ 100 MHz

Z @1-GHz SIZE

0603

0.35

200

600

0.34

190

0402

The capacitors should be mounted as close to the package balls as possible.

11.1.2 DLPC120-Q1 Reference Clock

The DLPC120-Q1 requires an external reference clock to feed its internal PLL. A crystal or oscillator can supply

this reference. The recommended crystal configurations and reference clock frequencies are listed in 表 11-3,

with additional required discrete components shown in 图11-2 and defined in 表11-3.

PLL_REFCLK_I

PLL_REFCLK_O

R

FB

R

S

Crystal

C

L2

L1

A. C_L= Crystal load capacitance

B. R_FB= Feedback Resistor

图11-2. Discrete Components Required When Using Crystal

11.1.2.1 Recommended Crystal Oscillator Configuration

表11-3. Recommended Crystal Configuration

PARAMETER

RECOMMENDED

UNIT

Crystal circuit configuration

Parallel resonant

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表11-3. Recommended Crystal Configuration (continued)

PARAMETER

RECOMMENDED

Fundamental (first harmonic)

16

UNIT

Crystal type

Crystal nominal frequency

MHz

PPM

Crystal frequency tolerance (including accuracy, temperature, aging and trim sensitivity) ±200

Maximum crystal equivalent series resistance (ESR)

Temperature range

80

Ω

°C

–40°C to +105°C

1

R_FBfeedback resistor (nominal)

C_L1external crystal load capacitor

C_L2external crystal load capacitor

MΩ

pF

See equation in ⁽¹⁾

See equation in ⁽²⁾

pF

A ground isolation ring around the

crystal is recommended

PCB layout

(1) CL1 = 2 × (CL –Cstray_pll_refclk_i), where: Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin

associated with the ASIC pin PLL_REFCLK_I. PLL_REFCLK_I device capacitance is approximately 3 pF.

(2) CL2 = 2 × (CL –Cstray_pll_refclk_o), where: Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin

associated with the ASIC pin PLL_REFCLK_O. PLL_REFCLK_O device capacitance is approximately 3 pF.

11.1.3 General PCB Recommendations

TI provides PCB design files that serve as a reference for DLPC120-Q1 and DLP30xx-Q1 chipset PCB

schematics and layout designs. Please contact a TI Applications Engineer to access these files.

11.1.4 PCB Routing Guidelines

All signals should follow a 0.005-in width 0.015-in spacing design rule. Minimum trace clearance from the ground

ring around the PCB shall be 0.1-in minimum. Actual trace widths and clearances will be determined based on

an analysis of impedance and stack-up requirements, some variation is expected.

表11-4. PCB Trace Matching Recommendations

GROUP

SIGNAL

CONSTRAINTS⁽¹⁾

MEM_CLK

MEM_CLKZ

MEM_DQS0

MEM_DQSZ0

MEM_DQS1

MEM_DQSZ1

Lengths Matched to 25 mils

Max Total Length: 1500 mils

Impedance: 100-Ωdifferential (± 10%)

Lengths Matched to 50 mils

Max Total Length: 1500 mils

Impedance: 50 Ω(± 10%)

DDR2 I/F

MEM_DQ[0:15]

MEM_RASZ

MEM_CASZ

MEM_WEZ

MEM_CSZ

MEM_CKE

MEM_A[0:12]

Lengths Matched to 100 mils

Max Total Length: 1500 mils

Impedance: 50 Ω(± 10%)

DMD_D[0:14]

DMD_DCLK

DMD_BUS

DMD_STRB

DMD_OEZ

DMD_LOADB

DMD_SAC_CLK

DMD_SAC_BUS

DMD_SCTRL

DMD_TRC

Lengths Matched to 50 mils

Max Total Length: 10000 mils

Impedance: 50 Ω(± 10%)

DMD I/F

DMD_JTCK

DMD_JTDI

DMD_JTDO

DMD_JTMS

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表11-4. PCB Trace Matching Recommendations (continued)

GROUP

SIGNAL

CONSTRAINTS⁽¹⁾

FLASH_DCLK,

FLASH_POCI,

FLASH_PICO,

FLASH_CSZ

Lengths Matched to 100 mils

Max Total Length: 2500 mils

Impedance: 50 Ω(± 10%)

Serial Flash I/F

(1) Trace lengths on Layers 1 and 10 should be less than 50 mils.

11.1.5 Number of Layer Changes

• As a reference, the TI design uses no more than three layer changes per trace.

• Individual differentially matched signal pairs can be routed on different layers, but the signals of a given pair

should not change.

11.1.6 Terminations

• All DMD I/F signals should be terminated at the source with a 20-Ωseries resistor.

• MEM_CLK and MEM_CLKZ should be terminated with an external 100-Ωdifferential resistor across the two

signals as close to the DRAM as possible. All other DDR2 control and data signals should be pulled to

VTT(0.9 V) with a 56-Ωresistor as close to the DRAM as possible.

11.1.7 General Handling Guidelines for Unused CMOS-Type Pins

To avoid potentially damaging current caused by floating CMOS input-only pins, it is recommended that unused

ASIC input pins be tied through a pull-up resistor to its associated power supply or a pull-down to ground. For

ASIC inputs with an internal pull-up or pull-down resistors, it is unnecessary to add an external pullup or

pulldown unless specifically recommended. Note that internal pull-up and pull-down resistors are weak and

should not be expected to drive the external line. The DLPC120-Q1 implements very few internal resistors and

these are noted in the pin list.

Unused output-only pins can be left open. When possible, it is recommended that unused Bi-directional I/O pins

be configured to their output state such that the pin can be left open. If this control is not available and the pins

may become an input, then they should be pulled-up (or down) using an appropriate resistor.

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12 Device and Documentation Support

12.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

12.2 Device Support

12.2.1 Device Nomenclature

12.2.1.1 Device Markings

Line 1: Part Number (P/N)

PDLPC120ZXSQ1

Line 2: TI Internal Marking Information

ECP292533A-1G

Line 3: Lot, Wafer, and Die Numbers

LLLLLL.ZZZXX

YYWW

Line 4: Data Code (YY = Year,

WW = Week)

TAIWAN

G1

Line 5: Country of Assembly Origin

Environmental

Pin A1 ID

Compliance Logo

图12-1. Device Marking

PDLPC120ZXSRQ1

—Q1“ - Automotive Grade

—R“ - Tape and reel required for

production orders. 500 pcs / reel.

Removed for tray packaging.

—ZXS“ - Package Designator. 216 pin

plastic ball grid array

—DLPC120“ - DLP Controller Base Part Name

—P“ - Indicates Prototype, removed from

production samples

图12-2. Part Number Definition

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12.3 Documentation Support

12.3.1 Related Documentation

For related documentation see the following:

• DLP3030-Q1 product folder for the DLP3030-Q1 Data Sheet.

• DLP3020-Q1 product folder for the DLP3020-Q1 Data Sheet.

• DLP3021-Q1 product folder for the DLP3021-Q1 Data Sheet.

12.4 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.5 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.6 Trademarks

TI E2E^™is a trademark of Texas Instruments.

DLP^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.7 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.8 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

34

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Product Folder Links: DLPC120-Q1

DLPC120-Q1

ZHCSHX7B –NOVEMBER 2017 –REVISED MAY 2022

www.ti.com.cn

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

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Product Folder Links: DLPC120-Q1

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

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TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DLPC120ZXSRQ1
厂家：	TEXAS INSTRUMENTS
描述：	适用于 DLP3030-Q1 芯片组的汽车类 DLP® 数字微镜器件控制器 \| ZXS \| 216 \| -40 to 105 控制器
文件：	总39页 (文件大小：1662K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLPC120ZXSRQ1 [TI]

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