DLP4710 [TI]
DLP® 0.47 1080p DMD;型号: | DLP4710 |
厂家: | TEXAS INSTRUMENTS |
描述: | DLP® 0.47 1080p DMD |
文件: | 总45页 (文件大小:1715K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DLP4710
ZHCSJ13B –NOVEMBER 2018 –REVISED MAY 2022
DLP4710 0.47 1080p DMD
1 特性
3 说明
• 0.47 英寸(11.93mm) 对角线微镜阵列
DLP4710 数字微镜器件 (DMD) 是一款数控微光机电系
统(MOEMS) 空间照明调制器(SLM)。当与适当的光学
系统配合使用时,DLP4710LC DMD 可显示非常清晰
的高质量图像或视频。此器件是 DLP4710 DMD、
– 1920 × 1080 铝制微米级微镜阵列,采用正交布
局
– 微镜间距:5.4μm
– 微镜倾斜(相对于平坦表面):±17°
– 底部照明,实现最优的效率和光学引擎尺寸
– 偏振无关型铝微镜表面
DLPC3479
控 制 器 和
DLPA3000/DLPA3005
PMIC/LED 驱 动 器 所 组 成 的 芯 片 组 的 组 件 。
DLP4710LC 外形小巧,与控制器和PMIC/LED 驱动器
共同组成完整的系统解决方案,从而实现小尺寸、低功
耗和高分辨率的高清显示产品。
• 32 位SubLVDS 输入数据总线
• 专用DLP3439 显示控制器
• 专用DLPA3000 或DLPA3005 PMIC/LED 驱动器
确保可靠运行
请访问 TI DLP®Pico™ 显示技术入门页,了解如何开始
使用DLP4710。
2 应用
DLP4710 生态系统包含现成的资源,可帮助用户加快
设计周期。这些资源包括可直接用于生产环境的光学模
块、光学模块制造商和设计公司。
• 智能全高清(HD) 投影仪
• 移动式附件全高清投影仪
• 无屏幕显示
• 交互式显示
• 低延迟游戏显示
• 头戴式显示器
器件信息
封装(1)
封装尺寸(标称值)
器件型号
DLP4710
FQL (100)
24.50mm × 11mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
DLP Pico Analog Device
VRESET
VOFFSET VBIAS
DLP
Pico Processor
DLP
Pico Processor
D_BP(0:7)
D_AP(0:7)
D_AN(0:7)
D_BP(0:7)
600 MHz
SubLVDS
DDR
600 MHz
SubLVDS
DDR
DLP DMD
DCLK_AP
DCLK_AN
DCLK_BP
DCLK_BN
Interface
Interface
Digital
Micromirror
Device
LS_WDATA
LS_CLK
120 MHz
SDR
Interface
120 MHz
SDR
Interface
LS_RDATA_B
LS_RDATA
DMD_DEN_ARSTZ
Slave
Master
VDDI
VDD
VSS
(System signal routing omitted for clarity)
0.47 1080p 芯片组
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: DLPS125
DLP4710
www.ti.com.cn
ZHCSJ13B –NOVEMBER 2018 –REVISED MAY 2022
Table of Contents
7.5 Optical Interface and System Image Quality
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 8
6.1 Absolute Maximum Ratings ....................................... 8
6.2 Storage Conditions..................................................... 8
6.3 ESD Ratings............................................................... 9
6.4 Recommended Operating Conditions.........................9
6.5 Thermal Information..................................................11
6.6 Electrical Characteristics...........................................11
6.7 Timing Requirements................................................12
6.8 Switching Characteristics .........................................17
6.9 System Mounting Interface Loads............................ 17
6.10 Physical Characteristics of the Micromirror Array...18
6.11 Micromirror Array Optical Characteristics............... 20
6.12 Window Characteristics.......................................... 21
6.13 Chipset Component Usage Specification............... 21
6.14 Software Requirements.......................................... 22
7 Detailed Description......................................................23
7.1 Overview...................................................................23
7.2 Functional Block Diagram.........................................24
7.3 Feature Description...................................................25
7.4 Device Functional Modes..........................................25
Considerations............................................................ 25
7.6 Micromirror Array Temperature Calculation.............. 26
7.7 Micromirror Landed-On/Landed-Off Duty Cycle ...... 27
8 Application and Implementation..................................31
8.1 Application Information............................................. 31
8.2 Typical Application.................................................... 31
9 Power Supply Recommendations................................33
9.1 DMD Power Supply Power-Up Procedure................33
9.2 DMD Power Supply Power-Down Procedure........... 33
9.3 Power Supply Sequencing Requirements................ 34
10 Layout...........................................................................36
10.1 Layout Guidelines................................................... 36
10.2 Layout Example...................................................... 36
11 Device and Documentation Support..........................37
11.1 Device Support........................................................37
11.2 Related Links.......................................................... 37
11.3 接收文档更新通知................................................... 38
11.4 支持资源..................................................................38
11.5 Trademarks............................................................. 38
11.6 Electrostatic Discharge Caution..............................38
11.7 术语表..................................................................... 38
12 Mechanical, Packaging, and Orderable
Information.................................................................... 39
4 Revision History
Changes from Revision A (November 2021) to Revision B (May 2022)
Page
• Updated Absolute Maximum Ratings disclosure to the latest TI standard......................................................... 8
• Updated Micromirror Array Optical Characteristics ......................................................................................... 20
• Added Third-Party Products Disclaimer ...........................................................................................................37
Changes from Revision * (November 2018) to Revision A (November 2021)
Page
• 更新了整个文档中的表、图和交叉参考的编号格式.............................................................................................1
• Updated |TDELTA| MAX from 30°C to 15°C..........................................................................................................9
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ZHCSJ13B –NOVEMBER 2018 –REVISED MAY 2022
5 Pin Configuration and Functions
L
J
G
E
C
A
K
H
F
D
B
1
3
5
2
4
6
25
26
27
28
29
30
31
图5-1. FQL Package. 100-Pin LGA. Bottom View.
表5-1. Connector Pins
PIN(1)
NAME
PACKAGE NET
LENGTH(2) (mm)
TYPE
SIGNAL
DATA RATE
DESCRIPTION
NO.
DATA INPUTS
D_AN(0)
D_AN(1)
D_AN(2)
D_AN(3)
D_AN(4)
D_AN(5)
D_AN(6)
D_AN(7)
D_AP(0)
D_AP(1)
D_AP(2)
D_AP(3)
D_AP(4)
D_AP(5)
D_AP(6)
D_AP(7)
D_BN(0)
D_BN(1)
G3
F4
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Data, Negative
5.01
2.03
2.41
4.71
3.23
3.87
6.32
1.84
5.01
2.03
2.41
4.71
3.23
3.87
6.32
1.84
2.51
4.43
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Negative
Data, Negative
E3
E6
J5
L5
G5
L3
H3
G4
E4
E5
J6
L6
G6
L4
G27
E26
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表5-1. Connector Pins (continued)
PIN(1)
NAME
D_BN(2)
PACKAGE NET
TYPE
SIGNAL
DATA RATE
DESCRIPTION
LENGTH(2) (mm)
NO.
D28
D26
L25
K25
L28
K27
F27
E27
D27
D25
L26
J25
K28
J27
J3
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Data, Negative
2.76
5.47
4.85
4.10
2.53
2.76
2.51
4.43
2.76
5.47
4.85
4.10
2.53
2.76
3.77
3.77
2.98
2.98
D_BN(3)
D_BN(4)
D_BN(5)
D_BN(6)
D_BN(7)
D_BP(0)
D_BP(1)
D_BP(2)
D_BP(3)
D_BP(4)
D_BP(5)
D_BP(6)
D_BP(7)
DCLK_AN
DCLK_AP
DCLK_BN
DCLK_BP
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Clock, Negative
Clock, Positive
Clock, Negative
Clock, Positive
K3
H26
H27
CONTROL INPUTS
LS_WDATA
D3
C3
I
I
LPSDR (1)
LPSDR
Single
Single
Write data for low speed interface.
Clock for low-speed interface
1.20
1.20
LS_CLK
Asynchronous reset DMD signal. A low
signal places the DMD in reset. A high
signal releases the DMD from reset
and places it in active mode.
DMD_DEN_ARSTZ
B6
I
LPSDR
4.19
LS_RDATA_A
LS_RDATA_B
POWER (3)
VBIAS
C6
C4
O
O
LPSDR
LPSDR
Single
Single
Read data for low-speed interface
Read data for low-speed interface
3.93
2.57
B27
B4
Power
Power
Power
24.51
24.51
49.56
Supply voltage for positive bias level at
micromirrors
VBIAS
VOFFSET
B2
Supply voltage for HVCMOS core
logic. Supply voltage for stepped high
level at micromirror address
electrodes.
Supply voltage for offset level at
micromirrors.
VOFFSET
C29
Power
49.56
VRESET
VRESET
B28
B3
Power
Power
24.82
24.82
Supply voltage for negative reset level
at micromirrors.
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表5-1. Connector Pins (continued)
PIN(1)
NAME
PACKAGE NET
LENGTH(2) (mm)
TYPE
SIGNAL
DATA RATE
DESCRIPTION
NO.
C2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
D2
D29
E2
E29
H2
Supply voltage for LVCMOS core logic.
Supply voltage for LPSDR inputs.
Supply voltage for normal high level at
micromirror address electrodes.
H28
H29
J2
J28
J29
K2
K29
L2
L29
E28
F2
F28
F29
F3
Supply voltage for SubLVDS receivers.
G2
G28
G29
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表5-1. Connector Pins (continued)
PIN(1)
NAME
PACKAGE NET
LENGTH(2) (mm)
TYPE
SIGNAL
DATA RATE
DESCRIPTION
NO.
B25
B26
B29
B5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
C25
C26
C27
C28
C5
D4
D5
D6
E25
F25
F26
F5
Common return.
Ground for all power.
F6
G25
G26
H25
H4
H5
H6
J26
J4
K26
K4
K5
K6
L27
(1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC
Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.
(2) Net trace lengths inside the package:
Relative dielectric constant for the FQL ceramic package is 9.8.
Propagation speed = 11.8 / sqrt (9.8) = 3.769 inches/ns.
Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.
(3) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are
also required.
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表5-2. Test Pads
NUMBER
A1
SYSTEM BOARD
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
A5
A6
A25
A26
A27
A28
A29
A30
A31
B30
B31
C30
C31
D1
E1
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6 Specifications
6.1 Absolute Maximum Ratings
see (1)
MIN
MAX
UNIT
Supply voltage for LVCMOS core logic(2)
Supply voltage for LPSDR low speed interface
VDD
2.3
V
–0.5
VDDI
Supply voltage for SubLVDS receivers(2)
2.3
11
V
V
V
V
V
–0.5
–0.5
–0.5
–15
VOFFSET
VBIAS
Supply voltage for HVCMOS and micromirror electrode(2) (3)
Supply voltage for micromirror electrode(2)
Supply voltage for micromirror electrode(2)
Supply voltage delta (absolute value)(4)
19
Supply voltage
VRESET
| VDDI–VDD |
0.5
0.3
| VBIAS–
VOFFSET |
Supply voltage delta (absolute value)(5)
Supply voltage delta (absolute value)(6)
11
34
V
V
| VBIAS–
VRESET |
Input voltage for other inputs LPSDR(2)
VDD + 0.5
V
V
–0.5
–0.5
Input voltage
VDDI +
0.5
Input voltage for other inputs SubLVDS(2) (7)
| VID |
IID
SubLVDS input differential voltage (absolute value)(7)
810
10
mV
mA
MHz
MHz
°C
Input pins
SubLVDS input differential current
Clock frequency for low speed interface LS_CLK
Clock frequency for high speed interface DCLK
Temperature –operational (8)
130
620
90
ƒclock
Clock frequency
ƒclock
–20
–40
TARRAY and
TWINDOW
Temperature –non-operational(8)
90
°C
Dew Point Temperature - operating and non-operating (non-
condensing)
Environmental
TDP
81
30
°C
°C
Absolute Temperature delta between any point on the window edge
and the ceramic test point TP1(9)
|TDELTA
|
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:
VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
(3) VOFFSET supply transients must fall within specified voltages.
(4) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.
(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current
draw.
(6) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current
draw.
(7) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential
inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(8) The highest temperature of the active array (as calculated by the 节7.6) or of any point along the Window Edge as defined in 图7-1.
The locations of thermal test points TP2, TP3, TP4, and TP5 in 图7-1 are intended to measure the highest window edge temperature.
If a particular application causes another point on the window edge to be at a higher temperature, that point should be used.
(9) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图
7-1. The window test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to result in the worst case delta. If a particular
application causes another point on the window edge to result in a larger delta temperature, that point should be used.
6.2 Storage Conditions
applicable for the DMD as a component or non-operational in a system
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MIN
MAX
85
24
36
6
UNIT
°C
TDMD
DMD storage temperature
–40
TDP-AVG
TDP-ELR
CTELR
Average dew point temperature, (non-condensing)(1)
Elevated dew point temperature range, (non-condensing)(2)
Cumulative time in elevated dew point temperature range
°C
28
°C
Months
(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR
.
6.3 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN
NOM
MAX
UNIT
SUPPLY VOLTAGE RANGE(4)
Supply voltage for LVCMOS core logic
VDD
1.7
1.8
1.95
V
Supply voltage for LPSDR low-speed interface
Supply voltage for SubLVDS receivers
Supply voltage for HVCMOS and micromirror electrode(5)
Supply voltage for mirror electrode
VDDI
1.7
9.5
1.8
10
1.95
10.5
18.5
–13.5
0.3
V
V
V
V
V
V
V
VOFFSET
VBIAS
17.5
18
VRESET
Supply voltage for micromirror electrode
Supply voltage delta (absolute value)(6)
Supply voltage delta (absolute value)(7)
Supply voltage delta (absolute value)(8)
–14.5
–14
|VDDI–VDD
|
10.5
33
|VBIAS–VOFFSET
|VBIAS–VRESET
|
|
CLOCK FREQUENCY
Clock frequency for low speed interface LS_CLK(9)
Clock frequency for high speed interface DCLK(10)
Duty cycle distortion DCLK
108
300
120
540
MHz
MHz
ƒclock
ƒclock
44%
56%
SUBLVDS INTERFACE(10)
| VID
VCM
|
150
700
575
90
250
900
350
1100
1225
110
mV
mV
mV
SubLVDS input differential voltage (absolute value) 图6-8, 图6-9
Common mode voltage 图6-8, 图6-9
VSUBLVDS
ZLINE
SubLVDS voltage 图6-8, 图6-9
Line differential impedance (PWB/trace)
Internal differential termination resistance 图6-10
100-Ωdifferential PCB trace
100
100
Ω
Ω
ZIN
80
120
6.35
152.4
mm
ENVIRONMENTAL
40 to
70(13)
Array Temperature –long-term operational(11) (12) (13) (14)
0
Array Temperature - short-term operational, 25 hr max(12) (15)
Array Temperature - short-term operational, 500 hr max(12) (15)
Array Temperature –short-term operational, 500 hr max(12) (15)
-10
0
–20
–10
70
TARRAY
°C
75
Absolute Temperature difference between any point on the window
edge and the ceramic test point TP1 (16)
|TDELTA
|
15
90
°C
°C
Window Temperature –operational(11) (17)
TWINDOW
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MIN
NOM
MAX
UNIT
°C
TDP-AVG
TDP-ELR
CTELR
ILLUV
Average dew point temperature (non-condensing)(18)
24
36
6
Elevated dew point temperature range (non-condensing)(19)
Cumulative time in elevated dew point temperature range
Illumination wavelengths < 420 nm (11)
28
°C
Months
0.68 mW/cm2
Thermally limited
10 mW/cm2
55 degrees
ILLVIS
ILLIR
Illumination wavelengths between 420 nm and 700 nm
Illumination wavelengths > 700 nm
ILLθ
Illumination marginal ray angle(20)
(1) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections
are also required.
(2) 节6.4 are applicable after the DMD is installed in the final product.
(3) The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by
the 节6.4. No level of performance is implied when operating the device above or below the 节6.4 limits.
(4) All voltage values are with respect to the ground pins (VSS).
(5) VOFFSET supply transients must fall within specified max voltages.
(6) To prevent excess current, the supply voltage delta |VDDI –VDD| must be less than specified limit.
(7) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than specified limit.
(8) To prevent excess current, the supply voltage delta |VBIAS –VRESET| must be less than specified limit.
(9) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.
(10) Refer to the SubLVDS timing requirements in 节6.7.
(11) Simultaneous exposure of the DMD to the maximum 节6.4 for temperature and UV illumination will reduce device lifetime.
(12) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1
(TP1) shown in 图7-1 and the Package Thermal Resistance using 节7.6.
(13) Per 图6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD
experiences in the end application. Refer to 节7.7 for a definition of micromirror landed duty cycle.
(14) Long-term is defined as the usable life of the device
(15) Short-term is the total cumulative time over the useful life of the device.
(16) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge shown in 图7-1.
The window test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to result in the worst case delta temperature. If a
particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.
(17) Window temperature is the highest temperature on the window edge shown in 图7-1. The locations of thermal test points TP2, TP3,
TP4, and TP5 in 图7-1 are intended to measure the highest window edge temperature. If a particular application causes another point
on the window edge to be at a higher temperature, that point should be used.
(18) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(19) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR
.
(20) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors
(POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily
been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not
been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM)
will contribute to thermal limitations described in this document, and may negatively affect lifetime.
80
70
60
50
40
30
0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50
90/10 85/15 80/20 75/25 70/30 65/35 60/40 55/45
100/0 95/5
D001
Micromirror Landed Duty Cycle
图6-1. Max Recommended Array Temperature –Derating Curve
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6.5 Thermal Information
DLP4710LC
THERMAL METRIC(1)
FQL (LGA)
100 PINS
1.1
UNIT
Thermal resistance
Active area to test point 1 (TP1)(1)
°C/W
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the package within the temperature range specified in the 节6.4. The total heat load on the DMD is largely driven by the
incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and
electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window
clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.
6.6 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS(2)
MIN
TYP
MAX
260
62
UNIT
CURRENT
VDD = 1.95 V
IDD
Supply current: VDD(3) (4)
Supply current: VDDI(3) (4)
Supply current: VOFFSET(5) (6)
Supply current: VBIAS(5) (6)
Supply current: VRESET(6)
mA
mA
mA
mA
mA
VDD = 1.8 V
180
40
VDDI = 1.95 V
IDDI
VDDI = = 1.8 V
VOFFSET = 10.5 V
VOFFSET = 10 V
VBIAS = 18.5 V
VBIAS = 18 V
7.4
1.1
5.4
IOFFSET
6.3
0.9
IBIAS
VRESET = –14.5 V
VRESET = –14 V
IRESET
4.4
POWER(7)
PDD
Supply power dissipation: VDD(3)
VDD = 1.95 V
507
120.9
77.7
mW
mW
mW
mW
(4)
VDD = 1.8 V
324
72
Supply power dissipation: VDDI(3)
VDDI = 1.95 V
VDD = 1.8 V
PDDI
(4)
VOFFSET = 10.5 V
VOFFSET = 10 V
VBIAS = 18.5 V
VBIAS = 18 V
Supply power dissipation:
VOFFSET(5) (6)
POFFSET
63
20.35
78.3
Supply power dissipation:
VBIAS(5) (6)
PBIAS
16.2
VRESET = –14.5 V
VRESET = –14 V
Supply power dissipation:
VRESET(6)
PRESET
mW
mW
61.6
PTOTAL
Supply power dissipation: Total
536.8
804.25
LPSDR INPUT(8)
VIH(DC)
DC input high voltage(9)
DC input low voltage(9)
AC input high voltage(9)
AC input low voltage(9)
0.7 × VDD
–0.3
VDD + 0.3
0.3 × VDD
VDD + 0.3
0.2 × VDD
0.4 × VDD
V
V
VIL(DC)
VIH(AC)
0.8 × VDD
–0.3
V
VIL(AC)
V
0.1 × VDD
V
∆VT
IIL
Hysteresis ( VT+ –VT–
Low–level input current
)
图6-10
VDD = 1.95 V; VI = 0 V
VDD = 1.95 V; VI = 1.95 V
nA
nA
–100
IIH
100
High–level input current
LPSDR OUTPUT(10)
VOH
DC output high voltage
0.8 × VDD
V
IOH = –2 mA
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PARAMETER
TEST CONDITIONS(2)
IOL = 2 mA
MIN
TYP
MAX
UNIT
VOL
DC output low voltage
0.2 × VDD
V
CAPACITANCE
Input capacitance LPSDR
Input capacitance SubLVDS
Output capacitance
10
20
10
pF
pF
pF
ƒ= 1 MHz
ƒ= 1 MHz
ƒ= 1 MHz
CIN
COUT
ƒ= 1 MHz; (1080 × 240)
micromirrors
CRESET
Reset group capacitance
400
450
pF
(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
(2) All voltage values are with respect to the ground pins (VSS).
(3) To prevent excess current, the supply voltage delta |VDDI –VDD| must be less than specified limit.
(4) Supply power dissipation based on non–compressed commands and data.
(5) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than specified limit.
(6) Supply power dissipation based on 3 global resets in 200 µs.
(7) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are
also required.
(8) LPSDR specifications are for pins LS_CLK and LS_WDATA.
(9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC
Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.
(10) LPSDR specification is for pin LS_RDATA.
6.7 Timing Requirements
Device electrical characteristics are over 节6.4 unless otherwise noted.
MIN
NOM
MAX
UNIT
LPSDR
tr
Rise slew rate(1)
1
1
3
3
V/ns
V/ns
V/ns
V/ns
ns
(30% to 80%) × VDD, 图6-3
(70% to 20%) × VDD, 图6-3
(20% to 80%) × VDD, 图6-3
(80% to 20%) × VDD, 图6-3
图6-2
tƒ
Fall slew rate(1)
tr
Rise slew rate(2)
0.25
0.25
7.7
3.1
3.1
tƒ
Fall slew rate(2)
tc
Cycle time LS_CLK,
Pulse duration LS_CLK high
Pulse duration LS_CLK low
8.3
tW(H)
tW(L)
tsu
ns
50% to 50% reference points, 图6-2
50% to 50% reference points, 图6-2
ns
LS_WDATA valid before LS_CLK ↑,
图6-2
Setup time
1.5
ns
LS_WDATA valid after LS_CLK ↑, 图
6-2
t h
Hold time
1.5
3.0
ns
ns
ns
tWINDOW
tDERATING
Window time(1) (3)
Window time derating(1) (3)
Setup time + Hold time, 图6-2
For each 0.25 V/ns reduction in slew
rate below 1 V/ns, 图6-5
0.35
SubLVDS
tr
Rise slew rate
0.7
0.7
1
1
V/ns
V/ns
ns
20% to 80% reference points, 图6-4
80% to 20% reference points, 图6-4
图6-6
tƒ
Fall slew rate
tc
Cycle time DCLK,
Pulse duration DCLK high
Pulse duration DCLK low
1.79
0.79
0.79
1.85
tW(H)
tW(L)
ns
50% to 50% reference points, 图6-6
50% to 50% reference points, 图6-6
ns
D(0:7) valid before
DCLK ↑or DCLK ↓, 图6-6
tsu
Setup time
D(0:7) valid after
DCLK ↑or DCLK ↓, 图6-6
t h
Hold time
tWINDOW
Window time
3.0
ns
Setup time + Hold time, 图6-6, 图6-7
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MIN
NOM
MAX
UNIT
tLVDS-
Power-up receiver(4)
2000
ns
ENABLE+REFGEN
(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in 图6-3.
(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in 图6-3 .
(3) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.
(4) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
t
c
t
t
w(L)
w(H)
LS_CLK
50%
50%
50%
t
h
t
su
LS_WDATA
50%
50%
t
window
Low-speed interface is LPSDR and adheres to the 节6.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low
Power Double Data Rate (LPDDR) JESD209B.
图6-2. LPSDR Switching Parameters
LS_CLK, LS_WDATA
DMD_DEN_ARSTZ
1.0 * VDD
1.0 * VDD
0.8 * VDD
VIH(AC)
VIH(DC)
0.8 * VDD
0.7 * VDD
VIL(DC)
VIL(AC)
0.3 * VDD
0.2 * VDD
0.2 * VDD
0.0 * VDD
0.0 * VDD
tr
tf
tr
tf
图6-3. LPSDR Input Rise and Fall Slew Rate
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VDCLK_P , VDCLK_N
VD_P(0:7) , VD_N(0:7)
1.0 * V
0.8 * V
ID
ID
V
CM
0.2 * V
0.0 * V
ID
ID
tr
tf
图6-4. SubLVDS Input Rise and Fall Slew Rate
VIH MIN
LS_CLK Midpoint
VIL MAX
tSU
tH
VIH MIN
LS_WDATA Midpoint
VIL MAX
tWINDOW
VIH MIN
Midpoint
LS_CLK
VIL MAX
tDERATING
tH
tSU
VIH MIN
Midpoint
VIL MAX
LS_WDATA
tWINDOW
图6-5. Window Time Derating Concept
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t
c
t
t
w(H)
w(L)
DCLK_P
DCLK_N
50%
50%
50%
t
h
t
su
D_P(0:7)
D_N(0:7)
50%
50%
t
window
图6-6. SubLVDS Switching Parameters
High Speed Training Scan Window
t
c
DCLK_P
DCLK_N
¼ t
c
¼ t
c
D_P(0:7)
D_N(0:7)
Note: Refer to 节7.3.3 for details.
图6-7. High-Speed Training Scan Window
(V + V ) / 2
IP IN
DCLK_P , D_P(0:7)
DCLK_N , D_N(0:7)
SubLVDS
Receiver
V
ID
V
IP
V
CM
V
IN
图6-8. SubLVDS Voltage Parameters
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1.225V
V
= V
+ | 1/2 * V
|
ID max
SubLVDS max
CM max
V
CM
V
ID
V
= V
– | 1/2 * V
|
SubLVDS min
CM min
ID max
0.575V
图6-9. SubLVDS Waveform Parameters
DCLK_P , D_P(0:7)
ESD
Internal
Termination
SubLVDS
Receiver
DCLK_N , D_N(0:7)
ESD
图6-10. SubLVDS Equivalent Input Circuit
Not to Scale
V
IH
V
T+
Δ V
T
V
T-
V
LS_CLK
IL
LS_WDATA
图6-11. LPSDR Input Hysteresis
LS_CLK
LS_WDATA
Stop Start
tPD
LS_RDATA
Acknowledge
图6-12. LPSDR Read Out
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Timing specification reference point
Device pin
Tester channel
output under test
CL
See Timing for more information.
图6-13. Test Load Circuit for Output Propagation Measurement
6.8 Switching Characteristics
Over operating free-air temperature range (unless otherwise noted).(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
15
UNIT
ns
Output propagation, Clock to Q, rising
edge of LS_CLK input to LS_RDATA
output. (figure 12 xref)
tPD
CL = 45 pF
Slew rate, LS_RDATA
0.5
V/ns
Output duty cycle distortion, LS_RDATA
40%
60%
(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
6.9 System Mounting Interface Loads
PARAMETER
MIN
NOM
MAX
UNIT
62
N
Thermal interface area (see 图6-14)
Maximum system mounting interface
load to be applied to the:
Clamping and electrical interface area (see 图
6-14)
110
N
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Datum 'A' area (3 places)
Datum 'E' area (1 place)
Thermal Interface Area
Clamping and Electrical Interface Area
图6-14. System Interface Loads
6.10 Physical Characteristics of the Micromirror Array
PARAMETER
VALUE
1920
1080
5.4
UNIT
micromirrors
micromirrors
µm
Number of active columns
Number of active rows
Micromirror (pixel) pitch
See 图6-15
See 图6-15
See 图6-16
ε
Micromirror active array
width
10.368
mm
Micromirror pitch × number of active columns; see 图6-15
Micromirror active array
height
5.832
20
mm
Micromirror pitch × number of active rows; see 图6-15
Micromirror active border Pond of micromirror (POM)(1)
micromirrors/side
(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.
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Width .
Mirror 1079
Mirror 1078
Mirror 1077
Mirror 1076
1920 × 1080 mirrors
Height
Mirror 3
Mirror 2
Mirror 1
Mirror 0
Illumination
图6-15. Micromirror Array Physical Characteristics
e
e
e
e
图6-16. Mirror (Pixel) Pitch
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6.11 Micromirror Array Optical Characteristics
PARAMETER
Micromirror tilt angle
TEST CONDITIONS
MIN
NOM
MAX
UNIT
degree
degree
DMD landed state(1)
17
Micromirror tilt angle tolerance(2) (3) (4) (5)
1.4
–1.4
Landed ON state
180
270
1
Micromirror tilt direction (6) (7)
degree
µs
Landed OFF state
Typical performance
Typical performance
Micromirror crossover time(8)
Micromirror switching time(9)
3
10
Bright pixel(s) in active area
Gray 10 Screen (12)
0
1
4
0
0
(11)
Bright pixel(s) in the POM (13) Gray 10 Screen (12)
Image
Dark pixel(s) in the active
White Screen
micromirrors
performance(10)
area (14)
Adjacent pixel(s) (15)
Any Screen
Any Screen
Unstable pixel(s) in active
area (16)
(1) Measured relative to the plane formed by the overall micromirror array.
(2) Additional variation exists between the micromirror array and the package datums.
(3) Represents the landed tilt angle variation relative to the nominal landed tilt angle.
(4) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result
in colorimetry variations, system efficiency variations, or system contrast variations.
(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of
the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON state
direction. A binary value of 0 results in a micromirror landing in the OFF state direction. See 图6-17.
(7) Micromirror tilt direction is measured as in a typical polar coordinate system: Measuring counter-clockwise from a 0° reference which is
aligned with the +X Cartesian axis.
(8) The time required for a micromirror to nominally transition from one landed state to the opposite landed state.
(9) The minimum time between successive transitions of a micromirror.
(10) Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions:
Test set degamma shall be linear
Test set brightness and contrast shall be set to nominal
The diagonal size of the projected image shall be a minimum of 20 inches
The projections screen shall be 1X gain
The projected image shall be inspected from a 38 inch minimum viewing distance
The image shall be in focus during all image quality tests
(11) Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels
(12) Gray 10 screen definition: All areas of the screen are colored with the following settings:
Red = 10/255
Green = 10/255
Blue = 10/255
(13) POM definition: Rectangular border of off-state mirrors surrounding the active area
(14) Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels
(15) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster
(16) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable
pixel appears to be flickering asynchronously with the image
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Off-state
light path
(1079, 1919)
Off-state
landed edge
Tilted axis of
pixel rotation
On-state
landed edge
(0, 0)
Incident
illumination
light path
图6-17. Landed Pixel Orientation and Tilt
6.12 Window Characteristics
PARAMETER(1)
MIN
NOM
Corning Eagle XG
1.5119
MAX UNIT
Window material designation
Window refractive index
Window aperture(2)
at wavelength 546.1 nm
See (2)
See (3)
Illumination overfill(3)
Window transmittance, single-pass
through both surfaces and glass
Minimum within the wavelength range
420 to 680 nm. Applies to all angles 0° to
30° AOI.
97%
97%
Window Transmittance, single-pass
through both surfaces and glass
Average over the wavelength range 420
to 680 nm. Applies to all angles 30° to
45° AOI.
(1) See Optical Interface and System Image Quality Considerations for more information.
(2) See the package mechanical characteristics for details regarding the size and location of the window aperture.
(3) The active area of the DLP4710LC device is surrounded by an aperture on the inside of the DMD window surface that masks
structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light
illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the
DMD. The illumination optical system should be designed to limit light flux incident outside the active array to less than 10% of the
average flux level in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of
overfill light on the outside of the active array may cause system performance degradation.
SPACER
6.13 Chipset Component Usage Specification
The DLP4710 is a component of one or more TI ®DLP chipsets. Reliable function and operation of the DLP4710
requires that it be used in conjunction with the other components of the applicable DLP chipset, including those
components that contain or implement TI DMD control technology. TI DMD control technology is the TI
technology and devices for operating or controlling a DLP DMD.
备注
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.
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6.14 Software Requirements
备注
The DLP4710 DMD has mandatory software requirements. Refer to Software Requirements for TI
®DLP ™Pico TRP Digital Micromirror Devices application report for additional information. Failure to
use the specified software will result in failure at power up.
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7 Detailed Description
7.1 Overview
The DLP4710LC device is a 0.47 inch diagonal spatial light modulator of aluminum micromirrors. Pixel array size
is 1920 columns by 1080 rows in a square grid pixel arrangement. The electrical interface is Sub Low Voltage
Differential Signaling (SubLVDS) data.
DLP4710LC device is part of the chipset comprising the DLP4710LC DMD, DLPC3479 controller, and
DLPA3000 or DLPA3005 PMIC/LED driver. To ensure reliable operation, the DLP4710LC DMD must always be
used with either the DLPC3479 controller and the DLPA3000 or DLPA3005 PMIC/LED drivers.
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7.2 Functional Block Diagram
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备注
Simplified for clarity.
7.3 Feature Description
7.3.1 Power Interface
The power management IC, DLPA3000/DLPA3005, contains three regulated DC supplies for the DMD reset
circuitry: VBIAS, VRESET and VOFFSET, as well as the 2 regulated DC supplies for the DLPC3479 controller.
7.3.2 Low-Speed Interface
The Low Speed Interface handles instructions that configure the DMD and control reset operation. LS_CLK is
the low–speed clock, and LS_WDATA is the low speed data input.
7.3.3 High-Speed Interface
The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed
DDR transfer and compression techniques to save power and time. The high-speed interface is composed of
differential SubLVDS receivers for inputs, with a dedicated clock.
7.3.4 Timing
The data sheet provides timing test results at the device pin. For output timing analysis, the tester pin electronics
and its transmission line effects must be considered. 图 6-13 shows an equivalent test load circuit for the output
under test. Timing reference loads are not intended as a precise representation of any particular system
environment or depiction of the actual load presented by a production test. TI recommends that system
designers use IBIS or other simulation tools to correlate the timing reference load to a system environment. The
load capacitance value stated is intended for characterization and measurement of AC timing signals only. This
load capacitance value does not indicate the maximum load the device is capable of driving.
7.4 Device Functional Modes
DMD functional modes are controlled by the DLPC3479 controller. See the DLPC3479 controller data sheet or
contact a TI applications engineer.
7.5 Optical Interface and System Image Quality Considerations
备注
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.
7.5.1 Optical Interface and System Image Quality
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
7.5.1.1 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area is
typically the same. Ensure this angle does not exceed the nominal device micromirror tilt angle unless
appropriate apertures are added in the illumination or projection pupils to block out flat-state and stray light from
the projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from any
other light path, including undesirable flat–state specular reflections from the DMD window, DMD border
structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture
exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger
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than the illumination numerical aperture angle (and vice versa), contrast degradation and objectionable artifacts
in the display border and/or active area may occur.
7.5.1.2 Pupil Match
The optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable
artifacts in the display border and/or active area. These artifacts may require additional system apertures to
control, especially if the numerical aperture of the system exceeds the pixel tilt angle.
7.5.1.3 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating
conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window
aperture opening and other surface anomalies that may be visible on the screen. Be sure to design an
illumination optical system that limits light flux incident anywhere on the window aperture from exceeding
approximately 10% of the average flux level in the active area. Depending on the particular optical architecture,
overfill light may require further reduction below the suggested 10% level in order to be acceptable.
7.6 Micromirror Array Temperature Calculation
2X 12.89
TP2
Off-state
Light
TP4
TP5
2X 5.50
TP3
Illumination
Direction
Window Edge
(4 surfaces)
TP3 (TP2)
TP5
TP4
TP1
TP1
12.70
2.00
图7-1. DMD Thermal Test Points
Micromirror array temperature can be computed analytically from measurement points on the outside of the
package, the ceramic package thermal resistance, the electrical power dissipation, and the illumination heat
load. The relationship between micromirror array temperature and the reference ceramic temperature is provided
by the following equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC
QARRAY = QELECTRICAL + QILLUMINATION
)
(1)
(2)
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QILLUMINATION = (CL2W × SL)
(3)
where
• TARRAY = Computed DMD array temperature (°C)
• TCERAMIC = Measured ceramic temperature (°C), TP1 location in 图7-1
• RARRAY–TO–CERAMIC = DMD package thermal resistance from array to outside ceramic (°C/W) specified in 节
6.5
• QARRAY = Total DMD power; electrical plus absorbed (calculated) (W)
• QELECTRICAL = Nominal DMD electrical power dissipation (W)
• CL2W = Conversion constant for screen lumens to absorbed optical power on the DMD (W/lm) specified below
• SL = Measured ANSI screen lumens (lm)
The electrical power dissipation of the DMD varies and depends on the voltages, data rates and operating
frequencies. Use a nominal electrical power dissipation of 0.25 W to calculate array temperature. Absorbed
optical power from the illumination source varies and depends on the operating state of the micromirrors and the
intensity of the light source. Equations shown above are valid for a 1-chip DMD system with total projection
efficiency through the projection lens from DMD to the screen of 87%.
The conversion constant CL2W is based on the DMD micromirror array characteristics. The conversion constant
assumes a spectral efficiency of 300 lm/W for the projected light and illumination distribution of 83.7% on the
DMD active array, and 16.3% on the DMD array border and window aperture. The conversion constant is
calculated to be 0.00266 W/lm.
The following is a sample calculation for typical projection application:
TCERAMIC = 55°C (measured)
SL = 1500 lm (measured)
QELECTRICAL = 0.25 W
CL2W = 0.00266 W/lm
QARRAY = 0.25 W + (0.00266 W/lm × 1500 lm) = 4.24 W
TARRAY = 55°C + (4.24 W × 1.1°C/W) = 59.66°C
7.7 Micromirror Landed-On/Landed-Off Duty Cycle
7.7.1 Definition of Micromirror Landed-On and Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the ON state versus the amount of time the same
micromirror is landed in the OFF state.
As an example, a landed duty cycle of 75/25 indicates that the referenced pixel is in the ON state 75% of the
time (and in the OFF state 25% of the time), whereas 25/75 indicates that the pixel is in the OFF state 75% of
the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time.
When assessing landed duty cycle, the time spent switching from the current state to the opposite state is
considered negligible and is thus ignored.
Because a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
nominally add to 100.In practice, image processing algorithms in the DLP chipset can result a total of less that
100.
7.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric
landed duty cycle for a prolonged period of time can reduce the DMD’s usable life.
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It is the symmetry or asymmetry of the landed duty cycle that is relevant. The symmetry of the landed duty cycle
is determined by how close the two numbers (percentages) are to being equal. For example, a landed duty cycle
of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly asymmetrical.
7.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD temperature and landed duty cycle interact to affect the usable life of the DMD. This interaction
can be used to reduce the impact that an asymmetrical landed duty cycle has on the useable life of the DMD. 图
6-1 describes this relationship. The importance of this curve is that:
• All points along this curve represent the same usable life.
• All points above this curve represent lower usable life (and the further away from the curve, the lower the
usable life).
• All points below this curve represent higher usable life (and the further away from the curve, the higher the
usable life).
In practice, this curve specifies the maximum operating DMD temperature that the DMD should be operated at
for a give long-term average landed duty cycle.
7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the landed duty cycle of a given pixel depends on the image content being
displayed by that pixel.
In the simplest case for example, when the system displays pure-white on a given pixel for a given time period,
that pixel operates very close to a 100/0 landed duty cycle during that time period. Likewise, when the system
displays pure-black, the pixel operates very close to a 0/100 landed duty cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in 表7-1.
表7-1. Grayscale Value
and Landed Duty Cycle
Nominal
Grayscale
Landed Duty
Value
Cycle
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0/100
10/90
20/80
30/70
40/60
50/50
60/40
70/30
80/20
90/10
100/0
To account for color rendition (and continuing to ignore image processing for this example) requires knowing
both the color intensity (from 0% to 100%) for each constituent primary color (red, green, and/or blue) for the
given pixel as well as the color cycle time for each primary color, where color cycle time describes the total
percentage of the frame time that a given primary must be displayed in order to achieve the desired white point.
During a given period of time, the nominal landed duty cycle of a given pixel can be calculated as shown in 方程
式4:
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Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_% (4)
×
Blue_Scale_Value)
where
• Red_Cycle_% represents the percentage of the frame time that red displays to achieve the desired white
point
• Green_Cycle_% represents the percentage of the frame time that green displays to achieve the desired white
point
• Blue_Cycle_% represents the percentage of the frame time that blue displays to achieve the desired white
point
For example, assume that the ratio of red, green and blue color cycle times are as listed in 表 7-2 (in order to
achieve the desired white point) then the resulting nominal landed duty cycle for various combinations of red,
green, blue color intensities are as shown in 表7-3.
表7-2. Example Landed Duty Cycle for Full-Color
Pixels
Red Cycle
Percentage
Green Cycle
Percentage
Blue Cycle
Percentage
50%
20%
30%
表7-3. Color Intensity Combinations
Nominal
Landed Duty
Cycle
Red Scale
Value
Green Scale
Value
Blue Scale
Value
0%
100%
0%
0%
0%
0%
0%
0/100
50/50
20/80
30/70
6/94
100%
0%
0%
0%
100%
0%
12%
0%
0%
35%
0%
0%
7/93
0%
60%
0%
18/82
70/30
50/50
80/20
13/87
25/75
24/76
100/0
100%
0%
100%
100%
0%
100%
100%
0%
100%
12%
0%
35%
35%
0%
60%
60%
100%
12%
100%
100%
The last factor to consider when estimating the landed duty cycle is any applied image processing. In the
DLPC34xx controller family, the two functions which influence the actual landed duty cycle are Gamma and
IntelliBright™, and bitplane sequencing rules.
Gamma is a power function of the form Output_Level = A × Input_LevelGamma, where A is a scaling factor that is
typically set to 1.
In the DLPC34xx controller family, gamma is applied to the incoming image data on a pixel-by-pixel basis. A
typical gamma factor is 2.2, which transforms the incoming data as shown in 图7-2.
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100
90
80
70
60
50
40
30
20
10
Gamma = 2.2
0
0
10
20
30
40
50
60
Input Level (%)
70
80
90 100
D002
图7-2. Example of Gamma = 2.2
As shown in 图7-2, when the gray scale value of a given input pixel is 40% (before gamma is applied), then gray
scale value is 13% after gamma is applied. Because gamma has a direct impact on the displayed gray scale
level of a pixel, it also has a direct impact on the landed duty cycle of a pixel.
The IntelliBright algorithms content adaptive illumination control (CAIC) and local area brightness boost (LABB)
also apply transform functions on the gray scale level of each pixel.
But while amount of gamma applied to every pixel (of every frame) is constant (the exponent, gamma, is
constant), CAIC and LABB are both adaptive functions that can apply a different amounts of either boost or
compression to every pixel of every frame.
Consideration must also be given to any image processing which occurs before the DLPC3439 or DLPC3479
controller.
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8 Application and Implementation
8.1 Application Information
The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two
directions, with the primary direction being into a projection or collection optic. Each application is derived
primarily from the optical architecture of the system and the format of the data coming into the dual DLPC3479
controllers. The new high tilt pixel in the bottom-illuminated DMD increases brightness performance and enables
a smaller system footprint for thickness constrained applications. Applications of interest include
DMD power-up and power-down sequencing is strictly controlled by the DLPA3000/DLPA3005. Refer to Power
Supply Recommendations for power-up and power-down specifications. To ensure reliable operation, the
DLP4710LC DMD must always be used with two DLPC3479 controllers and a DLPA3000 or DLPA3005
PMIC/LED driver.
8.2 Typical Application
A pico-projector that can be used as an accessory to a smartphone, tablet or a laptop is a common application
when using a DLP4710LC DMD and two DLPC3479 devices. The two DLPC3479 devices in the pico-projector
receive images from a multimedia front end within the product as shown in 图8-1.
PROJ_ON
PROJ_ON
GPIO_8 (Normal Park)
Focus stepper motor
VLED
SPI
Flash
SPI(4)
RESETZ
INTZ
Current Sense
Microcontroller
Front End
Monochrome
Illumination(1)
SPI_1
VCC_FLSH
SPI_0
DLPA3000
PARKZ
MSP430
Tiva
LED_SEL(2)
Illuminator
HOST_IRQ
I2C
DLPC3479
eDRAM
1.1 V for DLPC3479
1.8 V
VSPI
1.8 V for DMD and DLPC3479
VCC_INTF
BIAS, RST, OFS
3
Illumination
Optics
SYSPWR
TSTPT_4
GPIO_7
TRIG_OUT1
TRIG_OUT2
TRIG_IN
3DR
1.8 V
1.1 V
VIO
Sub-LVDS DATA (18)
CTRL
DLP4710LC
VCORE
DMD
Image
Sync
GPIO5
I2C_1
GPIO6
RESETZ
INTZ
I2C
I2C_0
VCC_FLSH
Oscillator
DLPC3479
eDRAM
SPI_0
SPI Flash
VCC_INTF
LS RDATA
Included in DLP® Chip Set
Non-DLP components
1.8 V
1.1 V
VIO
Sub-LVDS DATA (18)
VCORE
图8-1. Typical Application Diagram
8.2.1 Design Requirements
A pico-projector is created by using a DLP chip set comprised of a DLP4710 DMD, two DLPC3439 controllers
and a DLPA3000/DLPA3005 PMIC/LED driver. The DLPC3439 controllers do the digital image processing, the
DLPA3000/DLPA3005 provides the needed analog functions for the projector, and the DLP4710 DMD is the
display device for producing the projected image.
In addition to the three DLP chips in the chip set, other chips are needed. At a minimum a Flash part is needed
to store the software and firmware to control each DLPC3439 controller.
The illumination light that is applied to the DMD is typically from red, green, and blue LEDs. These are often
contained in three separate packages, but sometimes more than one color of LED die may be in the same
package to reduce the overall size of the pico-projector.
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For connecting the DLPC3439 controllers to the multimedia front end for receiving images, a 24-bit parallel
interface is used. An I2C interface should be connected to the multimedia front end for sending commands to
one of the DLPC3439 controllers for configuring the DLPC3439 controller for different features.
8.2.2 Detailed Design Procedure
For connecting the two DLPC3439 controllers, the DLPA3000/DLPA3005, and the DLP4710 DMD, see the
reference design schematic. When a circuit board layout is created from this schematic a very small circuit board
is possible. An example small board layout is included in the reference design data base. Layout guidelines
should be followed to achieve a reliable projector.
The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an optical
OEM who specializes in designing optics for DLP projectors.
8.2.3 Application Curve
As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the
brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white
screen lumens changes with LED currents is as shown in 图 8-2. For the LED currents shown, it’s assumed
that the same current amplitude is applied to the red, green, and blue LEDs.
图8-2. Luminance vs Current
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9 Power Supply Recommendations
The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET.
All VSS connections are also required. DMD power-up and power-down sequencing is strictly controlled by the
DLPA3000/DLPA3005 devices.
备注
For reliable operation of the DMD, the following power supply sequencing requirements must be
followed. Failure to adhere to the prescribed power-up and power-down procedures may affect device
reliability. VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during
power-up and power-down operations. Failure to meet any of the below requirements will result in a
significant reduction in the DMD’s reliability and lifetime. Refer to Figure 23. VSS must also be
connected.
VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-up
and power-down operations. Failure to meet any of the below requirements will result in a significant
reduction in the DMD’s reliability and lifetime. Refer to Figure 23. VSS must also be connected.
9.1 DMD Power Supply Power-Up Procedure
• During the power-up sequence, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and
VRESET voltages are applied to the DMD.
• During the power-up sequence, it is a strict requirement that the voltage difference between VBIAS and
VOFFSET must be within the specified limit shown in 节6.4. Refer to 表9-1 for the power-up sequence,
delay requirements.
• During the power-up sequence, there is no requirement for the relative timing of VRESET with respect to
VBIAS and VOFFSET.
• Power supply slew rates during the power-up sequence are flexible, provided that the transient voltage levels
follow the requirements specified in 节6.1, in 节6.4, and in 节9.3.
• During the power-up sequence, LPSDR input pins must not be driven high until after VDD/VDDI have settled
at operating voltages listed in 节6.4.
9.2 DMD Power Supply Power-Down Procedure
• The power-down sequence is the reverse order of the previous power-up sequence. During the power-down
sequence, VDD and VDDI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to
within 4 V of ground.
• During the power-down sequence, it is a strict requirement that the voltage difference between VBIAS and
VOFFSET must be within the specified limit shown in 节6.4.
• During the power-down sequence, there is no requirement for the relative timing of VRESET with respect to
VBIAS and VOFFSET.
• Power supply slew rates during the power-down sequence, are flexible, provided that the transient voltage
levels follow the requirements specified in 节6.1, in 节6.4, and in 节9.3.
• During the power-down sequence, LPSDR input pins must be less than VDD/VDDI specified in 节6.4.
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9.3 Power Supply Sequencing Requirements
DLP Display Controller and
PMIC control start of DMD
operation
DRAWING NOT TO SCALE.
DLP Display Controller and PMIC
disable VBIAS, VOFFSET and
VRESET
Mirror Park
Sequence
DETAILS OMITTED FOR CLARITY.
Note 4
Power Off
VDD / VDDI
VDD / VDDI
VDD / VDDI
VSS
VSS
VBIAS
VBIAS
VBIAS
VDD ≤ VBIAS < 6 V
VBIAS < 4 V
VSS
VSS
VOFFSET
VOFFSET
VDD ≤ VOFFSET < 6 V
VOFFSET < 4 V
VOFFSET
VSS
VSS
VSS
VRESET < 0.5 V
VSS
VRESET > - 4 V
VRESET
VRESET
VDD
VRESET
VDD
DMD_DEN_ARSTZ
VSS
VSS
VSS
VSS
INITIALIZATION
VDD
VDD
LS_CLK
VSS
LS_WDATA
VID
VID
D_P(0:7), D_N(0:7)
DCLK_P, DCLK_N
VSS
A. DLP controller and PMIC controls start of DMD operation
B. Mirror park sequence starts
C. Mirror park sequence ends. DLP controller and PMIC disables VBIAS, VOFFSET, and VRESET.
D. Power off.
E. Refer to 表9-1 and 图9-2 for critical power-up sequence delay requirements.
F. When system power is interrupted, the ASIC driver initiates hardware the power-down sequence, that disables VBIAS, VRESET and
VOFFSET after the micromirror park sequence is complete. Software the power-down sequence, disables VBIAS, VRESET, and
VOFFSET after the micromirror park sequence through software control.
G. To prevent excess current, the supply voltage delta |VBIAS –VRESET| must be less than specified limit shown in 节6.4.
H. Drawing is not to scale and details are omitted for clarity.
图9-1. Power Supply Sequencing Requirements (Power Up and Power Down)
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表9-1. Power-Up Sequence Delay Requirement
PARAMETER
MIN
MAX
UNIT
ms
V
tDELAY
Delay requirement from VOFFSET power up to VBIAS power up
Supply voltage level during power–up sequence delay (see 图9-2)
Supply voltage level during power–up sequence delay (see 图9-2)
2
VOFFSET
VBIAS
6
6
V
12 V
VOFFSET
8 V
VDD ≤ VOFFSET < 6 V
4 V
VSS
0 V
tDELAY
20 V
16 V
12 V
8 V
VBIAS
VDD ≤ VBIAS < 6 V
4 V
VSS
0 V
A. Refer to 表9-1 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay.
图9-2. Power-Up Sequence Delay Requirement
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10 Layout
10.1 Layout Guidelines
There are no specific layout guidelines for the DMD as typically DMD is connected using a board to board
connector to a flex cable. Flex cable provides the interface of data and Ctrl signals between the DLPC3439
controller and the DLP4710 DMD. For detailed layout guidelines refer to the layout design files. Some layout
guideline for the flex cable interface with DMD are:
• Match lengths for the LS_WDATA and LS_CLK signals.
• Minimize vias, layer changes, and turns for the HS bus signals. Refer 图10-1.
• Minimum of two 220-nF decoupling capacitor close to VBIAS. Capacitor C3 and C10 in 图10-1.
• Minimum of two 220-nF decoupling capacitor close to VRST. Capacitor C1 and C9 in 图10-1.
• Minimum of two 220-nF decoupling capacitor close to VOFS. Capacitor C2 and C8 in 图10-1.
• Minimum of four 220-nF decoupling capacitor close to VDDI and VDD. Capacitor C4, C5, C6 and C7 in 图
10-1.
10.2 Layout Example
图10-1. Power Supply Connections
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.1.2 Device Nomenclature
DLP4710A FQL
Package Type
Device Descriptor
图11-1. Part Number Description
11.1.3 Device Markings
The device marking includes the legible character string GHJJJJK DLP4710AFQL. GHJJJJK is the lot trace
code. DLP4710AFQL is the device marking.
Two-dimensional matrix code
DMD part number and lot trace code
Lot Trace Code
GHJJJJK
DLP4710AFQL
Part Marking
图11-2. DMD Marking Locations
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
表11-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
DLP4710
DLPC3439
DLPA3000
DLPA3005
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
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Product Folder Links: DLP4710
DLP4710
www.ti.com.cn
ZHCSJ13B –NOVEMBER 2018 –REVISED MAY 2022
11.3 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.5 Trademarks
Pico™, IntelliBright™, and TI E2E™ are trademarks of Texas Instruments.
DLP® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2022 Texas Instruments Incorporated
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DLP4710
www.ti.com.cn
ZHCSJ13B –NOVEMBER 2018 –REVISED MAY 2022
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: DLP4710
PACKAGE OPTION ADDENDUM
www.ti.com
11-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLP4710AFQL
ACTIVE
CLGA
FQL
100
80
RoHS & Green
NI/AU
N / A for Pkg Type
0 to 70
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-May-2022
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DLP4710AFQL
FQL
CLGA
100
80
8 x 10
150
315 135.9 12190
28
31.5 15.45
Pack Materials-Page 1
DWG NO.
SH
8
5
3
6
1
7
4
1
2513652
REVISIONS
C
COPYRIGHT 2014 TEXAS INSTRUMENTS
UN-PUBLISHED, ALL RIGHTS RESERVED.
NOTES UNLESS OTHERWISE SPECIFIED:
REV
A
DESCRIPTION
DATE
BY
2/20/2014
3/6/2014
5/22/2014
7/20/2016
4/23/2020
ECO 2140050: INITIAL RELEASE
ECO 2140429: CORRECT DATUM C IN VIEW J-J, SH. 3
ECO 2142093: DELETE BACK SIDE FLATNESS SPEC
ECO 2145057: ADD "FQL PACKAGE" TO DRAWING TITLE
BMH
BMH
BMH
BMH
BMH
1
2
3
4
NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC, AS SHOWN IN SECTION A-A.
B
C
SEE DETAIL B FOR "V-NOTCH" DIMENSIONS.
D
E
ECO 2187241: ADD APERTURE SLOT PICTORIALLY
DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY.
WHILE ONLY THE THREE DATUM A TARGET AREAS A1, A2, AND A3 ARE USED FOR MEASUREMENT, ALL
4 CORNERS SHOULD BE CONTACTED, INCLUDING E1, TO SUPPORT MECHANICAL LOADS.
D
C
B
A
D
C
B
A
5
ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN IN VIEW D (SHEET 2). NO
ENCAPSULANT IS ALLOWED ON TOP OF THE WINDOW.
6
7
ENCAPSULANT NOT TO EXCEED THE HEIGHT OF THE WINDOW.
ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION TOLERANCE AND HAS
A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES.
8
BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY.
+
-
0.2
0.1
(1.3)
0.188
23.0120.1
1
(OFF-STATE
DIRECTION)
4X (R0.2)
1
B
1
2
1.5
1
2X R0.40.1
(1.6)
+
-
0.3
0.1
11
3 0.075
1
(3)
1
0.4 MIN TYP.
C
1.5
A
A
0 MIN TYP.
+
-
0.2
0.1
5.5
+
-
0.2
0.1
SECTION A-A
NOTCH OFFSETS
4
1
(ILLUMINATION
DIRECTION)
FRONT SIDE
INDEX MARK
+
-
0.3
0.1
24.5
(1)
2X ENCAPSULANT
(2.183)
D
1.4030.077
1.1 0.05
5
6
1
45°1°
3 SURFACES INDICATED
IN VIEW D (SHEET 2)
3
4
A
0.042A
2X (0.2)
(3)
4
0.02D
1.60.1
0.780.063
ACTIVE ARRAY
R0.6 0.1
1
J
J
(SHEET 3)
(SHEET 3)
1
45°1°
DATE
DRAWN
UNLESS OTHERWISE SPECIFIED
DIMENSIONS ARE IN MILLIMETERS
TOLERANCES:
TEXAS
2/20/2014
2/20/2014
2/26/2014
2/25/2014
2/23/2014
2/26/2014
B. HASKETT
ENGINEER
B. HASKETT
QA/CE
INSTRUMENTS
Dallas Texas
ANGLES 1
TITLE
ICD, MECHANICAL, DMD,
.47 1080p SERIES 312
(FQL PACKAGE)
2 PLACE DECIMALS 0.25
1 PLACE DECIMALS 0.50
DIMENSIONAL LIMITS APPLY BEFORE PROCESSES
INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME
Y14.5M-1994
DETAIL B
P. KONRAD
CM
V-NOTCH
S. SUSI
SCALE 30 : 1
THIRD ANGLE
PROJECTION
DWG NO
REV
SIZE
D
0314DA
USED ON
REMOVE ALL BURRS AND SHARP EDGES
PARENTHETICAL INFORMATION FOR REFERENCE ONLY
M. DORAK
APPROVED
R. LONG
2513652
E
NEXT ASSY
SCALE
SHEET
OF
APPLICATION
15:1
1
3
INV11-2006a
5
3
6
1
2
7
8
4
DWG NO.
SH
8
5
3
6
1
7
4
2513652
2
4X (1.5)
2X 1.312
A3
2X 21.5
4X (3.25)
D
C
B
A
D
C
B
A
B
A2
1.5
2X 2.25
2X 2.25
C
1.5
4
E1
A1
1.312
21.5
VIEW C
DATUMS A AND E
(SUBSTRATE METALLIZATION OMITTED FOR CLARITY)
(FROM SHEET 1)
B
1.5
11.2
C
1.5
5.6
VIEW D
ENCAPSULANT MAXIMUM X/Y DIMENSIONS
5
2X 0 MIN
(FROM SHEET 1)
6
VIEW E
ENCAPSULANT MAXIMUM HEIGHT
DWG NO
REV
SIZE
DRAWN
DATE
2/20/2014
TEXAS
2513652
B. HASKETT
E
3
D
INSTRUMENTS
Dallas Texas
SCALE
SHEET
OF
2
INV11-2006a
5
3
6
1
2
7
8
4
DWG NO.
SH
8
5
3
6
1
7
4
2513652
3
(10.368)
ACTIVE ARRAY
7.513 0.075
4X (0.108)
8
0.5750.0635
6.9280.0635
G
1.771 0.05
D
C
B
A
D
C
B
A
7
2.916 0.075
8.009 0.05
(9.78)
WINDOW
(5.832)
ACTIVE ARRAY
(7.503)
APERTURE
C
1.5
1.5
B
H
(ILLUMINATION
DIRECTION)
0.683
11.1860.0635
±0.0635
(11.869) APERTURE
3.8940.05
12.9920.05
(16.886) WINDOW
100X SQUARE LGA PADS
0.52±0.05 X 0.52±0.05
VIEW F
WINDOW AND ACTIVE ARRAY
0.2ABC
(FROM SHEET 1)
0.1A
2.04
(1)
27 X 0.7424 = 20.0448
2
3
4
5
6
25 26 27 28 29 (30) (31)
16X CIRCULAR
TEST PADS
(0.52)
BACK SIDE
INDEX MARK
(A)
B
(0.068) TYP.
(42°) TYP.
C
D
E
3.341
(0.075) TYP.
1.5
C
F
9 X 0.7424
= 6.6816
G
H
J
1.5
DETAIL G
APERTURE TOP EDGE
B
SCALE 60 : 1
K
(42°) TYP.
(42°) TYP.
L
(0.15) TYP.
(0.068) TYP.
SYMBOLIZATION PAD
(7 X 3)
VIEW J-J
BACK SIDE METALLIZATION
DETAIL H
(FROM SHEET 1)
APERTURE BOTTOM EDGE
SCALE 60 : 1
DWG NO
REV
SIZE
DRAWN
DATE
2/20/2014
TEXAS
2513652
B. HASKETT
E
3
D
INSTRUMENTS
Dallas Texas
SCALE
SHEET
OF
3
INV11-2006a
5
3
6
1
2
7
8
4
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