DLP471TP_技术文档

DLP471TP

ZHCSNH4B –AUGUST 2020 –REVISED JULY 2023

DLP471TP 0.47 4K 超高清DMD

1 特性

3 说明

• 0.47 英寸对角线微镜阵列

DLP471TP 数字微镜器件 (DMD) 是一款数控微机电系

统 (MEMS) 空间照明调制器 (SLM)，可用于实现高亮

的 4K 超高清显示系统。TI DLP^®产品 0.47 英寸 4K

UHD 芯片组由 DMD、DLPC6540 显示控制器以及

DLPA3005 PMIC 和 LED 驱动器组成。芯片组的外形

紧凑，为体型小巧的 4K 超高清显示器提供完整的系统

解决方案。

– 4K 超高清(3840 × 2160) 显示分辨率

– 5.4 µm 微镜间距

– ±17° 微镜倾斜度（相对于平坦表面）

– 底部照明

• 高速串行接口(HSSI) 输入数据总线

• 支持4K UHD (60Hz)

• 支持1080p（高达240Hz）

• 由DLPC6540 显示控制器、DLPA3005 电源管理

IC (PMIC) 和LED 驱动器支持LED 正常运行

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

DLP471TP

封装

FQQ (270)

25.65mm × 16.9mm

2 应用

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 移动智能电视

• 移动投影仪

• 数字标牌

LS_Interface

HSSI Macro A Data Pair

DMD DCLKA

8

HSSI Macro B Data Pair

DMD DCLKB

DLPC6540

Display Controller

DLP471TP

HSSI DMD

Vx1

V

OFFSET

BIAS

2

I C/SPI

Power

Management

RESET

1.8 V

VREG

简化版应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS173

DLP471TP

ZHCSNH4B –AUGUST 2020 –REVISED JULY 2023

www.ti.com.cn

Table of Contents

7.7 Micromirror Power Density Calculation.....................25

7.8 Micromirror Landed-On/Landed-Off Duty Cycle....... 28

8 Application and Implementation..................................31

8.1 Application Information............................................. 31

8.2 Typical Application.................................................... 31

8.3 Temperature Sensor Diode.......................................32

9 Power Supply Recommendations................................33

9.1 DMD Power Supply Power-Up Procedure................33

9.2 DMD Power Supply Power-Down Procedure........... 33

10 Layout...........................................................................35

10.1 Layout Guidelines................................................... 35

10.2 Impedance Requirements.......................................35

10.3 Layers..................................................................... 35

10.4 Trace Width, Spacing..............................................36

10.5 Power......................................................................36

10.6 Trace Length Matching Recommendations............ 37

11 Device and Documentation Support..........................38

11.1 第三方产品免责声明................................................38

11.2 Device Support........................................................38

11.3 Documentation Support.......................................... 39

11.4 支持资源..................................................................39

11.5 Trademarks............................................................. 39

11.6 静电放电警告...........................................................39

11.7 术语表..................................................................... 39

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 8

6.1 Absolute Maximum Ratings........................................ 8

6.2 Storage Conditions..................................................... 9

6.3 ESD Ratings............................................................... 9

6.4 Recommended Operating Conditions.........................9

6.5 Thermal Information..................................................11

6.6 Electrical Characteristics...........................................12

6.7 Switching Characteristics..........................................13

6.8 Timing Requirements................................................14

6.9 System Mounting Interface Loads............................ 17

6.10 Micromirror Array Physical Characteristics.............18

6.11 Micromirror Array Optical Characteristics............... 19

6.12 Window Characteristics.......................................... 21

6.13 Chipset Component Usage Specification............... 21

7 Detailed Description......................................................22

7.1 Overview...................................................................22

7.2 Functional Block Diagram.........................................22

7.3 Feature Description...................................................23

7.4 Device Functional Modes..........................................23

7.5 Optical Interface and System Image Quality

Considerations............................................................ 23

7.6 Micromirror Array Temperature Calculation.............. 24

Information.................................................................... 40

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (June 2022) to Revision B (July 2023)

Page

• Added section "ILLUMINATION" to Recommended Operating Conditions ....................................................... 9

• Updated Micromirror Array Temperature Calculation ...................................................................................... 24

• Added Micromirror Power DensityCalculation ................................................................................................. 25

Changes from Revision * (August 2020) to Revision A (June 2022)

Page

• 根据最新的德州仪器 (TI) 和行业标准对本文档进行了更新.................................................................................1

• Updated |T_DELTA| MAX from 14°C to 15°C..........................................................................................................9

• Updated Micromirror Array Optical Characteristics ......................................................................................... 19

• Updated 图9-1 ................................................................................................................................................ 33

English Data Sheet: DLPS173

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5 Pin Configuration and Functions

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11

13 15 17 19 21 23 25

2

4

6

8

10 12 14 16 18 20 22 24

图5-1. FQQ Package 270-Pin CLGA (Bottom View)

表5-1. Pin Functions

PIN⁽²⁾

TRACE

LENGTH

(mm)

TYPE⁽¹⁾

DESCRIPTION

TERMINATION

NAME

PAD ID

A8

D_AP(0)

D_AN(0)

D_AP(1)

D_AN(1)

D_AP(2)

D_AN(2)

D_AP(3)

D_AN(3)

D_AP(4)

D_AN(4)

D_AP(5)

D_AN(5)

D_AP(6)

D_AN(6)

D_AP(7)

D_AN(7)

I

High-speed Differential Data Pair lane A0

High-speed Differential Data Pair lane A1

High-speed Differential Data Pair lane A2

High-speed Differential Data Pair lane A3

High-speed Differential Data Pair lane A4

High-speed Differential Data Pair lane A5

High-speed Differential Data Pair lane A6

High-speed Differential Data Pair lane A7

High-speed Differential Clock A

2.15873

2.16135

8.33946

8.34121

6.41271

6.41305

1.8959

Differential 100 Ω

A7

B2

C2

A6

A5

A10

A9

1.8959

D1

E1

12.11543

12.11539

12.01561

12.0164

12.98403

12.98177

2.29773

11.75367

11.57432

2.10786

2.10711

D3

E3

F3

G3

A12

A11

A3

DCLK_AP

DCLK_AN

D_BP(0)

A4

High-speed Differential Clock A

A14

A15

High-speed Differential Data Pair lane B0

D_BN(0)

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English Data Sheet: DLPS173

DLP471TP

ZHCSNH4B –AUGUST 2020 –REVISED JULY 2023

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表5-1. Pin Functions (continued)

PIN⁽²⁾

TRACE

LENGTH

(mm)

TYPE⁽¹⁾

DESCRIPTION

TERMINATION

NAME

PAD ID

F23

D_BP(1)

D_BN(1)

D_BP(2)

D_BN(2)

D_BP(3)

D_BN(3)

D_BP(4)

D_BN(4)

D_BP(5)

D_BN(5)

D_BP(6)

D_BN(6)

D_BP(7)

D_BN(7)

I

High-speed Differential Data Pair lane B1

High-speed Differential Data Pair lane B2

High-speed Differential Data Pair lane B3

High-speed Differential Data Pair lane B4

High-speed Differential Data Pair lane B5

High-speed Differential Data Pair lane B6

High-speed Differential Data Pair lane B7

High-speed Differential Clock B

LVDS Data

12.79448

12.79438

13.00876

13.00932

11.21886

11.21881

10.79038

10.78946

5.75986

5.75928

9.01461

9.01416

2.08767

2.12928

2.30933

0

Differential 100 Ω

G23

E24

E23

A22

A23

D25

D24

A20

A21

B24

B25

A18

A19

A17

A16

T16

R16

T14

R14

R18

T20

C21

R20

T18

R12

T12

I

DCLK_BP

I

DCLK_BN

I

LS_WDATA_P

LS_WDATA_N

LS_CLK_P

I

LVDS Data

0.27407

2.43086

2.40852

2.00263

4.61261

3.03604

2.88361

1.89945

4.02546

3.62598

I

LVDS CLK

LS_CLK_N

I

LVDS CLK

LS_RDATA_A_BISTA

BIST_B

O

I

LVCMOS Output

AMUX_OUT

DMUX_OUT

DMD_DEN_ARSTZ

TEMP_N

Analog Test Mux

Digital Test Mux

ARSTZ

17.5-kΩpulldown

I

Temp Diode N

TEMP_P

I

Temp Diode P

English Data Sheet: DLPS173

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表5-1. Pin Functions (continued)

PIN⁽²⁾

TRACE

TYPE⁽¹⁾

DESCRIPTION

TERMINATION

LENGTH

(mm)

NAME

PAD ID

B13, C5,

C9, C12,

C15, C18,

C22, D6,

D7, D14,

D16, D19,

D20, E21,

G21, J4,

J21, J23,

K3, K22,

L2, L4,

L22, M1,

M3, M21,

M23, M25,

N2, N4, N6,

N8, N16,

N18, N20,

N22, N24,

P3, P5, P7,

P9, P11,

VDD

P

Digital core supply voltage

Plane

P13, P15,

P17, P19,

P21, P23,

P25, R2,

R4, R6, R8,

R10, T3,

T5, T7, T9,

T11, T13,

T15, T17,

T19, T21,

T23

A24, B3,

B5, B7, B9,

B11, B14,

B16, B18,

B20, B22,

C1, C24,

D4, D23,

E2, F4,

VDDA

P

HSSI supply voltage

Plane

F22, H3,

H22

Supply voltage for negative bias of

micromirror reset signal

VRESET

VBIAS

A2, R1

B1, P1

P

Plane

Supply voltage for positive bias of

micromirror reset signal

A1, A25,

T1, T25

Supply voltage for HVCMOS logic, stepped

up logic level

VOFFSET

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English Data Sheet: DLPS173

DLP471TP

ZHCSNH4B –AUGUST 2020 –REVISED JULY 2023

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表5-1. Pin Functions (continued)

PIN⁽²⁾

TRACE

LENGTH

(mm)

TYPE⁽¹⁾

DESCRIPTION

TERMINATION

NAME

PAD ID

C4, C6, C8,

C10, C13,

C14, C17,

C19, C23,

D5, D8,

D15, D17,

D18, D21,

D22, F21,

H4, H21,

J3, J22, K4,

K21, K23,

L3, L21,

L23, M2,

M4, M22,

M24, N1,

N3, N5, N7,

N17, N19,

N21, N23,

N25, P2,

VSS

G

Ground

Plane

P4, P6, P8,

P10, P12,

P14, P16,

P18, P20,

P22, P24,

R3, R5, R7,

R9, R11,

R13, R15,

R17, R19,

R21, R23,

R25, T2,

T4, T8, T10

A13, B4,

B6, B8,

B10, B12,

B15, B17,

B19, B21,

B23, C3,

C7, C11,

C16, C20,

C25, D2,

E4, E22,

E25, F2,

G4, G22,

H23

VSSA

G

Ground

Plane

None

DMD_Detect

T6

NC

DMD detection

English Data Sheet: DLPS173

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表5-1. Pin Functions (continued)

PIN⁽²⁾

TRACE

TYPE⁽¹⁾

DESCRIPTION

TERMINATION

LENGTH

(mm)

NAME

PAD ID

D9, D10,

D11, D12,

D13, E10,

E11, E12,

E13, E14,

E15, E16,

E17, E18,

F24, G2,

K2, L24,

M12, M13,

M14, M15,

M16, M17,

M18, N9,

N10, N11,

N12, N13,

N14, N15,

R22,

N/C

NC

No connect pin

None

R24 ,T22,

T24

(1) I=Input, O=Output, P=Power, G=Ground, NC = No Connect

(2) Only 238 pins are electrically connected for functional use.

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English Data Sheet: DLPS173

DLP471TP

ZHCSNH4B –AUGUST 2020 –REVISED JULY 2023

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6 Specifications

6.1 Absolute Maximum Ratings

Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not

imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating

Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not

be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

MIN

MAX UNIT

SUPPLY VOLTAGE

Supply voltage for LVCMOS core logic and LVCMOS low speed interface

(LSIF)⁽¹⁾

V_DD

2.3

V

–0.5

V_DDA

Supply voltage for high speed serial interface (HSSI) receivers⁽¹⁾

Supply voltage for HVCMOS and micromirror electrode^{(1) (2)}

Supply voltage for micromirror electrode⁽¹⁾

2.2

11

V

–0.3

–0.5

–15

V_OFFSET

V_BIAS

19

0.5

0.3

11

V_RESET

Supply voltage for micromirror electrode⁽¹⁾

Supply voltage delta (absolute value)⁽³⁾

| V_DDA–V_DD

|

Supply voltage delta (absolute value)⁽⁴⁾

| V_BIAS–V_OFFSET

|

Supply voltage delta (absolute value)⁽⁵⁾

34

| V_BIAS–V_RESET

|

INPUT VOLTAGE

Input voltage for other inputs –LSIF and LVCMOS⁽¹⁾

Input voltage for other inputs –HSSI^{(1) (6)}

–0.5

–0.2

2.45

V

V_DDA

LOW SPEED INTERFACE (LSIF)

f_CLOCKLSIF clock frequency (LS_CLK)

130 MHz

| V_ID

I_ID

|

LSIF differential input voltage magnitude⁽⁶⁾

810

10

mV

mA

LSIF differential input current

HIGH SPEED SERIAL INTERFACE (HSSI)

f_CLOCKHSSI clock frequency (DCLK)

1.65 GHz

| V_ID

|

HSSI differential input voltage magnitude Data Lane⁽⁶⁾

HSSI differential input voltage magnitude Clock Lane⁽⁶⁾

700

mV

ENVIRONMENTAL

Temperature, operating⁽⁷⁾

0

90

°C

T_WINDOWand T_ARRAY

Temperature, non-operating⁽⁷⁾

–40

Absolute temperature delta between any point on the window edge and the

ceramic test point TP1⁽⁸⁾

|T_DELTA

T_DP

|

30

81

°C

Dew point temperature, operating and non–operating (noncondensing)

(1) All voltage values are with respect to the ground terminals (V_SS). The following required power supplies must be connected for proper

DMD operation: V_DD, V_DDA, V_OFFSET, V_BIAS, and V_RESET. All V_SSconnections are also required.

(2) V_OFFSETsupply transients must fall within specified voltages.

(3) Exceeding the recommended allowable absolute voltage difference between V_DDAand V_DDmay result in excessive current draw.

(4) Exceeding the recommended allowable absolute voltage difference between V_BIASand V_OFFSETmay result in excessive current draw.

(5) Exceeding the recommended allowable absolute voltage difference between V_BIASand V_RESETmay result in excessive current draw.

(6) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. LVDS and HSSI

differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(7) The highest temperature of the active array (as calculated using Micromirror Array Temperature Calculation) or of any point along the

window edge as defined in 图7-1. The locations of thermal test points TP2, TP3, TP4 and TP5 in 图7-1 are intended to measure the

highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature,

that point should be used.

(8) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图

7-1. The window test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to result in the worst case delta. If a particular

application causes another point on the window edge to result in a larger delta temperature, that point should be used.

English Data Sheet: DLPS173

8

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6.2 Storage Conditions

Applicable for the DMD as a component or non-operating in a system.

MIN

MAX

85

24

36

6

UNIT

°C

T_DMD

DMD temperature

–40

T_DP-AVG

T_DP-ELR

CT_ELR

Average dew point temperature, non-condensing⁽¹⁾

Elevated dew point temperature range, non-condensing⁽²⁾

Cumulative time in elevated dew point temperature range

°C

28

°C

months

(1) The average temperature over time (including storage and operating temperatures) that the device is not in the elevated dew point

temperature range.

(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total

cumulative time of CT_ELR

.

6.3 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V

Electrostatic

discharge

V_(ESD)

Charged device model (CDM), per JEDEC specification ANSI/ESDA/JEDEC

JS-002⁽²⁾

±500

V

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

Over operating free-air temperature range and supply voltages (unless otherwise noted). The functional performance of the

device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended

Operating Conditions. No level of performance is implied when operating the device above or below the Recommended

Operating Conditions limits.

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGES ^{(1) (2)}

Supply voltage for LVCMOS core logic and low speed

interface (LSIF)

V_DD

1.71

1.8

1.95

V

V_DDA

Supply voltage for high speed serial interface (HSSI) receivers

Supply voltage for HVCMOS and micromirror electrode⁽³⁾

Supply voltage for micromirror electrode

Supply voltage delta, absolute value⁽⁴⁾

1.71

9.5

1.8

10

1.95

10.5

V

V_OFFSET

V_BIAS

17.5

18

18.5

V_RESET

–14.5

–14

–13.5

0.3

| V_DDA–V_DD

|

| V_BIAS–V_OFFSET

|

Supply voltage delta, absolute value⁽⁵⁾

Supply voltage delta, absolute value

|

10.5

33

V

| V_BIAS–V_RESET

LVCMOS INPUT

V_IH

V_IL

High level input voltage⁽⁶⁾

Low level input voltage⁽⁶⁾

0.7 × V_DD

V

0.3 × V_DD

LOW SPEED SERIAL INTERFACE (LSIF)

f_CLOCK

DCD_IN

LSIF clock frequency (LS_CLK)⁽⁷⁾

108

44%

150

575

700

90

120

350

130

56%

440

MHz

LSIF duty cycle distortion (LS_CLK)

LSIF differential input voltage magnitude⁽⁷⁾

LSIF voltage⁽⁷⁾

| V_ID

|

mV

Ω

V_LVDS

V_CM

Z_LINE

Z_IN

1520

1300

110

Common mode voltage⁽⁷⁾

900

100

Line differential impedance (PWB/trace)

Internal differential termination resistance

80

120

Ω

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English Data Sheet: DLPS173

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6.4 Recommended Operating Conditions (continued)

Over operating free-air temperature range and supply voltages (unless otherwise noted). The functional performance of the

device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended

Operating Conditions. No level of performance is implied when operating the device above or below the Recommended

Operating Conditions limits.

MIN

TYP

MAX

UNIT

HIGH SPEED SERIAL INTERFACE (HSSI)

f_CLOCK

HSSI clock frequency (DCLK)⁽⁸⁾

1.2

44

1.6

56

GHz

%

DCD_IN

HSSI duty cycle distortion (DCLK)

50

| V_ID| Data

| V_ID| CLK

VCM_DCData

VCM_DCCLK

HSSI differential input voltage magnitude Data Lane⁽⁸⁾

HSSI differential input voltage magnitude Clock Lane⁽⁸⁾

Input common mode voltage (DC) Data Lane⁽⁸⁾

Input common mode voltage (DC) Clk Lane⁽⁸⁾

100

295

200

600

800

mV

600

AC peak to peak (ripple) on common mode voltage of Data

Lane and Clock Lane⁽⁸⁾

VCM_ACp-p

100

mV

Z_LINE

Line differential impedance (PWB/trace)

100

Ω

Z_IN

Internal differential termination resistance. ( R_Xterm

)

80

120

ENVIRONMENTAL

Array temperature, long–term operational^{(9) (10) (11) (12)}

Array temperature, short-term operational, 500 hr max^{(10) (13)}

Window temperature, operational⁽¹⁴⁾

10

0

40 to 70 ⁽¹¹⁾

°C

T_ARRAY

10

85

T_WINDOW

Absolute temperature delta between any point on the window

edge and the ceramic test point TP1⁽¹⁵⁾

|T_DELTA

|

15

°C

Average dew point temperature (non–condensing)⁽¹⁶⁾

Elevated dew point temperature range (non-condensing)⁽¹⁷⁾

Cumulative time in elevated dew point temperature range

T_DP-AVG

T_DP-ELR

CT_ELR

24

36

6

°C

28

months

ILLUMINATION

ILL_UV

Illumination power at wavelengths < 410 nm⁽⁹⁾

10 mW/cm²

ILL_VIS

20.5

W/cm²

Illumination power at wavelengths ≥410 nm and ≤800

nm⁽¹⁹⁾

ILL_IR

Illumination power at wavelengths > 800 nm

10 mW/cm²

ILL_BLU

6.5

1.2

55

W/cm²

deg

Illumination power at wavelengths ≥410 nm and ≤475

nm⁽¹⁹⁾

ILL_BLU1

ILL_θ

Illumination power at wavelengths ≥410 nm and ≤445

nm⁽¹⁹⁾

Illumination marginal ray angle⁽¹⁸⁾

(1) All power supply connections are required to operate the DMD: V_DD, V_DDA, V_OFFSET, V_BIAS, and V_RESET. All V_SSconnections are

required to operate the DMD.

(2) All voltage values are with respect to the V_SSground pins.

(3) V_OFFSETsupply transients must fall within specified max voltages.

(4) To prevent excess current, the supply voltage delta | V_DDA–V_DD| must be less than specified limit.

(5) To prevent excess current, the supply voltage delta | V_BIAS–V_OFFSET| must be less than specified limit.

(6) LVCMOS input pin is DMD_DEN_ARSTZ.

(7) See the low speed interface (LSIF) timing requirements in Timing Requirements.

(8) See the high speed serial interface (HSSI) timing requirements in Timing Requirements.

(9) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will

reduce device lifetime.

(10) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point

(TP1) shown in 图7-1 and the package thermal resistance using the Micromirror Array Temperature Calculation.

(11) Per 图6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD

experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty

cycle.

(12) Long-term is defined as the usable life of the device.

(13) Short-term is the total cumulative time over the useful life of the device.

English Data Sheet: DLPS173

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(14) The locations of thermal test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to measure the highest window edge

temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular

application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.

(15) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in

图7-1. The window test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to result in the worst case delta

temperature. If a particular application causes another point on the window edge to result in a larger delta in temperature, that point

should be used.

(16) The average over time (including storage and operating) that the device is not in the ‘elevated dew point temperature range'.

(17) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total

cumulative time of CT_ELR

.

(18) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors

(POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily

been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not

been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM)

will contribute to thermal limitations described in this document, and may negatively affect lifetime.

(19) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength

range specified and the micromirror array temperature (T_ARRAY).

80

70

60

50

40

30

0/100

100/0

5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50

65/35

95/5

90/10

85/15

80/20

75/25

70/30

60/40

55/45

50/50

Micromirror Landed Duty Cycle

图6-1. Maximum Recommended Array Temperature—Derating Curve

6.5 Thermal Information

DLP471TP

FQQ PACKAGE

270 PIN

THERMAL METRIC

Unit

Thermal Resistance, active area to test point 1 (TP1)⁽¹⁾

1.0

°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in the 节6.4. The total heat load on the DMD is largely driven by the

incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and

electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window

clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

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MAX UNIT

6.6 Electrical Characteristics

Over operating free-air temperature range and supply voltages (unless otherwise noted)

PARAMETER ^{(1) (2)}

TEST CONDITIONS ⁽¹⁾

MIN

TYP

CURRENT –TYPICAL

(3)

I_DD

Supply current V_DD

Supply current V_DDA

800

1000

20

1200 mA

25 mA

4.0 mA

mA

(3)

I_DDA

(4) (5)

I_OFFSET

I_BIAS

Supply current V_OFFSET

(4) (5)

Supply current V_BIAS

Supply current V_RESET

2.5

(5)

I_RESET

-9.3

-6.9

POWER –TYPICAL

(3)

P_DD

Supply power dissipation V_DD

1440

1620

230

2437.5 mW

2340 mW

(3)

P_DDA

Supply power dissipation V_DDA

Supply power dissipation V_OFFSET

(4) (5)

P_OFFSET

367.5 mW

70.3 mW

P_BIAS

Supply power dissipation V_BIAS

Supply power dissipation V_RESET

Supply power dissipation Total

43.2

(5)

P_RESET

107.8

3441

152.25 mW

5367.55 mW

P_TOTAL

LVCMOS INPUT

I_IL

Low level input current ⁽⁶⁾

High level input current ⁽⁶⁾

V_DD= 1.95 V, V_I= 0 V

nA

–100

0.8 x V_DD

100

I_IH

V_DD= 1.95 V, V_I= 1.95 V

135 uA

LVCMOS OUTPUT

V_OH

V_OL

DC output high voltage ⁽⁷⁾

DC output low voltage ⁽⁷⁾

I_OH= -2 mA

I_OL= 2 mA

V

0.2 x V_DD

V

RECEIVER EYE CHARACTERISTICS

A1

A2

X1

X2

Minimum data eye opening ^{(8) (9)}

400

600 mV

Maximum data signal swing ^{(8) (9)}

Maximum data eye closure ⁽⁸⁾

0.275

UI

0.4

20

Drift between Clock and Data between

Training Patterns

| t_DRIFT

|

ps

CAPACITANCE

C_IN

Input capacitance LVCMOS

f = 1 MHz

10 pF

20 pF

Input capacitance LSIF (low speed

interface)

C_IN

Input capacitance HSSI (high speed serial

interface)

C_IN

f = 1 MHz

20 pF

10 pF

C_OUT

Output capacitance

(1) All power supply connections are required to operate the DMD: V_DD, V_DDA, V_OFFSET, V_BIAS, and V_RESET. All V_SSconnections are

required to operate the DMD.

(2) All voltage values are with respect to the ground pins (V_SS).

(3) To prevent excess current, the supply voltage delta | V_DDA–V_DD| must be less than specified limit.

(4) To prevent excess current, the supply voltage delta | V_BIAS–V_OFFSET| must be less than specified limit.

(5) Supply power dissipation based on 3 global resets in 200 µs.

(6) LVCMOS input specifications are for pin DMD_DEN_ARSTZ.

(7) LVCMOS output specification is for pins LS_RDATA_A and LS_RDATA_B.

(8) Refer to 图6-11, Receiver Eye Mask (1e-12 BER).

(9) Defined in Recommended Operating Conditions.

English Data Sheet: DLPS173

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6.7 Switching Characteristics

Over operating free-air temperature range and supply voltages (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Output propagation, Clock to Q (C2Q), rising edge of

LS_CLK (differential clock signal) input to LS_RDATA

output. ⁽¹⁾

C_L= 5 pF

11.1

11.3

ns

t_pd

C_L= 10 pF

Slew rate, LS_RDATA

0.5

V/ns

20%–80%, C_L<10pF

Output duty cycle distortion, LS_RDATA_A and

LS_RDATA_B

50-(C2Q rise –C2Q fall )

×130e6×100

40%

60%

(1) See 图6-2.

LS_CLK_P

1

0

1

0

1

0

1

0

1

0

LS_CLK_N

1 period

LS_WDATA_P

LS_WDATA_N

Stop (1)

Start (0)

t_PD

LS_RDATA_A

BIST_A

Acknowledge

图6-2. Switching Characteristics

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MAX UNIT

6.8 Timing Requirements

Over operating free-air temperature range and supply voltages (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

LVCMOS

t_r

t_f

Rise time⁽¹⁾

Fall time⁽¹⁾

20% to 80% reference points

25

ns

80% to 20% reference points

LOW SPEED INTERFACE (LSIF)

t_r

Rise time⁽²⁾

20% to 80% reference points

450

ps

ns

t_f

Fall time⁽²⁾

80% to 20% reference points

t_W(H)

t_W(L)

Pulse duration high⁽³⁾

Pulse duration low⁽³⁾

LS_CLK. 50% to 50% reference points

3.1

LS_WDATA valid before rising edge of LS_CLK

(differential)

t_su

t_h

Setup time⁽⁴⁾

Hold time⁽⁴⁾

1.5

ns

LS_WDATA valid after rising edge of LS_CLK

(differential)

HIGH SPEED SERIAL INTERFACE (HSSI)

Rise time - data^{(5) (6)}

50

115

135

115

135

ps

ns

From –A1 to A1 minimum eye height specification

From A1 to –A1 minimum eye height specification

DCLK. 50% to 50% reference points

t_r

Rise time - clock^{(5) (6)}

Fall time —data^{(5) (6)}

50

t_f

Fall time —clock^{(5) (6)}

50

t_W(H)

t_W(L)

Pulse duration high⁽⁷⁾

Pulse duration low⁽⁷⁾

0.275

DCLK. 50% to 50% reference points

(1) See 图6-9 for rise time and fall time for LVCMOS.

(2) See 图6-4 for rise time and fall time for LSIF.

(3) See 图6-4 for pulse duration high and low time for LSIF.

(4) See 图6-4 for setup and hold time for LSIF.

(5) See 图6-11 for rise time and fall time for HSSI Eye Characteristics.

(6) See 图6-12 for rise time and fall time for HSSI.

(7) See 图6-12 for pulse duration high and low for HSSI.

1.255 V

V

LVDS(max)

V

CM

ID

V

LVDS(min)

0.575 V

A. See 方程式1 and 方程式2

图6-3. LSIF Waveform Requirements

1

V_{LVDS max}= V

:

_;+ , × V

,

;

ID max

;

:

CM max

:

2

(1)

(2)

1

V_{LVDS min}= V

:

_;F , × V

,

;

ID max

;

:

CM min

:

2

English Data Sheet: DLPS173

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t

W(H)|

W(L)|

LS_CLK_P

50%

LS_CLK_N

t

H|

SU|

LS_WDATA_P

50%

LS_WDATA_N

t

WINDOW|

图6-4. LSIF Timing Requirements

V

, V

LS_CLK_P LS_CLK_N LS_WDATA_P LS_WDATA_N

, V

100

90

80

70

60

50

40

30

20

10

0

t_r

t_f

图6-5. LSIF Rise, Fall Time Slew

+

(V_IP+ V_IN

)

V_CM

=

œ

2

LS_CLK_P,

LS_WDATA_P

V_ID

LS_CLK_N,

LS_WDATA_N

LVDS

Receiver

V_CM

V_IP

V_IN

图6-6. LSIF Voltage Requirements

LS_CLK_P

LS_WDATA_P

Internal

Termination

ESD

(Z_IN

)

LVDS

Receiver

LS_CLK_N

LS_WDATA_N

图6-7. LSIF Equivalent Input

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V

IH

V

T+

DV

T

V

Tœ

V

IL

DMD_DEN_ARTZ

Time

图6-8. LVCMOS Input Hysteresis

DMD_DEN_ARSTZ

100

90

80

V

OH

70

60

50

40

30

20

V

OL

10

0

t_r

t

f

图6-9. LVCMOS Rise, Fall Time Slew Rate

t

f

V

HSSI(max)

V

ID

CM

V

HSSI(min)

t

r

A. See 方程式3 and 方程式4

图6-10. HSSI Waveform Requirements

1

V_{HSSI max}= V

:

_;+ , × V

,

;

ID max

;

:

CM max

:

2

(3)

1

V_{HSSI min}= V

:

_;F , × V

,

;

ID max

;

:

CM min

:

2

(4)

English Data Sheet: DLPS173

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A2

A1

0V

-A1

-A2

X1

1-X1

X2 1-X2

0

1 UI

图6-11. HSSI Eye Characteristics

t

C|

t

W(H)|

W(L)|

DCLK_?P

50%

DCLK_?N

图6-12. HSSI CLK Characteristics

6.9 System Mounting Interface Loads

PARAMETER

Thermal interface area⁽¹⁾

MIN

TYP

MAX

100

UNIT

N

Electrical interface area⁽¹⁾

245

N

(1) The load should be uniformly applied within the area shown in 图6-13.

Electrical Interface Area

Thermal Interface Area

图6-13. System Mounting Interface Loads

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6.10 Micromirror Array Physical Characteristics

PARAMETER DESCRIPTION

VALUE

1920

1080

5.4

UNIT

Number of active columns^{(1) (2)}

Number of active rows^{(1) (2)}

Micromirror (pixel) pitch ⁽¹⁾

M

micromirrors

μm

N

P

Micromirror active array width⁽¹⁾

Micromirror active array height⁽¹⁾

Micromirror active border⁽³⁾

Micromirror pitch × number of active columns

Micromirror pitch × number of active rows

Pond of micromirror (POM)

10.368

5.832

20

mm

micromirrors/side

(1) See 图6-14.

(2) The fast switching speed of the DMD micromirrors combined with advanced DLP image processing algorithms enables each

micromirror

to display four distinct pixels on the screen during every frame, resulting in a full 3840 × 2160 pixel image being displayed.

(3) The structure and qualities of the border around the active array includes a band of partially functional micromirrors referred to as the

Pond Of Micromirrors (POM). These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state

but still require an electrical bias to tilt toward the OFF state.

Off-State

Light Path

0

1

2

3

Active Micromirror Array

N x P

M x N Micromirrors

Nœ 4

Nœ 3

Nœ 2

Nœ 1

M x P

P

Incident

Illumination

Light Path

P

Pond Of Micromirrors (POM) omitted for clarity.

Details omitted for clarity.

Not to scale.

P

图6-14. Micromirror Array Physical Characteristics

English Data Sheet: DLPS173

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6.11 Micromirror Array Optical Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

Micromirror tilt angle

Landed state ⁽¹⁾

17

1.4

°

Micromirror tilt angle tolerance^{(2) (3) (4) (5)}

Micromirror tilt direction ^{(6) (7)}

Micromirror crossover time ⁽⁸⁾

Micromirror switching time ⁽⁹⁾

–1.4

Landed ON state

Landed OFF state

Typical performance

Gray 10 Screen ⁽¹²⁾

White Screen

270

180

1

3

μs

6

Bright pixel(s) in active area ⁽¹¹⁾

0

1

4

0

Bright pixel(s) in the POM ⁽¹³⁾

Dark pixel(s) in the active area ⁽¹⁴⁾

Adjacent pixel(s) ⁽¹⁵⁾

Image

micromirrors

performance⁽¹⁰⁾

Any Screen

Unstable pixel(s) in active area ⁽¹⁶⁾

Any Screen

(1) Measured relative to the plane formed by the overall micromirror array.

(2) Additional variation exists between the micromirror array and the package datums.

(3) Represents the landed tilt angle variation relative to the nominal landed tilt angle.

(4) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different

devices.

(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some

system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field

reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result

in colorimetry variations, system efficiency variations or system contrast variations.

(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of

the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State

direction. A binary value of 0 results in a micromirror landing in the OFF State direction. See 图6-15.

(7) Micromirror tilt direction is measured as in a typical polar coordinate system: Measuring counter-clockwise from a 0° degree reference

which is aligned with the +X Cartesian axis.

(8) The time required for a micromirror to nominally transition from one landed state to the opposite landed state.

(9) The minimum time between successive transitions of a micromirror.

(10) Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions:

Test set degamma shall be linear

Test set brightness and contrast shall be set to nominal

The diagonal size of the projected image shall be a minimum of 20 inches

The projections screen shall be 1X gain

The projected image shall be inspected from a 38 inch minimum viewing distance

The image shall be in focus during all image quality tests

(11) Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels

(12) Gray 10 screen definition: All areas of the screen are colored with the following settings:

Red = 10/255

Green = 10/255

Blue = 10/255

(13) POM definition: Rectangular border of off-state mirrors surrounding the active area

(14) Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels

(15) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster

(16) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable

pixel appears to be flickering asynchronously with the image

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Border micromirrors omitted for clarity

Off State

Light Path

Details omitted for clarity.

Not to scale.

0

1

2

3

Tilted Axis of

Pixel Rotation

Off-State

Landed Edge

On-State

Landed Edge

Nœ 4

Nœ 3

Nœ 2

Nœ 1

Incident

Illumination

Light Path

图6-15. Micromirror Landed Orientation and Tilt

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6.12 Window Characteristics

DESCRIPTION⁽¹⁾

MIN

TYP MAX

Corning Eagle XG

1.5119

Window material

Window refractive index

Window aperture ⁽²⁾

Illumination overfill ⁽³⁾

At wavelength 546.1 nm

See ⁽²⁾

See ⁽³⁾

.

Minimum within the wavelength range 420 nm to

680 nm. Applies to all angles 0° to 30° AOI⁽⁴⁾

97%

Window transmittance, single-pass

through both surfaces and glass

Average over the wavelength range 420 nm to 680

nm. Applies to all angles 30° to 45° AOI⁽⁴⁾

(1) See 节7.5 for more information.

(2) See the package mechanical characteristics for details regarding the size and location of the window aperture.

(3) The active area of the DLP471TP device is surrounded by an aperture on the inside of the DMD window surface that masks structures

of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating

the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. The

illumination optical system should be designed to limit light flux incident outside the active array to less than 10% of the average flux

level in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of overfill light

on the outside of the active array may cause system performance degradation.

(4) Angle of incidence (AOI) is the angle between an incident ray and the normal to a reflecting or refracting surface.

6.13 Chipset Component Usage Specification

Reliable function and operation of the DLP471TP DMD requires that it be used in conjunction with the other

components of the applicable DLP chipset, including those components that contain or implement TI DMD

control technology. TI DMD control technology consists of the TI technology and devices used for operating or

controlling a DLP DMD.

备注

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system

operating conditions exceeding limits described previously.

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7 Detailed Description

7.1 Overview

The DMD is a 0.47-inch diagonal spatial light modulator which consists of an array of highly reflective aluminum

micromirrors. The DMD is an electrical input, optical output micro-optical-electrical-mechanical system

(MOEMS). The fast switching speed of the DMD micromirrors combined with advanced DLP image processing

algorithms enables each micromirror to display four distinct pixels on the screen during every frame, resulting in

a full 3840 × 2160 pixel image being displayed. The electrical interface is low voltage differential signaling

(LVDS). The DMD consists of a two-dimensional array of 1-bit CMOS memory cells. The array is organized in a

grid of M memory cell columns by N memory cell rows. Refer to the Functional Block Diagram. The positive or

negative deflection angle of the micromirrors can be individually controlled by changing the address voltage of

underlying CMOS addressing circuitry and micromirror reset signals (MBRST).

The DLP 0.47” 4K UHD chipset is comprised of the DLP471TP DMD, DLPC6540 display controller, and the

DLPA3005 PMIC and the LED driver. To ensure reliable operation, the DLP471TP DMD must always be used

with the DLP display controller and the PMIC specified in the chipset.

7.2 Functional Block Diagram

Channel A Interface

Control

Column Read/Write

Bit Lines

(0,0)

Word

Lines

Voltages

Voltage

Generators

Micromirror

Array

Row

(M-1,N-1)

Bit Lines

Control

Column Read/Write

Control

Channel B Interface

.

English Data Sheet: DLPS173

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7.3 Feature Description

7.3.1 Power Interface

The DMD requires 4 DC voltages: 1.8 V source, V_OFFSET, V_RESET, and V_BIAS. In a typical LED-based system, 1.8

V is provided by a TPS54320 and the V_OFFSET, V_RESET, and V_BIASis managed by the DLPA3005 PMIC and LED

driver.

7.3.2 Timing

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be considered. Timing reference loads are not intended to be precise

representations of any particular system environment or depiction of the actual load presented by a production

test. System designers should use IBIS or other simulation tools to correlate the timing reference load to a

system environment. The load capacitance value stated is only for characterization and measurement of AC

timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

7.4 Device Functional Modes

DMD functional modes are controlled by the DLPC6540 display controller. See the DLPC6540 display controller

data sheet or contact a TI applications engineer.

7.5 Optical Interface and System Image Quality Considerations

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous component and system design parameters.

Optimizing system optical performance and image quality strongly relate to optical system design parameter

trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical

performance is contingent on compliance to the optical system operating conditions described in the following

sections.

7.5.1 Numerical Aperture and Stray Light Control

The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area

should be the same. This angle should not exceed the nominal device micromirror tilt angle unless appropriate

apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the

projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from any

other light path, including undesirable flat-state specular reflections from the DMD window, DMD border

structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture

exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger

than the illumination numerical aperture angle (and vice versa), contrast degradation and objectionable artifacts

in the display border and/or active area could occur.

7.5.2 Pupil Match

TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally

centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable

artifacts in the display border and/or active area, which may require additional system apertures to control,

especially if the numerical aperture of the system exceeds the pixel tilt angle.

7.5.3 Illumination Overfill

The active area of the device is surrounded by an aperture on the inside DMD window surface that masks

structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating

conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window

aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system

should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately

10% of the average flux level in the active area. Depending on the particular system optical architecture, overfill

light may have to be further reduced below the suggested 10% level in order to be acceptable.

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7.6 Micromirror Array Temperature Calculation

TP2

Array

2X 7.37

TP4

TP5

2X 12.43

TP3

TP3 (TP2)

Window Edge

(4 surfaces)

TP4

TP5

TP1

5.45

12.43

TP1

图7-1. DMD Thermal Test Points

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Micromirror array temperature cannot be measured directly, therefore it must be computed analytically from

measurement points on the outside of the package, the package thermal resistance, the electrical power, and

the illumination heat load. The relationship between array temperature and the reference ceramic temperature

(thermal test TP1 in 图7-1) is provided by the following equations:

T_ARRAY= T_CERAMIC+ (Q_ARRAY× R_{ARRAY-TO-CERAMIC}

)

Q_ARRAY= Q_ELECTRICAL+ Q_ILLUMINATION

where

•

T_ARRAY= Computed array temperature (°C)

T_CERAMIC= Measured ceramic temperature (°C) (TP1 location)

R_{ARRAY-TO-CERAMIC}= Thermal resistance of package specified in 节6.5 from array to ceramic TP1 (°C/Watt)

Q_ARRAY= Total DMD power on the array (W) (electrical + absorbed)

Q_ELECTRICAL= Nominal electrical power (W)

Q_INCIDENT= Incident illumination optical power (W)

Q_ILLUMINATION= (DMD average thermal absorptivity × Q_INCIDENT) (W)

DMD average thermal absorptivity = 0.4

The electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating

frequencies. A nominal electrical power dissipation to use when calculating array temperature is 2.5 Watts. The

absorbed power from the illumination source is variable and depends on the operating state of the micromirrors

and the intensity of the light source. The equations shown above are valid for a single chip or multichip DMD

system. It assumes an illumination distribution of 83.7% on the active array, and 16.3% on the array border.

The sample calculation for a typical projection application is as follows:

Q_INCIDENT= 9.4 W (measured)

T_CERAMIC= 55.0°C (measured)

Q_ELECTRICAL= 2.5 W

Q_ARRAY= 2.5 W + (0.40 × 9.4 W) = 6.26 W

T_ARRAY= 55.0°C + (6.26 W × 1.0°C/W) = 61.3°C

7.7 Micromirror Power Density Calculation

The calculation of the optical power density of the illumination on the DMD in the different wavelength bands

uses the total measured optical power on the DMD, percent illumination overfill, area of the active array, and

ratio of the spectrum in the wavelength band of interest to the total spectral optical power.

• ILL_UV= [OP_UV-RATIO× Q_INCIDENT] × 1000 ÷ A_ILL(mW/cm²)

• ILL_VIS= [OP_VIS-RATIO× Q_INCIDENT] ÷ A_ILL(W/cm²)

• ILL_IR= [OP_IR-RATIO× Q_INCIDENT] × 1000 ÷ A_ILL(mW/cm²)

• ILL_BLU= [OP_BLU-RATIO× Q_INCIDENT] ÷ A_ILL(W/cm²)

• ILL_BLU1= [OP_BLU1-RATIO× Q_INCIDENT] ÷ A_ILL(W/cm²)

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• A_ILL= A_ARRAY÷ (1 - OV_ILL) (cm²)

where:

• ILL_UV= UV illumination power density on the DMD (mW/cm²)

• ILL_VIS= VIS illumination power density on the DMD (W/cm²)

• ILL_IR= IR illumination power density on the DMD (mW/cm²)

• ILL_BLU= BLU illumination power density on the DMD (W/cm²)

• ILL_BLU1= BLU1 illumination power density on the DMD (W/cm²)

• A_ILL= illumination area on the DMD (cm²)

• Q_INCIDENT= total incident optical power on DMD (W) (measured)

• A_ARRAY= area of the array (cm ²) (data sheet)

• OV_ILL= percent of total illumination on the DMD outside the array (%) (optical model)

• OP_UV-RATIO= ratio of the optical power for wavelengths <410 nm to the total optical power in the illumination

spectrum (spectral measurement)

• OP_VIS-RATIO= ratio of the optical power for wavelengths ≥410 and ≤800 nm to the total optical power in the

illumination spectrum (spectral measurement)

• OP_IR-RATIO= ratio of the optical power for wavelengths >800 nm to the total optical power in the illumination

spectrum (spectral measurement)

• OP_BLU-RATIO= ratio of the optical power for wavelengths ≥410 and ≤475 nm to the total optical power in the

illumination spectrum (spectral measurement)

• OP_BLU1-RATIO= ratio of the optical power for wavelengths ≥410 and ≤445 nm to the total optical power in the

illumination spectrum (spectral measurement)

The illumination area varies and depends on the illumination overfill. The total illumination area on the DMD is

the array area and overfill area around the array. The optical model is used to determine the percent of the total

illumination on the DMD that is outside the array (OV_ILL) and the percent of the total illumination that is on the

active array. From these values the illumination area (A_ILL) is calculated. The illumination is assumed to be

uniform across the entire array.

From the measured illumination spectrum, the ratio of the optical power in the wavelength bands of interest to

the total optical power is calculated.

Sample calculation:

Q_INCIDENT= 9.40 W (measured)

A_ARRAY= (1.0368 × 0.5832) = 0.6047 cm²(data sheet)

OV_ILL= 16.3% (optical model)

OP_UV-RATIO= 0.00021 (spectral measurement)

OP_VIS-RATIO= 0.99977 (spectral measurement)

OP_IR-RATIO= 0.00002 (spectral measurement)

OP_BLU-RATIO= 0.28100 (spectral measurement)

OP_BLU1-RATIO= 0.03200 (spectral measurement)

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A_ILL= 0.6047 ÷ (1 - 0.163) = 0.7224 cm²

ILL_UV= [0.00021 × 9.40W] × 1000 ÷ 0.7224 cm²= 2.732 mW/cm²

ILL_VIS= [0.99977 × 9.40W] ÷ 0.7224 cm²= 13.01 W/cm²

ILL_IR= [0.00002 × 9.40W] × 1000 ÷ 0.7224 cm²= 0.260 mW/cm²

ILL_BLU= [0.28100 × 9.40W] ÷ 0.7224 cm²= 3.66 W/cm²

ILL_BLU1= [0.03200 × 9.40W] ÷ 0.7224 cm²= 0.42 W/cm²

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7.8 Micromirror Landed-On/Landed-Off Duty Cycle

7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the percentage of time that an

individual micromirror is landed in the ON state versus the amount of time the same micromirror is landed in the

OFF state.

For example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the ON state 100% of the time

(and in the OFF state 0% of the time); whereas 0/100 would indicate that the pixel is in the OFF state 100% of

the time. Likewise, 50/50 indicates that the pixel is ON for 50% of the time (and OFF for 50% of the time).

Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other

state (OFF or ON) is considered negligible and is thus ignored.

Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)

always add to 100.

7.8.2 Landed Duty Cycle and Useful Life of the DMD

Knowing the long-term average landed duty cycle (of the end product or application) is important because

subjecting all (or a portion) of the DMD micromirror array (also called the active array) to an asymmetric landed

duty cycle for a prolonged period of time can reduce the DMD useful life.

Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed

duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed

duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly

asymmetrical.

7.8.3 Landed Duty Cycle and Operational DMD Temperature

Operational DMD temperature and landed duty cycle interact to affect DMD useful life, and this interaction can

be exploited to reduce the impact that an asymmetrical landed duty cycle has on the DMD useful life. This is

quantified in the de-rating curve shown in 图6-1. The importance of this curve is that:

• All points along this curve represent the same useful life.

• All points above this curve represent lower useful life (and the further away from the curve, the lower the

useful life).

• All points below this curve represent higher useful life (and the further away from the curve, the higher the

useful life).

In practice, this curve specifies the maximum operating DMD temperature that the DMD should be operated at

for a given long-term average landed duty cycle.

7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application

During a given period of time, the landed duty cycle of a given pixel follows from the image content being

displayed by that pixel.

For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel

operates under a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-black, the

pixel operates under a 0/100 landed duty cycle.

Between the two extremes (ignoring for the moment color and any image processing that may be applied to an

incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in 表7-1.

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表7-1. Grayscale Value and Landed Duty Cycle

GRAYSCALE VALUE

LANDED DUTY CYCLE

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0/100

10/90

20/80

30/70

40/60

50/50

60/40

70/30

80/20

90/10

100/0

Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from

0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color

cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a

given primary must be displayed in order to achieve the desired white point.

Use 方程式5 to calculate the landed duty cycle of a given pixel during a given time period

Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_% (5)

×

Blue_Scale_Value)

where

• Red_Cycle_%, represents the percentage of the frame time that red is displayed to achieve the desired white

point

• Green_Cycle_% represents the percentage of the frame time that green is displayed to achieve the desired

white point

• Blue_Cycle_%, represents the percentage of the frame time that blue is displayed to achieve the desired

white point

For example, assume that the red, green, and blue color cycle times are 30%, 50%, and 20% respectively (in

order to achieve the desired white point), then the landed duty cycle for various combinations of red, green, blue

color intensities would be as shown in 表7-2 and 表7-3.

表7-2. Example Landed Duty Cycle for Full-Color,

Color Percentage

CYCLE PERCENTAGE

RED

GREEN

BLUE

30%

50%

20%

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表7-3. Example Landed Duty Cycle for Full-Color

SCALE VALUE

GREEN

0%

LANDED DUTY

CYCLE

RED

0%

BLUE

0%

0/100

50/50

20/80

30/70

6/94

100%

0%

100%

0%

100%

0%

12%

0%

35%

0%

7/93

0%

60%

0%

18/82

70/30

50/50

80/20

13/87

25/75

24/76

100/0

100%

0%

100%

0%

100%

0%

100%

12%

0%

35%

60%

100%

12%

100%

0%

100%

The last factor to account for in estimating the landed duty cycle is any applied image processing. Within the

DLPC6540 controller, the gamma function affects the landed duty cycle.

Gamma is a power function of the form Output_Level = A × Input_Level^Gamma, where A is a scaling factor that is

typically set to 1.

In the DLPC6540 controller, gamma is applied to the incoming image data on a pixel-by-pixel basis. A typical

gamma factor is 2.2, which transforms the incoming data as shown in 图7-2.

100

90

80

Gamma = 2.2

70

60

50

40

30

20

10

0

10

20

30

40

50

60

Input Level (%)

70

80

90 100

D002

图7-2. Example of Gamma = 2.2

From 图 7-2, if the gray scale value of a given input pixel is 40% (before gamma is applied), then gray scale

value will be 13% after gamma is applied. Therefore, it can be seen that since gamma has a direct impact

displayed gray scale level of a pixel, it also has a direct impact on the landed duty cycle of a pixel.

Consideration must also be given to any image processing which occurs before the DLPC6540 controller.

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two

directions, with the primary direction being into a projection or collection optic. Each application is derived

primarily from the optical architecture of the system and the format of the data coming into the DLPC6540

controller. The high tilt pixel in the bottom-illuminated DMD increases brightness performance and enables a

smaller system footprint for thickness constrained applications. Typical applications using the DLP471TP include

mobile smart TV and digital signage.

DMD power-up and power-down sequencing is strictly controlled by the DLPA3005. Refer to 节 9 for power-up

and power-down specifications. To ensure reliable operation, the DLP471TP DMD must always be used with

DLPC6540 controller and a DLPA3005 PMIC/LED driver.

8.2 Typical Application

The DLP471TP DMD combined with DLPC6540 digital controller and a power management device provides full

4K UHD resolution for bright, colorful display applications. See Typical 4K UHD LED Application Diagram , which

shows the system components needed along with the LED configuration of the DLP 0.47”4K UHD chipset. The

components include the DLP471TP DMD, DLPC6540 display controller and the DLPA3005 PMIC and LED

driver.

Fan or

programmable DC supply

DC

Supply

SYSPWR (14.5 V to 20 V)

DC

Reg

L5

L4

L3

VSPI

1.8 V

1.8 V @ 3 A for

DMD and DLPC6540

GPIO (PROJ_ON)

Flash (2)

1.8

Reg

ADDR

DATA

1.1 V @ 3 A

(23) (18)

SYSPWR

1.1

Reg

L2

V_LED

PROJ_ON

L1

Front End

Device

I²C BUSY

DLPA3005

I²C

LED_SEL (2)

POSENSE

Vx1

Vx1:

3840 × 2160

@ 60Hz

EEPROM

I²C

RESETZ

INITZ

3.3 V @ 2 A

2.5 V

LDO 1

LDO 2

DLPC6540

Master

3D L/R

SPI (2)

PWRGOOD

(3)

V_BIAS,V_OFFSET,V_RESET

R_LIMcurrent sense

SPI BUS (Ctrl) (4)

1.15 V

1.21 V

1.8 V

3.3 V

2-Port HSSI

USB Mux

GPIO

DLPC471TP

.47 4K UHD DMD

LS Interface

1.8 V

USB 2.0

TI DLP chipset

Actuator

Driver

4-Position

Actuator

USB Camera

Third party component

图8-1. Typical 4K UHD LED Application Diagram

8.2.1 Design Requirements

Other core components of the display system include an illumination source, an optical engine for the

illumination and projection optics, other electrical and mechanical components, and software. The type of

illumination used and desired brightness will have a major effect on the overall system design and size.

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The display system uses the DLP471TP as the core imaging device and contains a 0.47-inch array of

micromirrors. The DLPC6540 controller is the digital interface between the DMD and the rest of the system,

taking digital input from front end receiver and driving the DMD over a high-speed interface. The DLPA3005

PMIC serves as a voltage regulator for the DMD, controller, and LED illumination functionality.

8.2.2 Detailed Design Procedure

For a complete DLP system, an optical module or light engine is required that contains the DLP471TP DMD,

associated illumination sources, optical elements, and necessary mechanical components.

To ensure reliable operation, the DMD must always be used with DLPC6540 display controller and the

DLPA3005 PMIC and LED driver . Refer to PCB Design Requirements for TI DLP Pico TRP Digital Micromirror

Devices for the DMD board design and manufacturing handling of the DMD sub assemblies.

8.2.3 Application Curves

The typical LED-current-to-luminance relationship when LED illumination is utilized is shown in 图8-2.

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1

2

3

4

5

6

7

LED CURRENT (A)

8

9

10 11 12

D001

图8-2. Luminance vs. Current

8.3 Temperature Sensor Diode

The software application provides functions to configure the TMP411 to read the DLP471TP DMD temperature

sensor diode. Customers can use this data to incorporate additional functionality in the overall system design,

such as adjusting illumination, fan speeds, and so on. All communication between the TMP411 and the

DLPC6540 controller is completed using the I²C interface. The TMP411 connects to the DMD through the pins

outlined in 节5.

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9 Power Supply Recommendations

The following power supplies are all required to operate the DMD:

• V_SS

• V_BIAS

• V_DD

• V_DDA

• V_OFFSET

• V_RESET

DMD power-up and power-down sequencing is strictly controlled by the DLP display controller.

CAUTION

For reliable operation of the DMD, the following power supply sequencing requirements must be

followed. Failure to adhere to any of the prescribed power-up and power-down requirements may

affect device reliability. See the DMD power supply sequencing requirements in 图9-1.

V_BIAS, V_DD, V_DDA, V_OFFSET, and V_RESETpower supplies must be coordinated during power-up and

power-down operations. Failure to meet any of the below requirements will result in a significant

reduction in the DMD reliability and lifetime. Common ground V_SSmust also be connected.

表9-1. Power Supply Sequence Requirements

SYMBOL

t_DELAY

PARAMETER

Delay requirement

DESCRIPTION

MIN

TYP

MAX UNIT

from V_OFFSETpower up to V_BIASpower up

at beginning of power-up sequence delay⁽¹⁾

at end of power-up sequence delay⁽¹⁾

2

ms

V_OFFSET

V_BIAS

Supply voltage level

6

V

(1) See 图9-1, Power-Up Sequence Delay Requirement.

9.1 DMD Power Supply Power-Up Procedure

• During power-up, V_DDand V_DDAmust always start and settle before V_OFFSETplus Delay1 specified in 表9-2,

V_BIAS, and V_RESETvoltages are applied to the DMD.

• During power-up, it is a strict requirement that the voltage difference between V_BIASand V_OFFSETmust be

within the specified limit shown in 节6.4.

• During power-up, there is no requirement for the relative timing of V_RESETwith respect to V_BIAS

.

• Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the

requirements specified in 节6.1, in 节6.4, and in 图9-1.

• During power-up, LVCMOS input pins must not be driven high until after V_DDhave settled at operating

voltages listed in 节6.4.

9.2 DMD Power Supply Power-Down Procedure

• During power-down, V_DDand V_DDAmust be supplied until after V_BIAS, V_RESET, and V_OFFSETare discharged to

within the specified limit of ground. See 表9-2.

• During power-down, it is a strict requirement that the voltage difference between V_BIASand V_OFFSETmust be

within the specified limit shown in 节6.4.

• During power-down, there is no requirement for the relative timing of V_RESETwith respect to V_BIAS

.

• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the

requirements specified in 节6.1, in 节6.4, and in 图9-1.

• During power-down, LVCMOS input pins must be less than specified in 节6.4.

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Note A

...

VDD and VDDA

VSS

Note I

t_DELAY3

Note B

ûV < Specification

VOFFSET

Note D

t_DELAY1

VBIAS

VSS

Note C

ûV < Specification

VRESET

Note E

...

Note G

t_DELAY2

Note H

DMD_EN_ARSTZ

Note F

VSS

Time

A. See 节5 for the Pin Functions Table.

B. To prevent excess current, the supply voltage difference |V_OFFSET–V_BIAS| must be less than the specified limit in 节6.4.

C. To prevent excess current, the supply difference |V_BIAS–V_RESET| must be less than the specified limit in 节6.4.

D. V_BIASshould power up after V_OFFSEThas powered up, per the Delay1 specification in 表9-2.

E. DLP controller software initiates the global V_BIAScommand.

F. After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates

DMD_EN_ARSTZ and disables V_BIAS, V_RESET, and V_OFFSET

.

G. Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware

DMD_EN_ARSTZ will go low.

H. V_DDmust remain high until after V_OFFSET, V_BIAS, V_RESETgo low, per Delay2 specification in 表9-2.

I.

To prevent excess current, the supply voltage delta |V_DDA–V_DD| must be less than specified limit in 节6.4.

图9-1. DMD Power Supply Requirements

表9-2. DMD Power-Supply Requirements

PARAMETER

Delay1⁽¹⁾

DESCRIPTION

MIN

NOM

MAX

UNIT

Delay from V_OFFSETsettled at recommended operating voltage to

V_BIASand V_RESETpower up

1

2

ms

Delay V_DDmust be held high from V_OFFSET, V_BIASand V_RESET

powering down.

Delay2⁽¹⁾

50

us

(1) See 图9-1.

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10 Layout

10.1 Layout Guidelines

The DLP471TP DMD is part of a chipset that is controlled by DLPC6540 display controller in conjunction with the

DLPA3005 PMIC and LED driver. These guidelines are targeted at designing a PCB board with the DLP471TP

DMD. The DMD board is a high-speed multi-layer PCB, with primarily high-speed digital logic including double

data rate 3.2 Gbps and 250 Mbps differential data buses run to the DMD. TI recommends that full or mini power

planes are used for V_OFFSET, V_RESET, and V_BIAS. Solid planes are required for ground (V_SS). The target

impedance for the PCB is 50 Ω ±10% with exceptions listed in 表 10-1. TI recommends a 10 layer stack-up as

described in 表10-2. TI recommends manufacturing the PCB with a high quality FR-4 material.

10.2 Impedance Requirements

TI recommends a target impedance for the PCB of 50 Ω ±10% for all signals. The exceptions are listed in 表

10-1.

表10-1. Special Impedance Requirements

Signal Type

Signal Name

Impedance (ohms)

DMD_HSSI0_N_(0…7),

DMD_HSSI0_P_(0…7),

DMD_HSSI1_N_(0…7),

DMD_HSSI1_P_(0…7),

DMD_HSSI0_CLK_N,

DMD_HSSI0_CLK_P,

DMD_HSSI1_CLK_N,

DMD_HSSI1_CLK_P

100-Ω differential (50-Ω single

DMD High Speed Data Signals

ended)

DMD_LS0_WDATA_N,

DMD_LS0_WDATA_P,

DMD_LS0_CLK_N,

DMD_LS0_CLK_P

DMD Low Speed Interface

Signals

100-Ω differential (50-Ω single

ended)

10.3 Layers

The layer stack-up and copper weight for each layer is shown in 表10-2.

表10-2. Layer Stack-Up

LAYER

NO.

LAYER NAME

COPPER WT. (oz.)

COMMENTS

DMD and escapes. Two data input connectors. Top components including

power generation and two-data input connectors. Low frequency signals

routing. Should have copper fill (GND) plated up to 1 oz.

Side A –DMD, primary

components, power mini-

planes

0.5 oz. (before

plating)

1

2

3

Ground

0.5

Solid ground plane (net GND) reference for signal layers #1, 3

High-speed signal layer. High-speed differential data buses from input

connector to DMD.

Signal (high frequency)

4

5

6

7

Ground

Power

Ground

0.5

Solid ground plane (net GND) reference for signal layers #3, #5

Primary split power planes for 1.8 V, 10 V, –14 V, 18 V

Solid ground plane (net GND) reference for signal layer #8

High-speed signal layer. High-speed differential data buses from input

connector to DMD

8

9

Signal (high frequency)

Ground

0.5

Solid ground plane (net GND) reference for signal layers #8, 10

Side B –secondary

components, power mini-

planes

0.5 oz. (before

plating)

Discrete components if necessary. Low-frequency signals routing. Should

have copper fill plated up to 1 oz.

10

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10.4 Trace Width, Spacing

Unless otherwise specified, TI recommends that all signals follow the 0.005”/0.015” (Trace-Width/Spacing)

design rule. Actual trace widths and clearances should be determined and calculated based on an analysis of

impedance and stack-up requirements.

The width of all voltage signals shall be maximized as space permits. In particular, the following width and

spacing requirements shall be observed for the specific signals listed in 表10-3.

表10-3. Special Trace Widths, Spacing Requirements

MINIMUM TRACE

WIDTH (MIL)

SIGNAL NAME

MINIMUM TRACE SPACING (MIL)

LAYOUT REQUIREMENT

GND

MAXIMIZE

5

Maximize trace width to connecting pin as a minimum.

Create mini planes on layers 1 and 10 as needed. Connect

to devices on layers 1 and 10 as necessary with multiple

vias.

P1P8V

100

15

Create mini planes on layers 1 and 10 as needed. Connect

to devices on layers 1 and 10 as necessary.

V_OFFSET

V_RESET

V_BIAS

40

15

Create mini planes on layers 1 and 10 as needed. Connect

to devices on layers 1 and 10 as necessary.

Create mini planes on layers 1 and 10 as needed. Connect

to devices on layers 1 and 10 as necessary.

10.5 Power

TI strongly discourages signal routing on power planes or on planes adjacent to power planes. If signals must be

routed on layers adjacent to power planes, they must not cross splits in power planes to prevent EMI and

preserve signal integrity.

Have all internal digital ground (GND) planes connected together in as many places as possible. If possible, all

internal ground planes should be connected together with a minimum distance between connections of 0.5”.

Extra vias may not be required if there are sufficient ground vias due to normal ground connections of devices.

The power and ground pins of each component should be connected to the power and ground planes with at

least one via for each pin. Trace lengths for component power and ground pins should be minimized (ideally,

less than 0.100”).

Ground plane slots are strongly discouraged.

English Data Sheet: DLPS173

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10.6 Trace Length Matching Recommendations

Recommended signal trace length matching requirements can be found in 表 10-4 and 表 10-5. When length

matching traces, the longer signals should be routed in a serpentine fashion, keeping the number of turns to a

minimum and the turn angles no sharper than 45 degrees as opposed to running long traces over large areas of

the PCB.

Signals in 表 10-4 should be routed for data rate operation at up to 3.2 Gbps. Layer changes for these signals

should be minimized, the number of vias should be minimized. Avoid sharp turns and layer switching while

keeping lengths to a minimum. When layer changes are necessary, GND vias should be placed around the

signal vias to provide a signal return path. The distance from one pair of differential signals to another shall be at

least 2 times the distance within the pair.

表10-4. HSSI High Speed DMD Data Signals

SIGNAL NAME

DMD_HSSI0_N(0...7),

REFERENCE SIGNAL

Routing Spec

Unit

DMD_HSSI0_CLK_N,

DMD_HSSI_CLK_P

+/- 0.25

inch

DMD_HSSI0_P(0...7)

DMD_HSSI1_N(0...7),

DMD_HSSI1_P(0...7)

DMD_HSSI0_CLK_N,

DMD_HSSI_CLK_P

+/- 0.25

inch

DMD_HSSI0_CLK_P

Intra-pair P

DMD_HSSI1_CLK_P

Intra-pair N

+/- 0.05

+/- 0.01

inch

表10-5. Other Timing Critical Signals

SIGNAL NAME

Constraints

Routing Layers

LS_CLK_P, LS_CLK_N

LS_WDATA_P,

LS_WDATA_N

Intra-pair (P to N)

Matched to 0.01 inches

Signal-to-signal

Layers 3, 8

LS_RDATA_A

Matched to +/- 0.25 inches

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11 Device and Documentation Support

11.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.2 Device Support

11.2.1 Device Nomenclature

DLP471TP FQQ

Package

Device Descriptor

图11-1. Part Number Description

11.2.2 Device Markings

The device marking includes both human-readable information and a 2-dimensional matrix code. The human-

readable information is described in 图 11-2 and includes the legible character string GHJJJJK DLP471TPFQQ.

GHJJJJK is the lot trace code and DLP471TPFQQ is the device marking.

Example: GHJJJJK DLP471TPFQQ

Two-Dimensional Matrix Code

(Part Number and Lot Trace Code)

DMD Part Number

Lot Trace Code

图11-2. DMD Marking Locations

English Data Sheet: DLPS173

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11.3 Documentation Support

11.3.1 Related Documentation

The following documents contain additional information related to the chipset components used with the DMD.

• DLPC6540 Display Controller Data Sheet

• DLPA3005 PMIC/LED Driver Data Sheet

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

DLP^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

English Data Sheet: DLPS173

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DLP471TP
厂家：	TEXAS INSTRUMENTS
描述：	0.47-inch 4K UHD DLP® digital micromirror device (DMD)
文件：	总48页 (文件大小：1895K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLP471TP [TI]

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