DLP300S [TI]

0.3 英寸、360 万像素近紫外 DLP® 数字微镜器件 (DMD);


型号：	DLP300S
厂家：	TEXAS INSTRUMENTS
描述：	0.3 英寸、360 万像素近紫外 DLP® 数字微镜器件 (DMD)
文件：	总40页 (文件大小：1744K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLP300S

ZHCSOH3B – JULY 2021 – REVISED MAY 2022

DLP300S 适用于低成本 TI DLP^®3D 打印机的 0.3 英寸 360 万像素 DMD

1 特性

3 说明

•

0.3 英寸 (7.93mm) 对角线微镜阵列

– 1280 × 720 铝制微米级微镜阵列，采用正交布

局

DLP300S 数字微镜器件 (DMD) 是一款数控微光机电

系统 (MOEMS) 空间照明调制器 (SLM)。当与适当的光

学系统成对使用时，DMD 可显示非常清晰的高质量图

像。该 DMD 是由 DLP300S DMD、DLPC1438 3D 打

印控制器和 DLPA200x PMIC/LED 驱动器所组成的芯

片组的一部分。DLP300S DMD 外形小巧，与控制器

和 PMIC/LED 驱动器共同组成完整的系统解决方案，

从而实现快速、高分辨率的可靠 DLP 3D 打印机。

– 360 万像素，树脂上 2560 x 1440 像素

– 5.4 微米微镜间距

– ±17° 微镜倾斜度（相对于平坦表面）

– 采用侧面照明，实现最优的效率和光学引擎尺寸

– 偏振无关型铝微镜表面

8 位 SubLVDS 输入数据总线

专用 DLPC1438 3D 打印控制器和 DLPA200x

PMIC/LED 驱动器，确保可靠运行

•

TI DLP® 光控制技术入门页，了解如何开始使用

DLP300S。

ti.com 上的 DLP 先进光控制资源可加快上市速度，这

些资源包括参考设计、光学模块制造商和 DLP 设计网

络合作伙伴。

2 应用

•

TI DLP® 3D 打印机

器件信息⁽¹⁾

– 增材制造

– 光聚合

器件型号

DLP300S

封装

封装尺寸（标称值）

– 掩模立体光刻（mSLA 3D 打印机）

曝光：可编程空间和时间曝光

FQK (57)

18.20mm × 7.00mm

•

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

D_P(0)

DLPC1438

Display

D_N(0)

Controller

VOFFSET

DLPA2000

D_P(1)

D_N(1)

DLPA2005

VBIAS

Power

Management

600 MHz

SubLVDS

DDR

D_P(6)

D_N(6)

VRESET

DLP300S DMD

Interface

Digital

Micromirror

Device

D_P(7)

D_N(7)

VDDI

VDD

DCLK_P

DCLK_N

LS_WDATA

LS_CLK

120 MHz

SDR

Interface

LS_RDATA

VSS

DMD_DEN_ARSTZ

(System signal routing omitted for clarity)

简化版应用

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS214

DLP300S

ZHCSOH3B – JULY 2021 – REVISED MAY 2022

www.ti.com.cn

Table of Contents

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings........................................ 6

6.2 Storage Conditions..................................................... 7

6.3 ESD Ratings............................................................... 7

6.4 Recommended Operating Conditions.........................7

6.5 Thermal Information....................................................9

6.6 Electrical Characteristics.............................................9

6.7 Timing Requirements................................................10

6.8 Switching Characteristics..........................................15

6.9 System Mounting Interface Loads............................ 15

6.10 Micromirror Array Physical Characteristics.............16

6.11 Micromirror Array Optical Characteristics............... 17

6.12 Window Characteristics.......................................... 19

6.13 Chipset Component Usage Specification............... 19

6.14 Software Requirements.......................................... 19

7 Detailed Description......................................................20

7.1 Overview...................................................................20

7.2 Functional Block Diagram.........................................21

7.3 Feature Description...................................................22

7.4 Device Functional Modes..........................................22

7.5 Optical Interface and System Image Quality

Considerations............................................................ 22

7.6 Micromirror Array Temperature Calculation.............. 23

7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 24

8 Application and Implementation..................................26

8.1 Application Information............................................. 26

8.2 Typical Application.................................................... 26

9 Power Supply Recommendations................................30

9.1 DMD Power Supply Power-Up Procedure................30

9.2 DMD Power Supply Power-Down Procedure........... 30

9.3 Power Supply Sequencing Requirements................ 31

10 Layout...........................................................................33

10.1 Layout Guidelines................................................... 33

10.2 Layout Example...................................................... 33

11 Device and Documentation Support..........................34

11.1 Device Support........................................................34

11.2 接收文档更新通知................................................... 34

11.3 Related Links.......................................................... 34

11.4 支持资源..................................................................35

11.5 Trademarks............................................................. 35

11.6 Electrostatic Discharge Caution..............................35

11.7 术语表..................................................................... 35

12 Mechanical, Packaging, and Orderable

Information.................................................................... 35

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (August 2021) to Revision B (May 2022)

Page

•

Updated Absolute Maximum Ratings disclosure to the latest TI standard......................................................... 6

Updated Micromirror Array Optical Characteristics ......................................................................................... 17

Added Third-Party Products Disclaimer ...........................................................................................................34

Changes from Revision (July 2021) to Revision A (August 2021)

Page

将器件状态从预告信息更改为量产数据 .............................................................................................................1

Updated Functional Block Diagram to show all high-speed data pairs.............................................................21

•

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5 Pin Configuration and Functions

图 5-1. FQK Package 57-Pin LGA (Bottom View)

表 5-1. Pin Functions – Connector Pins⁽¹⁾

NAME

PACKAGE NET

LENGTH⁽²⁾(mm)

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NO.

DATA INPUTS

D_N(0)

SubLVDS

Double

Data, Negative

10.54

13.14

14.24

14.35

5.89

D_P(0)

Data, Positive

Data, Negative

Data, Positive

Data, Negative

Data, Positive

Data, Negative

Data, Positive

Data, Negative

Data, Positive

Data, Negative

Data, Positive

Data, Negative

Data, Positive

Data, Negative

Data, Positive

Clock, Negative

Clock, Positive

D_N(1)

D10

D11

C11

B11

D12

D13

D_P(1)

D_N(2)

D_P(2)

D_N(3)

D_P(3)

D_N(4)

D_P(4)

5.89

D_N(5)

5.45

D_P(5)

5.45

D_N(6)

8.59

D_P(6)

8.59

D_N(7)

7.69

D_P(7)

7.69

DCLK_N

DCLK_P

CONTROL INPUTS

LS_WDATA

LS_CLK

8.10

C12

C13

LPSDR⁽¹⁾

LPSDR

Single

Write data for low speed interface.

Clock for low-speed interface

7.16

7.89

Asynchronous reset DMD signal. A low

signal places the DMD in reset. A high

signal releases the DMD from reset

and places it in active mode.

DMD_DEN_ARSTZ C14

LPSDR

LS_RDATA

POWER ⁽³⁾

VBIAS

C15

Single

Read data for low-speed interface

Power

Supply voltage for positive bias level at

micromirrors

VBIAS

C18

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表 5-1. Pin Functions – Connector Pins⁽¹⁾(continued)

NAME

VOFFSET

PACKAGE NET

LENGTH⁽²⁾(mm)

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NO.

Power

Supply voltage for HVCMOS core

logic. Supply voltage for stepped

high level at micromirror address

electrodes.

Supply voltage for offset level at

micromirrors.

VOFFSET

D17

Power

VRESET

VDD

VDDI

VSS

B18

Power

Ground

Supply voltage for negative reset level

at micromirrors.

B10

B19

Supply voltage for LVCMOS core logic.

Supply voltage for LPSDR inputs.

Supply voltage for normal high level at

micromirror address electrodes.

C10

C19

D18

D19

Supply voltage for SubLVDS receivers.

VSS

B12

B13

B14

B15

B16

B17

VSS

Common return.

Ground for all power.

VSS

C16

C17

D14

D15

D16

VSS

(1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC

Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.

(2) Net trace lengths inside the package:

Relative dielectric constant for the FQK ceramic package is 9.8.

Propagation speed = 11.8 / sqrt (9.8) = 3.769 inches/ns.

Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.

(3) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.

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表 5-2. Pin Functions – Test Pads

NUMBER

A13

SYSTEM BOARD

Do not connect

A14

A15

A16

A17

A18

E13

E14

E15

E16

E17

E18

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6 Specifications

6.1 Absolute Maximum Ratings

See ⁽¹⁾

MIN

–0.5

MAX

2.3

UNIT

Supply voltage for LVCMOS core logic⁽²⁾

Supply voltage for LPSDR low speed interface

VDD

VDDI

Supply voltage for SubLVDS receivers⁽²⁾

Supply voltage for HVCMOS and micromirror

electrode^{(2) (3)}

VOFFSET

Supply voltage for micromirror electrode⁽²⁾

Supply voltage delta (absolute value)⁽⁴⁾

Supply voltage delta (absolute value)⁽⁵⁾

Supply voltage delta (absolute value)⁽⁶⁾

–0.5

–15

0.5

0.3

Supply voltage

VBIAS

VRESET

| VDDI–VDD |

| VBIAS–VOFFSET |

| VBIAS–VRESET |

Input voltage for other inputs LPSDR⁽²⁾

–0.5

VDD + 0.5

Input voltage

Input pins

Input voltage for other inputs SubLVDS^{(2) (7)}

VDDI + 0.5

| VID |

IID

SubLVDS input differential voltage (absolute value)⁽⁷⁾

810

MHz

°C

SubLVDS input differential current

ƒ_clock

Clock frequency for low speed interface LS_CLK

Clock frequency for high speed interface DCLK

Temperature – operational ⁽⁸⁾

130

560

Clock

frequency

–20

–40

T_ARRAYand T_WINDOW

Temperature – non-operational⁽⁸⁾

°C

Dew Point Temperature - operating and non-operating

(non-condensing)

Environmental

T_DP

|T_DELTA

°C

Absolute Temperature delta between any point on the

window edge and the ceramic test point TP1⁽⁹⁾

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and

this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:

VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET.

(3) VOFFSET supply transients must fall within specified voltages.

(4) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.

(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current

draw.

(6) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current

draw.

(7) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential

inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(8) The highest temperature of the active array (as calculated in 节 7.6) or of any point along the Window Edge as defined in 图 7-1. The

locations of thermal test points TP2 and TP3 in 图 7-1 are intended to measure the highest window edge temperature. If a particular

application causes another point on the window edge to be at a higher temperature, that point should be used.

(9) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in

图 7-1. The window test points TP2 and TP3 shown in 图 7-1 are intended to result in the worst case delta. If a particular application

causes another point on the window edge to result in a larger delta temperature, that point should be used.

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6.2 Storage Conditions

Applicable for the DMD as a component or non-operational in a system

MIN

MAX

UNIT

°C

T_DMD

DMD storage temperature

–40

T_DP-AVG

T_DP-ELR

CT_ELR

Average dew point temperature, (non-condensing)⁽¹⁾

Elevated dew point temperature range, (non-condensing)⁽²⁾

Cumulative time in elevated dew point temperature range

°C

Months

(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total

cumulative time of CT_ELR

6.3 ESD Ratings

VALUE

UNIT

V_(ESD)Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

NOM

MAX

UNIT

SUPPLY VOLTAGE RANGE⁽³⁾

Supply voltage for LVCMOS core logic

VDD

1.65

1.8

1.95

Supply voltage for LPSDR low-speed interface

Supply voltage for SubLVDS receivers

Supply voltage for HVCMOS and micromirror electrode⁽⁴⁾

Supply voltage for mirror electrode

VDDI

1.65

9.5

1.8

1.95

10.5

18.5

–13.5

0.3

VOFFSET

VBIAS

17.5

–14.5

VRESET

Supply voltage for micromirror electrode

Supply voltage delta (absolute value)⁽⁵⁾

Supply voltage delta (absolute value)⁽⁶⁾

Supply voltage delta (absolute value)⁽⁷⁾

–14

|VDDI–VDD|

|VBIAS–VOFFSET|

|VBIAS–VRESET|

CLOCK FREQUENCY

ƒ_clock

10.5

Clock frequency for low speed interface LS_CLK⁽⁸⁾

Clock frequency for high speed interface DCLK⁽⁹⁾

Duty cycle distortion DCLK

108

300

120

540

MHz

ƒ_clock

44%

56%

SUBLVDS INTERFACE⁽⁹⁾

| V_ID

V_CM

SubLVDS input differential voltage (absolute value) 图 6-9, 图 6-10

Common mode voltage 图 6-9, 图 6-10

SubLVDS voltage 图 6-9, 图 6-10

150

700

575

250

900

350

1100

1225

110

Ω

V_SUBLVDS

Z_LINE

Line differential impedance (PWB/trace)

Internal differential termination resistance 图 6-11

100-Ω differential PCB trace

100

Z_IN

120

Ω

6.35

152.4

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6.4 Recommended Operating Conditions (continued)

Over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

NOM

MAX

UNIT

ENVIRONMENTAL

Array Temperature – long-term operational^{(10) (11) (12)}

–20

–10

T_ARRAY

Array Temperature - short-term operational, 25 hr max^{(11) (13)}

Array Temperature - short-term operational, 500 hr max^{(11) (13)}

°C

Absolute Temperature difference between any point on the window

edge and the ceramic test point TP1 ⁽¹⁴⁾

|T_DELTA

T_WINDOW

T_DP-AVG

Window temperature – operational⁽¹⁵⁾

°C

Average dew point temperature (non-condensing)⁽¹⁶⁾

Elevated dew point temperature range (non-condensing)⁽¹⁷⁾

Cumulative time in elevated dew point temperature range

Illumination overfill in critical areal^{(19) (20)}

T_DP-ELR

°C

CT_ELR

Months

W/cm²

mW/cm²

Q_AP-ILL

ILL_UV

Illumination wavelengths < 380 nm⁽¹⁰⁾

ILL_{380 - 390 nm}

ILL_{390 - 400 nm}

ILL_{400 - 550 nm}

ILL_{> 550 nm}

ILL_θ

Illumination wavelengths between 380 nm and 390 nm

Illumination wavelengths between 390 nm and 400 nm

Illumination wavelengths between 400 nm and 550 nm

Illumination wavelengths > 550 nm

55 mW/cm²

450 mW/cm²

W/cm²

10 mW/cm²

55 deg

Illumination marginal ray angle⁽¹⁸⁾

(1) 节 6.4 is applicable after the DMD is installed in the final product.

(2) The functional performance of the device specified in this datasheet is achieved when operating the device within the limits defined by

节 6.4. No level of performance is implied when operating the device above or below the 节 6.4 limits.

(3) All voltage values are with respect to the ground pins (VSS).

(4) VOFFSET supply transients must fall within specified maximum voltages.

(5) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.

(6) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.

(7) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit.

(8) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.

(9) Refer to the SubLVDS timing requirements in 节 6.7.

(10) Simultaneous exposure of the DMD to the maximum limits in 节 6.4 for temperature and UV illumination will reduce device lifetime.

(11) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1

(TP1) shown in 图 7-1 and the Package Thermal Resistance using 节 7.6.

(12) Long-term is defined as the usable life of the device.

(13) Short-term is the total cumulative time over the useful life of the device.

(14) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge shown in 图

7-1. The window test points TP2 and TP3 shown in 图 7-1 are intended to result in the worst case delta temperature. If a particular

application causes another point on the window edge to result in a larger delta temperature, that point should be used.

(15) Window temperature is the highest temperature on the window edge shown in 图 7-1. The locations of thermal test points TP2 and

TP3 in 图 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the

window edge to result in a higher temperature, that point should be used.

(16) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(17) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total

cumulative time of CT_ELR

(18) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors

(POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily

been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not

been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM)

will contribute to thermal limitations described in this document, and may negatively affect lifetime.

(19) The active area of the device is surrounded by an aperture on the inside of the DMD window surface that masks structures of the DMD

device assembly from normal view. The window aperture is sized to anticipate several optical operating conditions. Overfill light directly

illuminating the window aperture can create adverse imaging effects, and additional device heating leading to reduced device lifetime.

Direct incident illumination should be prevented from striking the DMD window aperture.

(20) Applies to the region in red in 图 6-1, at the inside plane of the glass window where the physical aperture is located.

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4X 0.52 mm critical area on aperture

Array

Window

图 6-1. Illumination Overfill Diagram - Critical Area

6.5 Thermal Information

DLP300S

FQK (LGA)

57 PINS

5.4

THERMAL METRIC⁽¹⁾

UNIT

Thermal resistance

Active area to test point 1 (TP1)⁽¹⁾

°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in the 节 6.4. The total heat load on the DMD is largely driven by

the incident light absorbed by the active area although other contributions include light energy absorbed by the window aperture and

electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window

clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)⁽¹⁰⁾

PARAMETER

TEST CONDITIONS⁽²⁾

MIN

TYP

MAX UNIT

CURRENT

VDD = 1.95 V

60.5

I_DD

Supply current: VDD^{(3) (5)}

Supply current: VDDI^{(3) (5)}

Supply current: VOFFSET^{(4) (6)}

Supply current: VBIAS^{(4) (6)}

Supply current: VRESET⁽⁶⁾

VDD = 1.8 V

11.3

1.5

VDDI = 1.95 V

VDD = 1.8 V

16.5

I_DDI

VOFFSET = 10.5 V

VOFFSET = 10 V

VBIAS = 18.5 V

VBIAS = 18 V

2.2

I_OFFSET

0.6

I_BIAS

0.3

VRESET = –14.5 V

VRESET = –14 V

2.4

I_RESET

1.7

POWER⁽¹⁾

P_DD

VDD = 1.95 V

118

Supply power dissipation: VDD^{(3) (5)}

Supply power dissipation: VDDI^{(3) (5)}

VDD = 1.8 V

VDDI = 1.95 V

VDD = 1.8 V

P_DDI

VOFFSET = 10.5 V

VOFFSET = 10 V

VBIAS = 18.5 V

VBIAS = 18 V

Supply power dissipation:

VOFFSET^{(4) (6)}

P_OFFSET

P_BIAS

Supply power dissipation: VBIAS^{(4) (6)}

VRESET = –14.5 V

VRESET = –14 V

P_RESET

P_TOTAL

Supply power dissipation: VRESET⁽⁶⁾

Supply power dissipation: Total

160

219

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MAX UNIT

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6.6 Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)⁽¹⁰⁾

PARAMETER

TEST CONDITIONS⁽²⁾

MIN

TYP

LPSDR INPUT⁽⁷⁾

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

∆V_T

DC input high voltage⁽⁹⁾

DC input low voltage⁽⁹⁾

AC input high voltage⁽⁹⁾

AC input low voltage⁽⁹⁾

0.7 × VDD

–0.3

VDD + 0.3

0.3 × VDD

VDD + 0.3

0.2 × VDD

0.4 × VDD

0.8 × VDD

–0.3

Hysteresis ( V_T+– V_T–

)

图 6-12

0.1 × VDD

–100

I_IL

Low–level input current

VDD = 1.95 V; V_I= 0 V

I_IH

High–level input current

VDD = 1.95 V; V_I= 1.95 V

100

LPSDR OUTPUT⁽⁸⁾

V_OH

V_OL

DC output high voltage

DC output low voltage

I_OH= –2 mA

I_OL= 2 mA

0.8 × VDD

0.2 × VDD

CAPACITANCE

Input capacitance LPSDR

ƒ = 1 MHz

C_IN

Input capacitance SubLVDS

Output capacitance

C_OUT

(1) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.

(2) All voltage values are with respect to the ground pins (VSS).

(3) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.

(4) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.

(5) Supply power dissipation based on non–compressed commands and data.

(6) Supply power dissipation based on 3 global resets in 200 µs.

(7) LPSDR specifications are for pins LS_CLK and LS_WDATA.

(8) LPSDR specification is for pin LS_RDATA.

(9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC

Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.

(10) Device electrical characteristics are over 节 6.4 unless otherwise noted.

6.7 Timing Requirements

Device electrical characteristics are over 节 6.4 unless otherwise noted.

MIN

NOM

MAX

UNIT

LPSDR

t_r

Rise slew rate⁽¹⁾

(30% to 80%) × VDD, 图 6-3

(70% to 20%) × VDD, 图 6-3

(20% to 80%) × VDD, 图 6-4

(80% to 20%) × VDD, 图 6-4

图 6-2

V/ns

t_ƒ

Fall slew rate⁽¹⁾

t_r

Rise slew rate⁽²⁾

0.25

7.7

3.1

t_ƒ

Fall slew rate⁽²⁾

t_c

Cycle time LS_CLK,

Pulse duration LS_CLK high

Pulse duration LS_CLK low

8.3

t_W(H)

t_W(L)

50% to 50% reference points, 图 6-2

LS_WDATA valid before LS_CLK ↑, 图

6-2

t_su

Setup time

1.5

LS_WDATA valid after LS_CLK ↑, 图

t _h

Hold time

1.5

6-2

t_WINDOW

t_DERATING

Window time^{(1) (4)}

Window time derating^{(1) (4)}

Setup time + Hold time, 图 6-2

For each 0.25 V/ns reduction in slew

rate below 1 V/ns, 图 6-6

0.35

SubLVDS

t_r

Rise slew rate

Fall slew rate

20% to 80% reference points, 图 6-5

80% to 20% reference points, 图 6-5

0.7

V/ns

t_ƒ

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6.7 Timing Requirements (continued)

Device electrical characteristics are over 节 6.4 unless otherwise noted.

MIN

1.79

0.79

NOM

MAX

UNIT

t_c

Cycle time DCLK,

图 6-7

1.85

t_W(H)

t_W(L)

Pulse duration DCLK high

Pulse duration DCLK low

50% to 50% reference points, 图 6-7

D(0:3) valid before

DCLK ↑ or DCLK ↓, 图 6-7

t_su

Setup time

D(0:3) valid after

DCLK ↑ or DCLK ↓, 图 6-7

t _h

Hold time

t_WINDOW

Window time

Setup time + Hold time, 图 6-7, 图 6-8

0.3

t_LVDS-

Power-up receiver⁽³⁾

2000

ENABLE+REFGEN

(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in 图 6-3.

(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in 图 6-4.

(3) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.

(4) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.

w(L)

w(H)

50%

LS_CLK

SU|

50%

LS_WDATA

WINDOW|

Low-speed interface is LPSDR and adheres to the 节 6.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low

Power Double Data Rate (LPDDR) JESD209B.

图 6-2. LPSDR Switching Parameters

LS_CLK and LS_WDATA

100

IH(AC)

IH(DC)

IL(DC)

IL(AC)

Time

图 6-3. LPSDR Input Slew Rate

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DMD_DEN_ARSTZ

100

IL(AC)

Time

图 6-4. LPSDR Input Slew Rate

VDCLK_P and VDCLK_N

VD_P(0:3) and VD_N(0:3)

100

Time

图 6-5. SubLVDS Input Rise and Fall Slew Rate

V_{IH MIN}

LS_CLK Midpoint

V_{IL MAX}

t_SU

t_H

V_{IH MIN}

LS_WDATA Midpoint

V_{IL MAX}

t_WINDOW

V_{IH MIN}

Midpoint

LS_CLK

V_{IL MAX}

t_DERATING

t_H

t_SU

V_{IH MIN}

Midpoint

V_{IL MAX}

LS_WDATA

t_WINDOW

图 6-6. Window Time Derating Concept

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w(H)

w(L)

DCLK_P

50%

DCLK_N

SU|

D_P(0:7)

50%

D_N(0:7)

WINDOW|

图 6-7. SubLVDS Switching Parameters

(1)

WINDOW

DCLK_P

50%

DCLK_N

¼ t

D_P(0:7)

50%

D_N(0:7)

(1) High-speed training scan window

(2) Refer to 节 7.3.3 for details

图 6-8. High-Speed Training Scan Window

(V_IP+ V_IN

)

V_CM

DCLP_P, D_P(0:7)

DCLP_N, D_N(0:7)

V_ID

SubLVDS

Receiver

V_CM

V_IP

V_IN

图 6-9. SubLVDS Voltage Parameters

1.255 V

LVDS(max)

LVDS(min)

0.575 V

图 6-10. SubLVDS Waveform Parameters

V_SubLVDS(max)= V_CM(max)+ ½ × |V_ID(max)

V_SubLVDS(min)= V_CM(min)– ½ × |V_ID(max)

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DCLP_P, D_P(0:7)

DCLP_N, D_N(0:7)

ESD

Internal

Termination

SubLVDS

Receiver

图 6-11. SubLVDS Equivalent Input Circuit

LS_CLK and LS_WDATA

T+

Tœ

Time

图 6-12. LPSDR Input Hysteresis

LS_CLK

LS_WDATA

Stop

Start

t_PD

LS_RDATA

Acknowledge

图 6-13. LPSDR Read Out

Timing specification reference point

Device pin

output under test

C_L

Tester channel

See 节 7.3.4 for more information.

图 6-14. Test Load Circuit for Output Propagation Measurement

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6.8 Switching Characteristics

Over operating free-air temperature range (unless otherwise noted).⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

11.1

11.3

UNIT

C_L= 5 pF

Output propagation, Clock to Q, rising

edge of LS_CLK input to LS_RDATA

output. 图 6-13

t_PD

C_L= 10 pF

C_L= 85 pF

Slew rate, LS_RDATA

0.5

V/ns

Output duty cycle distortion, LS_RDATA

40%

60%

(1) Device electrical characteristics are over 节 6.4 unless otherwise noted.

6.9 System Mounting Interface Loads

PARAMETER

MIN

NOM

MAX

125

UNIT

Maximum system mounting interface load to Electrical Interface Area (see 图 6-15)

be applied to the:

Clamping and Thermal Interface Area (see 图

6-15)

Electrical Interface Area

125 N Maximum

Clamping and Thermal Interface Area # 1

33.5 N Maximum

Clamping and Thermal Interface Area # 2

33.5 N Maximum

图 6-15. System Interface Loads

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6.10 Micromirror Array Physical Characteristics

PARAMETER

VALUE

1280

720

UNIT

micromirrors

µm

Number of active columns

Number of active rows

Micromirror (pixel) pitch

See 图 6-16

See 图 6-17

5.4

Micromirror pitch × number of active

columns; see 图 6-16

Micromirror active array width

Micromirror active array height

Micromirror active border

6.912

3.888

Micromirror pitch × number of active rows;

see 图 6-16

micromirrors/

side

Pond of micromirror (POM)⁽¹⁾

(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.

These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical

bias to tilt toward OFF.

Width .

Mirror 719

Mirror 718

Mirror 717

Mirror 716

Illumination

1280 × 720 mirrors

Height

Mirror 3

Mirror 2

Mirror 1

Mirror 0

图 6-16. Micromirror Array Physical Characteristics

e°

图 6-17. Mirror (Pixel) Pitch

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6.11 Micromirror Array Optical Characteristics

PARAMETER

Micromirror tilt angle

TEST CONDITIONS

MIN

NOM

MAX

UNIT

degree

DMD landed state⁽¹⁾

Micromirror tilt angle tolerance^{(2) (3) (4) (5)}

–1.4

1.4

Landed ON state

180

270

Micromirror tilt direction ^{(6) (7)}

degree

µs

Landed OFF state

Typical performance

Micromirror crossover time⁽⁸⁾

Micromirror switching time⁽⁹⁾

Bright pixel(s) in active area

Gray 10 Screen ⁽¹²⁾

(11)

Bright pixel(s) in the POM ⁽¹³⁾Gray 10 Screen ⁽¹²⁾

Image

Dark pixel(s) in the active

White Screen

micromirrors

performance⁽¹⁰⁾

area ⁽¹⁴⁾

Adjacent pixel(s) ⁽¹⁵⁾

Any Screen

Unstable pixel(s) in active

area ⁽¹⁶⁾

(1) Measured relative to the plane formed by the overall micromirror array.

(2) Additional variation exists between the micromirror array and the package datums.

(3) Represents the landed tilt angle variation relative to the nominal landed tilt angle.

(4) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different

devices.

(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some

system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field

reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result

in colorimetry variations, system efficiency variations, or system contrast variations.

(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of

the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON state

direction. A binary value of 0 results in a micromirror landing in the OFF state direction. See 图 6-18.

(7) Micromirror tilt direction is measured as in a typical polar coordinate system: Measuring counter-clockwise from a 0° reference which is

aligned with the +X Cartesian axis.

(8) The time required for a micromirror to nominally transition from one landed state to the opposite landed state.

(9) The minimum time between successive transitions of a micromirror.

(10) Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions:

Test set degamma shall be linear

Test set brightness and contrast shall be set to nominal

The diagonal size of the projected image shall be a minimum of 20 inches

The projections screen shall be 1X gain

The projected image shall be inspected from a 38 inch minimum viewing distance

The image shall be in focus during all image quality tests

(11) Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels

(12) Gray 10 screen definition: All areas of the screen are colored with the following settings:

Red = 10/255

Green = 10/255

Blue = 10/255

(13) POM definition: Rectangular border of off-state mirrors surrounding the active area

(14) Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels

(15) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster

(16) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable

pixel appears to be flickering asynchronously with the image

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(1279, 719)

Incident

illumination

light path

On-state

landed edge

Tilted axis of

pixel rotation

Off-state

landed edge

(0, 0)

Off-state

light path

Bond pad 1

图 6-18. Landed Pixel Orientation and Tilt

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6.12 Window Characteristics

PARAMETER⁽³⁾

MIN

TYP

MAX

UNIT

Window material

Corning Eagle

Window aperture⁽¹⁾

Illumination overfill⁽²⁾

See ⁽¹⁾

See ⁽²⁾

Window transmittance, single-pass

through both surfaces and glass ⁽⁴⁾

Minimum within the wavelength range 390

nm to 450 nm, 0-30° AOI.

93%

98%

75%

99%

90%

Average within the wavelength range 390 nm

to 450 nm, 0-30° AOI.

Minimum within the wavelength range 450

nm to 550 nm. 0-30° AOI.

(1) See the package mechanical characteristics for details regarding the size and location of the window aperture.

(2) The active area of the device is surrounded by an aperture on the inside of the DMD window surface that masks structures of the DMD

device assembly from normal view. The window aperture is sized to anticipate several optical operating conditions. Overfill light directly

illuminating the window aperture can create adverse imaging effects, and additional device heating leading to reduced device lifetime.

Direct incident illumination should be prevented from striking the DMD window aperture.

(3) See 节 7.5 for more information.

(4) See the TI application report DLPA031, Wavelength Transmittance Considerations for DLP DMD Window.

SPACER

6.13 Chipset Component Usage Specification

The DLP300S is a component of one or more TI DLP^®chipsets. Reliable function and operation of the DLP300S

requires that it be used in conjunction with the other components of the applicable DLP chipset, including

those components that contain or implement TI DMD control technology. TI DMD control technology is the TI

technology and devices for operating or controlling a DLP DMD.

备注

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system

operating conditions exceeding limits described previously.

6.14 Software Requirements

CAUTION

The DMD has mandatory software requirements. Refer to Software Requirements for TI DLP^®Pico^®

TRP Digital Micromirror Devices application report for additional information. Failure to use the

specified software results in failure at power up.

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7 Detailed Description

7.1 Overview

The DLP300S DMD is a 0.3 inch diagonal spatial light modulator of aluminum micromirrors. Pixel array size

is 1280 columns by 720 rows in a square grid pixel arrangement. The fast switching speed of the DMD

micromirrors combined with advanced DLP image processing algorithms enable each micromirror to display 4

distinct pixels on the screen during every frame, resulting in a full 3.6MP image being displayed. The electrical

interface is Sub Low Voltage Differential Signaling (SubLVDS) data.

This DMD is part of the chipset that includes the DLP300S DMD, DLPC1438 display and light controller and

DLPA200x PMIC/LED driver. To ensure reliable operation, this DMD must always be used with DLPC1438

display and light controller and DLPA200x PMIC/LED driver.

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7.2 Functional Block Diagram

High-Speed

Interface

Control

Misc

Column Write

Bit Lines

(0,0)

Word

Lines

Voltages

Voltage

Generators

SRAM

Row

(719,1279)

Control

Column Read

Control

Low-Speed

Interface

A. Details omitted for clarity

B. Orientation is not representative of optical system

C. Scale is not representative of layout

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7.3 Feature Description

7.3.1 Power Interface

The power management IC, DLPA200x, contains 3 regulated DC supplies for the DMD reset circuitry: VBIAS,

VRESET and VOFFSET, as well as the 2 regulated DC supplies for the DLPC1438 controller.

7.3.2 Low-Speed Interface

The Low Speed Interface handles instructions that configure the DMD and control reset operation. LS_CLK is

the low–speed clock, and LS_WDATA is the low speed data input.

7.3.3 High-Speed Interface

The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed

DDR transfer and compression techniques to save power and time. The high-speed interface is composed of

differential SubLVDS receivers for inputs, with a dedicated clock.

7.3.4 Timing

The data sheet provides timing test results at the device pin. For output timing analysis, the tester pin electronics

and its transmission line effects must be considered. The Test Load Circuit Output Propagation Measurement

shows an equivalent test load circuit for the output under test. Timing reference loads are not intended as

a precise representation of any particular system environment or depiction of the actual load presented by a

production test. TI recommends that system designers use IBIS or other simulation tools to correlate the timing

reference load to a system environment. The load capacitance value stated is intended for characterization and

measurement of AC timing signals only. This load capacitance value does not indicate the maximum load the

device is capable of driving.

7.4 Device Functional Modes

DMD functional modes are controlled by the DLPC1438 controller. See the DLPC1438 controller data sheet or

contact a TI applications engineer.

7.5 Optical Interface and System Image Quality Considerations

备注

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system

operating conditions exceeding limits described previously.

7.5.1 Optical Interface and System Image Quality

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous component and system design parameters.

Optimizing system optical performance and image quality strongly relate to optical system design parameter

trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical

performance is contingent on compliance to the optical system operating conditions described in the following

sections.

7.5.1.1 Numerical Aperture and Stray Light Control

The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area

is typically the same. Ensure this angle does not exceed the nominal device micromirror tilt angle unless

appropriate apertures are added in the illumination or projection pupils to block out flat-state and stray light from

the projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from

any other light path, including undesirable flat–state specular reflections from the DMD window, DMD border

structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture

exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger

than the illumination numerical aperture angle (and vice versa), contrast degradation and objectionable artifacts

in the display border or active area may occur.

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7.5.1.2 Pupil Match

The optical and image quality specifications assume that the exit pupil of the illumination optics is nominally

centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable

artifacts in the display border or active area. These artifacts may require additional system apertures to control,

especially if the numerical aperture of the system exceeds the pixel tilt angle.

7.5.1.3 Illumination Overfill

The active area of the device is surrounded by an aperture on the inside of the DMD window surface that masks

structures of the DMD device assembly from normal view. The window aperture is sized to anticipate several

optical operating conditions. Overfill light directly illuminating the window aperture can create adverse imaging

effects, and additional device heating leading to reduced device lifetime. Direct incident illumination should be

prevented from striking the DMD window aperture.

7.6 Micromirror Array Temperature Calculation

TP3

Illumination

Direction

TP2

Off-state Light

Window Edge

(4 surfaces)

TP2

TP3

TP1

图 7-1. Thermal Test Point Location - FQK Package

Micromirror array temperature cannot be measured directly, therefore it must be computed analytically from

measurement points on the outside of the package, the package thermal resistance, the electrical power, and

the illumination heat load. The relationship between array temperature and the reference ceramic temperature

shown as TP1 in 图 7-1 is provided by the following equations:

T_ARRAY= T_CERAMIC+ (Q_ARRAY× R_{ARRAY-TO-CERAMIC}

)

(1)

(2)

Q_ARRAY= Q_ELECTRICAL+ Q_ILLUMINATION

where

•

T_ARRAY= Computed micromirror array temperature (°C)

T_CERAMIC= Measured ceramic temperature (°C) (TP1 location)

R_{ARRAY-TO-CERAMIC}= Thermal resistance of package specified in 节 6.5 from array to ceramic TP1 (°C/W)

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•

Q_ARRAY= Total DMD power on the array (electrical + absorbed) (W)

Q_ELECTRICAL= Nominal electrical power (W)

Q_INCIDENT= measured total illumination optical power at DMD (W)

Q_ILLUMINATION= (Q_INCIDENT× DMD average thermal absortivity) (W)

DMD average thermal absortivity = 0.40

The electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating

frequencies. A nominal electrical power dissipation to use when calculating array temperature is 0.1 W. The

absorbed power from the illumination source is variable and depends on the operating state of the micromirrors

and the intensity of the light source. The equations shown above are valid for each DMD chip in a system. It

assumes illumination distribution of 83.7% on the active array and 16.3% on the area outside the array.

Q_ELECTRICAL= 0.1 W

(3)

(4)

(5)

(6)

(7)

Q_INCIDENT= 0.9 W (measured)

T_CERAMIC= 35.0 °C (measured)

Q_ARRAY= 0.1 W + (0.9 W x 0.40) = 0.46 W

T_ARRAY= 35.0 °C + (0.46 W x 5.4 °C /W) = 37.5°C

7.7 Micromirror Landed-On/Landed-Off Duty Cycle

7.7.1 Definition of Micromirror Landed-On and Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a

percentage) that an individual micromirror is landed in the ON state versus the amount of time the same

micromirror is landed in the OFF state.

As an example, a landed duty cycle of 75/25 indicates that the referenced pixel is in the ON state 75% of the

time (and in the OFF state 25% of the time), whereas 25/75 indicates that the pixel is in the OFF state 75% of

the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time.

When assessing landed duty cycle, the time spent switching from the current state to the opposite state is

considered negligible and is thus ignored.

Because a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)

nominally add to 100. In practice, image processing algorithms in the DLP chipset can result a total of less that

100.

7.7.2 Landed Duty Cycle and Useful Life of the DMD

Knowing the long-term average landed duty cycle (of the end product or application) is important because

subjecting all (or a portion) of the micromirror array (also called the active array) to an asymmetric landed duty

cycle for a prolonged period of time can reduce the usable life of the DMD.

The symmetry of the landed duty cycle is determined by how close the two numbers (percentages) are to being

equal. For example, a landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0

or 0/100 is perfectly asymmetrical.

7.7.3 Landed Duty Cycle and Operational DMD Temperature

Operational DMD temperature and landed duty cycle interact to affect the usable life of the DMD. This interaction

can be used to reduce the impact that an asymmetrical landed duty cycle has on the useable life of the DMD.

7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application

During a given period of time, the landed duty cycle of a given pixel depends on the image content being

displayed by that pixel. To enhance reliability, when coupled with the DLPC1438 controller, the DLP300S DMD

operates at a maximum 78/22 duty cycle and a minimum of 22/78 duty cycle.

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In the simplest case for example, when the system displays maximum full scale brightness on a given pixel for a

given time period, that pixel operates very close to a 78/22 landed duty cycle during that time period. Likewise,

when the system displays a pixel value of zero, the pixel operates very close to a 22/78 landed duty cycle.

The nominal landed duty cycle is additionally biased from the worst case above toward 50/50 during the time

between print layers. The duty cycle approaches 50/50 when the illuminated print time is the same as the

between layer time.

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8 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of

two directions, with the primary direction being into a projection or collection optic. Each application depends

primarily on the optical architecture of the system and format of the data coming into the DLPC1438 controller.

Applications include:

•

DLP 3D Printer

– Additive manufacturing

– Vat polymerization

– Masked stereolithography (mSLA 3D printer)

Light exposure: programmable spatial and temporal light exposure

•

DMD power-up and power-down sequencing is strictly controlled by the DLPA2000/DLPA2005. Refer to 节 9

for power-up and power-down specifications. For reliable operation, the DLP300S DMD must be used with the

DLPC1438 controller and DLPA2000/DLPA2005 PMIC/LED driver.

8.2 Typical Application

图 8-1 and 图 8-2 show typical DLP 3D printer system block diagrams using the DLP300S DMD, DLPC1438

controller, and DLPA200x PMIC/LED driver.

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1.1 V

1.1 Reg

SYSPWR

Supplies

1.8 V

1.8 V external

DLPA200x

LED

1.8 V

VSPI

PROJ_ON

LED_SEL (2)

PROJ_ON

SPI (4)

INTZ

GPIO_8

SPI1

RESETZ

PARKZ

I C

LIM

Thermistor

Video

Front End

HOST_IRQ

FPGA

CMP_OUT

VDDLP12

VDD

I C

SPI_RDY

SPI (4)

Parallel (12)

FPGA_READY

1.1 V

Illumination

optics

DLPC1438

System

Controller

ACT_SYNC

RC_

CHARGE

SPI0

GPIO_10

, V

BIAS OFFSET

Flash

VCC_18

1.8 V

RESET

DMD

VCC_INTF

VCC_FLSH

CTRL

Sub-LVDS DATA

Frame

Memory

1.8 V

SPI (4)

Flash

TI DLP Chipset

Actuator

Driver

Actuator

Non-TI Device

Optional Non-TI Device

图 8-1. With FPGA

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1.1 V

1.1 Reg

SYSPWR

Supplies

1.8 V

1.8 V external

DLPA200x

LED

1.8 V

VSPI

PROJ_ON

LED_SEL (2)

PROJ_ON

SPI (4)

INTZ

GPIO_8

SPI1

RESETZ

PARKZ

I C

LIM

Thermistor

HOST_IRQ

CMP_OUT

Front End

Processor

VDDLP12

VDD

DLPC1438

Parallel (12)

1.1 V

Illumination

optics

RC_

CHARGE

SPI0

GPIO_10

, V

BIAS OFFSET

VCC_18

1.8 V

RESET

DMD

VCC_INTF

VCC_FLSH

CTRL

Sub-LVDS DATA

1.8 V

SPI (4)

Flash

TI DLP Chipset

Non-TI Device

图 8-2. Without FPGA

8.2.1 Design Requirements

A DLP 3D printer can be created using the DLP300S, DLPC1438, and DLPA200x PMIC/LED driver. In addition

to the DLP chipset, other IC components may be needed including a flash device to store the software and

firmware to control the DLPC1438.

A 405nm LED typically supplies the illumination for the DMD. In addition to LEDs, other light sources are

supported.

8.2.2 Detailed Design Procedure

The optical engine, which includes the LED, DMD, and sometimes the electronics is typically supplied by an

optical OEM who specializes in designing optics for DLP projectors.

8.2.3 Application Curve

This device drives current though the LED(s). As the LED current increases, the brightness of the optical engine

increases. This increase is somewhat non-linear, and the curve for typical optical output power changes with

LED currents as shown in 图 8-3.

SPACE

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0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

100

200

300 400

Current (mA)

500

600

700

D001

图 8-3. Optical Output vs LED Current

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9 Power Supply Recommendations

The following power supplies are all required to operate the DMD:

•

V_SS

V_BIAS

V_DD

V_DDI

V_OFFSET

V_RESET

DMD power-up and power-down sequencing is strictly controlled by the DLPAxxxx device.

CAUTION

For reliable operation of the DMD, the following power supply sequencing requirements must be

followed. Failure to adhere to any of the prescribed power-up and power-down requirements may

affect device reliability. See the DMD power supply sequencing requirements in 图 9-1.

V_BIAS, V_DD, V_DDI, V_OFFSET, and V_RESETpower supplies must be coordinated during power-up and

power-down operations. Failure to meet any of the below requirements significantly reduces DMD

reliability and lifetime. Common ground V_SSmust also be connected.

9.1 DMD Power Supply Power-Up Procedure

•

During power-up, V_DDand V_DDImust always start and settle before V_OFFSET, V_BIAS, and V_RESETvoltages are

applied to the DMD.

•

During power-up, it is a strict requirement that the voltage difference between V_BIASand V_OFFSETmust be

within the specified limit shown in 节 6.4. Refer to 表 9-1 for power-up delay requirements.

•

During power-up, there is no requirement for the relative timing of V_RESETwith respect to V_BIASand V_OFFSET

Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the

requirements specified in 节 6.1, in 节 6.4, and in 节 9.3.

•

During power-up, LPSDR input pins must not be driven high until after V_DD/V_DDIhave settled at operating

voltages listed in 节 6.4.

9.2 DMD Power Supply Power-Down Procedure

•

Power-down sequence is the reverse order of the previous power-up sequence. During power-down, V_DDand

V_DDImust be supplied until after V_BIAS, V_RESET, and V_OFFSETare discharged to within 4 V of ground.

During power-down, it is a strict requirement that the voltage difference between V_BIASand V_OFFSETmust be

within the specified limit shown in 节 6.4.

During power-down, there is no requirement for the relative timing of V_RESETwith respect to V_BIASand

V_OFFSET

Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the

requirements specified in 节 6.1, in 节 6.4, and in 节 9.3.

During power-down, LPSDR input pins must be less than V_DD/V_DDIspecified in 节 6.4.

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9.3 Power Supply Sequencing Requirements

DLP Display Controller and

PMIC control start of DMD

operation

DLP Display Controller and PMIC

disable VBIAS, VOFFSET and

VRESET

Mirror Park

Sequence

Note 4

Power Off

VDD / VDDI

VSS

VBIAS

VDD < VBIAS

< 6 V

VBIAS < 4 V

VSS

VOFFSET

VDD < VOFFSET

< 6 V

VOFFSET < 4 V

VOFFSET

VSS

VRESET < 0.5 V

VRESET > - 4 V

VRESET

VDD

VRESET

VDD

DMD_DEN_ARSTZ

VSS

INITIALIZATION

VDD

LS_CLK

LS_WDATA

VID

D_P(0:3), D_N(0:3)

DCLK_P, DCLK_N

A. Refer to 表 9-1 and 图 9-2 for critical power-up sequence delay requirements.

B. To prevent excess current, the supply voltage delta |V_BIAS– V_OFFSET| must be less than specified in 节 6.4. OEMs may find that the

most reliable way to ensure this is to power V_OFFSETprior to V_BIASduring power-up and to remove V_BIASprior to V_OFFSETduring

power-down. Refer to 表 9-1 and 图 9-2 for power-up delay requirements.

C. To prevent excess current, the supply voltage delta |V_BIAS– V_RESET| must be less than specified limit shown in 节 6.4.

D. When system power is interrupted, the ASIC driver initiates hardware power-down that disables V_BIAS, V_RESETand V_OFFSETafter the

Micromirror Park Sequence. Software power-down disables V_BIAS, V_RESET, and V_OFFSETafter the Micromirror Park Sequence through

software control.

E. Drawing is not to scale and details are omitted for clarity.

图 9-1. Power Supply Sequencing Requirements (Power Up and Power Down)

表 9-1. Power-Up Sequence Delay Requirement

PARAMETER

MIN

MAX

UNIT

t_DELAY

Delay requirement from V_OFFSETpower up to V_BIASpower up

V_OFFSETSupply voltage level during power–up sequence delay (see 图 9-2)

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表 9-1. Power-Up Sequence Delay Requirement (continued)

PARAMETER

MIN

MAX

UNIT

V_BIAS

Supply voltage level during power–up sequence delay (see 图 9-2)

VOFFSET

VDD ≤ VOFFSET ≤ 6 V

VSS

DELAY

VBIAS

VDD ≤ VBIAS ≤ 6 V

VSS

Time

A. Refer to 表 9-1 for V_OFFSETand V_BIASsupply voltage levels during power-up sequence delay.

图 9-2. Power-Up Sequence Delay Requirement

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10 Layout

10.1 Layout Guidelines

There are no specific layout guidelines for the DMD as typically DMD is connected using a board to board

connector to a flex cable. Flex cable provides the interface of data and control signals between the DLPC1438

controller and the DLP300S DMD. For detailed layout guidelines refer to the layout design files. Some layout

guideline for the flex cable interface with DMD are:

•

Match lengths for the LS_WDATA and LS_CLK signals.

Minimize vias, layer changes, and turns for the HS bus signals. Refer 图 10-1.

Minimum of two 100-nF decoupling capacitor close to VBIAS. Capacitor C6 and C7 in 图 10-1.

Minimum of two 100-nF decoupling capacitor close to VRST. Capacitor C9 and C8 in 图 10-1.

Minimum of two 220-nF decoupling capacitor close to VOFS. Capacitor C5 and C4 in 图 10-1.

Minimum of four 100-nF decoupling capacitor close to VDDI and VDD. Capacitor C1, C2, C3 and C10 in 图

10-1.

10.2 Layout Example

图 10-1. Power Supply Connections

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11 Device and Documentation Support

11.1 Device Support

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

11.1.2 Device Nomenclature

DLP300S FQK

Package Type

Device Descriptor

图 11-1. Part Number Description

11.1.3 Device Markings

The device marking includes the legible character string GHJJJJK DLP300SFQK. GHJJJJK is the lot trace code.

DLP300SFQK is the orderable device number.

Lot Trace Code

GHJJJJK

DLP300SFQK

Part Marking

图 11-2. DMD Marking

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 Related Links

表 11-1 lists quick access links. Categories include technical documents, support and community resources,

tools and software, and quick access to sample or buy.

表 11-1. Related Links

TECHNICAL

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

DOCUMENTS

DLP300S

DLPC1438

DLPA2000

Click here

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表 11-1. Related Links (continued)

TECHNICAL

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

DOCUMENTS

DLPA2005

Click here

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI

的《使用条款》。

11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

DLP^®and Pico^®are registered trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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18-May-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DLP300SFQK

ACTIVE

CLGA

FQK

120

RoHS & Green

NI/AU

N / A for Pkg Type

0 to 40

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

DWG NO.

2512014

REVISIONS

NOTES UNLESS OTHERWISE SPECIFIED:

REV

DESCRIPTION

DATE

6/6/2013

6/17/2013

4/8/2020

ECO 2133835: INITIAL RELEASE

ECO 2134093: CORRECT WINDOW THK TOL, ZONE B6

ECO 2186947: ADD APERTURE SLOTS PICTORIALLY

BMH

PPC

DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY.

ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION

TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES.

BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY.

NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC,

AS SHOWN IN SECTION A-A.

ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN IN VIEW C

(SHEET 2). NO ENCAPSULANT IS ALLOWED ON TOP OF THE WINDOW.

ENCAPSULANT NOT TO EXCEED THE HEIGHT OF THE WINDOW.

DATUM B IS DEFINED BY A DIA. 2.5 PIN, WITH A FLAT ON THE SIDE FACING

TOWARD THE CENTER OF THE ACTIVE ARRAY, AS SHOWN IN VIEW B (SHEET 2).

WHILE ONLY THE THREE DATUM A TARGET AREAS A1, A2, AND A3 ARE USED

FOR MEASUREMENT, ALL 4 CORNERS SHOULD BE CONTACTED, INCLUDING E1,

TO SUPPORT MECHANICAL LOADS.

1.1760.05

4X (R0.2)

0.3

0.1

90° 1°

(ILLUMINATION

DIRECTION)

4X R0.40.1

2X 2.50.075

(2.5)

1.25

3.5

0.2

0.1

0.2

0.1

2.25

0.2

0.1

(1)

0.8

16.4 0.08

0.3

0.1

18.2

(OFF-STATE

DIRECTION)

5 6

2X ENCAPSULANT

1.1 0.05

1.403 0.077

(2.183)

3 SURFACES INDICATED

IN VIEW B (SHEET 2)

0.038A

0.02D

1 8



0.780.063

ACTIVE ARRAY

1.60.1

(1.6)

(2.5)

0.4 MIN

TYP.

(SHEET 3)

0 MIN TYP.

DATE

DRAWN

UNLESS OTHERWISE SPECIFIED

DIMENSIONS ARE IN MILLIMETERS

TOLERANCES:

TEXAS

6/6/2013

6/7/2013

6/6/2013

6/10/2013

6/6/2013

B. HASKETT

ENGINEER

B. HASKETT

QA/CE

INSTRUMENTS

Dallas Texas

ANGLES 1

TITLE

SECTION A-A

NOTCH OFFSETS

ICD, MECHANICAL, DMD,

.3 720p SERIES 245

(FQK PACKAGE)

2 PLACE DECIMALS 0.25

1 PLACE DECIMALS 0.50

DIMENSIONAL LIMITS APPLY BEFORE PROCESSES

INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME

Y14.5M-1994

P. KONRAD

S. SUSI

THIRD ANGLE

PROJECTION

DWG NO

REV

SIZE

0314DA

USED ON

REMOVE ALL BURRS AND SHARP EDGES

PARENTHETICAL INFORMATION FOR REFERENCE ONLY

S. CROFF

APPROVED

R. LONG

2512014

NEXT ASSY

SCALE

SHEET

APPLICATION

20:1

INV11-2006a

DWG NO.

7.2

2512014

2X (1)

2X 1.176

2X (0.8)

2X 16.4

4X 1.5

1.25

2.5

4X (2)

(1.1)

VIEW B

DATUMS A, B, C, AND E

1.176

16.4

(FROM SHEET 1)

(2.5)

1.25

3.6

VIEW C

ENCAPSULANT MAXIMUM X/Y DIMENSIONS

(FROM SHEET 1)

2X 0 MIN

VIEW D

ENCAPSULANT MAXIMUM HEIGHT

DWG NO

REV

SIZE

DRAWN

DATE

TEXAS

6/6/2013

2512014

B. HASKETT

INSTRUMENTS

Dallas Texas

SCALE

SHEET

INV11-2006a

DWG NO.

2512014

(6.912)

ACTIVE ARRAY

6.4490.075

4X (0.108)

0.9710.05

0.193 0.0635

(6.15)

WINDOW

(3.888)

ACTIVE ARRAY

4.319 0.0635

(ILLUMINATION

DIRECTION)

(2.5)

(4.512)

APERTURE

5.1790.05

1.25

1.784 0.075

0.4240.0635

2.961 0.05

7.1390.0635

(7.563)

APERTURE



8.815 0.05

(11.776)

WINDOW

VIEW E

WINDOW AND ACTIVE ARRAY

(FROM SHEET 1)

57X LGA PADS

0.52±0.05 X 0.52±0.05

12X TEST PADS

(0.52 0.05)

0.2ABC



0.1A

BACK INDEX MARK

(42°)

TYP.

(42°)

TYP.

17 18

(0.15) TYP.

(0.075) TYP.

1.25

(2.5)

2 X 0.7424

= 1.4848

0.7424

2X (0.7424)

(0.068) TYP.

(42°) TYP.



(0.7424)

DETAIL G

2.874

18 X 0.7424 = 13.3632

DETAIL F

APERTURE LEFT EDGE

APERTURE RIGHT EDGE

SCALE 60 : 1

VIEW H-H

SCALE 60 : 1

BACK SIDE METALLIZATION

(FROM SHEET 1)

DWG NO

REV

SIZE

DRAWN

DATE

6/6/2013

TEXAS

2512014

B. HASKETT

INSTRUMENTS

Dallas Texas

SCALE

SHEET

INV11-2006a

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

DLP300S [TI]

相关型号：

DLP300SFQK

DLP3010

DLP3010AFQK

DLP3010FQK

DLP3010LC

DLP3010LCFQK

DLP301S

DLP301SFQS

DLP3020-Q1

DLP3020AFQRQ1

DLP3021-Q1

DLP3021FFQRQ1