DLP3010LCFQK [TI]
DLP® 0.3 英寸 720p 数字微镜器件 (DMD) | FQK | 57 | 0 to 70;型号: | DLP3010LCFQK |
厂家: | TEXAS INSTRUMENTS |
描述: | DLP® 0.3 英寸 720p 数字微镜器件 (DMD) | FQK | 57 | 0 to 70 光电 |
文件: | 总44页 (文件大小:1232K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DLP3010LC
DLPS179C – APRIL 2020 – REVISED JULY 2023
DLP3010LC 0.3 720p Digital Micromirror Device
1 Features
3 Description
•
0.3-Inch (7.93-mm) diagonal micromirror array
– 1280 × 720 array of aluminum micrometer-
sized mirrors, in an orthogonal layout
– 5.4 – micron micromirror pitch
– ±17° micromirror tilt (relative to flat surface)
– Side illumination for optimal efficiency and
optical engine size
– Polarization independent aluminum micromirror
surface
8-Bit SubLVDS input data bus
The 7212-313BK digital micromirror device (DMD)
is a digitally controlled micro-opto-electromechanical
system (MOEMS) spatial light modulator (SLM).
When coupled to an appropriate optical system,
the DMD displays a very crisp and high quality
image or video. This DMD is a component of the
chipset comprising the DMD, DLPC3478 display and
light controller, and DLPA200x/DLPA300x PMIC/LED
driver. The compact physical size of this DMD coupled
with the controller and the PMIC/LED driver provides
a complete system solution that enables small form
factor, low power, and high-resolution, light-control
applications like such as 3D scanners.
•
•
Dedicated DLPC3478 display and light controller
and DLPA200x or DLPA300x PMIC/LED driver for
reliable operation
Device Information(1)
2 Applications
PART NUMBER PACKAGE
BODY SIZE (NOM)
•
Integrated display and 3D depth capture
– Smart phone, tablets, laptop, camera
– Battery-powered mobile accessory
3D depth capture: 3D camera, 3D reconstruction,
AR/VR, dental scanner
7212-313BK FQK (57)
18.20-mm × 7.00-mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
3D machine vision: robotics, metrology, in-line
inspection (AOI)
•
•
3D biometrics: facial and finger print recognition
Light exposure: 3D printers, programmable spatial
and temporal light exposure
7212-313BK 0.3 720p Chipset
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLP3010LC
DLPS179C – APRIL 2020 – REVISED JULY 2023
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 Storage Conditions..................................................... 7
6.3 ESD Ratings............................................................... 7
6.4 Recommended Operating Conditions.........................7
6.5 Thermal Information..................................................10
6.6 Electrical Characteristics...........................................10
6.7 Timing Requirements................................................ 11
6.8 Switching Characteristics(1) ..................................... 15
6.9 System Mounting Interface Loads............................ 16
6.10 Physical Characteristics of the Micromirror Array...17
6.11 Micromirror Array Optical Characteristics............... 18
6.12 Window Characteristics.......................................... 20
6.13 Chipset Component Usage Specification............... 20
6.14 Software Requirements.......................................... 20
7 Detailed Description......................................................21
7.1 Overview...................................................................21
7.2 Functional Block Diagram.........................................22
7.3 Feature Description...................................................23
7.4 Device Functional Modes..........................................23
7.5 Optical Interface and System Image Quality
7.6 Micromirror Array Temperature Calculation.............. 24
7.7 Micromirror Power Density Calculation.....................25
7.8 Micromirror Landed-On/Landed-Off Duty Cycle....... 27
8 Application and Implementation..................................30
8.1 Application Information............................................. 30
8.2 Typical Application.................................................... 30
9 Power Supply Recommendations................................33
9.1 DMD Power Supply Power-Up Procedure................33
9.2 DMD Power Supply Power-Down Procedure........... 33
9.3 Power Supply Sequencing Requirements................ 34
10 Layout...........................................................................36
10.1 Layout Guidelines................................................... 36
10.2 Layout Example...................................................... 36
11 Device and Documentation Support..........................37
11.1 Device Support........................................................37
11.2 Documentation Support.......................................... 37
11.3 Receiving Notification of Documentation Updates..37
11.4 Related Links.......................................................... 37
11.5 Support Resources................................................. 38
11.6 Trademarks............................................................. 38
11.7 Electrostatic Discharge Caution..............................38
11.8 Glossary..................................................................38
12 Mechanical, Packaging, and Orderable
Information.................................................................... 38
Considerations............................................................ 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2022) to Revision C (July 2023)
Page
•
•
•
Added "ILLUMINATION" to Recommended Operating Conditions ....................................................................7
Updated Micromirror Array Temperature Calculation ...................................................................................... 24
Added Micromirror Power Density Calculation ................................................................................................ 25
Changes from Revision A (November 2021) to Revision B (May 2022)
Page
•
•
•
Updated Absolute Maximum Ratings disclosure to the latest TI standard......................................................... 6
Updated Micromirror Array Optical Characteristics ......................................................................................... 18
Added Third-Party Products Disclaimer ...........................................................................................................37
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5 Pin Configuration and Functions
Figure 5-1. FQK Package 57-Pin LGA (Bottom View)
Table 5-1. Pin Functions – Connector Pins(1)
PIN
NAME
PACKAGE NET
LENGTH(2) (mm)
TYPE
SIGNAL
DATA RATE
DESCRIPTION
NO.
DATA INPUTS
D_N(0)
C9
B9
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Data, Negative
10.54
10.54
13.14
13.14
14.24
14.24
14.35
14.35
5.89
D_P(0)
Data, Positive
Data, Negative
Data, Positive
Data, Negative
Data, Positive
Data, Negative
Data, Positive
Data, Negative
Data, Positive
Data, Negative
Data, Positive
Data, Negative
Data, Positive
Data, Negative
Data, Positive
Clock, Negative
Clock, Positive
D_N(1)
D10
D11
C11
B11
D12
D13
D4
D_P(1)
D_N(2)
D_P(2)
D_N(3)
D_P(3)
D_N(4)
D_P(4)
D5
5.89
D_N(5)
C5
5.45
D_P(5)
B5
5.45
D_N(6)
D6
8.59
D_P(6)
D7
8.59
D_N(7)
C7
7.69
D_P(7)
B7
7.69
DCLK_N
DCLK_P
CONTROL INPUTS
LS_WDATA
LS_CLK
D8
8.10
D9
8.10
C12
C13
I
I
LPSDR(1)
LPSDR
Single
Single
Write data for low speed interface.
Clock for low-speed interface
7.16
7.89
Asynchronous reset DMD signal. A low
signal places the DMD in reset. A high
signal releases the DMD from reset
and places it in active mode.
DMD_DEN_ARSTZ C14
I
LPSDR
LPSDR
LS_RDATA
POWER (3)
VBIAS
C15
O
Single
Read data for low-speed interface
C1
Power
Power
Supply voltage for positive bias level at
micromirrors
VBIAS
C18
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Table 5-1. Pin Functions – Connector Pins(1) (continued)
PIN
NAME
VOFFSET
PACKAGE NET
LENGTH(2) (mm)
TYPE
SIGNAL
DATA RATE
DESCRIPTION
NO.
D1
Power
Supply voltage for HVCMOS core
logic. Supply voltage for stepped
high level at micromirror address
electrodes.
Supply voltage for offset level at
micromirrors.
VOFFSET
D17
Power
VRESET
VRESET
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDI
VDDI
VDDI
VDDI
VSS
B1
B18
B6
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Supply voltage for negative reset level
at micromirrors.
B10
B19
C6
Supply voltage for LVCMOS core logic.
Supply voltage for LPSDR inputs.
Supply voltage for normal high level at
micromirror address electrodes.
C10
C19
D2
D18
D19
B2
C2
Supply voltage for SubLVDS receivers.
C3
D3
B3
VSS
B4
VSS
B8
VSS
B12
B13
B14
B15
B16
B17
C4
VSS
VSS
Common return.
Ground for all power.
VSS
VSS
VSS
VSS
VSS
C8
VSS
C16
C17
D14
D15
D16
VSS
VSS
VSS
VSS
(1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC
Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.
(2) Net trace lengths inside the package:
Relative dielectric constant for the FQK ceramic package is 9.8.
Propagation speed = 11.8 / sqrt (9.8) = 3.769 inches/ns.
Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.
(3) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.
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Table 5-2. Pin Functions – Test Pads
NUMBER
A13
SYSTEM BOARD
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
A14
A15
A16
A17
A18
E13
E14
E15
E16
E17
E18
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6 Specifications
6.1 Absolute Maximum Ratings
See (1)
MIN
–0.5
–0.5
–0.5
MAX
2.3
2.3
11
UNIT
Supply voltage for LVCMOS core logic(2)
Supply voltage for LPSDR low speed interface
VDD
V
V
V
VDDI
Supply voltage for SubLVDS receivers(2)
Supply voltage for HVCMOS and micromirror
electrode(2) (3)
VOFFSET
Supply voltage for micromirror electrode(2)
Supply voltage for micromirror electrode(2)
Supply voltage delta (absolute value)(4)
Supply voltage delta (absolute value)(5)
Supply voltage delta (absolute value)(6)
–0.5
–15
19
0.5
V
V
Supply voltage
VBIAS
VRESET
| VDDI–VDD |
| VBIAS–VOFFSET |
| VBIAS–VRESET |
0.3
V
11
V
34
V
Input voltage for other inputs LPSDR(2)
–0.5
–0.5
VDD + 0.5
VDDI + 0.5
810
V
Input voltage
Input pins
Input voltage for other inputs SubLVDS(2) (7)
V
| VID |
IID
SubLVDS input differential voltage (absolute value)(7)
mV
mA
MHz
MHz
°C
°C
SubLVDS input differential current
10
ƒclock
ƒclock
Clock frequency for low speed interface LS_CLK
Clock frequency for high speed interface DCLK
Temperature – operational (8)
130
Clock
frequency
560
–20
–40
90
TARRAY and TWINDOW
Temperature – non-operational(8)
90
Dew Point Temperature - operating and non-operating
(non-condensing)
Environmental
TDP
|TDELTA
81
30
°C
°C
Absolute Temperature delta between any point on the
window edge and the ceramic test point TP1(9)
|
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:
VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET.
(3) VOFFSET supply transients must fall within specified voltages.
(4) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.
(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current
draw.
(6) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current
draw.
(7) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential
inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(8) The highest temperature of the active array (as calculated by the Section 7.6) or of any point along the Window Edge as defined
in Figure 7-1. The locations of thermal test points TP2 and TP3 in Figure 7-1 are intended to measure the highest window edge
temperature. If a particular application causes another point on the window edge to be at a higher temperature, that point should be
used.
(9) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in
Figure 7-1. The window test points TP2 and TP3 shown in Figure 7-1 are intended to result in the worst case delta. If a particular
application causes another point on the window edge to result in a larger delta temperature, that point should be used.
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6.2 Storage Conditions
applicable for the DMD as a component or non-operational in a system
MIN
MAX
85
24
36
6
UNIT
°C
TDMD
DMD storage temperature
–40
TDP-AVG
TDP-ELR
CTELR
Average dew point temperature, (non-condensing)(1)
Elevated dew point temperature range, (non-condensing)(2)
Cumulative time in elevated dew point temperature range
°C
28
°C
Months
(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR
.
6.3 ESD Ratings
VALUE
UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN
NOM
MAX
UNIT
SUPPLY VOLTAGE RANGE(4)
Supply voltage for LVCMOS core logic
VDD
1.65
1.8
1.95
V
Supply voltage for LPSDR low-speed interface
Supply voltage for SubLVDS receivers
Supply voltage for HVCMOS and micromirror electrode(5)
Supply voltage for mirror electrode
VDDI
1.65
9.5
1.8
10
1.95
10.5
18.5
–13.5
0.3
V
V
V
V
V
V
V
VOFFSET
VBIAS
17.5
–14.5
18
VRESET
Supply voltage for micromirror electrode
Supply voltage delta (absolute value)(6)
Supply voltage delta (absolute value)(7)
Supply voltage delta (absolute value)(8)
–14
|VDDI–VDD|
|VBIAS–VOFFSET|
|VBIAS–VRESET|
CLOCK FREQUENCY
ƒclock
10.5
33
Clock frequency for low speed interface LS_CLK(9)
Clock frequency for high speed interface DCLK(10)
Duty cycle distortion DCLK
108
300
120
600
MHz
MHz
ƒclock
44%
56%
SUBLVDS INTERFACE(10)
SubLVDS input differential voltage (absolute value) Figure 6-9, Figure
6-10
| VID
VCM
|
150
250
900
350
mV
Common mode voltage Figure 6-9, Figure 6-10
SubLVDS voltage Figure 6-9, Figure 6-10
Line differential impedance (PWB/trace)
Internal differential termination resistance Figure 6-11
100-Ω differential PCB trace
700
575
90
1100
1225
110
mV
mV
Ω
VSUBLVDS
ZLINE
100
100
ZIN
80
120
Ω
6.35
152.4
mm
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UNIT
DLPS179C – APRIL 2020 – REVISED JULY 2023
6.4 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN
NOM
MAX
ENVIRONMENTAL
Array Temperature – long-term operational(11) (12) (13) (14)
0
–20
–10
70
40 to 70(13)
Array Temperature - short-term operational, 25 hr max(12) (15)
TARRAY
–10
0
°C
°C
Array Temperature - short-term operational, 500 hr max(12) (15)
Array Temperature – short-term operational, 500 hr max(12) (15)
75
Absolute Temperature difference between any point on the window
|TDELTA
|
15
edge and the ceramic test point TP1 (16)
TWINDOW
TDP-AVG
TDP-ELR
CTELR
Window temperature – operational(11) (17)
90
24
36
6
°C
°C
Average dew point temperature (non-condensing)(18)
Elevated dew point temperature range (non-condensing)(19)
Cumulative time in elevated dew point temperature range
28
°C
Months
ILLUMINATION
ILLUV
Illumination power at wavelengths < 410 nm(11)
Illumination power at wavelengths ≥ 410 nm and ≤ 800 nm(21)
Illumination power at wavelengths > 800 nm
10 mW/cm2
26.1 W/cm2
10 mW/cm2
8.3 W/cm2
1.5 W/cm2
ILLVIS
ILLIR
ILLBLU
Illumination power at wavelengths ≥ 410 nm and ≤ 475 nm(21)
Illumination power at wavelengths ≥ 410 nm and ≤ 445 nm(21)
Illumination marginal ray angle(20)
ILLBLU1
ILLθ
55
deg
(1) Section 6.4 are applicable after the DMD is installed in the final product.
(2) The functional performance of the device specified in this datasheet is achieved when operating the device within the limits defined by
the Section 6.4. No level of performance is implied when operating the device above or below the Section 6.4 limits.
(3) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET.
(4) All voltage values are with respect to the ground pins (VSS).
(5) VOFFSET supply transients must fall within specified maximum voltages.
(6) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.
(7) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.
(8) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit.
(9) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.
(10) Refer to the SubLVDS timing requirements in Section 6.7.
(11) Simultaneous exposure of the DMD to the maximum Section 6.4 for temperature and UV illumination will reduce device lifetime.
(12) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1
(TP1) shown in Figure 7-1 and the Package Thermal Resistance using Section 7.6.
(13) Per Figure 6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the
DMD experiences in the end application. Refer to Section 7.8 for a definition of micromirror landed duty cycle.
(14) Long-term is defined as the usable life of the device.
(15) Short-term is the total cumulative time over the useful life of the device.
(16) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge shown in Figure
7-1. The window test points TP2 and TP3 shown in Figure 7-1 are intended to result in the worst case delta temperature. If a particular
application causes another point on the window edge to result in a larger delta temperature, that point should be used.
(17) Window temperature is the highest temperature on the window edge shown in Figure 7-1. The locations of thermal test points TP2 and
TP3 in Figure 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on
the window edge to result in a larger delta temperature, that point should be used.
(18) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(19) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR
.
(20) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors
(POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily
been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not
been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM)
will contribute to thermal limitations described in this document, and may negatively affect lifetime.
(21) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength
range specified and the micromirror array temperature (TARRAY).
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80
70
60
50
40
30
0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50
90/10 85/15 80/20 75/25 70/30 65/35 60/40 55/45
100/0 95/5
D001
Micromirror Landed Duty Cycle
Figure 6-1. Maximum Recommended Array Temperature (Derating Curve)
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6.5 Thermal Information
DLP3010LC
FQK (LGA)
57 PINS
5.4
THERMAL METRIC(1)
UNIT
Thermal resistance
Active area to test point 1 (TP1)(1)
°C/W
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the package within the temperature range specified in the Section 6.4. The total heat load on the DMD is largely driven by
the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and
electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window
clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.
6.6 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)(10)
PARAMETER
TEST CONDITIONS(2)
MIN
TYP
MAX UNIT
CURRENT
VDD = 1.95 V
60.5
mA
IDD
Supply current: VDD(3) (5)
Supply current: VDDI(3) (5)
Supply current: VOFFSET(4) (6)
Supply current: VBIAS(4) (6)
Supply current: VRESET(6)
VDD = 1.8 V
54
11.3
1.5
VDDI = 1.95 V
VDD = 1.8 V
16.5
mA
IDDI
VOFFSET = 10.5 V
VOFFSET = 10 V
VBIAS = 18.5 V
VBIAS = 18 V
2.2
mA
IOFFSET
0.6
mA
IBIAS
0.3
VRESET = –14.5 V
VRESET = –14 V
2.4
mA
IRESET
1.7
POWER(1)
PDD
VDD = 1.95 V
118
Supply power dissipation: VDD(3) (5)
Supply power dissipation: VDDI(3) (5)
mW
VDD = 1.8 V
97.2
20
15
6
VDDI = 1.95 V
VDD = 1.8 V
32
PDDI
mW
VOFFSET = 10.5 V
VOFFSET = 10 V
VBIAS = 18.5 V
VBIAS = 18 V
23
Supply power dissipation:
VOFFSET(4) (6)
POFFSET
mW
11
PBIAS
Supply power dissipation: VBIAS(4) (6)
mW
VRESET = –14.5 V
VRESET = –14 V
35
PRESET
Supply power dissipation: VRESET(6)
Supply power dissipation: Total
mW
24
PTOTAL
LPSDR INPUT(7)
162.2
219
mW
VIH(DC)
VIL(DC)
VIH(AC)
VIL(AC)
∆VT
DC input high voltage(9)
0.7 × VDD
–0.3
VDD + 0.3
0.3 × VDD
VDD + 0.3
0.2 × VDD
0.4 × VDD
V
V
DC input low voltage(9)
AC input high voltage(9)
AC input low voltage(9)
0.8 × VDD
–0.3
V
V
Hysteresis ( VT+ – VT–
)
Figure 6-12
0.1 × VDD
–100
V
IIL
Low–level input current
High–level input current
VDD = 1.95 V; VI = 0 V
VDD = 1.95 V; VI = 1.95 V
nA
nA
IIH
100
LPSDR OUTPUT(8)
VOH
VOL
DC output high voltage
IOH = –2 mA
IOL = 2 mA
0.8 × VDD
V
V
DC output low voltage
0.2 × VDD
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6.6 Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)(10)
PARAMETER
TEST CONDITIONS(2)
MIN
TYP
MAX UNIT
CAPACITANCE
Input capacitance LPSDR
Input capacitance SubLVDS
Output capacitance
ƒ = 1 MHz
10
10
pF
pF
pF
pF
CIN
ƒ = 1 MHz
COUT
ƒ = 1 MHz
10
CRESET
Reset group capacitance
ƒ = 1 MHz; (720 × 160) micromirrors
200
220
(1) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.
(2) All voltage values are with respect to the ground pins (VSS).
(3) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.
(4) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.
(5) Supply power dissipation based on non–compressed commands and data.
(6) Supply power dissipation based on 3 global resets in 200 µs.
(7) LPSDR specifications are for pins LS_CLK and LS_WDATA.
(8) LPSDR specification is for pin LS_RDATA.
(9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC
Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.
(10) Device electrical characteristics are over Section 6.4 unless otherwise noted.
6.7 Timing Requirements
Device electrical characteristics are over Section 6.4 unless otherwise noted.
MIN
NOM
MAX
UNIT
LPSDR
tr
Rise slew rate(1)
Fall slew rate(1)
Rise slew rate(2)
Fall slew rate(2)
Cycle time LS_CLK,
(30% to 80%) × VDD, Figure 6-3
(70% to 20%) × VDD, Figure 6-3
(20% to 80%) × VDD, Figure 6-4
(80% to 20%) × VDD, Figure 6-4
Figure 6-2
1
1
3
3
V/ns
V/ns
V/ns
V/ns
ns
tƒ
tr
0.25
0.25
7.7
tƒ
tc
8.3
50% to 50% reference points, Figure
6-2
tW(H)
tW(L)
tsu
Pulse duration LS_CLK high
Pulse duration LS_CLK low
Setup time
3.1
3.1
1.5
ns
ns
ns
50% to 50% reference points, Figure
6-2
LS_WDATA valid before LS_CLK ↑,
Figure 6-2
LS_WDATA valid after LS_CLK ↑,
Figure 6-2
t h
Hold time
1.5
3
ns
ns
ns
tWINDOW
tDERATING
SubLVDS
tr
Window time(1) (4)
Window time derating(1) (4)
Setup time + Hold time, Figure 6-2
For each 0.25 V/ns reduction in slew
rate below 1 V/ns, Figure 6-6
0.35
1
20% to 80% reference points, Figure
6-5
Rise slew rate
0.7
V/ns
80% to 20% reference points, Figure
6-5
tƒ
Fall slew rate
0.7
1.79
0.79
1
V/ns
ns
tc
Cycle time DCLK,
Pulse duration DCLK high
Figure 6-7
1.85
50% to 50% reference points, Figure
6-7
tW(H)
ns
50% to 50% reference points, Figure
6-7
tW(L)
tsu
Pulse duration DCLK low
Setup time
0.79
ns
D(0:3) valid before
DCLK ↑ or DCLK ↓, Figure 6-7
D(0:3) valid after
DCLK ↑ or DCLK ↓, Figure 6-7
t h
Hold time
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6.7 Timing Requirements (continued)
Device electrical characteristics are over Section 6.4 unless otherwise noted.
MIN
NOM
MAX
UNIT
Setup time + Hold time, Figure 6-7,
Figure 6-8
tWINDOW
Window time
0.3
ns
tLVDS-
Power-up receiver(3)
2000
ns
ENABLE+REFGEN
(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 6-3.
(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-4.
(3) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
(4) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.
t
C
t
t
w(L)
w(H)
50%
LS_CLK
t
t
H|
SU|
50%
LS_WDATA
t
WINDOW|
Low-speed interface is LPSDR and adheres to the Section 6.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B,
Low Power Double Data Rate (LPDDR) JESD209B.
Figure 6-2. LPSDR Switching Parameters
LS_CLK and LS_WDATA
100
V
V
IH(AC)
IH(DC)
80
70
V
V
IL(DC)
IL(AC)
30
20
t
F
t
R
Time
Figure 6-3. LPSDR Input Slew Rate
DMD_DEN_ARSTZ
100
80
V
IL(AC)
20
t
F
t
R
Time
Figure 6-4. LPSDR Input Slew Rate
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VDCLK_P and VDCLK_N
VD_P(0:3) and VD_N(0:3)
100
80
70
V
CM
50
20
t
F
t
R
Time
Figure 6-5. SubLVDS Input Rise and Fall Slew Rate
VIH MIN
LS_CLK Midpoint
VIL MAX
tSU
tH
VIH MIN
LS_WDATA Midpoint
VIL MAX
tWINDOW
VIH MIN
Midpoint
LS_CLK
VIL MAX
tDERATING
tH
tSU
VIH MIN
Midpoint
VIL MAX
LS_WDATA
tWINDOW
Figure 6-6. Window Time Derating Concept
t
C
t
t
w(H)
w(L)
DCLK_P
50%
DCLK_N
t
t
H|
SU|
D_P(0:7)
50%
D_N(0:7)
t
WINDOW|
Figure 6-7. SubLVDS Switching Parameters
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t
C
(1)
WINDOW
t
|
DCLK_P
50%
DCLK_N
¼ t
C|
¼ t
C|
D_P(0:7)
50%
D_N(0:7)
(1) High-speed training scan window
(2) Refer to Section 7.3.3 for details
Figure 6-8. High-Speed Training Scan Window
+
(VIP + VIN
2
)
VCM
=
œ
DCLP_P, D_P(0:7)
DCLP_N, D_N(0:7)
VID
SubLVDS
Receiver
VCM
VIP
VIN
Figure 6-9. SubLVDS Voltage Parameters
1.255 V
V
LVDS(max)
V
V
CM
ID
V
LVDS(min)
0.575 V
Figure 6-10. SubLVDS Waveform Parameters
VSubLVDS(max) = VCM(max) + ½ × |VID(max)
VSubLVDS(min) = VCM(min) – ½ × |VID(max)
|
|
DCLP_P, D_P(0:7)
ESD
ESD
Internal
Termination
SubLVDS
Receiver
DCLP_N, D_N(0:7)
Figure 6-11. SubLVDS Equivalent Input Circuit
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LS_CLK and LS_WDATA
V
IH
V
T+
DV
T
V
Tœ
V
IL
Time
Figure 6-12. LPSDR Input Hysteresis
LS_CLK
LS_WDATA
Stop
Start
tPD
LS_RDATA
Acknowledge
Figure 6-13. LPSDR Read Out
Timing specification reference point
Device pin
output under test
Tester channel
CL
See Section 7.3.4 for more information.
Figure 6-14. Test Load Circuit for Output Propagation Measurement
6.8 Switching Characteristics(1)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
11.1
11.3
15
UNIT
ns
CL = 5 pF
CL = 10 pF
CL = 85 pF
Output propagation, Clock to Q, rising
edge of LS_CLK input to LS_RDATA
output. Figure 6-13
tPD
ns
ns
Slew rate, LS_RDATA
0.5
V/ns
Output duty cycle distortion, LS_RDATA
40%
60%
(1) Device electrical characteristics are over Section 6.4 unless otherwise noted.
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6.9 System Mounting Interface Loads
PARAMETER
MIN
NOM
MAX
125
67
UNIT
N
Maximum system mounting interface load to Electrical Interface Area (see Figure 6-15)
be applied to the:
Clamping and Thermal Interface Area (see
N
Figure 6-15)
Electrical Interface Area
125 N Maximum
Clamping and Thermal Interface Area # 1
33.5 N Maximum
Clamping and Thermal Interface Area # 2
33.5 N Maximum
Figure 6-15. System Interface Loads
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6.10 Physical Characteristics of the Micromirror Array
PARAMETER
VALUE
1280
720
UNIT
micromirrors
micromirrors
µm
Number of active columns
Number of active rows
Micromirror (pixel) pitch
See Figure 6-16
See Figure 6-16
See Figure 6-17
5.4
Micromirror pitch × number of active
columns; see Figure 6-16
Micromirror active array width
Micromirror active array height
Micromirror active border
6.912
3.888
20
mm
mm
Micromirror pitch × number of active rows;
see Figure 6-16
micromirrors/
side
Pond of micromirror (POM)(1)
(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.
Width .
Mirror 719
Mirror 718
Mirror 717
Mirror 716
Illumination
1280 × 720 mirrors
Height
Mirror 3
Mirror 2
Mirror 1
Mirror 0
Figure 6-16. Micromirror Array Physical Characteristics
e
e
e
e
Figure 6-17. Mirror (Pixel) Pitch
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6.11 Micromirror Array Optical Characteristics
PARAMETER
Micromirror tilt angle
TEST CONDITIONS
MIN
NOM
MAX
UNIT
degree
degree
DMD landed state(1)
17
Micromirror tilt angle tolerance(2) (3) (4) (5)
–1.4
1.4
Landed ON state
180
270
1
Micromirror tilt direction (6) (7)
degree
µs
Landed OFF state
Typical performance
Typical performance
Micromirror crossover time(8)
Micromirror switching time(9)
3
10
Bright pixel(s) in active area
Gray 10 Screen (12)
0
1
4
0
0
(11)
Bright pixel(s) in the POM (13) Gray 10 Screen (12)
Image
Dark pixel(s) in the active
White Screen
micromirrors
performance(10)
area (14)
Adjacent pixel(s) (15)
Any Screen
Any Screen
Unstable pixel(s) in active
area (16)
(1) Measured relative to the plane formed by the overall micromirror array.
(2) Additional variation exists between the micromirror array and the package datums.
(3) Represents the landed tilt angle variation relative to the nominal landed tilt angle.
(4) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result
in colorimetry variations, system efficiency variations, or system contrast variations.
(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of
the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON state
direction. A binary value of 0 results in a micromirror landing in the OFF state direction. See Figure 6-18.
(7) Micromirror tilt direction is measured as in a typical polar coordinate system: Measuring counter-clockwise from a 0° reference which is
aligned with the +X Cartesian axis.
(8) The time required for a micromirror to nominally transition from one landed state to the opposite landed state.
(9) The minimum time between successive transitions of a micromirror.
(10) Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions:
Test set degamma shall be linear
Test set brightness and contrast shall be set to nominal
The diagonal size of the projected image shall be a minimum of 20 inches
The projections screen shall be 1X gain
The projected image shall be inspected from a 38 inch minimum viewing distance
The image shall be in focus during all image quality tests
(11) Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels
(12) Gray 10 screen definition: All areas of the screen are colored with the following settings:
Red = 10/255
Green = 10/255
Blue = 10/255
(13) POM definition: Rectangular border of off-state mirrors surrounding the active area
(14) Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels
(15) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster
(16) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable
pixel appears to be flickering asynchronously with the image
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(0,719)
(1279, 719)
Incident
Illumination
Light Path
Tilted Axis of
Pixel Rotation
On-State
Landed Edge
Off-State
Landed Edge
(0,0)
(1279,0)
Off-State
Light Path
Figure 6-18. Landed Pixel Orientation and Tilt
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6.12 Window Characteristics
PARAMETER(3)
MIN
NOM
MAX
Window material designation
Corning Eagle
XG
Window refractive index
Window aperture(1)
at wavelength 546.1 nm
1.5119
See (1)
See (2)
Illumination overfill(2)
Window transmittance, single-pass
through both surfaces and glass
Minimum within the wavelength range 420 to
680 nm. Applies to all angles 0° to 30° AOI.
97%
97%
Window Transmittance, single-pass
through both surfaces and glass
Average over the wavelength range 420 to
680 nm. Applies to all angles 30° to 45° AOI.
(1) See the package mechanical characteristics for details regarding the size and location of the window aperture.
(2) The active area of the 7212-313BK device is surrounded by an aperture on the inside of the DMD window surface that masks
structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light
illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using
the DMD. The illumination optical system should be designed to limit light flux incident outside the active array to less than 10% of the
average flux level in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of
overfill light on the outside of the active array may cause system performance degradation.
(3) See Section 7.5 for more information.
SPACER
6.13 Chipset Component Usage Specification
The 7212-313BK is a component of one or more TI DLP® chipsets. Reliable function and operation of the
7212-313BK requires that it be used in conjunction with the other components of the applicable DLP chipset,
including those components that contain or implement TI DMD control technology. TI DMD control technology is
the TI technology and devices for operating or controlling a DLP DMD.
Note
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.
6.14 Software Requirements
CAUTION
The 7212-313BK DMD has mandatory software requirements. Refer to Software Requirements for
TI DLP®Pico™ TRP Digital Micromirror Devices application report for additional information. Failure
to use the specified software will result in failure at power up.
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7 Detailed Description
7.1 Overview
The 7212-313BK DMD is a 0.3 inch diagonal spatial light modulator of aluminum micromirrors. Pixel array size
is 1280 columns by 720 rows in a square grid pixel arrangement. The electrical interface is Sub Low Voltage
Differential Signaling (SubLVDS) data.
This DMD is part of the chipset that includes the 7212-313BK DMD, DLPC3478 display and light controller
and DLPA200x/DLPA300x PMIC/LED driver. To ensure reliable operation, this DMD must always be used with
DLPC3478 display and light controller and DLPA200x/DLPA300x PMIC/LED driver.
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7.2 Functional Block Diagram
High-Speed
Interface
Control
Misc
Column Write
Bit Lines
(0,0)
Word
Lines
Voltages
Voltage
Generators
SRAM
Row
(719,1279)
Control
Column Read
Control
Low-Speed
Interface
A. Details omitted for clarity
B. Orientation is not representative of optical system
C. Scale is not representative of layout
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7.3 Feature Description
7.3.1 Power Interface
The power management IC, DLPA200x/DLPA300x, contains 3 regulated DC supplies for the DMD reset circuitry:
VBIAS, VRESET and VOFFSET, as well as the 2 regulated DC supplies for the DLPC3478 controller.
7.3.2 Low-Speed Interface
The Low Speed Interface handles instructions that configure the DMD and control reset operation. LS_CLK is
the low–speed clock, and LS_WDATA is the low speed data input.
7.3.3 High-Speed Interface
The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed
DDR transfer and compression techniques to save power and time. The high-speed interface is composed of
differential SubLVDS receivers for inputs, with a dedicated clock.
7.3.4 Timing
The data sheet provides timing test results at the device pin. For output timing analysis, the tester pin electronics
and its transmission line effects must be considered. Test Load Circuit for Output Propagation Measurement
shows an equivalent test load circuit for the output under test. Timing reference loads are not intended as
a precise representation of any particular system environment or depiction of the actual load presented by a
production test. TI recommends that system designers use IBIS or other simulation tools to correlate the timing
reference load to a system environment. The load capacitance value stated is intended for characterization and
measurement of AC timing signals only. This load capacitance value does not indicate the maximum load the
device is capable of driving.
7.4 Device Functional Modes
DMD functional modes are controlled by the DLPC3478 controller. See the DLPC3478 controller data sheet or
contact a TI applications engineer.
7.5 Optical Interface and System Image Quality Considerations
Note
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.
7.5.1 Optical Interface and System Image Quality
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
7.5.1.1 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
is typically the same. Ensure this angle does not exceed the nominal device micromirror tilt angle unless
appropriate apertures are added in the illumination or projection pupils to block out flat-state and stray light from
the projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from
any other light path, including undesirable flat–state specular reflections from the DMD window, DMD border
structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture
exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger
than the illumination numerical aperture angle (and vice versa), contrast degradation and objectionable artifacts
in the display border and/or active area may occur.
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7.5.1.2 Pupil Match
The optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable
artifacts in the display border and/or active area. These artifacts may require additional system apertures to
control, especially if the numerical aperture of the system exceeds the pixel tilt angle.
7.5.1.3 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating
conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window
aperture opening and other surface anomalies that may be visible on the screen. Be sure to design an
illumination optical system that limits light flux incident anywhere on the window aperture from exceeding
approximately 10% of the average flux level in the active area. Depending on the particular optical architecture,
overfill light may require further reduction below the suggested 10% level in order to be acceptable.
7.6 Micromirror Array Temperature Calculation
TP3
Illumination
Direction
TP2
Off-state Light
Window Edge
(4 surfaces)
TP2
TP3
TP1
TP1
Figure 7-1. DMD Thermal Test Points
Micromirror array temperature cannot be measured directly, therefore it must be computed analytically from
measurement points on the outside of the package, the package thermal resistance, the electrical power, and
the illumination heat load. The relationship between array temperature and the reference ceramic temperature
(thermal test TP1 in Figure 7-1) is provided by the following equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY-TO-CERAMIC
)
QARRAY = QELECTRICAL + QILLUMINATION
where
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•
•
•
•
•
•
•
•
TARRAY = Computed array temperature (°C)
TCERAMIC = Measured ceramic temperature (°C) (TP1 location)
RARRAY-TO-CERAMIC = Thermal resistance of package specified in Section 6.5 from array to ceramic TP1 (°C/Watt)
QARRAY = Total DMD power on the array (W) (electrical + absorbed)
QELECTRICAL = Nominal electrical power (W)
QINCIDENT = Incident illumination optical power (W)
QILLUMINATION = (DMD average thermal absorptivity × QINCIDENT) (W)
DMD average thermal absorptivity = 0.4
The electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating
frequencies. A nominal electrical power dissipation to use when calculating array temperature is 0.10 Watts. The
absorbed power from the illumination source is variable and depends on the operating state of the micromirrors
and the intensity of the light source. The equations shown above are valid for a single chip or multichip DMD
system. It assumes an illumination distribution of 83.7% on the active array, and 16.3% on the array border.
The sample calculation for a typical projection application is as follows:
QINCIDENT = 2.2 W (measured)
TCERAMIC = 55.0°C (measured)
QELECTRICAL = 0.10 W
QARRAY = 0.10 W + (0.40 × 2.2 W) = 0.98 W
TARRAY = 55.0°C + (0.98 W × 5.4°C/W) = 60.3°C
7.7 Micromirror Power Density Calculation
The calculation of the optical power density of the illumination on the DMD in the different wavelength bands
uses the total measured optical power on the DMD, percent illumination overfill, area of the active array, and
ratio of the spectrum in the wavelength band of interest to the total spectral optical power.
•
•
•
•
•
•
ILLUV = [OPUV-RATIO × QINCIDENT] × 1000 ÷ AILL (mW/cm2)
ILLVIS = [OPVIS-RATIO × QINCIDENT] ÷ AILL (W/cm2)
ILLIR = [OPIR-RATIO × QINCIDENT] × 1000 ÷ AILL (mW/cm2)
ILLBLU = [OPBLU-RATIO × QINCIDENT] ÷ AILL (W/cm2)
ILLBLU1 = [OPBLU1-RATIO × QINCIDENT] ÷ AILL (W/cm2)
AILL = AARRAY ÷ (1 - OVILL) (cm2)
where:
•
•
•
•
•
ILLUV = UV illumination power density on the DMD (mW/cm2)
ILLVIS = VIS illumination power density on the DMD (W/cm2)
ILLIR = IR illumination power density on the DMD (mW/cm2)
ILLBLU = BLU illumination power density on the DMD (W/cm2)
ILLBLU1 = BLU1 illumination power density on the DMD (W/cm2)
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•
•
•
•
•
AILL = illumination area on the DMD (cm2)
QINCIDENT = total incident optical power on DMD (W) (measured)
AARRAY = area of the array (cm 2) (data sheet)
OVILL = percent of total illumination on the DMD outside the array (%) (optical model)
OPUV-RATIO = ratio of the optical power for wavelengths <410 nm to the total optical power in the illumination
spectrum (spectral measurement)
•
•
•
•
OPVIS-RATIO = ratio of the optical power for wavelengths ≥410 and ≤800 nm to the total optical power in the
illumination spectrum (spectral measurement)
OPIR-RATIO = ratio of the optical power for wavelengths >800 nm to the total optical power in the illumination
spectrum (spectral measurement)
OPBLU-RATIO = ratio of the optical power for wavelengths ≥410 and ≤475 nm to the total optical power in the
illumination spectrum (spectral measurement)
OPBLU1-RATIO = ratio of the optical power for wavelengths ≥410 and ≤445 nm to the total optical power in the
illumination spectrum (spectral measurement)
The illumination area varies and depends on the illumination overfill. The total illumination area on the DMD
is the array area and overfill area around the array. The optical model is used to determine the percent of the
total illumination on the DMD that is outside the array (OVILL) and the percent of the total illumination that is on
the active array. From these values the illumination area (AILL) is calculated. The illumination is assumed to be
uniform across the entire array.
From the measured illumination spectrum, the ratio of the optical power in the wavelength bands of interest to
the total optical power is calculated.
Sample calculation:
QINCIDENT = 2.20 W (measured)
AARRAY = (0.6912× 0.3888) = 0.2687 cm2 (data sheet)
OVILL = 16.3% (optical model)
OPUV-RATIO = 0.00021 (spectral measurement)
OPVIS-RATIO = 0.99977 (spectral measurement)
OPIR-RATIO = 0.00002 (spectral measurement)
OPBLU-RATIO = 0.28100 (spectral measurement)
OPBLU1-RATIO = 0.03200 (spectral measurement)
AILL = 0.2687 ÷ (1 - 0.163) = 0.3211 cm2
ILLUV = [0.00021 × 2.20W] × 1000 ÷ 0.3211 cm2 = 1.439 mW/cm2
ILLVIS = [0.99977 × 2.20W] ÷ 0.3211 cm2 = 6.85 W/cm2
ILLIR = [0.00002 × 2.20W] × 1000 ÷ 0.3211 cm2 = 0.137 mW/cm2
ILLBLU = [0.28100 × 2.20W] ÷ 0.3211 cm2 = 1.93 W/cm2
ILLBLU1 = [0.03200 × 2.20W] ÷ 0.3211 cm2 = 0.219 W/cm2
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7.8 Micromirror Landed-On/Landed-Off Duty Cycle
7.8.1 Definition of Micromirror Landed-On and Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the ON state versus the amount of time the same
micromirror is landed in the OFF state.
As an example, a landed duty cycle of 75/25 indicates that the referenced pixel is in the ON state 75% of the
time (and in the OFF state 25% of the time), whereas 25/75 indicates that the pixel is in the OFF state 75% of
the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time.
When assessing landed duty cycle, the time spent switching from the current state to the opposite state is
considered negligible and is thus ignored.
Because a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
nominally add to 100.In practice, image processing algorithms in the DLP chipset can result a total of less that
100.
7.8.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the DMD’s usable life.
It is the symmetry or asymmetry of the landed duty cycle that is relevant. The symmetry of the landed duty cycle
is determined by how close the two numbers (percentages) are to being equal. For example, a landed duty cycle
of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly asymmetrical.
7.8.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD temperature and landed duty cycle interact to affect the usable life of the DMD. This interaction
can be used to reduce the impact that an asymmetrical landed duty cycle has on the useable life of the DMD.
Figure 6-1 describes this relationship. The importance of this curve is that:
•
•
All points along this curve represent the same usable life.
All points above this curve represent lower usable life (and the further away from the curve, the lower the
usable life).
•
All points below this curve represent higher usable life (and the further away from the curve, the higher the
usable life).
In practice, this curve specifies the maximum operating DMD temperature that the DMD should be operated at
for a give long-term average landed duty cycle.
7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the landed duty cycle of a given pixel depends on the image content being
displayed by that pixel.
In the simplest case for example, when the system displays pure-white on a given pixel for a given time period,
that pixel operates very close to a 100/0 landed duty cycle during that time period. Likewise, when the system
displays pure-black, the pixel operates very close to a 0/100 landed duty cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in Table 7-1.
Table 7-1. Grayscale
Value and Landed Duty
Cycle
Nominal
Grayscale
Landed Duty
Value
Cycle
0%
0/100
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Table 7-1. Grayscale
Value and Landed Duty
Cycle (continued)
Nominal
Grayscale
Landed Duty
Value
Cycle
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10/90
20/80
30/70
40/60
50/50
60/40
70/30
80/20
90/10
100/0
To account for color rendition (and continuing to ignore image processing for this example) requires knowing
both the color intensity (from 0% to 100%) for each constituent primary color (red, green, and/or blue) for the
given pixel as well as the color cycle time for each primary color, where color cycle time describes the total
percentage of the frame time that a given primary must be displayed in order to achieve the desired white point.
During a given period of time, the nominal landed duty cycle of a given pixel can be calculated as shown in
Equation 1:
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_%
(1)
×
Blue_Scale_Value)
where
•
•
•
Red_Cycle_% represents the percentage of the frame time that red displays to achieve the desired white
point
Green_Cycle_% represents the percentage of the frame time that green displays to achieve the desired white
point
Blue_Cycle_% represents the percentage of the frame time that blue displays to achieve the desired white
point
For example, assume that the ratio of red, green and blue color cycle times are as listed in Table 7-2 (in order
to achieve the desired white point) then the resulting nominal landed duty cycle for various combinations of red,
green, blue color intensities are as shown in Table 7-3.
Table 7-2. Example Landed Duty Cycle for Full-Color
Pixels
Red Cycle
Percentage
Green Cycle
Percentage
Blue Cycle
Percentage
50%
20%
30%
Table 7-3. Color Intensity Combinations
Nominal
Landed Duty
Cycle
Red Scale
Value
Green Scale
Value
Blue Scale
Value
0%
100%
0%
0%
0%
0%
0%
0/100
50/50
20/80
30/70
100%
0%
0%
0%
100%
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Table 7-3. Color Intensity Combinations (continued)
Nominal
Landed Duty
Cycle
Red Scale
Value
Green Scale
Value
Blue Scale
Value
12%
0%
0%
35%
0%
0%
0%
6/94
7/93
0%
60%
0%
18/82
70/30
50/50
80/20
13/87
25/75
24/76
100/0
100%
0%
100%
100%
0%
100%
100%
0%
100%
12%
0%
35%
35%
0%
60%
60%
100%
12%
100%
100%
The last factor to consider when estimating the landed duty cycle is any applied image processing. In the
DLPC34xx controller family, the two functions which influence the actual landed duty cycle are Gamma and
IntelliBright™, and bitplane sequencing rules.
Gamma is a power function of the form Output_Level = A × Input_LevelGamma, where A is a scaling factor that is
typically set to 1.
In the DLPC34xx controller family, gamma is applied to the incoming image data on a pixel-by-pixel basis. A
typical gamma factor is 2.2, which transforms the incoming data as shown in Figure 7-2.
Figure 7-2. Example of Gamma = 2.2
As shown in Figure 7-2, when the gray scale value of a given input pixel is 40% (before gamma is applied),
then gray scale value is 13% after gamma is applied. Because gamma has a direct impact on the displayed gray
scale level of a pixel, it also has a direct impact on the landed duty cycle of a pixel.
The IntelliBright algorithms content adaptive illumination control (CAIC) and local area brightness boost (LABB)
also apply transform functions on the gray scale level of each pixel.
But while amount of gamma applied to every pixel (of every frame) is constant (the exponent, gamma, is
constant), CAIC and LABB are both adaptive functions that can apply a different amounts of either boost or
compression to every pixel of every frame.
Be sure to account for any image processing which occurs before the controller.
7.8.5
The IntelliBright algorithm content adaptive illumination control (CAIC) and local area brightness boost (LABB)
also apply transform functions on the gray scale level of each pixel.
But while the amount of gamma correction applied to every pixel (of every frame) is constant (the exponent,
gamma, is constant), CAIC and LABB are both adaptive functions that can apply a different amounts of either
boost or compression to every pixel of every frame.
The CAIC and LABB algorithms receive no information regarding any previous gain or boost processing. In
cases where the application performs any processing of the input data before the image reaches the DLPC3478
controller, unexpected behavior such as saturation may occur.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of
two directions, with the primary direction being into a projection or collection optic. Each application depends
primarily on the optical architecture of the system and the format of the data coming into the DLPC3478
controller. The new high-tilt pixel in the side-illuminated DMD increases brightness performance and enables a
smaller system electronics footprint for thickness constrained applications. Applications include
•
Integrated display and 3D depth capture
– Smart phone, tablets, laptop, camera
– Battery-powered mobile accessory
•
•
•
•
3D depth capture: 3D camera, 3D reconstruction, AR/VR, dental scanner
3D machine vision: robotics, metrology, in-line inspection (AOI)
3D biometrics: facial and finger print recognition
Light exposure: 3D printers, programmable spatial and temporal light exposure
DMD power-up and power-down sequencing is strictly controlled by the DLPA200x/DLPA300x. Refer to Section
9 for power-up and power-down specifications. 7212-313BK DMD reliability is specified when used with
DLPC3478 controller and DLPA200x/DLPA300x PMIC/LED driver only.
8.2 Typical Application
DLP3010LC DMD with DLPC3478 controller enables high accuracy and very small form factor 3D depth scanner
products. Figure 8-1 shows a typical 3D depth scanner system block diagram using external pattern streaming
mode.
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1.1 V
1.1 Reg
L3
SYSPWR
L2
DC
Supplies
1.8 V
1.8 V external
L1
DLPA200x
V
LED
1.8 V
VSPI
PROJ_ON
LED_SEL (2)
SPI (4)
PROJ_ON
GPIO_8
SPI1
2
I C
RESETZ
PARKZ
R
LIM
INTZ
1.1 V
Thermistor
Video
Front End
HOST_IRQ
CMP_OUT
HDMI
VDDLP12
VDD
Illumination
optics
Parallel Interface (28)
Flash
DLPC347x
System
Controller
RC_
CHARGE
SPI (4)
SPI0
GPIO_10
Keypad
V
, V
BIAS OFFSET
,
TRIG_OUT_1
TRIG_OUT_2
TSTPT_4
GPIO_7
VCC_18
1.8 V
TI DLP Chipset
Non-TI Device
V
RESET
DMD
VCC_INTF
CTRL
Sub-LVDS DATA
VCC_FLSH
1.8 V
Figure 8-1. Typical Application
8.2.1 Design Requirements
A high-accuracy 3D depth scanner product can be created by using a DLP chipset comprised of DLP3010
DMD, DLPC3478 controller and DLPA200x or DLPA300x PMIC/LED driver. The DLPC3478 simplifies the pattern
generation, the DLPA200x or DLPA300x provides the needed analog functions and the DMD displays the
required patterns for accurate 3D depth scanning.
In addition to the three DLP devices in the chipset, other IC components may be needed. At a minimum, this
design requires a flash device to store the software and firmware to control the DLPC3478 .
Red, green, and blue LEDs typically supply the illumination light that is applied to the DMD. These LEDs are
often contained in three separate packages, but sometimes more than one color of LED die may be in the same
package to reduce the overall size of the pico-projector. In addition to LEDs, other light sources like laser diodes,
vertical-cavity surface-emitting laser (VCSEL) are also supported.
The parallel interface connects the DLPC3478 controller to the host processing for receiving patterns or video
data. Connect an I2C interface to the host processor to send commands to the DLPC3478 controller. The battery
(SYSPWR) and a regulated 1.8-V supply are the only power supplies needed external to the projector in case
of DLPA200x. The DLPA300x supplies 1.8 V without external regulator. A single signal (PROJ_ON) controls the
entire DLP system power. When PROJ_ON is high, the DLP system turns on and when PROJ_ON is low, the
DLPC3478 turns off. When the DLPC3478 is off, the DLP system draws only a few microamperes of current on
SYSPWR. When PROJ_ON is low, the 1.8-V power supply can remain at 1.8 V for use by other sub systems.
When PROJ_ON is low, the DLPA200x or DLPA300x draws no current on the 1.8-V supply.
8.2.2 Detailed Design Procedure
For more information on connecting the DLPC3478, the DLPA200x/DLPA300x, and the DMD, see the reference
design schematic. Based on the reference schematic a small circuit board can be created. An example small
board layout is included in the reference design data base. Layout guidelines should be followed to achieve a
reliable projector.
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The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an optical
OEM who specializes in designing optics for DLP projectors.
8.2.3 Application Curve
This device drives current time-sequentially though the LEDs. As the LED currents through the red, green, and
blue LEDs increases, the brightness of the projector increases. This increase is somewhat non-linear, and the
curve for typical white screen lumens changes with LED currents as shown in Figure 8-2. For the LED currents
shown, assumed that the same current amplitude is applied to the red, green, and blue.
SPACE
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
100
200
300 400
Current (mA)
500
600
700
D001
ILED(red) = ILED(green) = ILED(blue)
Figure 8-2. Luminance vs Current
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9 Power Supply Recommendations
The following power supplies are all required to operate the DMD:
•
•
•
•
•
•
VSS
VBIAS
VDD
VDDI
VOFFSET
VRESET
DMD power-up and power-down sequencing is strictly controlled by the DLPAxxxx device.
CAUTION
For reliable operation of the DMD, the following power supply sequencing requirements must be
followed. Failure to adhere to any of the prescribed power-up and power-down requirements may
affect device reliability. See the DMD power supply sequencing requirements in Figure 9-1.
VBIAS, VDD, VDDI, VOFFSET, and VRESET power supplies must be coordinated during power-up and
power-down operations. Failure to meet any of the below requirements will result in a significant
reduction in the DMD reliability and lifetime. Common ground VSS must also be connected.
9.1 DMD Power Supply Power-Up Procedure
•
During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET voltages are
applied to the DMD.
•
During power-up, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be
within the specified limit shown in Section 6.4. Refer to Table 9-1 for power-up delay requirements.
•
•
During power-up, there is no requirement for the relative timing of VRESET with respect to VBIAS and VOFFSET
Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the
requirements specified in Section 6.1, in Section 6.4, and in Section 9.3.
.
•
During power-up, LPSDR input pins must not be driven high until after VDD /VDDI have settled at operating
voltages listed in Section 6.4.
9.2 DMD Power Supply Power-Down Procedure
•
•
•
•
•
Power-down sequence is the reverse order of the previous power-up sequence. During power-down, VDD and
VDDI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.
During power-down, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be
within the specified limit shown in Section 6.4.
During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS and
VOFFSET
.
Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements specified in Section 6.1, inSection 6.4, and in Section 9.3.
During power-down, LPSDR input pins must be less than VDD /VDDI specified in Section 6.4.
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9.3 Power Supply Sequencing Requirements
DLP Display Controller and
PMIC control start of DMD
operation
DLP Display Controller and PMIC
disable VBIAS, VOFFSET and
VRESET
Mirror Park
Sequence
Note 4
Power Off
VDD / VDDI
VDD / VDDI
VDD / VDDI
VSS
VSS
VBIAS
VBIAS
VBIAS
VDD < VBIAS
< 6 V
VBIAS < 4 V
VSS
VSS
VOFFSET
VOFFSET
VDD < VOFFSET
< 6 V
VOFFSET < 4 V
VOFFSET
VSS
VSS
VSS
VRESET < 0.5 V
VSS
VRESET > - 4 V
VRESET
VRESET
VDD
VRESET
VDD
DMD_DEN_ARSTZ
VSS
VSS
VSS
VSS
INITIALIZATION
VDD
VDD
LS_CLK
VSS
LS_WDATA
VID
VID
D_P(0:3), D_N(0:3)
DCLK_P, DCLK_N
VSS
A. Refer to Table 9-1 and Figure 9-2 for critical power-up sequence delay requirements.
B. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in Section 6.4. OEMs may find that
the most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during
power-down. Refer to Table 9-1 and Figure 9-2 for power-up delay requirements.
C. To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit shown in Section 6.4.
D. When system power is interrupted, the ASIC driver initiates hardware power-down that disables VBIAS, VRESET and VOFFSET after the
Micromirror Park Sequence. Software power-down disables VBIAS, VRESET, and VOFFSET after the Micromirror Park Sequence through
software control.
E. Drawing is not to scale and details are omitted for clarity.
Figure 9-1. Power Supply Sequencing Requirements (Power Up and Power Down)
Table 9-1. Power-Up Sequence Delay Requirement
PARAMETER
MIN
MAX
UNIT
ms
V
tDELAY
Delay requirement from VOFFSET power up to VBIAS power up
2
VOFFSET Supply voltage level during power–up sequence delay (see Figure 9-2)
6
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Table 9-1. Power-Up Sequence Delay Requirement (continued)
PARAMETER
MIN
MAX
UNIT
VBIAS
Supply voltage level during power–up sequence delay (see Figure 9-2)
6
V
12
VOFFSET
8
VDD ≤ VOFFSET ≤ 6 V
4
VSS
0
t
DELAY
20
16
12
8
VBIAS
VDD ≤ VBIAS ≤ 6 V
4
VSS
0
Time
A. Refer to Table 9-1 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay.
Figure 9-2. Power-Up Sequence Delay Requirement
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10 Layout
10.1 Layout Guidelines
There are no specific layout guidelines for the DMD as typically DMD is connected using a board to board
connector to a flex cable. Flex cable provides the interface of data and control signals between the DLPC3478
controller and the 7212-313BK DMD. For detailed layout guidelines refer to the layout design files. Some layout
guideline for the flex cable interface with DMD are:
•
•
•
•
•
•
Match lengths for the LS_WDATA and LS_CLK signals.
Minimize vias, layer changes, and turns for the HS bus signals. Refer Figure 10-1.
Minimum of two 100-nF decoupling capacitor close to VBIAS. Capacitor C6 and C7 in Figure 10-1.
Minimum of two 100-nF decoupling capacitor close to VRST. Capacitor C9 and C8 in Figure 10-1.
Minimum of two 220-nF decoupling capacitor close to VOFS. Capacitor C5 and C4 in Figure 10-1.
Minimum of four 100-nF decoupling capacitor close to VDDI and VDD. Capacitor C1, C2, C3 and C10 in
Figure 10-1.
10.2 Layout Example
Figure 10-1. Power Supply Connections
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Device Nomenclature
DLP3010LC FQK
Package type
Device descriptor
Figure 11-1. Part Number Description
11.1.3 Device Markings
The device marking includes the legible character string GHJJJJK DLP3010LCFQK. GHJJJJK is the lot trace
code. DLP3010LCFQK is the orderable device number.
Lot Trace Code
GHJJJJK
DLP3010LCFQK
Part Marking
Figure 11-2. DMD Marking
11.2 Documentation Support
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Related Links
Table 11-1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 11-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
DLPC3478
DLPA2000
DLPA2005
DLPA3000
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
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Table 11-1. Related Links (continued)
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
DLPA3005
Click here
Click here
Click here
Click here
Click here
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.6 Trademarks
Pico™, IntelliBright™, and TI E2E™ are trademarks of Texas Instruments.
DLP® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
38
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Product Folder Links: DLP3010LC
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLP3010LCFQK
ACTIVE
CLGA
FQK
57
120
RoHS & Green
NI/AU
N / A for Pkg Type
0 to 70
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DLP3010LCFQK
FQK
CLGA
57
120
10 x 12
150
315 135.9 12190
23
31
16.2
Pack Materials-Page 1
DWG NO.
SH
8
5
3
6
1
7
4
1
2512014
REVISIONS
C
COPYRIGHT 2013 TEXAS INSTRUMENTS
UN-PUBLISHED, ALL RIGHTS RESERVED.
NOTES UNLESS OTHERWISE SPECIFIED:
REV
A
DESCRIPTION
DATE
BY
6/6/2013
6/17/2013
4/8/2020
ECO 2133835: INITIAL RELEASE
ECO 2134093: CORRECT WINDOW THK TOL, ZONE B6
ECO 2186947: ADD APERTURE SLOTS PICTORIALLY
BMH
BMH
PPC
1
2
DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY.
B
C
ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION
TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES.
3
4
BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY.
NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC,
AS SHOWN IN SECTION A-A.
D
C
B
A
D
C
B
A
5
ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN IN VIEW C
(SHEET 2). NO ENCAPSULANT IS ALLOWED ON TOP OF THE WINDOW.
6
7
ENCAPSULANT NOT TO EXCEED THE HEIGHT OF THE WINDOW.
DATUM B IS DEFINED BY A DIA. 2.5 PIN, WITH A FLAT ON THE SIDE FACING
TOWARD THE CENTER OF THE ACTIVE ARRAY, AS SHOWN IN VIEW B (SHEET 2).
WHILE ONLY THE THREE DATUM A TARGET AREAS A1, A2, AND A3 ARE USED
FOR MEASUREMENT, ALL 4 CORNERS SHOULD BE CONTACTED, INCLUDING E1,
TO SUPPORT MECHANICAL LOADS.
8
1.1760.05
4X (R0.2)
4
4
+
-
0.3
7
0.1
90° 1°
4
4
(ILLUMINATION
DIRECTION)
4X R0.40.1
4
2X 2.50.075
(2.5)
4
1.25
4
A
A
B
4
3.5
+
-
0.2
0.1
7
+
-
0.2
0.1
2.25
4
4
+
-
0.2
0.1
(1)
0.8
16.4 0.08
4
+
-
0.3
0.1
18.2
(OFF-STATE
DIRECTION)
5 6
2X ENCAPSULANT
D
1.1 0.05
1.403 0.077
(2.183)
3 SURFACES INDICATED
IN VIEW B (SHEET 2)
0.038A
0.02D
1 8
A
8
0.780.063
ACTIVE ARRAY
1.60.1
(1.6)
(2.5)
4
0.4 MIN
TYP.
H
H
(SHEET 3)
(SHEET 3)
0 MIN TYP.
DATE
DRAWN
UNLESS OTHERWISE SPECIFIED
DIMENSIONS ARE IN MILLIMETERS
TOLERANCES:
TEXAS
6/6/2013
6/6/2013
6/7/2013
6/6/2013
6/10/2013
6/6/2013
B. HASKETT
ENGINEER
B. HASKETT
QA/CE
INSTRUMENTS
Dallas Texas
ANGLES 1
TITLE
SECTION A-A
NOTCH OFFSETS
ICD, MECHANICAL, DMD,
.3 720p SERIES 245
(FQK PACKAGE)
2 PLACE DECIMALS 0.25
1 PLACE DECIMALS 0.50
DIMENSIONAL LIMITS APPLY BEFORE PROCESSES
INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME
Y14.5M-1994
P. KONRAD
CM
S. SUSI
THIRD ANGLE
PROJECTION
DWG NO
REV
SIZE
D
0314DA
USED ON
REMOVE ALL BURRS AND SHARP EDGES
PARENTHETICAL INFORMATION FOR REFERENCE ONLY
S. CROFF
APPROVED
R. LONG
2512014
C
NEXT ASSY
SCALE
SHEET
OF
APPLICATION
20:1
1
3
INV11-2006a
5
3
6
1
2
7
8
4
DWG NO.
SH
8
5
7.2
5
3
6
1
7
4
2512014
2
2X (1)
A2
2X 1.176
2X (0.8)
2X 16.4
A3
D
C
B
A
D
C
B
A
4X 1.5
1.25
C
2.5
B
4X (2)
7
(1.1)
VIEW B
A1
8
E1
DATUMS A, B, C, AND E
1.176
16.4
(FROM SHEET 1)
(2.5)
1.25
C
B
3.6
5
VIEW C
ENCAPSULANT MAXIMUM X/Y DIMENSIONS
(FROM SHEET 1)
2X 0 MIN
6
VIEW D
ENCAPSULANT MAXIMUM HEIGHT
DWG NO
REV
SIZE
DRAWN
DATE
TEXAS
6/6/2013
2512014
B. HASKETT
C
D
INSTRUMENTS
Dallas Texas
SCALE
SHEET
OF
2
3
INV11-2006a
3
6
1
2
7
8
4
DWG NO.
SH
8
5
3
6
1
7
4
2512014
3
(6.912)
ACTIVE ARRAY
6.4490.075
4X (0.108)
3
0.9710.05
0.193 0.0635
D
C
B
A
D
C
B
A
B
(6.15)
WINDOW
(3.888)
ACTIVE ARRAY
4.319 0.0635
(ILLUMINATION
DIRECTION)
(2.5)
(4.512)
APERTURE
G
F
5.1790.05
C
1.25
1.784 0.075
2
0.4240.0635
2.961 0.05
7.1390.0635
(7.563)
APERTURE
8.815 0.05
(11.776)
WINDOW
VIEW E
WINDOW AND ACTIVE ARRAY
(FROM SHEET 1)
57X LGA PADS
0.52±0.05 X 0.52±0.05
12X TEST PADS
(0.52 0.05)
0.2ABC
0.1A
BACK INDEX MARK
(42°)
TYP.
(42°)
TYP.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18
19
(0.15) TYP.
A
B
C
D
E
B
(0.075) TYP.
1.25
C
(2.5)
2 X 0.7424
= 1.4848
0.7424
2X (0.7424)
(0.068) TYP.
(0.068) TYP.
(42°) TYP.
(0.7424)
DETAIL G
2.874
18 X 0.7424 = 13.3632
DETAIL F
APERTURE LEFT EDGE
APERTURE RIGHT EDGE
SCALE 60 : 1
VIEW H-H
SCALE 60 : 1
BACK SIDE METALLIZATION
(FROM SHEET 1)
DWG NO
REV
SIZE
DRAWN
DATE
6/6/2013
TEXAS
2512014
B. HASKETT
C
3
D
INSTRUMENTS
Dallas Texas
SCALE
SHEET
OF
3
INV11-2006a
5
3
6
1
2
7
8
4
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