DLP2010AFQJ [TI]

0.20-inch, WVGA DLP® digital micromirror device (DMD) | FQJ | 40 | 0 to 70;


型号：	DLP2010AFQJ
厂家：	TEXAS INSTRUMENTS
描述：	0.20-inch, WVGA DLP® digital micromirror device (DMD) \| FQJ \| 40 \| 0 to 70 光电
文件：	总43页 (文件大小：1738K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLP2010

ZHCSJE6B –FEBRUARY 2019 –REVISED MAY 2022

DLP2010 .2 WVGA DMD

1 特性

3 说明

• 0.2 英寸(5.29mm) 对角线微镜阵列

DLP2010 数字微镜器件 (DMD) 是一款数控微光机电系

统(MOEMS) 空间照明调制器(SLM)。当与适当的光学

系统配合使用时，此 DMD 可显示图像、视频和图案。

此器件是由 DLP2010 DMD 、 DLPC3430 或

DLPC3435 控制器以及 DLPA200x/DLPA3000

PMIC/LED 驱动器组成的芯片组的一个组件。此 DMD

紧凑的物理尺寸适合用于注重小外形尺寸和低功耗的便

携式设备。紧凑的封装与 LED 的小尺寸相得益彰，是

空间受限型光引擎的理想选择。

– 在正交布局中显示854 × 480 像素阵列

– 5.4 微米微镜间距

– ±17° 微镜倾斜度（相对于平坦表面）

– 采用侧面照明，实现最优的效率和光学引擎尺寸

– 偏振无关型铝微镜表面

• 4 位SubLVDS 输入数据总线

• 专用DLPC3430 或DLPC3435 显示控制器以及

DLPA200x/DLPA3000 PMIC 和LED 驱动器，确保

可靠运行

请访问 TI DLP^®Pico^TM显示技术入门页，了解如何开

始使用DLP2010。

2 应用

生态系统包含现成的资源，可帮助用户加快设计周期。

这些资源包括可直接用于量产环境的光学模块、光学模

块制造商和设计公司。

• 产品嵌入式显示屏，包括：

– 平板电脑、移动电话

– 人工智能(AI) 助理、智能音箱

• 控制面板、安防系统和恒温器

• 可穿戴显示器

器件信息

器件型号⁽¹⁾

DLP2010

封装尺寸（标称值）

封装

FQJ (40)

15.9mm × 5.3mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

D_P(0)

VOFFSET

VBIAS

DLPC343x

D_N(0)

Display Controller

D_P(1)

VRESET

D_N(1)

DLPA2000

(PMIC and LED Driver)

600-MHz

D_P(2)

SubLVDS

D_N(2)

DLP2010 DMD

DDR Interface

D_P(3)

D_N(3)

Digital

Micromirror

Device

DCLK_P

DCLK_N

VDDI

VDD

VSS

DMD_DEN_ARSTZ

LS_WDATA

120-MHz

LS_CLK

SDR Interface

LS_RDATA

(System signal routing omitted for clarity)

0.2 WVGA 芯片组

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS123

DLP2010

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ZHCSJE6B –FEBRUARY 2019 –REVISED MAY 2022

Table of Contents

7.5 Optical Interface and System Image Quality

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings........................................ 6

6.2 Storage Conditions..................................................... 7

6.3 ESD Ratings............................................................... 7

6.4 Recommended Operating Conditions.........................7

6.5 Thermal Information....................................................9

6.6 Electrical Characteristics.............................................9

6.7 Timing Requirements................................................ 11

6.8 Switching Characteristics⁽¹⁾..................................... 14

6.9 System Mounting Interface Loads............................ 16

6.10 Physical Characteristics of the Micromirror Array...17

6.11 Micromirror Array Optical Characteristics............... 18

6.12 Window Characteristics.......................................... 20

6.13 Chipset Component Usage Specification............... 20

6.14 Software Requirements.......................................... 20

7 Detailed Description......................................................21

7.1 Overview...................................................................21

7.2 Functional Block Diagram.........................................21

7.3 Feature Description...................................................22

7.4 Device Functional Modes..........................................22

Considerations............................................................ 22

7.6 Micromirror Array Temperature Calculation.............. 23

7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 24

8 Application and Implementation..................................28

8.1 Application Information............................................. 28

8.2 Typical Application.................................................... 28

9 Power Supply Recommendations................................31

9.1 DMD Power Supply Power-Up Procedure................31

9.2 DMD Power Supply Power-Down Procedure........... 31

9.3 Power Supply Sequencing Requirements................ 32

10 Layout...........................................................................34

10.1 Layout Guidelines................................................... 34

10.2 Layout Example...................................................... 34

11 Device and Documentation Support..........................36

11.1 Device Support........................................................36

11.2 Related Links.......................................................... 36

11.3 接收文档更新通知................................................... 36

11.4 支持资源..................................................................37

11.5 Trademarks............................................................. 37

11.6 Electrostatic Discharge Caution..............................37

11.7 术语表..................................................................... 37

12 Mechanical, Packaging, and Orderable

Information.................................................................... 38

4 Revision History

Changes from Revision A (January 2022) to Revision B (May 2022)

Page

• Updated Absolute Maximum Ratings disclosure to the latest TI standard......................................................... 6

• Updated Micromirror Array Optical Characteristics ......................................................................................... 18

• Added Third-Party Products Disclaimer ...........................................................................................................36

Changes from Revision * (February 2019) to Revision A (January 2022)

Page

• 更新了整个文档中的表、图和交叉参考的编号格式.............................................................................................1

• Updated |T_DELTA| MAX from 30°C to 15°C..........................................................................................................7

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5 Pin Configuration and Functions

图5-1. FQJ Package 40-Pin Connector Bottom View

表5-1. Pin Functions –Connector Pins⁽¹⁾

NAME

PACKAGE NET

LENGTH⁽²⁾(mm)

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NO.

DATA INPUTS

D_N(0)

H10

SubLVDS Double

Data, Negative

7.03

7.02

7.00

7.03

D_P(0)

Data, Positive

Data, Negative

Data, Positive

Data, Negative

Data, Positive

Data, Negative

Data, Positive

Clock, Negative

Clock, Positive

D_N(1)

D_P(1)

D_N(2)

D_P(2)

D_N(3)

D_P(3)

DCLK_N

DCLK_P

CONTROL INPUTS

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表5-1. Pin Functions –Connector Pins⁽¹⁾(continued)

NAME

PACKAGE NET

TYPE

SIGNAL

DATA RATE

DESCRIPTION

LENGTH⁽²⁾(mm)

NO.

Asynchronous reset DMD signal. A low

signal places the DMD in reset. A high

signal releases the DMD from reset and

places it in active mode.

DMD_DEN_ARSTZ

G12

LPSDR⁽¹⁾

5.72

LS_CLK

G19

G18

G11

LPSDR

Single

Clock for low-speed interface

3.54

8.11

LS_WDATA

LS_RDATA

POWER

Write data for low-speed interface

Read data for low-speed interface

Supply voltage for positive bias level at

micromirrors

VBIAS⁽³⁾

H17

H13

H18

Power

Supply voltage for HVCMOS core logic.

Includes: supply voltage for stepped high

level at micromirror address electrodes and

supply voltage for offset level at

micromirrors

VOFFSET⁽³⁾

VRESET⁽³⁾

Supply voltage for negative reset level at

micromirrors

VDD⁽³⁾

VDD

VDDI⁽³⁾

VDDI

VSS⁽³⁾

VSS

G20

H14

H15

H16

H19

H20

Power

Ground

Supply voltage for micromirror low voltage

CMOS core logic includes supply voltage

for LPSDR inputs and supply voltage for

normal high level at micromirror address

electrodes.

Supply voltage for SubLVDS receivers

G10 Ground

G13 Ground

G14 Ground

G15 Ground

G16 Ground

G17 Ground

VSS

Ground. Common return for all power.

VSS

Ground

VSS

H11 Ground

H12 Ground

VSS

(1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC

Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.

(2) Net trace lengths inside the package:

Relative dielectric constant for the FQJ ceramic package is 9.8.

Propagation speed = 11.8 / sqrt(9.8) = 3.769 inches/ns.

Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.

(3) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.

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表5-2. Pin Functions –Test Pads

NUMBER

SYSTEM BOARD

NUMBER

SYSTEM BOARD

Do not connect

D17

D18

Do not connect

E17

E18

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

Do not connect

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

B17

B18

Do not connect

C17

C18

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6 Specifications

6.1 Absolute Maximum Ratings

See ⁽¹⁾

MIN

MAX

UBIT

for LVCMOS core logic⁽²⁾

Supply voltage for LPSDR low speed interface

VDD

2.3

–0.5

VDDI

for SubLVDS receivers⁽²⁾

2.3

10.6

–0.5

–15

VOFFSET

for HVCMOS and micromirror electrode^{(2) (3)}

for micromirror electrode⁽²⁾

VBIAS

Supply voltage

VRESET

for micromirror electrode⁽²⁾

0.5

delta (absolute value)⁽⁴⁾

0.3

| VDDI–VDD |

| VBIAS–VOFFSET |

| VBIAS–VRESET |

for other inputs LPSDR⁽²⁾

delta (absolute value)⁽⁵⁾

delta (absolute value)⁽⁶⁾

VDD + 0.5

VDDI + 0.5

810

–0.5

Input voltage

Input pins

for other inputs SubLVDS^{(2) (7)}

| VID |

IID

SubLVDS input differential voltage (absolute value)⁽⁷⁾

SubLVDS input differential current

8.1

Clock frequency for low speed interface LS_CLK

Clock frequency for high speed interface DCLK

Temperature –operational⁽⁸⁾

130

ƒ_clock

Clock frequency

MHz

620

–20

–40

T_ARRAYand T_WINDOW

Temperature –non-operational⁽⁸⁾

Dew Point Temperature - operating and non-operating (non-

condensing)

Environmental

°C

T_DP

|T_DELTA

Absolute Temperature delta between any point on the

window edge and the ceramic test point TP1⁽⁹⁾

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:

VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET.

(3) VOFFSET supply transients must fall within specified voltages.

(4) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.

(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current

draw.

(6) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current

draw.

(7) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential

inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(8) The highest temperature of the active array (as calculated by the 节7.6), or of any point along the Window Edge as defined in 图7-1.

The locations of thermal test points TP2 and TP3 in 图7-1 are intended to measure the highest window edge temperature. If a

particular application causes another point on the window edge to be at a higher temperature, that point should be used.

(9) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图

7-1. The window test points TP2 and TP3 shown in 图7-1 are intended to result in the worst case delta. If a particular application

causes another point on the window edge to result in a larger delta temperature, that point should be used.

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6.2 Storage Conditions

applicable for the DMD as a component or non-operational in a system

MIN

MAX

UNIT

°C

T_DMD

DMD storage temperature

–40

T_DP-AVG

T_DP-ELR

CT_ELR

Average dew point temperature, (non-condensing)⁽¹⁾

Elevated dew point temperature range, (non-condensing)⁽²⁾

Cumulative time in elevated dew point temperature range

°C

Months

(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total

cumulative time of CT_ELR

6.3 ESD Ratings

VALUE

UNIT

V_(ESD)Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)^{(1) (2) (3)}

MIN

NOM

MAX

UNIT

SUPPLY VOLTAGE RANGE⁽⁴⁾

Supply voltage for LVCMOS core logic

Supply voltage for LPSDR low-speed

interface

VDD

1.65

1.8

1.95

VDDI

Supply voltage for SubLVDS receivers

1.65

9.5

1.8

1.95

10.5

Supply voltage for HVCMOS and micromirror

electrode⁽⁵⁾

VOFFSET

VBIAS

Supply voltage for mirror electrode

17.5

18.5

–13.5

0.3

VRESET

Supply voltage for micromirror electrode

Supply voltage delta (absolute value)⁽⁶⁾

Supply voltage delta (absolute value)⁽⁷⁾

Supply voltage delta (absolute value)⁽⁸⁾

–14.5

–14

|VDDI–VDD|

10.5

|VBIAS–VOFFSET|

|VBIAS–VRESET|

CLOCK FREQUENCY

Clock frequency for low speed interface

LS_CLK⁽⁹⁾

108

120

MHz

ƒ_clock

Clock frequency for high speed interface

DCLK⁽¹⁰⁾

300

600

Duty cycle distortion DCLK

44%

56%

SUBLVDS INTERFACE⁽¹⁰⁾

SubLVDS input differential voltage (absolute

value) 图6-8, 图6-9

| V_ID

V_CM

150

250

900

350

700

575

1100

1225

110

Ω

Common mode voltage 图6-8, 图6-9

SubLVDS voltage 图6-8, 图6-9

V_SUBLVDS

Z_LINE

Line differential impedance (PWB/trace)

100

Internal differential termination resistance 图

6-10

Z_IN

120

Ω

6.35

152.4

100-Ωdifferential PCB trace

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6.4 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)^{(1) (2) (3)}

MIN

NOM

MAX

UNIT

ENVIRONMENTAL

40 to

70⁽¹³⁾

Array Temperature –long-term

–20

–10

operational^{(11) (12) (13) (14)}

Array Temperature - short-term operational,

–10

25 hr max^{(12) (15)}

T_ARRAY

°C

Array Temperature - short-term operational,

500 hr max^{(12) (15)}

Array Temperature –short-term operational,

500 hr max^{(12) (15)}

Absolute Temperature difference between

|T_DELTA

T_WINDOW

T_DP-AVG

any point on the window edge and the

ceramic test point TP1 ⁽¹⁶⁾

Window temperature –operational^{(11) (17)}

°C

Average dew point temperature (non-

condensing)⁽¹⁸⁾

Elevated dew point temperature range (non-

condensing)⁽¹⁹⁾

T_DP-ELR

°C

Cumulative time in elevated dew point

temperature range

CT_ELR

ILL_UV

ILL_VIS

Months

Illumination wavelengths < 420 nm⁽¹¹⁾

0.68 mW/cm²

Thermally

limited

10 mW/cm²

55 deg

Illumination wavelengths between 420 nm

and 700 nm

ILL_IR

ILL_θ

Illumination wavelengths > 700 nm

Illumination marginal ray angle⁽²⁰⁾

(1) 节6.4 are applicable after the DMD is installed in the final product.

(2) The functional performance of the device specified in this datasheet is achieved when operating the device within the limits defined by

the 节6.4. No level of performance is implied when operating the device above or below the 节6.4 limits.

(3) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET.

(4) All voltage values are with respect to the ground pins (VSS).

(5) VOFFSET supply transients must fall within specified maximum voltages.

(6) To prevent excess current, the supply voltage delta |VDDI –VDD| must be less than specified limit.

(7) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than specified limit.

(8) To prevent excess current, the supply voltage delta |VBIAS –VRESET| must be less than specified limit.

(9) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.

(10) Refer to the SubLVDS timing requirements in 节6.7.

(11) Simultaneous exposure of the DMD to the maximum 节6.4 for temperature and UV illumination will reduce device lifetime.

(12) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1

(TP1) shown in 图7-1 and the Package Thermal Resistance using 节7.6.

(13) Per 图6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD

experiences in the end application. Refer to 节7.7 for a definition of micromirror landed duty cycle.

(14) Long-term is defined as the usable life of the device

(15) Short-term is the total cumulative time over the useful life of the device.

(16) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge shown in 图7-1.

The window test points TP2 and TP3 shown in 图7-1 are intended to result in the worst case delta temperature. If a particular

application causes another point on the window edge to result in a larger delta temperature, that point should be used.

(17) Window temperature is the highest temperature on the window edge shown in 图7-1. The locations of thermal test points TP2 and

TP3 in 图7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the

window edge to result in a larger delta temperature, that point should be used.

(18) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(19) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total

cumulative time of CT_ELR

(20) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors

(POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily

been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not

been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM)

will contribute to thermal limitations described in this document, and may negatively affect lifetime.

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0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50

90/10 85/15 80/20 75/25 70/30 65/35 60/40 55/45

100/0 95/5

D001

Micromirror Landed Duty Cycle

图6-1. Maximum Recommended Array Temperature –Derating Curve

6.5 Thermal Information

DLP2010

FQJ Package

40 PINS

THERMAL METRIC⁽¹⁾

UNIT

Thermal resistance Active area to test point 1 (TP1)⁽¹⁾

7.9

°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in the 节6.4. The total heat load on the DMD is largely driven by the

incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and

electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window

clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS⁽²⁾

MIN

TYP

MAX UNIT

CURRENT

VDD = 1.95 V

34.7

I_DD

Supply current: VDD^{(3) (4)}

Supply current: VDDI^{(3) (4)}

Supply current: VOFFSET^{(5) (6)}

Supply current: VBIAS^{(5) (6)}

Supply current: VRESET⁽⁶⁾

VDD = 1.8 V

27.5

6.6

0.9

0.2

VDDI = 1.95 V

9.4

I_DDI

VDD = 1.8 V

VOFFSET = 10.5 V

VOFFSET = 10 V

VBIAS = 18.5 V

VBIAS = 18 V

1.7

I_OFFSET

0.4

I_BIAS

VRESET = –14.5 V

VRESET = –14 V

I_RESET

1.2

POWER⁽⁷⁾

P_DD

VDD = 1.95 V

VDD = 1.8 V

67.7

Supply power dissipation: VDD^{(3) (4)}

Supply power dissipation: VDDI^{(3) (4)}

Supply power dissipation: VOFFSET^{(5) (6)}

Supply power dissipation: VBIAS^{(5) (6)}

49.5

11.9

VDDI = 1.95 V

VDD = 1.8 V

18.3

P_DDI

VOFFSET = 10.5 V

VOFFSET = 10 V

VBIAS = 18.5 V

VBIAS = 18 V

17.9

P_OFFSET

7.4

P_BIAS

3.6

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MAX UNIT

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6.6 Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS⁽²⁾

VRESET = –14.5 V

VRESET = –14 V

MIN

TYP

P_RESET

Supply power dissipation: VRESET⁽⁶⁾

Supply power dissipation: Total

16.8

90.8

P_TOTAL

LPSDR INPUT⁽⁸⁾

140.3 mW

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

∆V_T

DC input high voltage⁽⁹⁾

0.7 × VDD

–0.3

VDD + 0.3

DC input low voltage⁽⁹⁾

AC input high voltage⁽⁹⁾

AC input low voltage⁽⁹⁾

Hysteresis ( V_T+–V_T–

Low–level input current

0.3 × VDD

VDD + 0.3

0.2 × VDD

0.4 × VDD

0.8 × VDD

–0.3

0.1 × VDD

)

图6-11

I_IL

VDD = 1.95 V; V_I= 0 V

VDD = 1.95 V; V_I= 1.95 V

–100

I_IH

100

High–level input current

LPSDR OUTPUT⁽¹⁰⁾

V_OH

V_OL

DC output high voltage

DC output low voltage

0.8 × VDD

I_OH= –2 mA

I_OL= 2 mA

0.2 × VDD

CAPACITANCE

Input capacitance LPSDR

ƒ= 1 MHz

C_IN

Input capacitance SubLVDS

Output capacitance

C_OUT

ƒ= 1 MHz; (480 × 108)

micromirrors

C_RESET

Reset group capacitance

113

(1) Device electrical characteristics are over 节6.4 unless otherwise noted.

(2) All voltage values are with respect to the ground pins (VSS).

(3) To prevent excess current, the supply voltage delta |VDDI –VDD| must be less than specified limit.

(4) Supply power dissipation based on non–compressed commands and data.

(5) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than specified limit.

(6) Supply power dissipation based on 3 global resets in 200 µs.

(7) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.

(8) LPSDR specifications are for pins LS_CLK and LS_WDATA.

(9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC

Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.

(10) LPSDR specification is for pin LS_RDATA.

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6.7 Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

MIN

NOM

MAX UNIT

LPSDR

Rise slew rate⁽¹⁾

Fall slew rate⁽¹⁾

Rise slew rate⁽²⁾

Fall slew rate⁽²⁾

Cycle time LS_CLK,

t_R

V/ns

(30% to 80%) × VDD, 图6-3

(70% to 20%) × VDD, 图6-3

(20% to 80%) × VDD, 图6-3

(80% to 20%) × VDD, 图6-3

图6-2

t_F

t_R

0.25

7.7

3.1

t_F

t_C

8.3

t_W(H)

Pulse duration LS_CLK

high

50% to 50% reference points, 图6-2

t_W(L)

Pulse duration LS_CLK

low

3.1

t_SU

1.5

3.0

Setup time

LS_WDATA valid before LS_CLK ↑, 图6-2

LS_WDATA valid after LS_CLK ↑, 图6-2

Setup time + Hold time, 图6-2

t _H

Hold time

Window time^{(1) (3)}

t_WINDOW

t_DERATING

For each 0.25 V/ns reduction in slew rate below

1 V/ns, 图6-5

0.35

Window time derating^{(1) (3)}

SubLVDS

t_R

Rise slew rate

0.7

V/ns

20% to 80% reference points, 图6-4

80% to 20% reference points, 图6-4

图6-6

t_F

Fall slew rate

t_C

Cycle time LS_CLK,

Pulse duration DCLK high

Pulse duration DCLK low

1.61

0.71

1.67

t_W(H)

t_W(L)

50% to 50% reference points, 图6-6

D(0:3) valid before

DCLK ↑or DCLK ↓, 图6-6

t_SU

Setup time

D(0:3) valid after

DCLK ↑or DCLK ↓, 图6-6

t _H

Hold time

t_WINDOW

Window time

3.0

Setup time + Hold time, 图6-6, 图6-7

t_LVDS-

Power-up receiver⁽⁴⁾

2000

ENABLE+REFGEN

(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in 图6-3.

(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in 图6-3.

(3) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.

(4) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.

w(L)

w(H)

50%

LS_CLK

SU|

50%

LS_WDATA

WINDOW|

A. Low-speed interface is LPSDR and adheres to the 节6.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low

Power Double Data Rate (LPDDR) JESD209B.

图6-2. LPSDR Switching Parameters

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LS_CLK, LS_WDATA

1.0 * VDD

DMD_DEN_ARSTZ

1.0 * VDD

0.8 * VDD

V_IH(AC)

V_IH(DC)

0.8 * VDD

0.7 * VDD

V_IL(DC)

V_IL(AC)

0.3 * VDD

0.2 * VDD

0.0 * VDD

t_r

t_f

t_r

t_f

图6-3. LPSDR Input Rise and Fall Slew Rate

V_{DCLK_P}, V_{DCLK_N}

V_{D_P(0:7)}, V_{D_N(0:7)}

1.0 * V

0.8 * V

0.2 * V

0.0 * V

t_r

t_f

图6-4. SubLVDS Input Rise and Fall Slew Rate

V_{IH MIN}

LS_CLK Midpoint

V_{IL MAX}

t_SU

t_H

V_{IH MIN}

LS_WDATA Midpoint

V_{IL MAX}

t_WINDOW

V_{IH MIN}

Midpoint

LS_CLK

V_{IL MAX}

t_DERATING

t_H

t_SU

V_{IH MIN}

Midpoint

V_{IL MAX}

LS_WDATA

t_WINDOW

图6-5. Window Time Derating Concept

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W(H)

W(L)

DCLK_P

50%

DCLK_N

SU|

D_P(0:3)

50%

D_N(0:3)

WINDOW|

图6-6. SubLVDS Switching Parameters

(1)

WINDOW

DCLK_P

50%

DCLK_N

¼ t

D_P(0:3)

50%

D_N(0:3)

(1) High-speed training scan window

Note: Refer to 节7.3.3 for details.

图6-7. High-Speed Training Scan Window

(V_IP+ V_IN

)

V_CM

DCLK_P, D_P(0:3)

DCLK_N, D_N(0:3)

V_ID

SubLVDS

Receiver

V_CM

V_IP

V_IN

图6-8. SubLVDS Voltage Parameters

1.255 V

LVDS(max)

LVDS(min)

0.575 V

A. V_SubLVDS(max)= V_CM(max)+ | ½ × V_ID(max)

B. V_SubLVDS(min)= V_CM(min)–| ½ × V_ID(max)

图6-9. SubLVDS Waveform Parameters

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DCLK_P, D_P(0:3)

ESD

Internal

Termination

SubLVDS

Receiver

DCLK_N, D_N(0:3)

图6-10. SubLVDS Equivalent Input Circuit

LS_CLK and LS_WDATA

T+

Tœ

Time

图6-11. LPSDR Input Hysteresis

LS_CLK

LS_WDATA

Stop

Start

t_PD

LS_RDATA

Acknowledge

图6-12. LPSDR Read Out

Data Sheet Timing Reference Point

Device Pin

Tester Channel

Output Under Test

A. See 节7.3.4 for more information.

图6-13. Test Load Circuit for Output Propagation Measurement

6.8 Switching Characteristics⁽¹⁾

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output propagation, Clock to Q, rising edge of

LS_CLK input to LS_RDATA output. 图6-12

C_L= 45 pF

t_PD

Slew rate, LS_RDATA

0.5

V/ns

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Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output duty cycle distortion, LS_RDATA

40%

60%

(1) Device electrical characteristics are over 节6.4 unless otherwise noted.

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6.9 System Mounting Interface Loads

PARAMETER

MIN

NOM

MAX

UNIT

Connector area (see 图6-14)

Maximum system mounting

interface load to be applied to the:

DMD mounting area uniformly distributed over 4

areas (see 图6-14)

100

5ꢀšµu Z![ !Œꢁꢀ

(3 places)

5ꢀšµu Z9[ !Œꢁꢀ

(1 place)

DMD Mounting Area

(4 ‰oꢀꢂꢁ• }‰‰}•]šꢁ 5ꢀšµu• Z![ ꢀvꢃ Z9[)

Connector Area

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6.10 Physical Characteristics of the Micromirror Array

PARAMETER

VALUE

854

UNIT

micromirrors

µm

Number of active columns

Number of active rows

See 图6-15

480

See 图6-15

Micromirror (pixel) pitch

5.4

See 图6-16

Micromirror active array width

Micromirror active array height

Micromirror active border

4.6116

2.592

Micromirror pitch × number of active columns; see 图6-15

Micromirror pitch × number of active rows; see 图6-15

Pond of micromirror (POM)⁽¹⁾

micromirrors/side

(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.

These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical

bias to tilt toward OFF.

Width .

Mirror 479

Mirror 478

Mirror 477

Mirror 476

Illumination

854 × 480 mirrors

Height

Mirror 3

Mirror 2

Mirror 1

Mirror 0

图6-15. Micromirror Array Physical Characteristics

e°

图6-16. Mirror (Pixel) Pitch

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6.11 Micromirror Array Optical Characteristics

PARAMETER

Micromirror tilt angle

TEST CONDITIONS

MIN

NOM

MAX

UNIT

DMD landed state⁽¹⁾

degrees

Micromirror tilt angle tolerance^{(2) (3) (4) (5)}

1.4

–1.4

Landed ON state

180

270

Micromirror tilt direction^{(6) (7)}

degrees

Landed OFF state

Typical Performance

Micromirror crossover time⁽⁸⁾

Micromirror switching time⁽⁹⁾

μs

Bright pixel(s) in active

Gray 10 Screen ⁽¹²⁾

area ⁽¹¹⁾

Bright pixel(s) in the

POM ⁽¹³⁾

Image performance⁽¹⁰⁾Dark pixel(s) in the

active area ⁽¹⁴⁾

micromirrors

White Screen

Any Screen

Adjacent pixel(s) ⁽¹⁵⁾

Unstable pixel(s) in

active area ⁽¹⁶⁾

(1) Measured relative to the plane formed by the overall micromirror array.

(2) Additional variation exists between the micromirror array and the package datums.

(3) Represents the landed tilt angle variation relative to the nominal landed tilt angle.

(4) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different

devices.

(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some

system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field

reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result

in colorimetry variations, system efficiency variations or system contrast variations.

(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of

the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON state

direction. A binary value of 0 results in a micromirror landing in the OFF state direction. See 图6-17

(7) Micromirror tilt direction is measured as in a typical polar coordinate system: Measuring counter-clockwise from a 0° reference which is

aligned with the +X Cartesian axis.

(8) The time required for a micromirror to nominally transition from one landed state to the opposite landed state.

(9) The minimum time between successive transitions of a micromirror.

(10) Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions:

Test set degamma shall be linear

Test set brightness and contrast shall be set to nominal

The diagonal size of the projected image shall be a minimum of 20 inches

The projections screen shall be 1X gain

The projected image shall be inspected from a 38 inch minimum viewing distance

The image shall be in focus during all image quality tests

(11) Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels

(12) Gray 10 screen definition: All areas of the screen are colored with the following settings:

Red = 10/255

Green = 10/255

Blue = 10/255

(13) POM definition: Rectangular border of off-state mirrors surrounding the active area

(14) Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels

(15) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster

(16) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable

pixel appears to be flickering asynchronously with the image

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(843, 479)

Incident

illumination

light path

On-state

landed edge

Tilted axis of

pixel rotation

Off-state

landed edge

(0, 0)

Off-state

light path

图6-17. Landed Pixel Orientation and Tilt

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6.12 Window Characteristics

PARAMETER⁽¹⁾

MIN

NOM

Corning Eagle XG

1.5119

Window material designation

Window refractive index

Window aperture⁽²⁾

at wavelength 546.1 nm

See ⁽²⁾

See ⁽³⁾

Illumination overfill⁽³⁾

Window transmittance, single-pass

through both surfaces and glass

Minimum within the wavelength range

420 to 680 nm. Applies to all angles 0° to

30° AOI.

97%

Window Transmittance, single-pass

through both surfaces and glass

Average over the wavelength range 420

to 680 nm. Applies to all angles 30° to

45° AOI.

(1) See 节7.5 for more information.

(2) See the package mechanical characteristics for details regarding the size and location of the window aperture.

(3) The active area of the DLP2010 device is surrounded by an aperture on the inside of the DMD window surface that masks structures

of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating

the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. The

illumination optical system should be designed to limit light flux incident outside the active array to less than 10% of the average flux

level in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of overfill light

on the outside of the active array may cause system performance degradation.

6.13 Chipset Component Usage Specification

The DLP2010 is a component of one or more TI DLP^®chipsets. Reliable function and operation of the DLP2010

requires that it be used in conjunction with the other components of the applicable DLP chipset, including those

components that contain or implement TI DMD control technology. TI DMD control technology is the TI

technology and devices for operating or controlling a DLP DMD.

备注

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system

operating conditions exceeding limits described previously.

6.14 Software Requirements

CAUTION

The DLP2010 DMD has mandatory software requirements. Refer to Software Requirements for TI

DLP^®Pico^®TRP Digital Micromirror Devices application report for additional information. Failure to

use the specified software will result in failure at power up.

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7 Detailed Description

7.1 Overview

The DLP2010 is a 0.2 inch diagonal spatial light modulator of aluminum micromirrors. Pixel array size is 854

columns by 480 rows in a square grid pixel arrangement. The electrical interface is sub low voltage differential

signaling (SubLVDS) data.

This DMD is part of the chipset that is composed of the DMD, DLPC3430 or DLPC3435 display controller and

the DLPA200x/DLPA3000 PMIC and LED driver. To ensure reliable operation, the DMD must always be used

with the DLPC3430 or DLPC3435 display controller and the DLPA200x/DLPA3000 PMIC and LED driver.

7.2 Functional Block Diagram

High-Speed

Interface

Control

Misc

Column Write

Bit Lines

(0,0)

Word

Lines

Voltages

Voltage

Generators

SRAM

Row

(479,853)

Control

Column Read

Control

Low-Speed

Interface

Details omitted for clarity.

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7.3 Feature Description

7.3.1 Power Interface

The power management component DLPA200x/DLPA3000, contains three 3 regulated DC supplies for the DMD

reset circuitry: VBIAS, VRESET and VOFFSET, as well as the two regulated DC supplies for the DLPC3430 or

DLPC3435 controller.

7.3.2 Low-Speed Interface

The low speed interface handles instructions that configure the DMD and control reset operation. LS_CLK is the

low–speed clock, and LS_WDATA is the low speed data input.

7.3.3 High-Speed Interface

The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed

DDR transfer and compression techniques to save power and time. The high-speed interface uses differential

SubLVDS receivers for inputs, with a dedicated clock.

7.3.4 Timing

The data sheet provides timing test results at the device pin. For output timing analysis, the tester pin electronics

and its transmission line effects must be considered. Test Load Circuit for Output Propagation Measurement

shows an equivalent test load circuit for the output under test. Timing reference loads are not intended as a

precise representation of any particular system environment or depiction of the actual load presented by a

production test. TI recommends that system designers use IBIS or other simulation tools to correlate the timing

reference load to a system environment. The load capacitance value stated is intended for characterization and

measurement of AC timing signals only. This load capacitance value does not indicate the maximum load the

device is capable of driving.

7.4 Device Functional Modes

DMD functional modes are controlled by the DLPC3430 or DLPC3435 controller. See the DLPC3430 or

DLPC3435 controller data sheet or contact a TI applications engineer.

7.5 Optical Interface and System Image Quality Considerations

备注

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system

operating conditions exceeding limits described previously.

7.5.1 Optical Interface and System Image Quality

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous component and system design parameters.

Optimizing system optical performance and image quality strongly relate to optical system design parameter

trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical

performance is contingent on compliance to the optical system operating conditions described in the following

sections.

7.5.1.1 Numerical Aperture and Stray Light Control

The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area is

typically the same. Ensure this angle does not exceed the nominal device micromirror tilt angle unless

appropriate apertures are added in the illumination or projection pupils to block out flat-state and stray light from

the projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from any

other light path, including undesirable flat–state specular reflections from the DMD window, DMD border

structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture

exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger

than the illumination numerical aperture angle (and vice versa), contrast degradation and objectionable artifacts

in the display border and/or active area may occur.

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7.5.1.2 Pupil Match

The optical and image quality specifications assume that the exit pupil of the illumination optics is nominally

centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable

artifacts in the display border and/or active area. These artifacts may require additional system apertures to

control, especially if the numerical aperture of the system exceeds the pixel tilt angle.

7.5.1.3 Illumination Overfill

The active area of the device is surrounded by an aperture on the inside DMD window surface that masks

structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating

conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window

aperture opening and other surface anomalies that may be visible on the screen. Be sure to design an

illumination optical system that limits light flux incident anywhere on the window aperture from exceeding

approximately 10% of the average flux level in the active area. Depending on the particular optical architecture,

overfill light may require further reduction below the suggested 10% level in order to be acceptable.

7.6 Micromirror Array Temperature Calculation

Illumination

Direction

Off-state

Light

图7-1. DMD Thermal Test Points

Micromirror array temperature can be computed analytically from measurement points on the outside of the

package, the ceramic package thermal resistance, the electrical power dissipation, and the illumination heat

load. The relationship between micromirror array temperature and the reference ceramic temperature is provided

by the following equations:

T_ARRAY= T_CERAMIC+ (Q_ARRAY× R_{ARRAY–TO–CERAMIC}

Q_ARRAY= Q_ELECTRICAL+ Q_ILLUMINATION

Q_ILLUMINATION= (C_L2W× SL)

)

(1)

(2)

(3)

where

• T_ARRAY= Computed DMD array temperature (°C)

• T_CERAMIC= Measured ceramic temperature (°C), TP1 location in DMD Thermal Test Points

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• R_{ARRAY–TO–CERAMIC}= DMD package thermal resistance from array to outside ceramic (°C/W) specified in

Thermal Information

• Q_ARRAY= Total DMD power; electrical plus absorbed (calculated) (W)

• Q_ELECTRICAL= Nominal DMD electrical power dissipation (W)

• C_L2W= Conversion constant for screen lumens to absorbed optical power on the DMD (W/lm) specified below

• SL = Measured ANSI screen lumens (lm)

Electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating

frequencies. A nominal electrical power dissipation to use when calculating array temperature is 0.07 W.

Absorbed optical power from the illumination source varies and depends on the operating state of the

micromirrors and the intensity of the light source. Equation 1 through Equation 1 are valid for a 1-chip DMD

system with total projection efficiency through the projection lens from DMD to the screen of 87%.

The conversion constant CL2W is based on the DMD micromirror array characteristics. It assumes a spectral

efficiency of 300 lm/W for the projected light and illumination distribution of 83.7% on the DMD active array, and

16.3% on the DMD array border and window aperture. The conversion constant is calculated to be 0.00266

W/lm.

The following is a sample calculation for typical projection application:

T_CERAMIC= 55°C (measured)

SL = 150 lm (measured)

Q_ELECTRICAL= 0.070 W

CL2W = 0.00266 W/lm

Q_ARRAY= 0.070 W + (0.00266 W/lm × 150 lm) = 0.469 W

T_ARRAY= 55°C + (0.469 W × 7.9°C/W) = 58.7°C

7.7 Micromirror Landed-On/Landed-Off Duty Cycle

7.7.1 Definition of Micromirror Landed-On and Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a

percentage) that an individual micromirror is landed in the ON state versus the amount of time the same

micromirror is landed in the OFF state.

As an example, a landed duty cycle of 75/25 indicates that the referenced pixel is in the ON state 75% of the

time (and in the OFF state 25% of the time), whereas 25/75 indicates that the pixel is in the OFF state 75% of

the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time.

When assessing landed duty cycle, the time spent switching from the current state to the opposite state is

considered negligible and is thus ignored.

Because a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)

nominally add to 100.In practice, image processing algorithms in the DLP chipset can result a total of less that

100.

7.7.2 Landed Duty Cycle and Useful Life of the DMD

Knowing the long-term average landed duty cycle (of the end product or application) is important because

subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric

landed duty cycle for a prolonged period of time can reduce the DMD’s usable life.

It is the symmetry or asymmetry of the landed duty cycle that is relevant. The symmetry of the landed duty cycle

is determined by how close the two numbers (percentages) are to being equal. For example, a landed duty cycle

of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly asymmetrical.

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7.7.3 Landed Duty Cycle and Operational DMD Temperature

Operational DMD temperature and landed duty cycle interact to affect the usable life of the DMD. This interaction

can be used to reduce the impact that an asymmetrical landed duty cycle has on the useable life of the DMD. 图

6-1 describes this relationship. The importance of this curve is that:

• All points along this curve represent the same usable life.

• All points above this curve represent lower usable life (and the further away from the curve, the lower the

usable life).

• All points below this curve represent higher usable life (and the further away from the curve, the higher the

usable life).

In practice, this curve specifies the maximum operating DMD temperature that the DMD should be operated at

for a give long-term average landed duty cycle.

7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application

During a given period of time, the landed duty cycle of a given pixel depends on the image content being

displayed by that pixel.

In the simplest case for example, when the system displays pure-white on a given pixel for a given time period,

that pixel operates very close to a 100/0 landed duty cycle during that time period. Likewise, when the system

displays pure-black, the pixel operates very close to a 0/100 landed duty cycle.

Between the two extremes (ignoring for the moment color and any image processing that may be applied to an

incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in 表7-1.

表7-1. Grayscale Value

and Landed Duty Cycle

Nominal

Grayscale

Landed Duty

Value

Cycle

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0/100

10/90

20/80

30/70

40/60

50/50

60/40

70/30

80/20

90/10

100/0

To account for color rendition (and continuing to ignore image processing for this example) requires knowing

both the color intensity (from 0% to 100%) for each constituent primary color (red, green, and/or blue) for the

given pixel as well as the color cycle time for each primary color, where color cycle time describes the total

percentage of the frame time that a given primary must be displayed in order to achieve the desired white point.

During a given period of time, the nominal landed duty cycle of a given pixel can be calculated as shown in 方程

式4:

Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_% (4)

Blue_Scale_Value)

where

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• Red_Cycle_% represents the percentage of the frame time that red displays to achieve the desired white

point

• Green_Cycle_% represents the percentage of the frame time that green displays to achieve the desired white

point

• Blue_Cycle_% represents the percentage of the frame time that blue displays to achieve the desired white

point

For example, assume that the ratio of red, green and blue color cycle times are as listed in 表 7-2 (in order to

achieve the desired white point) then the resulting nominal landed duty cycle for various combinations of red,

green, blue color intensities are as shown in 表7-3.

表7-2. Example Landed Duty Cycle for Full-Color

Pixels

Red Cycle

Percentage

Green Cycle

Percentage

Blue Cycle

Percentage

50%

20%

30%

表7-3. Color Intensity Combinations

Nominal

Landed Duty

Cycle

Red Scale

Value

Green Scale

Value

Blue Scale

Value

100%

0/100

50/50

20/80

30/70

6/94

100%

12%

35%

7/93

60%

18/82

70/30

50/50

80/20

13/87

25/75

24/76

100/0

100%

12%

35%

60%

100%

12%

100%

The last factor to consider when estimating the landed duty cycle is any applied image processing. In the

DLPC34xx controller family, the two functions which influence the actual landed duty cycle are Gamma and

IntelliBright^™, and bitplane sequencing rules.

Gamma is a power function of the form Output_Level = A × Input_Level^Gamma, where A is a scaling factor that is

typically set to 1.

In the DLPC34xx controller family, gamma is applied to the incoming image data on a pixel-by-pixel basis. A

typical gamma factor is 2.2, which transforms the incoming data as shown in 图7-2.

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100

Gamma = 2.2

Input Level (%)

90 100

D002

图7-2. Example of Gamma = 2.2

As shown in 图7-2, when the gray scale value of a given input pixel is 40% (before gamma is applied), then gray

scale value is 13% after gamma is applied. Because gamma has a direct impact on the displayed gray scale

level of a pixel, it also has a direct impact on the landed duty cycle of a pixel.

The IntelliBright algorithms content adaptive illumination control (CAIC) and local area brightness boost (LABB)

also apply transform functions on the gray scale level of each pixel. But while amount of gamma applied to every

pixel (of every frame) is constant (the exponent, gamma, is constant), CAIC and LABB are both adaptive

functions that can apply a different amounts of either boost or compression to every pixel of every frame. Be

sure to account for any image processing which occurs before the controller.

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two

directions, with the primary direction being into a projection or collection optic. Each application depends

primarily on the optical architecture of the system and the format of the data coming into the DLPC3430 or

DLPC3435 controller. The new high-tilt pixel in the side-illuminated DMD increases brightness performance and

enables a smaller system electronics footprint for thickness constrained applications. Applications include

• projection embedded in display devices

– smartphones

– tablets

– cameras

– camcorders

• wearable (near-eye) displays

• battery powered mobile accessory

• interactive display

• low-latency gaming display

• digital signage

DMD power-up and power-down sequencing is strictly controlled by the DLPA200x/DLPA3000. Refer to 节 9 for

power-up and power-down specifications. DLP2010 DMD reliability is specified when used with DLPC3430 or

DLPC3435 controller and DLPA200x/DLPA3000 PMIC/LED driver only.

8.2 Typical Application

This section describes a pico-projector using a DLP chipset that includes a DLP2010 DMD, DLPC3430 or

DLPC3435 controller and DLPA200x/DLPA3000 PMIC/LED driver. The DLPC3430 or DLPC3435 controller does

the digital image processing, the DLPA200x/DLPA3000 provides the needed analog functions for the projector,

and DMD is the display device for producing the projected image.

The DLPC3430 controller in the pico-projector embedded module typically receives images/video from a host

processor within the product. DLPC3430 controller then drives the DMD synchronized with the R, G, B LEDs in

the optical engine to display the image/video as output of the optical engine.

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1.1 V

1.1 Reg

SYSPWR

Supplies

1.8 V

1.8 V external

DLPA200x

LED

1.8 V

VSPI

PROJ_ON

LED_SEL (2)

SPI (4)

PROJ_ON

GPIO_8

SPI1

I C

RESETZ

PARKZ

LIM

INTZ

1.1 V

Thermistor

Video

Front End

HOST_IRQ

DSI (10)

CMP_OUT

HDMI

VDDLP12

VDD

Illumination

optics

Parallel Interface (28)

Flash

DLPC34xx

System

Controller

RC_

CHARGE

SPI (4)

SPI0

GPIO_10

Keypad

, V

BIAS OFFSET

VCC_18

1.8 V

TI DLP Chipset

Non-TI Device

RESET

DMD

VCC_INTF

VCC_FLSH

CTRL

Sub-LVDS DATA

1.8 V

图8-1. Typical Application

8.2.1 Design Requirements

In addition to the three DLP devices in the chipset, other IC components may be needed. At a minimum, this

design requires a flash device to store the software and firmware to control the DLPC3430 or DLPC3435.

Red, green, and blue LEDs typically supply the illumination light that is applied to the DMD. These LEDs are

often contained in three separate packages, but sometimes more than one color of LED die may be in the same

package to reduce the overall size of the pico-projector.

A parallel interface connects the DLPC3430 or DLPC3435 to the host processing for receiving images. When the

parallel interface is used, use an I²C interface to the host processor for sending commands to the DLPC3430 or

DLPC3435.

The battery (SYSPWR) and a regulated 1.8-V supply are the only power supplies needed external to the

projector in case of DLPA200x. The DLPA3000 supplies the 1.8V without external regulator.

8.2.2 Detailed Design Procedure

For connecting together the DLPC3430 or DLPC3435, the DLPA200x/DLPA3000, and the DMD, see the

reference design schematic. When a circuit board layout is created from this schematic a very small circuit board

is possible. An example small board layout is included in the reference design data base. Layout guidelines

should be followed to achieve a reliable projector.

The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an optical

OEM who specializes in designing optics for DLP projectors.

A miniature stepper motor can optionally be added to the optical engine for creating a motorized focus. Direct

control and driving of the motor can be done by the DLPA200x/DLPA3000, and software commands sent over

I²C to the DLPC3430 or DLPC3435 are available to move the motor to the desired position.

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8.2.3 Application Curve

This device drives current time-sequentially though the LEDs. As the LED currents through the red, green, and

blue LEDs increases, the brightness of the projector increases. This increase is somewhat non-linear, and the

curve for typical white screen lumens changes with LED currents as shown in 图 8-2. For the LED currents

shown, assumed that the same current amplitude is applied to the red, green, and blue.

SPACE

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

100

200

300 400

Current (mA)

500

600

700

D001

I_LED(red)= I_LED(green)= I_LED(blue)

图8-2. Luminance vs Current

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9 Power Supply Recommendations

The following power supplies are all required to operate the DMD:

• VSS

• VBIAS

• VDD

• VDDI

• VOFFSET

• VRESET

The DLPAxxxx device strictly controls the DMD power-up and power-down sequences as described in 图9-1.

CAUTION

To ensure reliable operation of the DMD, follow the power supply sequencing requirements

described in this section. Failure to adhere to any of these requirements can result in a significant

reduction in the DMD reliability and lifetime.

VBIAS, VDD, VDDI, VOFFSET, and VRESET power supplies must be coordinated during power-up

and power-down operations . Common ground (VSS) to all lines must also be connected.

9.1 DMD Power Supply Power-Up Procedure

• During the power-up sequence, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and

VRESET voltages are applied to the DMD.

• During the power-up sequence, it is a strict requirement that the voltage difference between VBIAS and

VOFFSET must be within the specified limit shown in 节6.4. Refer to 表9-1 for the power-up sequence,

delay requirements.

• During the power-up sequence, there is no requirement for the relative timing of VRESET with respect to

VBIAS and VOFFSET.

• Power supply slew rates during the power-up sequence are flexible, provided that the transient voltage levels

follow the requirements specified in 节6.1, in 节6.4, and in 节9.3.

• During the power-up sequence, LPSDR input pins must not be driven high until after VDD/VDDI have settled

at operating voltages listed in 节6.4.

9.2 DMD Power Supply Power-Down Procedure

• The power-down sequence is the reverse order of the previous power-up sequence. During the power-down

sequence, VDD and VDDI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to

within 4 V of ground.

• During the power-down sequence, it is a strict requirement that the voltage difference between VBIAS and

VOFFSET must be within the specified limit shown in 节6.4.

• During the power-down sequence, there is no requirement for the relative timing of VRESET with respect to

VBIAS and VOFFSET.

• Power supply slew rates during the power-down sequence, are flexible, provided that the transient voltage

levels follow the requirements specified in 节6.1, in 节6.4, and in 节9.3.

• During the power-down sequence, LPSDR input pins must be less than VDD/VDDI specified in 节6.4.

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9.3 Power Supply Sequencing Requirements

(4)

Mirror park sequence

VDD / VDDI

VDD and VDDI

VSS

VBIAS

VDD ≤ VBIAS < 6 V

VBIAS < 4 V

ûV < Specification⁽²⁾

VSS

ûV < Specification⁽¹⁾⁽²⁾

VOFFSET

VDD ≤ VOFFSET < 6 V

ûV < Specification⁽³⁾

VOFFSET

VOFFSET < 4 V

VSS

VRESET < 0.5 V

VRESET > œ4 V

VRESET

VDD

VRESET

VDD

DMD_DEN_ARSTZ

VSS

Initialization

VDD

LS_CLK

LS_WDATA

VID

D_P(0:3), D_N(0:3)

DCLK_P, DCLK_N

DLP controller and PMIC controls start of DMD operation

Mirror park sequence starts

Mirror park sequence ends. DLP controller and PMIC disables VBIAS, VOFFSET, and VRESET.

Power off.

Refer to 表9-1 and 图9-2 for critical power-up sequence delay requirements.

When system power is interrupted, the ASIC driver initiates hardware the power-down sequence, that disables VBIAS, VRESET and

VOFFSET after the micromirror park sequence is complete. Software the power-down sequence, disables VBIAS, VRESET, and

VOFFSET after the micromirror park sequence through software control.

To prevent excess current, the supply voltage delta |VBIAS –VRESET| must be less than specified limit shown in 节6.4.

Drawing is not to scale and details are omitted for clarity.

图9-1. Power Supply Sequencing Requirements

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表9-1. Power-Up Sequence Delay Requirement

PARAMETER

MIN

MAX

UNIT

t_DELAY

Delay requirement from VOFFSET power up to VBIAS power up

Supply voltage level during power–up sequence delay (see 图9-2)

VOFFSE

VBIAS

VOFFSET

VDD ≤ VOFFSET ≤ 6 V

VSS

DELAY

VBIAS

VDD ≤ VBIAS ≤ 6 V

VSS

Time

Refer to 表9-1 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay.

图9-2. Power-Up Sequence Delay Requirement

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10 Layout

10.1 Layout Guidelines

There are no specific layout guidelines because in most cases the DMD is connected using a board-to-board

connector to a flex cable. The flex cable provides the interface of data and control signals between the

DLPC3430 or DLPC3435 controller and the DLP2010 DMD. For detailed layout guidelines refer to the layout

design files.

Layout guidelines for the flex cable interface with DMD are:

• Match lengths for the LS_WDATA and LS_CLK signals.

• Minimize vias, layer changes, and turns for the HS bus signals. Refer 图10-1.

• Place a decoupling capacitor (minimum 100-nF) close to VBIAS. See capacitor C4 in 图10-2.

• Place a decoupling capacitor (minimum 100-nF) close to VRST. See capacitor C6 in 图10-2.

• Place a decoupling capacitor (minimum 220-nF) close to VOFS. See capacitor C7 in 图10-2.

• Place the optional decoupling capacitor (minimum between 200-nF and 220-nF) to meet the ripple

requirements of the DMD. See capacitor C5 in 图10-2.

• Place a decoupling capacitor (minimum 100-nF) close to VDDI. See capacitor C1 in 图10-2.

• Place a decoupling capacitor (minimum 100-nF) close to both groups of VDD pins, for a total of 200 nF for

VDD. See capacitors C2 and C3 in 图10-2.

10.2 Layout Example

图10-1. High-Speed (HS) Bus Connections

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图10-2. Power Supply Connections

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11 Device and Documentation Support

11.1 Device Support

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.1.2 Device Nomenclature

图11-1. Part Number Description

11.1.3 Device Markings

Device Marking will include the human–readable character string GHJJJJK VVVV on the electrical connector.

GHJJJJK is the lot trace code. VVVV is a 4 character encoded device part number.

GHJJJJKHVVVV

图11-2. DMD Marking

11.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

表11-1. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

DLPC3430

DLPC3435

DLPA2000

DLPA2005

DLPA3000

Click here

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

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11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.5 Trademarks

IntelliBright^™and TI E2E^™are trademarks of Texas Instruments.

DLP^®and Pico^®are registered trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

28-Sep-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DLP2010AFQJ

ACTIVE

CLGA

FQJ

120

RoHS & Green

Call TI

N / A for Pkg Type

0 to 70

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

DWG NO.

2512515

REVISIONS

NOTES UNLESS OTHERWISE SPECIFIED:

REV

DESCRIPTION

DATE

BMH

9/14/2012

ECO 2127544: INITIAL RELEASE

ECO 2129552: ENLARGE APERTURE ON RIGHT SIDE;

MOVE ACTIVE ARRAY Y-LOCATION DIM, SH. 3

ECO 2131252: ENLARGE APERTURE ALONG BOTTOM EDGE

ECO 2135244: CORRECT WINDOW THK TOL, ZONE B6

ECO 2138016: INCREASE WINDOW THK NOMINAL

ECO 2186532: ADD APERTURE SLOTS PICTORIALLY

DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY.

12/10/2012

BMH

ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION

TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES.

2/20/2013

8/5/2013

11/21/2013

3/31/2020

BMH

BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY.

DMD MARKING TO APPEAR IN CONNECTOR RECESS.

NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC,

AS SHOWN IN SECTION A-A.

ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN IN VIEW C

(SHEET 2). NO ENCAPSULANT IS ALLOWED ON TOP OF THE WINDOW.

ENCAPSULANT NOT TO EXCEED THE HEIGHT OF THE WINDOW.

DATUM B IS DEFINED BY A DIA. 2.5 PIN, WITH A FLAT ON THE SIDE FACING

TOWARD THE CENTER OF THE ACTIVE ARRAY, AS SHOWN IN VIEW B (SHEET 2).

WHILE ONLY THE THREE DATUM A TARGET AREAS A1, A2, AND A3 ARE USED

FOR MEASUREMENT, ALL 4 CORNERS SHOULD BE CONTACTED, INCLUDING E1,

TO SUPPORT MECHANICAL LOADS.

1.1760.05

4X (R0.2)

0.3

0.1

5.3

90° 1°

(ILLUMINATION

DIRECTION)

4X R0.4 0.1

2X 2.5 0.075

(2.5)

1.25

2.65

0.2

0.1

0.2

0.1

1.4

0.2

0.1

(1)

0.8

14.1 0.08

0.3

0.1

15.9

(OFF-STATE

DIRECTION)

6 7

1.0030.077

0.7 0.05

2X ENCAPSULANT

(1.783)

3 SURFACES INDICATED

IN VIEW B (SHEET 2)

0.038A

0.02D

1 9



0.78 0.063

ACTIVE ARRAY

1.40.1

(2.5)

 0.05

(1.4)

0.4 MIN

TYP.

(0.88)

(SHEET 3)

0 MIN TYP.

(PANASONIC AXT640124DD1, 40-CONTACT, 0.4 mm

PITCH BOARD-TO-BOARD CONNECTOR HEADER)

MATES WITH PANASONIC AXT540124DD1 OR EQUIVALENT

DATE

DRAWN

UNLESS OTHERWISE SPECIFIED

DIMENSIONS ARE IN MILLIMETERS

TOLERANCES:

TEXAS

9/14/2012

9/26/2012

9/18/2012

B. HASKETT

INSTRUMENTS

ENGINEER

Dallas Texas

CONNECTOR SOCKET

SECTION A-A

NOTCH OFFSETS

B. HASKETT

QA/CE

ANGLES 1

TITLE

ICD, MECHANICAL, DMD,

.2 WVGA SERIES 244

(FQJ PACKAGE)

2 PLACE DECIMALS 0.25

1 PLACE DECIMALS 0.50

P. KONRAD

DIMENSIONAL LIMITS APPLY BEFORE PROCESSES

INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME

Y14.5M-1994

F. ARMSTRONG

THIRD ANGLE

PROJECTION

DWG NO

REV

SIZE

0314DA

USED ON

REMOVE ALL BURRS AND SHARP EDGES

M. DORAK

APPROVED

2512515

PARENTHETICAL INFORMATION FOR REFERENCE ONLY

NEXT ASSY

SCALE

SHEET

APPLICATION

M. SOUCEK

20:1

INV11-2006a

DWG NO.

2512515

2X (1)

2X 1.176

2X (0.8)

2X 14.1

4X 1.45

1.25

2.5

4X (1.2)

(1.1)

VIEW B

DATUMS A, B, C, AND E

1.176

14.1

(FROM SHEET 1)

5.5

(2.5)

1.25

2.75

VIEW C

ENCAPSULANT MAXIMUM X/Y DIMENSIONS

(FROM SHEET 1)

2X 0 MIN

VIEW D

ENCAPSULANT MAXIMUM HEIGHT

DWG NO

REV

SIZE

DRAWN

DATE

9/14/2012

TEXAS

2512515

B. HASKETT

INSTRUMENTS

Dallas Texas

SCALE

SHEET

INV11-2006a

DWG NO.

2512515

(4.6116)

ACTIVE ARRAY

6.454 0.075

4X (0.108)

0.940.05

0.1340.0635

(4.86)

WINDOW

(2.592)

ACTIVE ARRAY

(ILLUMINATION

DIRECTION)

3.0160.0635

(3.15)

APERTURE

3.920.05

(2.5)

1.25

1.102 0.075

0.424 0.0635

2.9610.05

4.8390.0635

(5.263)

APERTURE



6.505 0.05

(9.466)

WINDOW

VIEW E

WINDOW AND ACTIVE ARRAY

(FROM SHEET 1)

53X TEST PADS

0.2ABC

50X 0.6±0.1 X 0.54±0.1

3X Ø0.54±0.1



0.1A

(9.8)

3.326

BACK INDEX MARK

0.4ABC



(42°) TYP.

2.23

1.25

(2.5)

2X (1.86)

0.4ABC

(0.15) TYP.

(0.075) TYP.



2X 0.93

5 X 0.892 = 4.46

(42°) TYP.

(0.068) TYP.

1.026

18 X 0.8 = 14.4



DETAIL G

APERTURE RIGHT EDGE

DETAIL F

APERTURE LEFT EDGE

VIEW H-H

(POND OF MIRRORS OMITTED FOR CLARITY)

SCALE 60 : 1

TEST PADS AND CONNECTOR

(FROM SHEET 1)

DWG NO

REV

SIZE

DRAWN

DATE

9/14/2012

TEXAS

2512515

B. HASKETT

INSTRUMENTS

Dallas Texas

SCALE

SHEET

INV11-2006a

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