DLP230KPAFQP [TI]
0.23-inch, HD DLP® digital micromirror device (DMD) | FQP | 54 | 0 to 70;型号: | DLP230KPAFQP |
厂家: | TEXAS INSTRUMENTS |
描述: | 0.23-inch, HD DLP® digital micromirror device (DMD) | FQP | 54 | 0 to 70 商用集成电路 |
文件: | 总43页 (文件大小:2716K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DLP230KP
ZHCSIP9C –JULY 2018 –REVISED MAY 2022
DLP230KP 0.23 HD DMD
1 特性
3 说明
• 超紧凑0.23 英寸(5.95mm) 对角线微镜阵列
DLP230KP 数字微镜器件 (DMD) 是一款数控微光机电
系统(MOEMS) 空间光调制器(SLM)。当与适当的光学
系统搭配使用时,此器件 DMD 可显示清晰和高质量的
高清 HD 图像或视频。该芯片组包括此 DMD 和
DLPC3434 控制器。DLPA2000 、DLPA2005 和
DLPA3000 PMIC/LED 驱动器也支持该芯片组。此器
件外形小巧,适用于重视高画质、小尺寸和低功耗的便
携设备。
– 1280 × 720 像素屏幕显示
– 5.4µm 微镜间距
– 17° 微镜倾斜(相对于平坦表面)
– 采用侧面照明,实现最优的效率和光学引擎尺寸
– 偏振无关型铝微镜表面
• 8 位SubLVDS 输入数据总线
• 显示应用专用的DLPC3434 控制器
• 专用DLPA2000、DLPA2005 或DLPA3000
PMIC/LED 驱动器,确保可靠运行
请访问 TI DLP®Pico™ 显示技术入门页面,了解有关
DMD 技术的更多信息。
2 显示应用
DMD 提供现成的资源,可帮助用户缩短设计周期。这
些资源包括可直接用于生产环境的光学模块、 光学模
块制造商和设计公司。
• 超高移动性,超低功耗Pico 投影仪
• 手机、平板电脑和笔记本电脑
• 智能扬声器
器件信息
• 智能家居
封装(1)
封装尺寸(标称值)
器件型号
DLP230KP
FQP (54)
16.8mm × 5.92mm × 3.58mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
.
.
D_P(0)
DLPC3434
Display
Controller
D_N(0)
VOFFSET
DLPA2000
D_P(1)
D_N(1)
DLPA2005
DLPA3000
Power
VBIAS
Management
600 MHz
SubLVDS
DDR
D_P(6)
D_N(6)
VRESET
DLP230KP DMD
Interface
Digital
Micromirror
Device
D_P(7)
D_N(7)
VDDI
VDD
DCLK_P
DCLK_N
LS_WDATA
LS_CLK
120 MHz
SDR
Interface
LS_RDATA
VSS
DMD_DEN_ARSTZ
(System signal routing omitted for clarity)
简化版应用
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: DLPS138
DLP230KP
ZHCSIP9C –JULY 2018 –REVISED MAY 2022
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Table of Contents
7.6 Micromirror Array Temperature Calculation.............. 24
7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 25
8 Application and Implementation..................................29
8.1 Application Information............................................. 29
8.2 Typical Application.................................................... 30
9 Power Supply Recommendations................................32
9.1 Power Supply Power-Up Procedure......................... 32
9.2 Power Supply Power-Down Procedure.....................32
9.3 Power Supply Sequencing Requirements................ 33
10 Layout...........................................................................35
10.1 Layout Guidelines................................................... 35
10.2 Layout Example...................................................... 35
11 Device and Documentation Support..........................36
11.1 Device Support........................................................36
11.2 Chipset Resources..................................................36
11.3 接收文档更新通知................................................... 36
11.4 支持资源..................................................................37
11.5 Trademarks............................................................. 37
11.6 Electrostatic Discharge Caution..............................37
11.7 术语表..................................................................... 37
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 显示应用............................................................................ 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 Storage Conditions..................................................... 7
6.3 ESD Ratings............................................................... 7
6.4 Recommended Operating Conditions.........................7
6.5 Thermal Information..................................................10
6.6 Electrical Characteristics...........................................10
6.7 Timing Requirements................................................12
6.8 Switching Characteristics(1) ..................................... 16
6.9 System Mounting Interface Loads............................ 17
6.10 Micromirror Array Physical Characteristics.............18
6.11 Micromirror Array Optical Characteristics............... 19
6.12 Window Characteristics.......................................... 21
6.13 Chipset Component Usage Specification............... 21
7 Detailed Description......................................................22
7.1 Overview...................................................................22
7.2 Functional Block Diagram.........................................22
7.3 Feature Description...................................................23
7.4 Device Functional Modes..........................................23
7.5 Optical Interface and System Image Quality
Information.................................................................... 38
12.1 Package Option Addendum....................................39
Considerations............................................................ 23
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision B (April 2022) to Revision C (May 2022)
Page
• Updated Absolute Maximum Ratings disclosure to the latest TI standard......................................................... 6
• Updated Micromirror Array Optical Characteristics ......................................................................................... 19
• Added Third-Party Products Disclaimer ...........................................................................................................36
Changes from Revision A (September 2018) to Revision B (April 2022)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Updated maximum |TDELTA| specification from "25°C" to "15°C" in Recommended Operating Conditions ..... 10
• Changed Related Links section title to Chipset Resources..............................................................................36
• Changed Related Links table title to Chipset Resources..................................................................................36
Changes from Revision * (July 2018) to Revision A (September 2018)
Page
• 更新了简化版应用..............................................................................................................................................1
• 将数据表状态从预告信息更改为量产数据..........................................................................................................1
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5 Pin Configuration and Functions
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
A
B
C
D
E
F
图5-1. FQP Package, 54-Pin CLGA (Bottom View)
表5-1. Pin Functions –Connector Pins
PIN(1)
PACKAGE NET
LENGTH(2) (mm)
TYPE
SIGNAL
DATA RATE
DESCRIPTION
NAME
NO.
DATA INPUTS
D_N(0)
A2
A1
C1
B4
F5
D4
E1
F3
A3
B1
C2
A4
E5
D5
E2
F2
C3
D3
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Data, negative
1.96
1.42
1.35
3.36
4.29
3.20
1.76
2.66
1.97
1.49
1.44
3.45
4.32
3.27
1.85
2.75
1.94
2.02
D_N(1)
Data, negative
Data, negative
Data, negative
Data, negative
Data, negative
Data, negative
Data, negative
Data, positive
Data, positive
Data, positive
Data, positive
Data, positive
Data, positive
Data, positive
Data, positive
Clock, negative
Clock, positive
D_N(2)
D_N(3)
D_N(4)
D_N(5)
D_N(6)
D_N(7)
D_P(0)
D_P(1)
D_P(2)
D_P(3)
D_P(4)
D_P(5)
D_P(6)
D_P(7)
DCLK_N
DCLK_P
CONTROL INPUTS
LS_WDATA
LS_CLK
DMD_DEN_ARSTZ
A12
B12
B14
I
I
I
LPSDR(1)
LPSDR
LPSDR
Single
Single
Single
Write data for low speed interface.
Clock for low-speed interface.
2.16
3.38
0.67
Asynchronous reset DMD signal. A low
signal places the DMD in reset. A high
signal releases the DMD from reset
and places it in active mode.
DMD_DEN_ARSTZ
F1
I
LPSDR
LPSDR
Single
Single
14.90
2.44
LS_RDATA
C13
O
Read data for low-speed interface.
POWER
(3)
VBIAS
A15
A5
Power
Power
Supply voltage for positive bias level at
micromirrors.
(3)
VBIAS
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表5-1. Pin Functions –Connector Pins (continued)
PIN(1)
PACKAGE NET
LENGTH(2) (mm)
TYPE
SIGNAL
DATA RATE
DESCRIPTION
NAME
NO.
(3)
(3)
VOFFSET
F13
Power
Supply voltage for HVCMOS core
logic. Supply voltage for stepped high
level at micromirror address
electrodes.
Supply voltage for offset level at
micromirrors.
VOFFSET
F4
Power
VRESET
VRESET
B15
B5
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Supply voltage for negative reset level
at micromirrors.
(3)
VDD
C15
C5
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDI
VDDI
VDDI
VDDI
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D14
D15
E14
E15
F14
F15
C14
C4
Supply voltage for LVCMOS core logic.
Supply voltage for LPSDR inputs.
Supply voltage for normal high level at
micromirror address electrodes.
Supply voltage for SubLVDS receivers.
D13
E13
A13
A14
B13
B2
B3
C12
D1
Common return.
Ground for all power.
D12
D2
E12
E3
E4
F12
(1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC
Standard No. 209B, Low Power Double Data Rate (LPDDR). See JESD209B.
(2) Net trace lengths inside the package:
Relative dielectric constant for the FQP ceramic package is 9.8.
Propagation speed = 11.8 / sqrt (9.8) = 3.769 in/ns.
Propagation delay = 0.265 ns/inch = 265 ps/in = 10.43 ps/mm.
(3) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also
required.
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表5-2. Pin Functions –Test Pads
NUMBER
SYSTEM BOARD
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
Do not connect
A6
A7
A8
A9
A10
A11
F6
F7
F8
F9
F10
F11
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted(1)
MIN
–0.5
–0.5
–0.5
MAX
2.3
2.3
11
UNIT
Supply voltage for LVCMOS core logic(2)
Supply voltage for LPSDR low speed interface
VDD
V
V
V
VDDI
Supply voltage for SubLVDS receivers(2)
Supply voltage for HVCMOS and micromirror
electrode(2) (3)
VOFFSET
Supply voltage for micromirror electrode(2)
Supply voltage for micromirror electrode(2)
Supply voltage delta (absolute value)(4)
Supply voltage delta (absolute value)(5)
Supply voltage delta (absolute value)(6)
19
0.5
0.3
11
V
V
V
V
V
Supply voltage
VBIAS
–0.5
–15
VRESET
|VDDI–VDD
|
|VBIAS–VOFFSET
|VBIAS–VRESET
|
34
|
Input voltage for other inputs LPSDR(2)
VDD + 0.5
VDDI + 0.5
810
V
V
–0.5
–0.5
Input voltage
Input pins
Input voltage for other inputs SubLVDS(2) (7)
|VID
|
SubLVDS input differential voltage (absolute value)(7)
SubLVDS input differential current
mV
mA
MHz
MHz
°C
IID
10
Clock frequency for low speed interface LS_CLK
Clock frequency for high speed interface DCLK
130
ƒclock
ƒclock
Clock
frequency
620
Temperature –operational (8)
–20
–40
90
TARRAY and TWINDOW
Temperature –non-operational(8)
90
°C
Environmental
Absolute temperature delta between any point on the
window edge and the ceramic test point TP1(9)
|TDELTA
TDP
|
30
81
°C
°C
Dew Point - operating and non-operating
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:
VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
(3) VOFFSET supply transients must fall within specified voltages.
(4) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.
(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw.
(6) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.
(7) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. SubLVDS differential
inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(8) The highest temperature of the active array (as calculated in 节7.6) or of any point along the window edge is defined in 图7-1. The
location of thermal test point TP2 in 图7-1 is intended to measure the highest window edge temperature. If a particular application
causes another point on the window edge to be at a higher temperature, that point should be used.
(9) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图
7-1. The window test point TP2 shown in 图7-1 is intended to result in the worst case delta. If a particular application causes another
point on the window edge to result in a larger delta temperature, that point should be used.
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6.2 Storage Conditions
Applicable for the DMD as a component or non-operating in a system.
MIN
MAX
85
24
36
6
UNIT
°C
TDMD
TDP
DMD storage temperature
–40
Average dew point temperature (non-condensing) (1)
Elevated dew point temperature range (non-condensing) (2)
Cumulative time in elevated dew point temperature range
°C
TDP-ELR
CTELR
28
°C
months
(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR
.
6.3 ESD Ratings
VALUE
UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
NOM
MAX
UNIT
SUPPLY VOLTAGE RANGE(3)
VDD
Supply voltage for LVCMOS core logic
1.65
1.8
1.95
V
Supply voltage for LPSDR low-speed interface
Supply voltage for SubLVDS receivers
Supply voltage for HVCMOS and micromirror electrode(4)
Supply voltage for mirror electrode
VDDI
1.65
9.5
1.8
10
1.95
10.5
18.5
–13.5
0.3
V
V
V
V
V
V
V
VOFFSET
VBIAS
17.5
18
VRESET
Supply voltage for micromirror electrode
Supply voltage delta (absolute value)(5)
Supply voltage delta (absolute value)(6)
Supply voltage delta (absolute value)(7)
–14.5
–14
|VDDI–VDD
|
10.5
33
|VBIAS–VOFFSET
|VBIAS–VRESET
|
|
CLOCK FREQUENCY
Clock frequency for low speed interface LS_CLK(8)
Clock frequency for high speed interface DCLK(9)
Duty cycle distortion DCLK
108
300
120
540
MHz
MHz
ƒclock
ƒclock
44%
56%
SUBLVDS INTERFACE(9)
|VID
|
SubLVDS input differential voltage (absolute value). See
图6-8, 图6-9
150
250
900
350
mV
VCM
700
575
90
1100
1225
110
mV
mV
Common mode voltage. See 图6-8, 图6-9
SubLVDS voltage. See 图6-8, 图6-9
Line differential impedance (PWB/trace)
Internal differential termination resistance. See 图6-10
100-Ωdifferential PCB trace
VSUBLVDS
ZLINE
ZIN
100
100
Ω
Ω
80
120
6.35
152.4
mm
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UNIT
Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
NOM
MAX
ENVIRONMENTAL
TARRAY
0
40 to 70(12)
°C
°C
Array temperature –long-term operational(10) (11) (12) (13)
Array temperature –short-term operational, 25 hr max(11)
–20
–10
(14)
0
°C
°C
Array temperature –short-term operational, 500 hr
–10
max(11) (14)
70
75
Array temperature –short-term operational, 500 hr
max(11) (14)
Window temperature –operational(15) (16)
TWINDOW
90
15
°C
°C
|TDELTA
|
Absolute temperature diffference between any point on
the window edge and the ceramic test point TP1(17)
TDP-AVG
TDP-ELR
Average dew point temperature (non-condensing) (18)
24
36
°C
°C
Elevated dew point temperature range (non-condensing)
28
(19)
CTELR
ILLUV
ILLVIS
Cumulative time in elevated dew point temperature range
Illumination wavelengths < 420 nm (10)
6
months
0.68
mW/cm2
Illumination wavelengths between 420 nm and 700 nm
Thermally
limited
ILLIR
ILLθ
Illumination wavelengths > 700 nm
Illumination marginal ray angle(15)
10
55
mW/cm2
degrees
(1) The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by
the 节6.4. No level of performance is implied when operating the device above or below the 节6.4 limits.
(2) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also
required.
(3) All voltage values are with respect to the ground pins (VSS).
(4) VOFFSET supply transients must fall within specified max voltages.
(5) To prevent excess current, the supply voltage delta |VDDI –VDD| must be less than the specified limit.
(6) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than the specified limit.
(7) To prevent excess current, the supply voltage delta |VBIAS –VRESET| must be less than the specified limit.
(8) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.
(9) Refer to the SubLVDS timing requirements in 节6.7.
(10) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will
reduce device lifetime.
(11) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1
(TP1) shown in 图7-1 and the package thermal resistance using 节7.6.
(12) Per 图6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD
experiences in the end application. Refer to 节7.7 for a definition of micromirror landed duty cycle.
(13) Long-term is defined as the usable life of the device.
(14) Short-term is the total cumulative time over the useful life of the device.
(15) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including at the pond of
micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not
necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance
has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array
(including POM) will contribute to thermal limitations described in this document and may negatively affect lifetime.
(16) Window temperature is the highest temperature on the window edge shown in 图7-1. The location of thermal test point TP2 in 图7-1
is intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to
be at a higher temperature, that point should be used.
(17) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge shown in 图7-1.
The window test point TP2 shown in 图7-1 is intended to result in the worst case delta temperature. If a particular application causes
another point on the window edge to result in a larger delta temperature, that point should be used.
(18) The average over time (including storage and operating) that the device is not in the 'elevated dew point temperature range'.
(19) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR
.
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80
70
60
50
40
30
0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50
90/10 85/15 80/20 75/25 70/30 65/35 60/40 55/45
100/0 95/5
D001
Micromirror Landed Duty Cycle
图6-1. Maximum Recommended Array Temperature –Derating Curve
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6.5 Thermal Information
DLP230KP
FQP (CLGA)
54 PINS
THERMAL METRIC(1)
UNIT
Thermal resistance
Active area to test point 1 (TP1)(1)
9.0
°C/W
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the package within the temperature range specified in the 节6.4. The total heat load on the DMD is largely driven by the
incident light absorbed by the active area, although other contributions include light energy absorbed by the window aperture and
electrical power dissipated by the array. Optical systems should be designed to minimize the light energy falling outside the window
clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.
6.6 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS(2)
MIN
TYP
MAX UNIT
CURRENT
VDD = 1.95 V
65
(3) (4)
(3) (4)
IDD
Supply current: VDD
Supply current: VDDI
mA
VDD = 1.8 V
53
11
VDDI = 1.95 V
VDD = 1.8 V
12
IDDI
mA
VOFFSET = 10.5 V
VOFFSET = 10 V
VBIAS = 18.5 V
VBIAS = 18 V
1.5
mA
(5) (6)
IOFFSET
Supply current: VOFFSET
1.4
0.3
mA
(5) (6)
IBIAS
Supply current: VBIAS
Supply current: VRESET
0.29
VRESET = –14.5 V
VRESET = –14 V
–1.3
(6)
IRESET
mA
–1.2
POWER(7)
PDD
VDD = 1.95 V
126.75
mW
(3) (4)
(3) (4)
Supply power dissipation: VDD
Supply power dissipation: VDDI
VDD = 1.8 V
95.4
19.8
14
VDDI = 1.95 V
VDD = 1.8 V
23.4
mW
PDDI
(5)
VOFFSET = 10.5 V
VOFFSET = 10 V
VBIAS = 18.5 V
VBIAS = 18 V
15.75
mW
Supply power dissipation: VOFFSET
POFFSET
(6)
5.55
mW
(5) (6)
PBIAS
Supply power dissipation: VBIAS
5.22
18.85
mW
VRESET = –14.5 V
VRESET = –14 V
(6)
PRESET
Supply power dissipation: VRESET
Supply power dissipation: Total
16.80
PTOTAL
LPSDR INPUT(8)
151.22
190.3
mW
VIH(DC)
VIL(DC)
VIH(AC)
VIL(AC)
∆VT
DC input high voltage(9)
0.7 × VDD
–0.3
VDD + 0.3
0.3 × VDD
VDD + 0.3
0.2 × VDD
0.4 × VDD
V
V
DC input low voltage(9)
AC input high voltage(9)
AC input low voltage(9)
Hysteresis ( VT+ –VT–
Low–level input current
0.8 × VDD
–0.3
V
V
0.1 × VDD
V
)
图6-10
IIL
VDD = 1.95 V; VI = 0 V
VDD = 1.95 V; VI = 1.95 V
nA
nA
–100
IIH
100
High–level input current
LPSDR OUTPUT(10)
VOH DC output high voltage
0.8 × VDD
V
IOH = –2 mA
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Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS(2)
MIN
TYP
MAX UNIT
0.2 × VDD
VOL
DC output low voltage
IOL = 2 mA
V
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MAX UNIT
Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS(2)
MIN
TYP
CAPACITANCE
Input capacitance LPSDR
Input capacitance SubLVDS
Output capacitance
10
20
pF
pF
pF
pF
ƒ= 1 MHz
CIN
ƒ= 1 MHz
COUT
10
ƒ= 1 MHz
CRESET
Reset group capacitance
90
150
ƒ= 1 MHz; (540 × 120) micromirrors
(1) Device electrical characteristics are over 节6.4 unless otherwise noted.
(2) All voltage values are with respect to the ground pins (VSS).
(3) To prevent excess current, the supply voltage delta |VDDI –VDD| must be less than the specified limit.
(4) Supply power dissipation based on non–compressed commands and data.
(5) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than the specified limit.
(6) Supply power dissipation based on 3 global resets in 200 µs.
(7) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also
required.
(8) LPSDR specifications are for pins LS_CLK and LS_WDATA.
(9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC
Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.
(10) LPSDR specification is for pin LS_RDATA.
6.7 Timing Requirements
Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
MIN
NOM
MAX UNIT
LPSDR
Rise slew rate(1)
Fall slew rate(1)
Rise slew rate(2)
Fall slew rate(2)
Cycle time LS_CLK
1
1
3
3
V/ns
V/ns
V/ns
V/ns
ns
tr
(30% to 80%) × VDD, 图6-3
(70% to 20%) × VDD, 图6-3
(20% to 80%) × VDD, 图6-3
(80% to 20%) × VDD, 图6-3
图6-2
tƒ
0.25
0.25
7.7
tr
tƒ
tc
8.3
tW(H)
Pulse duration LS_CLK
high
3.1
ns
50% to 50% reference points, 图6-2
tW(L)
tsu
3.1
1.5
1.5
3
ns
ns
ns
ns
ns
Pulse duration LS_CLK low
Setup time
50% to 50% reference points, 图6-2
LS_WDATA valid before LS_CLK ↑, 图6-2
LS_WDATA valid after LS_CLK ↑, 图6-2
Setup time + hold time, 图6-2
t h
Hold time
tWINDOW
Window time(1) (3)
For each 0.25 V/ns reduction in slew rate
below 1 V/ns, 图6-5
0.35
tDERATING
Window time derating(1) (3)
SubLVDS
tr
Rise slew rate
0.7
0.7
1
1
V/ns
V/ns
ns
20% to 80% reference points, 图6-4
80% to 20% reference points, 图6-4
图6-6
tƒ
Fall slew rate
tc
Cycle time DCLK
1.79
0.79
0.79
1.85
tW(H)
tW(L)
Pulse duration DCLK high
Pulse duration DCLK low
ns
50% to 50% reference points, 图6-6
50% to 50% reference points, 图6-6
ns
D(0:7) valid before
DCLK ↑or DCLK ↓, 图6-6
tsu
Setup time
D(0:7) valid after
DCLK ↑or DCLK ↓, 图6-6
t h
Hold time
tWINDOW
Window time
0.3
ns
ns
Setup time + hold time, 图6-6, 图6-7
tLVDS-
Power-up receiver(4)
2000
ENABLE+REFGEN
(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in 图6-3.
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(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in 图6-3.
(3) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.
(4) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
t
c
t
t
w(L)
w(H)
LS_CLK
50%
50%
50%
t
h
t
su
LS_WDATA
50%
50%
t
window
Low-speed interface is LPSDR and adheres to the 节6.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low
Power Double Data Rate (LPDDR) JESD209B.
图6-2. LPSDR Switching Parameters
LS_CLK, LS_WDATA
DMD_DEN_ARSTZ
1.0 * VDD
1.0 * VDD
0.8 * VDD
VIH(AC)
VIH(DC)
0.8 * VDD
0.7 * VDD
VIL(DC)
VIL(AC)
0.3 * VDD
0.2 * VDD
0.2 * VDD
0.0 * VDD
0.0 * VDD
tr
tf
tr
tf
图6-3. LPSDR Input Rise and Fall Slew Rate
图6-4. SubLVDS Input Rise and Fall Slew Rate
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VIH MIN
LS_CLK Midpoint
VIL MAX
tSU
tH
VIH MIN
LS_WDATA Midpoint
VIL MAX
tWINDOW
VIH MIN
Midpoint
LS_CLK
VIL MAX
tDERATING
tH
tSU
VIH MIN
Midpoint
VIL MAX
LS_WDATA
tWINDOW
图6-5. Window Time Derating Concept
图6-6. SubLVDS Switching Parameters
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Note: Refer to 节7.3.3 for details.
图6-7. High-Speed Training Scan Window
图6-8. SubLVDS Voltage Parameters
1.225V
V
= V
+ | 1/2 * V
ID max
|
SubLVDS max
CM max
V
CM
V
ID
V
= V
– | 1/2 * V
|
SubLVDS min
CM min
ID max
0.575V
图6-9. SubLVDS Waveform Parameters
图6-10. SubLVDS Equivalent Input Circuit
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Not to Scale
V
V
IH
V
T+
Δ V
T
V
T-
LS_CLK
IL
LS_WDATA
图6-11. LPSDR Input Hysteresis
LS_CLK
LS_WDATA
Stop Start
tPD
LS_RDATA
Acknowledge
图6-12. LPSDR Read Out
Data Sheet Timing Reference Point
Device Pin
Tester Channel
Output Under Test
C
L
See 节7.3.4 for more information.
图6-13. Test Load Circuit for Output Propagation Measurement
6.8 Switching Characteristics(1)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
CL = 5 pF
11.1
11.3
15
Output propagation, clock to Q, rising
edge of LS_CLK input to LS_RDATA
output. See 图6-12.
tPD
CL = 10 pF
CL = 85 pF
ns
ns
Slew rate, LS_RDATA
0.5
V/ns
Output duty cycle distortion, LS_RDATA
40%
60%
(1) Device electrical characteristics comply with the values in 节6.4 unless otherwise noted.
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6.9 System Mounting Interface Loads
PARAMETER
MIN
NOM
MAX
UNIT
Maximum system mounting interface load to be applied to the:
45
N
N
•
•
Thermal interface area (1)
Clamping and electrical interface area (1)
100
(1) Uniformly distributed within area shown in 图6-14.
Datum 'A' Area
(3 places)
Datum 'E' Area
(1 place)
Thermal Interface Area
Electrical Interface Area
图6-14. System Interface Loads
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6.10 Micromirror Array Physical Characteristics
PARAMETER
VALUE
UNIT
Number of active
columns(1)
960
See 图6-15
micromirrors
Number of active rows(1)
micromirrors
µm
540
5.4
See 图6-15
See 图6-16
Micromirror (pixel) pitch
ε
Micromirror active array
width
5.184
mm
Micromirror pitch × number of active columns; see 图6-15
Micromirror active array
height
2.916
20
mm
Micromirror pitch × number of active rows; see 图6-15
Micromirror active border Pond of micromirror (POM)(2)
micromirrors/side
(1) The fast switching speed of the DMD micromirrors combined with advanced DLP image processing algorithms enables each
micromirror to display two distinct pixels on the screen during every frame, resulting in a full 1280 × 720 pixel image being displayed.
(2) The structure and qualities of the border around the active array include a band of partially functional micromirrors called the POM.
These micromirrors are structurally or electrically prevented from tilting toward the bright or ON state, but require an electrical bias to
tilt toward OFF.
图6-15. Micromirror Array Physical Characteristics
ε
ε
ε
ε
图6-16. Mirror (Pixel) Pitch
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6.11 Micromirror Array Optical Characteristics
PARAMETER
Micromirror tilt angle
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DMD landed state(1)
17
°
°
Micromirror tilt angle tolerance(2) (3) (4) (5)
1.4
–1.4
Landed ON state
180
270
1
Micromirror tilt direction(6) (7)
°
Landed OFF state
Typical performance
Typical performance
Micromirror crossover time(8)
Micromirror switching time(9)
3
μs
10
Bright pixel(s) in active
Gray 10 screen (12)
Gray 10 screen (12)
0
1
area (11)
Bright pixel(s) in the
POM (13)
Image performance(10) Dark pixel(s) in the
active area (14)
micromirrors
White screen
Any screen
Any screen
4
0
0
Adjacent pixel(s) (15)
Unstable pixel(s) in
active area (16)
(1) Measured relative to the plane formed by the overall micromirror array.
(2) Additional variation exists between the micromirror array and the package datums.
(3) Represents the landed tilt angle variation relative to the nominal landed tilt angle.
(4) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result
in colorimetry variations, system efficiency variations or system contrast variations.
(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of
the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON state
direction. A binary value of 0 results in a micromirror landing in the OFF state direction. See 图6-17
(7) Micromirror tilt direction is measured as in a typical polar coordinate system: Measuring counter-clockwise from a 0° reference which is
aligned with the +X Cartesian axis.
(8) The time required for a micromirror to nominally transition from one landed state to the opposite landed state.
(9) The minimum time between successive transitions of a micromirror
(10) Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions:
Test set degamma shall be linear
Test set brightness and contrast shall be set to nominal
The diagonal size of the projected image shall be a minimum of 20 inches
The projections screen shall be 1X gain
The projected image shall be inspected from a 38 inch minimum viewing distance
The image shall be in focus during all image quality tests
(11) Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels
(12) Gray 10 screen definition: All areas of the screen are colored with the following settings:
Red = 10/255
Green = 10/255
Blue = 10/255
(13) POM definition: Rectangular border of off-state mirrors surrounding the active area
(14) Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels
(15) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster
(16) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable
pixel appears to be flickering asynchronously with the image.
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图6-17. Landed Pixel Orientation and Tilt
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6.12 Window Characteristics
PARAMETER(1)
MIN
NOM
Corning Eagle XG
1.5119
MAX UNIT
Window material designation
Window refractive index
Window aperture(2)
At wavelength 546.1 nm
See (2)
See (3)
Illumination overfill(3)
Minimum within the wavelength range
420 to 680 nm. Applies to all angles 0° to
30° AOI.
97%
97%
Window transmittance, single-pass
through both surfaces and glass
Average over the wavelength range 420
to 680 nm. Applies to all angles 30° to
45° AOI.
(1) See 节7.5 for more information.
(2) See the package mechanical characteristics for details regarding the size and location of the window aperture.
(3) The active area of the DLP230KP device is surrounded by an aperture on the inside of the DMD window surface that masks structures
of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating
the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. The
illumination optical system should be designed to limit light flux incident outside the active array to less than 10% of the average flux
level in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of overfill light
on the outside of the active array may cause system performance degradation.
6.13 Chipset Component Usage Specification
备注
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.
The DLP230KP is a component of one or more DLP® chipsets. Reliable function and operation of the DLP230KP
requires that it be used in conjunction with the other components of the applicable DLP chipset, including those
components that contain or implement TI DMD control technology. TI DMD control technology consists of the TI
technology and devices used for operating or controlling a DLP DMD.
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7 Detailed Description
7.1 Overview
The DLP230KP is a 0.23-inch diagonal spatial light modulator of aluminum micromirrors. Micromirror array size
is 960 columns by 540 rows in a square micromirror arrangement. The fast switching speed of the DMD
micromirrors combined with advanced DLP image processing algorithms enables each micromirror to display
two distinct pixels on the screen during every frame, resulting in a full 1280 × 720 pixel image being displayed.
The electrical interface is sub low voltage differential signaling (SubLVDS) data.
This chipset comprises this DMS and the DLPC3434 controller. The DLPA2000, DLP2005, and DLP3000
PMIC/LED drivers also support this chipset. To ensure reliable operation, the DLP230KP DMD must always be
used with the DLPC3434 ZVB display controller and the DLPA2000, DLP2005, or DLP3000 PMIC/LED driver.
7.2 Functional Block Diagram
High-Speed
Interface
Control
Misc
Column Write
Bit Lines
(0,0)
Word
Lines
Voltages
Voltage
Generators
SRAM
(539,959)
Row
Control
Column Read
Control
Low-Speed
Interface
A. Details omitted for clarity.
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7.3 Feature Description
7.3.1 Power Interface
The power management IC DLPA2000, DLPA2005, and DLPA3000 contain three regulated DC supplies for the
DMD reset circuitry: VBIAS, VRESET and VOFFSET, as well as the two regulated DC supplies for the DLPC3434ZVB
controller.
7.3.2 Low-Speed Interface
The low speed interface handles instructions that configure the DMD and control reset operation. LS_CLK is the
low–speed clock, and LS_WDATA is the low speed data input.
7.3.3 High-Speed Interface
The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed
DDR transfer and compression techniques to save power and time. The high-speed interface is composed of
differential SubLVDS receivers for inputs with a dedicated clock.
7.3.4 Timing
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. 图 6-13 shows an equivalent test load circuit for the output
under test. Timing reference loads are not intended as a precise representation of any particular system
environment or depiction of the actual load presented by a production test. System designers should use IBIS or
other simulation tools to correlate the timing reference load to a system environment. The load capacitance
value stated is only for characterization and measurement of AC timing signals. This load capacitance value
does not indicate the maximum load the device is capable of driving.
7.4 Device Functional Modes
The DLPC3434 controller manages the functional modes of the DMD. For more infromation, download the
controller data sheet or contact a TI applications engineer.
7.5 Optical Interface and System Image Quality Considerations
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
7.5.1 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the
projection lens. The mirror tilt angle defines DMD capability to separate the ON optical path from any other light
path, including undesirable flat–state specular reflections from the DMD window, DMD border structures, or
other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the
mirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger than the
illumination numerical aperture angle, objectionable artifacts in the display’s border and/or active area could
occur.
7.5.2 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable
artifacts in the display’s border and/or active area, which may require additional system apertures to control,
especially if the numerical aperture of the system exceeds the pixel tilt angle.
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7.5.3 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD chip assembly from normal view and is sized to anticipate several optical operating
conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window
aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system
should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately
10% of the average flux level in the active area. Depending on the particular system’s optical architecture,
overfill light may have to be further reduced below the suggested 10% level in order to be acceptable.
7.6 Micromirror Array Temperature Calculation
Array
2.96
Illumination
Direction
TP2
Off-state
Window Edge
(4 surfaces)
TP2
TP1
8.00
TP1
1.10
图7-1. DMD Thermal Test Points
Micromirror array temperature cannot be measured directly, therefore it must be computed analytically from
measurement points on the outside of the package, the package thermal resistance, the electrical power, and
the illumination heat load. The relationship between array temperature and the reference ceramic temperature
(thermal test point TP1 in 图7-1) is provided by the following equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC
QARRAY = QELECTRICAL + QILLUMINATION
QILLUMINATION = (CL2W × SL)
)
where
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• TARRAY = Computed DMD array temperature (°C)
• TCERAMIC = Measured ceramic temperature (°C), TP1 location in 图7-1
• RARRAY–TO–CERAMIC = Thermal resistance from array to TP1 on ceramic (°C/W) specified in 节6.5
• QARRAY = Total (electrical + absorbed) DMD power on array (W)
• QELECTRICAL = Nominal DMD electrical power dissipation (W)
• CL2W = Conversion constant for screen lumens to absorbed optical power on the DMD (W/lm) specified below
• SL = Measured ANSI screen lumens (lm)
Electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating
frequencies. Nominal electrical power dissipation to use when calculating array temperature is 0.17 W. Absorbed
optical power from the illumination source is variable and depends on the operating state of the micromirrors and
the intensity of the light source. Equations shown above are valid for a 1-chip DMD system with total projection
efficiency through the projection lens from DMD to the screen of 87%.
The conversion constant CL2W is based on the DMD micromirror array characteristics. It assumes a spectral
efficiency of 300 lm/W for the projected light and illumination distribution of 83.7% on the DMD active array, and
16.3% on the DMD array border and window aperture. The conversion constant is calculated to be 0.00266
W/lm.
Sample calculations for typical projection application:
TCERAMIC = 55°C (measured)
SL = 200 lm (measured)
QELECTRICAL = 0.17 W
CL2W = 0.00266 W/lm
QARRAY = 0.17 W + (0.00266 W/lm × 200 lm) = 0.702 W
TARRAY = 55°C + (0.702 W × 9°C/W) = 61.32°C
7.7 Micromirror Landed-On/Landed-Off Duty Cycle
7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the ON state versus the amount of time the same
micromirror is landed in the OFF state.
As an example, a landed duty cycle of 75/25 indicates that the referenced pixel is in the ON state 75% of the
time and in the OFF state 25% of the time, whereas 25/75 would indicate that the pixel is in the ON state 25% of
the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
nominally add to 100.
7.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD’s micromirror array to an asymmetric landed duty cycle for a prolonged
period of time can reduce the DMD’s usable life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed
duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed
duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
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7.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD temperature and landed duty cycle interact to affect the DMD’s usable life. This is quantified
in the de-rating curve shown in 图6-1. The importance of this curve is that:
• All points along this curve represent the same usable life.
• All points above this curve represent lower usable life (and the further away from the curve, the lower the
usable life).
• All points below this curve represent higher usable life (and the further away from the curve, the higher the
usable life).
In practice, this curve specifies the maximum operating DMD temperature that the DMD should be operated at
for a given long-term average landed duty cycle.
7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the nominal landed duty cycle of a given pixel is determined by the image content
being displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
will experience very close to a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-
black, the pixel will experience very close to a 0/100 landed duty cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in 表7-1.
表7-1. Grayscale Value
and Landed Duty Cycle
Grayscale
Value
Nominal Landed
Duty Cycle
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0/100
10/90
20/80
30/70
40/60
50/50
60/40
70/30
80/20
90/10
100/0
Accounting for color rendition (but still ignoring image processing) requires knowing both the color scale value
(from 0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the
color cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that
a given primary must be displayed in order to achieve the desired white point.
During a given period of time, the nominal landed duty cycle of a given pixel can be calculated as follows:
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) +
(Blue_Cycle_%×Blue_Scale_Value)
(1)
where
Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_% represent the percentage of the frame time that red, green,
and blue are displayed (respectively) to achieve the desired white point.
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For example, assuming that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in
order to achieve the desired white point), then the nominal landed duty cycle for various combinations of red,
green, blue color intensities would be as shown in 表7-2.
表7-2. Example Landed Duty Cycle for Full-Color
Pixels
Red Cycle
Percentage
Green Cycle
Percentage
Blue Cycle
Percentage
50%
20%
30%
Nominal
Landed Duty
Cycle
Red Scale
Value
Green Scale
Blue Scale
Value
Value
0%
100%
0%
0%
0%
0%
0%
0/100
50/50
20/80
30/70
6/94
100%
0%
0%
0%
100%
0%
12%
0%
0%
35%
0%
0%
7/93
0%
60%
0%
18/82
70/30
50/50
80/20
13/87
25/75
24/76
100/0
100%
0%
100%
100%
0%
100%
100%
0%
100%
12%
0%
35%
35%
0%
60%
60%
100%
12%
100%
100%
The last factor to account for in estimating the landed duty cycle is any applied image processing. Within the
DLP controller DLPC3434ZVB, the three functions which influence the actual landed duty cycle are gamma,
IntelliBright™, and bitplane sequencing rules.
Gamma is a power function of the form Output_Level = A × Input_LevelGamma, where A is a scaling factor that is
typically set to 1.
In the DLPC3434ZVB controller, gamma is applied to the incoming image data on a pixel-by-pixel basis. A
typical gamma factor is 2.2, which transforms the incoming data as shown in 图7-2.
100
90
80
Gamma = 2.2
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
Input Level (%)
70
80
90 100
D002
图7-2. Example of Gamma = 2.2
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For example, from 图 7-2, if the gray scale value of a given input pixel is 40% (before gamma is applied), then
the gray scale value is 13% after gamma is applied. This reduction indicates that gamma has a direct impact on
the displayed gray scale level of a pixel, and it also has a direct impact on the landed duty cycle of a pixel.
The IntelliBright algorithm for content adaptive illumination control (CAIC) and local area brightness boost
(LABB) also apply transform functions on the gray scale level of each pixel.
But while the amount of gamma applied to every pixel of every frame is constant (the exponent, gamma, is
constant), CAIC and LABB are both adaptive functions that can apply different amounts of either boost or
compression to every pixel of every frame.
Give consideration to any image processing which occurs before the DLPC3434 controller.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two
directions, with the primary direction being into a projection or collection optic. Each application is derived
primarily from the optical architecture of the system and the format of the data coming into the DLPC3434
controller. The new high tilt pixel in the side-illuminated DMD increases brightness performance and enables a
smaller system footprint for thickness-constrained applications. Applications of interest include projection
technology embedded in display devices such as ultra low-power battery operated mobile accessory projectors,
phones, tablets, ultra mobile low end smart TVs, and virtual assistants.
The PMIC/LED driver strictly controls the DMD power-up and power-down sequencing. Refer to 节 9 for power-
up and power-down specifications. To ensure reliable operation, the DLP230KP DMD must always be used with
the DLPC3434 display controller and either the DLPA2000, DLPA2005, or DLPA3000 PMIC/LED driver.
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8.2 Typical Application
A common application when using a DLP230KP DMD and a DLPC3434 is for creating a Pico projector that can
be used as an accessory to a smartphone, tablet, or a laptop. The DLPC3434 controller in the Pico projector
receives images from a multimedia front end within the product as shown in 图8-1.
DMD/
DLPC
Bucks
1.1 V
1.8 V
2.5 V
3.3 V
AUX
LDOs
+ Battery
–
SYSPWR
V
LED
DC
Supplies
Charger
DLPA3000
Fan(s)
Sensors
SPI(4)
INTZ
R
LIM
SPI1
RESETZ
PARKZ
Thermistor
CMP_OUT
Illumination
optics
PROJ_ON
GPIO_8
1.1 V
VDD
DLPC3436
I2C
HOST_IRQ
HDMI
GPIO_10
Parallel (28)
SUB_FRAME
ACT_SYNC
Parallel (28)
Front-End
Chip
RC_CHARGE
VCC, V
,
BIAS
Flash,
SDRAM
FPD-Link
V
, V
OFFSET RESET
DLP230NP
FPGA
RESETZ
I2C
FPGA RSTZ
1.8 V
CTRL, DATA
(XC7Z020-
1CLG484I4493)
Frame
Memory
Keypad
SPI0
SPI (4)
Flash
ꢀꢁOSD
ꢀꢁAutolock
ꢀꢁScaler
ꢀꢁDeinterlacer
ꢀꢁMicro-controller
VCC_18
SD Card
Reader,
Video
Flash
TI Device
VCC_INTF
VCC_FLSH
Non-TI Device
Decoder
DAC_DATA,
DAC_CLK
Actuator
Driver
Actuator
图8-1. Typical Application Diagram
8.2.1 Design Requirements
A pico projector is created by using a DLP chipset comprised of a DLP230KP DMD, a DLPC3434 controller, and
a DLPA2000/2005/3000 PMIC/LED driver. The DLPC3434 controller performs the digital image processing, the
DLPA2000/2005/3000 provides the needed analog functions for the projector, and the DLP230KP DMD is the
display device for producing the projected image.
In addition to the three DLP chips in the chipset, other chips are needed. At a minimum a flash part is needed to
store the DLPC3434 controller software.
The illumination light that is applied to the DMD is typically from red, green, and blue LEDs. These are often
contained in three separate packages, but sometimes more than one color of LED die may be in the same
package to reduce the overall size of the pico projector.
The DLPC3434 controller receives image data from the multimedia front end over a 24-bit parallel interface. An
I2C interface should be connected from the multimedia front end for sending commands to the DLPC3434
controller for configuring the chipset for different features.
8.2.2 Detailed Design Procedure
For connecting together the DLPC3434 controller, the DLPA2000/2005/3000, and the DLP230KP DMD, see the
reference design schematic. When a circuit board layout is created from this schematic a very small circuit board
is possible. An example small board layout is included in the reference design data base. Layout guidelines
should be followed to achieve a reliable projector.
The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an optical
OEM who specializes in designing optics for DLP projectors.
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8.2.3 Application Curve
As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the
brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white
screen lumens changes with LED currents is as shown in 图8-2. For the LED currents shown, it is assumed that
the same current amplitude is applied to the red, green, and blue LEDs.
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
500
1000
1500
Current (mA)
2000
2500
3000
D001
图8-2. Luminance vs LED Current
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9 Power Supply Recommendations
The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All
VSS connections are also required. DMD power-up and power-down sequencing is strictly controlled by the
DLPA2000/2005/3000 devices.
CAUTION
For reliable operation of the DMD, the following power supply sequencing requirements must be
followed. Failure to adhere to the prescribed power-up and power-down procedures may affect
device reliability.
VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-up and
power-down operations. Failure to meet any of the specified requirements results in a significant
reduction in the DMD reliability and lifetime. Refer to 图9-2. VSS must also be connected.
9.1 Power Supply Power-Up Procedure
• During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET voltages are
applied to the DMD.
• During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the
specified limit shown in 节6.4. Refer to 图9-2 for power-up delay requirements.
• During power-up, the DMD’s LPSDR input pins shall not be driven high until after VDD and VDDI have settled
at operating voltage.
• During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS
Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the
requirements listed previously and in 图9-1.
.
9.2 Power Supply Power-Down Procedure
• The power-down sequence is the reverse order of the previous power-up sequence. VDD and VDDI must be
supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.
• During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement that
the delta between VBIAS and VOFFSET must be within the specified limit shown in 节6.4 (Refer to Note 2 for 图
9-1).
• During power-down, the DMD’s LPSDR input pins must be less than VDDI, the specified limit shown in 节
6.4.
• During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS
.
• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements listed previously and in 图9-1.
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9.3 Power Supply Sequencing Requirements
A. Refer to 表9-1 and 图9-2 for critical power-up sequence delay requirements.
B. To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than specified in 节6.4. OEMs may find that the
most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-
down. Refer to 表9-1 and 图9-2 for power-up delay requirements.
C. To prevent excess current, the supply voltage delta |VBIAS –VRESET| must be less than the specified limit shown in 节6.4.
D. When system power is interrupted, the DLPA2000/2005/3000 initiates hardware power-down that disables VBIAS, VRESET and VOFFSET
after the micromirror park sequence.
E. Drawing is not to scale and details are omitted for clarity.
图9-1. Power Supply Sequencing Requirements (Power Up and Power Down)
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表9-1. Power-Up Sequence Delay Requirement
PARAMETER
MIN
MAX UNIT
tDELAY
VOFFSET
VBIAS
Delay requirement from VOFFSET power up to VBIAS power up
Supply voltage level at beginning of power–up sequence delay (see 图9-2)
Supply voltage level at end of power–up sequence delay (see 图9-2)
2
ms
6
6
V
V
12
8
VOFFSET
VDD ≤ VOFFSET ≤ 6 V
4
VSS
0
t
DELAY
20
16
12
8
VBIAS
VDD ≤ VBIAS ≤ 6 V
4
VSS
0
Time
Refer to 表9-1 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay.
图9-2. Power-Up Sequence Delay Requirement
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10 Layout
10.1 Layout Guidelines
The DLP230KP DMD connects to a PCB or a flex circuit using an interposer. For additional layout guidelines
regarding length matching, and impedance, see the DLPC3434 controller datasheet. For a detailed layout
example refer to the layout design files. Some layout guidelines for routing to the DMD are:
• Match lengths for the LS_WDATA and LS_CLK signals.
• Minimize vias, layer changes, and turns for the HS bus signals. Refer to 图10-1.
• Minimum of two 100-nF (25 V) capacitors - one close to VBIAS pin. Capacitors C4 and C8 in 图10-1.
• Minimum of two 100-nF (25 V) capacitors - one close to each VRST pin. Capacitors C3 and C7 in 图10-1.
• Minimum of two 220-nF (25 V) capacitors - one close to each VOFS pin. Capacitors C5 and C6 in 图10-1.
• Minimum of four 100-nF (6.3 V) capacitors - two close to each side of the DMD. Capacitors C1, C2, C9 and
C10 in 图10-1.
10.2 Layout Example
图10-1. Power Supply Connections
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.1.2 Device Nomenclature
图11-1. Part Number Description
11.1.3 Device Markings
The device marking includes the legible character string GHJJJJK. DLP230KPAFQP is the device marking.
Lot Trace Code
GHJJJJK
DLP230KPAFQP
Part Marking
图11-2. DMD Marking
11.2 Chipset Resources
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
表11-1. Chipset Resources
Technical
documents
Design &
development
Chipset Devices
Product folder
Ordering & quality
Support & training
DLP230KP
DLPC3434
DLPA3000
DLPA2000
DLPA2005
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.3 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
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11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.5 Trademarks
Pico™ and TI E2E™ are trademarks of Texas Instruments.
IntelliBright™ is a trademark of Texas Instruments.
DLP® is a registered trademark of Texas Instruments.
is a registered trademark of TI.
所有商标均为其各自所有者的财产。
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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12.1 Package Option Addendum
12.1.1 Packaging Information
Package
Type
Package
Drawing
Package
Qty
Orderable Device
Status (1)
Pins
Eco Plan (2) Lead/Ball Finish
RoHS & Green Call TI
MSL Peak Temp (3)
Op Temp (°C)
–40°C to 90°C
Device Marking(4) (5)
DLP230KPAFQP
ACTIVE
CLGA
FQP
54
100
Level-1-NC-NC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1%
by weight in homogeneous material)
space
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(5) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by
third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable
steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain
information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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DWG NO.
SH
8
5
3
6
1
7
4
1
2515699
REVISIONS
C
COPYRIGHT 2017 TEXAS INSTRUMENTS
UN-PUBLISHED, ALL RIGHTS RESERVED.
NOTES UNLESS OTHERWISE SPECIFIED:
REV
A
DESCRIPTION
ECO 2168534: INITIAL RELEASE
ECO 2168970: CORRECT SUBSTRATE THICKNESS TOL;
ENLARGE APERTURE SLIGHTLY
ECO 2186788: ADD APERTURE SLOT PICTORIALLY
DATE
BY
BMH
9/5/2017
1
2
DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY.
9/15/17
B
C
BMH
BMH
ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION
TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES.
4/7/2020
3
4
BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY.
NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC,
AS SHOWN IN SECTION A-A.
D
C
B
A
D
C
B
A
5
ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN IN VIEW C
(SHEET 2). NO ENCAPSULANT IS ALLOWED ON TOP OF THE WINDOW.
6
7
ENCAPSULANT NOT TO EXCEED THE HEIGHT OF THE WINDOW.
DATUM B IS DEFINED BY A DIA. 2.5 PIN, WITH A FLAT ON THE SIDE FACING
TOWARD THE CENTER OF THE ACTIVE ARRAY, AS SHOWN IN VIEW B (SHEET 2).
WHILE ONLY THE THREE DATUM A TARGET AREAS A1, A2, AND A3 ARE USED
FOR MEASUREMENT, ALL 4 CORNERS SHOULD BE CONTACTED, INCLUDING E1,
TO SUPPORT MECHANICAL LOADS.
8
4
1.1760.05
4
+
-
0.2
0.1
1.71
+
-
0.2
0.1
C
2.96
4
4
(ILLUMINATION
DIRECTION)
1.25
4
90° 1°
4
+
-
0.3
2.50.075
5.92
0.1
4X R0.4 0.1
4
2.5
7
4
A
B
A
4
4
4X (R0.2)
+
-
0.2
0.1
150.08
0.8
4
+
0.3
0.1
FRONT SIDE INDEX MARK
16.8
-
(OFF-STATE
DIRECTION)
5
6
2X ENCAPSULANT
SEE VIEWS C AND D (SHEET 2)
FOR DIMENSIONS
D
1.10.05
1.4030.077
(2.183)
1
8
3 SURFACES INDICATED
IN VIEW B (SHEET 2)
0.038A
0.02D
A
8
4
0.780.063
(2.5)
ACTIVE ARRAY
1.4 0.1
H
H
(SHEET 3)
(SHEET 3)
(1.4)
0.4 MIN TYP
DATE
DRAWN
UNLESS OTHERWISE SPECIFIED
TEXAS
0 MIN TYP
9/5/2017
9/5/2017
9/10/2017
9/6/2017
9/5/2017
9/11/2017
B. HASKETT
ENGINEER
B. HASKETT
QA/CE
DIMENSIONS ARE IN MILLIMETERS
TOLERANCES:
INSTRUMENTS
Dallas Texas
ANGLES 1
TITLE
ICD, MECHANICAL, DMD,
.23 TRP SERIES 246
(FQP PACKAGE)
SECTION A-A
2 PLACE DECIMALS 0.25
1 PLACE DECIMALS 0.50
P. KONRAD
CM
(ROTATED 90°)
SCALE 20 : 1
DIMENSIONAL LIMITS APPLY BEFORE PROCESSES
INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME
Y14.5M-1994
J. GRIMMETT
THIRD ANGLE
PROJECTION
DWG NO
REV
SIZE
D
0314DA
USED ON
REMOVE ALL BURRS AND SHARP EDGES
M. DORAK
APPROVED
R. LONG
2515699
C
PARENTHETICAL INFORMATION FOR REFERENCE ONLY
NEXT ASSY
SCALE
SHEET
OF
APPLICATION
20:1
1
3
INV11-2006a
5
3
6
1
2
7
8
4
DWG NO.
SH
8
5
3
6
1
7
4
2515699
2
2X (1)
A3
2X 15
2X 1.176
A2
2X (0.8)
D
C
B
A
D
C
B
A
4X 1.46
1.25
C
2.5
B
7
4X (1.5)
(1.1)
8
E1
A1
7
VIEW B
DATUMS A, B, C, AND E
(FROM SHEET 1)
15
1.176
3.06
1.25
C
6.12
2.5
B
5
VIEW C
ENCAPSULANT MAXIMUM X/Y DIMENSIONS
(FROM SHEET 1)
2X 0 MIN
6
VIEW D
DWG NO
REV
SIZE
DRAWN
DATE
9/5/2017
TEXAS
2515699
B. HASKETT
C
3
D
ENCAPSULANT MAXIMUM HEIGHT
INSTRUMENTS
Dallas Texas
SCALE
SHEET
OF
2
INV11-2006a
5
3
6
1
2
7
8
4
DWG NO.
SH
8
5
3
6
1
7
4
2515699
3
3
4X (0.108)
(5.184)
ACTIVE ARRAY
5.4410.075
0.9830.05
0.203 0.0635
D
C
B
A
D
C
B
A
2
1.4580.075
1.25
C
(ILLUMINATION
DIRECTION)
(3.556)
APERTURE
(2.916)
(5.16)
WINDOW
ACTIVE ARRAY
2.5
F
3.353 0.0635
G
B
4.1770.05
0.4480.0635
2.989 0.05
5.5350.0635
(5.983)
APERTURE
(OFF-STATE
DIRECTION)
7.0870.05
(10.076) WINDOW
VIEW E
WINDOW AND ACTIVE ARRAY
(FROM SHEET 1)
4 X 0.7424
= 2.9696
3.49
9 X 0.7424 = 6.6816
2.106
12X CIRCULAR TEST PADS
(Ø0.52)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BACK SIDE
INDEX MARK
(42°)
TYP.
(0.15) TYP.
(42°)
TYP.
A
(0.075) TYP.
B
1.856
C
5 X 0.7424
= 3.712
D
2.5
1.25
C
E
F
B
(0.068) TYP.
(0.068) TYP.
(42°)
TYP.
DETAIL G
APERTURE RIGHT EDGE
DETAIL F
APERTURE LEFT EDGE
54X SQUARE LGA PADS
0.52±0.05 X 0.52±0.05
VIEW H-H
SCALE 60 : 1
BACK SIDE METALLIZATION
0.2ABC
0.1A
SCALE 60 : 1
(FROM SHEET 1)
DWG NO
REV
SIZE
DRAWN
DATE
9/5/2017
TEXAS
2515699
B. HASKETT
C
3
D
INSTRUMENTS
Dallas Texas
SCALE
SHEET
OF
3
INV11-2006a
5
3
6
1
2
7
8
4
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