DAC7642VFRG4 [TI]
PARALLEL, WORD INPUT LOADING, 8us SETTLING TIME, 16-BIT DAC, PQFP32, GREEN, PLASTIC, LQFP-32;
| 型号： | DAC7642VFRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PARALLEL, WORD INPUT LOADING, 8us SETTLING TIME, 16-BIT DAC, PQFP32, GREEN, PLASTIC, LQFP-32 输入元件 转换器 |
| 文件： | 总25页 (文件大小：1390K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC7642
DAC7643
DAC7643
DAC7642
SBAS233 – DECEMBER 2001
16-Bit, Dual Voltage Output
DIGITAL-TO-ANALOG CONVERTER
DESCRIPTION
FEATURES
ꢀ LOW POWER: 4mW
The DAC7642 and DAC7643 are dual channel, 16-bit, volt-
age output Digital-to-Analog Converters (DACs) which pro-
vide 15-bit monotonic performance over the specified tem-
perature range. They accept 16-bit parallel input data, have
double-buffered DAC input logic (allowing simultaneous up-
date of all DACs), and provide a readback mode of the
internal input registers. Programmable asynchronous reset
clears all registers to a mid-scale code of 8000H (DAC7642)
or to a zero-scale code of 0000H (DAC7643). These DACs
can operate from a single +5V supply or from +5V and –5V
supplies, providing an output range of 0 to +2.5V or –2.5V to
+2.5V, respectively.
ꢀ UNIPOLAR OR BIPOLAR OPERATION
ꢀ SETTLING TIME: 10µs to 0.003% FSR
ꢀ 15-BIT LINEARITY AND MONOTONICITY:
–40°C to +85°C
ꢀ RESET TO MID-SCALE (DAC7642) OR
ZERO-SCALE (DAC7643)
ꢀ DATA READBACK
ꢀ DOUBLE-BUFFERED DATA INPUTS
APPLICATIONS
ꢀ PROCESS CONTROL
Low power and small size per DAC make the DAC7642 and
DAC7643 ideal for automatic test equipment, DAC-per-pin
programmers, data acquisition systems, and closed-loop
servo-control. The DAC7642 and DAC7643 are available in
a LQFP-32 package and specified over a –40°C to +85°C
temperature range.
ꢀ CLOSED-LOOP SERVO-CONTROL
ꢀ MOTOR CONTROL
ꢀ DATA ACQUISITION SYSTEMS
ꢀ DAC-PER-PIN PROGRAMMERS
VREF
L
VREF
H
Sense
Sense
VREF
L
VREFH
VCC
VSS
DAC7642
DAC7643
16
I/O
Buffer
Input
Register A
DAC
Register A
DATA I/O
DAC A
VOUT
A
A
VOUT
Sense
Sense
Input
Register B
DAC
Register B
DAC B
VOUT
B
B
DACSEL
CS
VOUT
Control
Logic
R/W
GND
RST
LOADDACS
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2001, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
VCC to VSS ............................................................................. –0.3V to 11V
V
V
V
V
CC to GND .......................................................................... –0.3V to 5.5V
REFL to VSS ............................................................. –0.3V to (VCC – VSS
CC to VREFH ............................................................ –0.3V to (VCC – VSS
REFH to VREFL ......................................................... –0.3V to (VCC – VSS
)
)
)
Digital Input Voltage to GND ................................... –0.3V to VCC + 0.3V
Digital Output Voltage to GND ................................. –0.3V to VCC + 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ........................................–40°C to +85°C
Storage Temperature Range .........................................–65°C to +125°C
Lead Temperature (soldering, 10s) ............................................... +300°C
ESD damage can range from subtle performance
degradation to complete device failure. Precision integrated
circuits may be more susceptible to damage because very
small parametric changes could cause the device not to meet
its published specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
MONOTONICITY PACKAGE-LEAD DESIGNATOR(1)
DAC7642VF
14 Bits
LQFP-32
VF
–40°C to +85°C
DAC7642
DAC7642VFT
DAC7642VFR
Tape and Reel, 250
Tape and Reel, 1000
"
"
"
"
"
"
DAC7642VFB
15 Bits
LQFP-32
VF
–40°C to +85°C
DAC7642B
DAC7642VFBT
Tape and Reel, 250
"
"
"
"
"
"
DAC7642VFBR Tape and Reel, 1000
DAC7643VF
14 Bits
LQFP-32
VF
–40°C to +85°C
DAC7643
DAC7643VFT
DAC7643VFR
Tape and Reel, 250
Tape and Reel, 1000
"
"
"
"
"
"
DAC7643VFB
15 Bits
LQFP-32
VF
–40°C to +85°C
DAC7643B
DAC7643VFBT
Tape and Reel, 250
"
"
"
"
"
"
DAC7643VFBR Tape and Reel, 1000
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
DAC7642, DAC7643
2
SBAS233
www.ti.com
ELECTRICAL CHARACTERISTICS (Dual Supply)
At TA = TMIN to TMAX, VCC = +5V, VSS = –5V, VREFH = +2.5V, and VREFL = –2.5V, unless otherwise noted.
DAC7642VF
DAC7643VF
DAC7642VFB
DAC7643VFB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ACCURACY
Linearity Error
Linearity Match
±3
±4
±2
±4
±3
±2
±2
±1
±3
±2
LSB
LSB
LSB
Bits
mV
ppm/°C
mV
ppm/°C
mV
mV
ppm/V
Differential Linearity Error
Monotonicity, TMIN to TMAX
Bipolar Zero Error
Bipolar Zero Error Drift
Full-Scale Error
Full-Scale Error Drift
Bipolar Zero Matching
Full-Scale Matching
Power-Supply Rejection Ratio (PSRR)
14
15
±1
5
±1
5
±1
±1
10
±3
10
±3
10
±3
ꢀ
ꢀ
ꢀ
ꢀ
±1
±1
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
±3
±3
ꢀ
Channel-to-Channel Matching
Channel-to-Channel Matching
At Full-Scale
±3
100
ANALOG OUTPUT
Voltage Output
Output Current
Maximum Load Capacitance
Short-Circuit Current
Short-Circuit Duration
R
L = 10kΩ
VREF
–1.25
L
VREF
+1.25
H
ꢀ
ꢀ
ꢀ
ꢀ
V
mA
pF
No Oscillation
500
–10, +30
Indefinite
ꢀ
ꢀ
ꢀ
mA
GND, VCC or VSS
REFERENCE INPUT
Ref High Input Voltage Range
Ref Low Input Voltage Range
Ref High Input Current
VREFL + 1.25
–2.5
+2.5
VREFH – 1.25
ꢀ
ꢀ
ꢀ
ꢀ
V
V
µA
µA
500
–500
ꢀ
ꢀ
Ref Low Input Current
DYNAMIC PERFORMANCE
Settling Time
Channel-to-Channel Crosstalk
Digital Feedthrough
Output Noise Voltage
DAC Glitch
To ±0.003%, 5V Output Step
8
0.5
2
60
40
10
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
µs
LSB
nV-s
nV/√Hz
nV-s
See Figure 5
f = 10kHz
7FFFH to 8000H or 8000H to 7FFFH
DIGITAL INPUT
VIH
VIL
IIH
0.7 • VCC
ꢀ
ꢀ
V
V
µA
µA
0.3 • VCC
±10
±10
ꢀ
ꢀ
ꢀ
IIL
DIGITAL OUTPUT
VOH
VOL
IOH = –0.8mA
IOL = 1.2mA
3.6
4.5
0.3
ꢀ
ꢀ
V
V
0.4
ꢀ
POWER SUPPLY
VCC
VSS
ICC
ISS
Power
+4.75
–5.25
+5.0
–5.0
0.7
–0.8
7.5
+5.25
–4.75
1.1
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
mA
mA
mW
–1.2
–40
ꢀ
11.5
+85
ꢀ
ꢀ
TEMPERATURE RANGE
Specified Performance
ꢀ
°C
ꢀ Specifications same as DAC7642VF and DAC7643VF.
DAC7642, DAC7643
3
SBAS233
www.ti.com
ELECTRICAL CHARACTERISTICS (Single Supply)
At TA = TMIN to TMAX, VCC = +5V, VSS = 0V, VREFH = +2.5V, and VREFL = 0V, unless otherwise noted.
DAC7642VF
DAC7643VF
DAC7642VFB
DAC7643VFB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ACCURACY
Linearity Error(1)
Linearity Match
Differential Linearity Error
Monotonicity, TMIN to TMAX
Zero-Scale Error
Zero-Scale Error Drift
Full-Scale Error
Full-Scale Error Drift
Zero-Scale Matching
Full-Scale Matching
Power-Supply Rejection Ratio (PSRR)
±3
±4
±2
±4
±3
±2
±2
±1
±3
±2
LSB
LSB
LSB
Bits
mV
ppm/°C
mV
ppm/°C
mV
mV
ppm/V
14
15
±1
5
±1
5
±1
±1
10
±3
10
±3
10
±3
ꢀ
ꢀ
ꢀ
ꢀ
±1
±1
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
±3
±3
ꢀ
Channel-to-Channel Matching
Channel-to-Channel Matching
At Full-Scale
±3
100
ANALOG OUTPUT
Voltage Output
Output Current
Maximum Load Capacitance
Short-Circuit Current
Short-Circuit Duration
RL = 10kΩ
No Oscillation
GND or VCC
0
VREF
+1.25
H
ꢀ
ꢀ
ꢀ
ꢀ
V
mA
pF
–1.25
500
–10, +30
Indefinite
ꢀ
ꢀ
ꢀ
mA
REFERENCE INPUT
Ref High Input Voltage Range
Ref Low Input Voltage Range
Ref High Input Current
VREFL + 1.25
0
+2.5
VREFH – 1.25
ꢀ
ꢀ
ꢀ
ꢀ
V
V
µA
µA
250
–250
ꢀ
ꢀ
Ref Low Input Current
DYNAMIC PERFORMANCE
Settling Time
Channel-to-Channel Crosstalk
Digital Feedthrough
Output Noise Voltage, f = 10kHz
DAC Glitch
To ±0.003%, 2.5V Output Step
8
0.5
2
60
40
10
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
µs
LSB
nV-s
nV/√Hz
nV-s
See Figure 6
7FFFH to 8000H or 8000H to 7FFFH
DIGITAL INPUT
VIH
VIL
IIH
0.7 • VCC
ꢀ
ꢀ
V
V
µA
µA
0.3 • VCC
±10
±10
ꢀ
ꢀ
ꢀ
IIL
DIGITAL OUTPUT
VOH
VOL
IOH = –0.8mA
IOL = 1.2mA
3.6
4.5
0.3
ꢀ
ꢀ
V
V
0.4
ꢀ
POWER SUPPLY
VCC
VSS
ICC
+4.75
0
+5.0
0
0.5
2.5
+5.25
0
0.9
4.5
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
mA
mW
Power
TEMPERATURE RANGE
Specified Performance
–40
+85
ꢀ
ꢀ
°C
ꢀ Specifications same as DAC7642VF and DAC7643VF.
NOTE: (1) If VSS = 0V, specification applies at Code 0040H and above due to possible negative zero-scale error.
DAC7642, DAC7643
4
SBAS233
www.ti.com
PIN CONFIGURATION
Top View
LQFP
VCC
GND
1
2
3
4
5
6
7
8
24 VSS
23 DACSEL
22 RST
DB15
DB14
DB13
DB12
DB11
DB10
21 LOADDACS
20 R/W
DAC7642
DAC7643
19 CS
18 DB0
17 DB1
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
PIN
NAME
DESCRIPTION
1
2
VCC
GND
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CS
Positive Power Supply
Ground
20
R/W
Enabled by CS, Controls Data Read from and Write
to the Input Registers.
21
LOADDACS
RST
DAC Output Registers Load Control. Rising edge
triggered.TransfersDatafromtheInputRegistersto
the DAC Registers, Updating the DAC Output.
3
Data Bit 15, MSB
Data Bit 14
Data Bit 13
Data Bit 12
Data Bit 11
Data Bit 10
Data Bit 9
4
5
22
23
Reset, Rising Edge Triggered. DAC7642 resets to
mid-scale, DAC7643 resets to zero. (Resets Both
Input Registers and DAC Registers)
6
7
DACSEL
VSS
Enabled by CS. Selects the individual DAC Input
Registers. (LOW Selects Register A, HIGH Selects
Register B)
8
9
10
11
12
13
14
15
16
17
18
19
Data Bit 8
24
25
26
Negative Power Supply
DAC B Voltage Output
Data Bit 7
VOUT
B
Data Bit 6
VOUTB Sense
DAC B Output Amplifier Inverting Input. Used to
close the feedback loop at the load.
Data Bit 5
27
28
29
30
31
V
REFH Sense
VREF
VOUT
DAC A and B Reference High Sense Input
DAC A and B Reference High Input
DAC A and B Reference Low Input
Data Bit 4
H
Data Bit 3
L
Data Bit 2
VREFL Sense
VOUTA Sense
DAC A and B Reference Low Sense Input
Data Bit 1
DAC A Output Amplifier Inverting Input. Used to
close the feedback loop at the load.
Data Bit 0, LSB
Chip Select, Active LOW
32
VOUTA
DAC A Output Voltage
DAC7642, DAC7643
5
SBAS233
www.ti.com
TYPICAL CHARACTERISTICS: VSS = 0V
At TA = +25°C, VCC = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified.
+25°C
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
(DAC B, +25°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
+85°C
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
–40°C
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, –40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, –40°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
DAC7642, DAC7643
6
SBAS233
www.ti.com
TYPICAL CHARACTERISTICS: VSS = 0V (Cont.)
At TA = +25°C, VCC = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified.
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
3
2
3
2
Code (FFFFH)
Code (0040H)
DAC A
DAC A
1
1
0
0
DAC B
DAC B
–1
–2
–3
–1
–2
–3
–40
–15
10
35
60
85
–40
–15
10
35
60
85
Temperature (°C)
Temperature (°C)
V
REFH CURRENT vs CODE
VREFL CURRENT vs CODE
(all DACs sent to indicated code)
(all DACs sent to indicated code)
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.00
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
SUPPLY CURRENT vs TEMPERATURE
SUPPLY CURRENT vs DIGITAL INPUT CODE
1
1.0
Data = FFFFH (all DACs)
No Load
No Load
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0.0
All DACs
–40
–15
10
35
60
85
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Temperature (°C)
Digital Input Code
DAC7642, DAC7643
7
SBAS233
www.ti.com
TYPICAL CHARACTERISTICS: VSS = 0V (Cont.)
At TA = +25°C, VCC = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified.
OUTPUT VOLTAGE vs SETTLING TIME
(0V to +2.5V)
OUTPUT VOLTAGE vs SETTLING TIME
(+2.5V to 2mV)
+5V
LDAC
0
Large-Signal Settling Time: 1V/div
Small-Signal Settling
Time: 500µV/div
Small-Signal Settling Time: 500µV/div
Large-Signal Settling Time: 1V/div
+5V
LDAC
0
Time (2µs/div)
Time (2µs/div)
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs MIDSCALE GLITCH PERFORMANCE
vs MIDSCALE GLITCH PERFORMANCE
+5V
LDAC
0
+5V
LDAC
0
8000H to 7FFFH
7FFFH to 8000H
Time (1µs/div)
Time (1µs/div)
BROADBAND NOISE
OUTPUT NOISE VOLTAGE vs FREQUENCY
1000
100
10
10
100
1000
10000
100000
1000000
Time (10µs/div)
Frequency (Hz)
DAC7642, DAC7643
8
SBAS233
www.ti.com
TYPICAL CHARACTERISTICS: VSS = 0V (Cont.)
At TA = +25°C, VCC = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified.
LOGIC SUPPLY CURRENT
VOUT vs RLOAD
vs LOGIC INPUT LEVEL FOR DIGITAL INPUTS
5
4
3
2
1
0
0.50
0.40
0.30
0.20
0.10
0.00
Typical of One
Digital Input
Source
Sink
0.01
0.1
1
10
100
0
1
2
3
4
5
RLOAD (kΩ)
Logic Input Level for Digital Inputs (V)
VSS = –5V
At TA = +25°C, VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
+25°C
(DAC B, +25°C)
1.0
0.5
0
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
+85°C
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85°C)
1.0
0.5
0
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
DAC7642, DAC7643
9
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TYPICAL CHARACTERISTICS: VSS = –5V (Cont.)
At TA = +25°C, VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified.
–40°C
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, –40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, –40°C)
1.0
0.5
0
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
V
REFH CURRENT vs CODE
VREFL CURRENT vs CODE
(all DACs sent to indicated code)
(all DACs sent to indicated code)
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
BIPOLAR ZERO ERROR vs TEMPERATURE
3
3
Code (FFFFH)
Code (8000H)
2
1
2
1
DAC A
DAC A
0
0
–1
–2
–3
–1
–2
–3
DAC B
DAC B
–40
–15
10
35
60
85
–40
–15
10
35
60
85
Temperature (°C)
Temperature (°C)
DAC7642, DAC7643
10
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TYPICAL CHARACTERISTICS: VSS = –5V (Cont.)
At TA = +25°C, VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified.
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
SUPPLY CURRENT vs DIGITAL INPUT CODE
3
2
1.00
0.75
No Load
Code (0000H)
DAC A
ICC
0.50
1
0.25
0
0.00
–0.25
–0.50
–0.75
–1.00
DAC B
–1
–2
–3
ISS
–40
–15
10
35
60
85
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Temperature (°C)
Digital Input Code
VOUT vs RLOAD
SUPPLY CURRENT vs TEMPERATURE
5
4
1
ICC
Source
3
0.5
0
2
1
0
–1
–2
–3
–4
–5
–0.5
–1
Sink
ISS
Data = FFFFH (all DACs)
No Load
–1.5
0.01
0.1
1
10
100
–40
–15
10
35
60
85
RLOAD (kΩ)
Temperature (°C)
OUTPUT VOLTAGE vs SETTLING TIME
OUTPUT VOLTAGE vs SETTLING TIME
(–2.5V to +2.5V)
(+2.5V to –2.5V)
+5V
LDAC
0
Large-Signal Settling Time: 2V/div
Small-Signal Settling Time:
500µV/div
Small-Signal Settling Time: 500µV/div
Large-Signal Settling Time: 2V/div
+5V
LDAC
0
Time (2µs/div)
Time (2µs/div)
DAC7642, DAC7643
11
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TYPICAL CHARACTERISTICS: VSS = –5V (Cont.)
At TA = +25°C, VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified.
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs MIDSCALE GLITCH PERFORMANCE
vs MIDSCALE GLITCH PERFORMANCE
7FFFH to 8000H
8000H to 7FFFH
+5V
LDAC
0
+5V
LDAC
0
Time (1µs/div)
Time (1µs/div)
by the external voltage references VREFL and VREFH, respec-
tively. The digital input is a 16-bit parallel word and the DAC
input registers offer a readback capability. The converters
can be powered from either a single +5V supply or a dual
±5V supply. Each device offers a reset function which imme-
diately sets all DAC output voltages, DAC registers and Input
registers to mid-scale, code 8000H (DAC7642), or to zero-
scale, code 0000H (DAC7643). See Figures 2 and 3 for the
basic configurations of the DAC7642 and DAC7643.
THEORY OF OPERATION
The DAC7642 and DAC7643 are dual channel, voltage
output, 16-bit DACs. The architecture is an R-2R ladder
configuration with the three MSB’s segmented followed by an
operational amplifier that serves as a buffer. Each DAC has
its own R-2R ladder network, segmented MSBs, and output
op amp, as shown in Figure 1. The minimum voltage output
(zero-scale) and maximum voltage output (full-scale) are set
RF
VOUT Sense
VOUT
R
2R
2R
2R
2R
2R
2R
2R
2R
2R
VREF
VREFH Sense
VREF
H
L
VREFL Sense
FIGURE 1. DAC7642 and DAC7643 Architecture.
DAC7642, DAC7643
12
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0V to +2.5V
+2.5V
0V to +2.5V
32 31 30 29 28 27 26 25
VOUTA
VREFL
Sense
VREFH
VOUTB
Sense
VOUTA
Sense
VREFH
Sense
VOUTB
VREFL
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCC
VSS
+5V
1µF
0.1µF
GND
DACSEL
RST
SELECT DAC CHANNEL
RESET DAC REGISTERS
LOAD DAC REGISTERS
READ/WRITE
DB15
DB14
DB13
DB12
DB11
DB10
DAC7642
DAC7643
LDAC
R/W
DATA BUS
CS
CHIP SELECT
DB0
DATA BUS
DB1
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
10 11 12 13 14 15 16
9
FIGURE 2. Basic Single-Supply Operation of the DAC7642 and DAC7643.
–2.5V to
–2.5V to
–2.5V
+2.5V
+2.5V
+2.5V
32 31 30 29 28 27 26 25
VOUTA
VREFL
Sense
VREFH
VOUTB
Sense
VOUTA
Sense
VREFH
Sense
VOUTB
VREFL
1µF
0.1µF
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCC
VSS
+5V
–5V
1µF
0.1µF
GND
DACSEL
RST
SELECT DAC CHANNEL
RESET DAC REGISTERS
LOAD DAC REGISTERS
READ/WRITE
DB15
DB14
DB13
DB12
DB11
DB10
DAC7642
DAC7643
LDAC
R/W
DATA BUS
CS
CHIP SELECT
DB0
DATA BUS
DB1
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
10 11 12 13 14 15 16
9
FIGURE 3. Basic Dual-Supply Operation of the DAC7642 and DAC7643.
DAC7642, DAC7643
13
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ANALOG OUTPUTS
When VSS = –5V (dual-supply operation), the output amplifier
can swing to within 2.25V of the supply rails over the –40°C
to +85°C temperature range. When VSS = 0V (single-supply
operation), and with RLOAD also connected to ground, the
output can swing to ground. Care must also be taken when
measuring the zero-scale error when VSS = 0V. Since the
DAC output cannot swing below ground, the output voltage
may not change for the first few digital input codes (0000H,
0001H, 0002H, etc.) if the output amplifier has a negative
offset. At the negative limit of –2mV, the first specified output
starts at code 0040H.
RW2
VOUT
OUTA Sense 31
REFL Sense 30
REFL 29
REFH 28
A
32
RW1
VOUT
V
V
+V
DAC7642
DAC7643
V
V
+2.5V
VOUT
V
REFH Sense 27
OUTB Sense 26
RW1
V
VOUT
B
25
RW2
Due to the high accuracy of these DACs, system design
problems such as grounding and contact resistance become
very important. A 16-bit converter with a 2.5V full-scale range
has a 1LSB value of 38µV. With a load current of 1mA, a series
wiring and connector resistance of only 40mΩ (RW2) will cause
a voltage drop of 40µV, as shown in Figure 4. To understand
what this means in terms of a system layout, the resistivity of
a typical 1 ounce copper-clad printed circuit board is 1/2 mΩ
per square. For a 1mA load, a 10 milli-inch wide printed circuit
conductor 600 milli-inches long will result in a voltage drop of
30µV.
FIGURE 4. Analog Output Closed-Loop Configuration. RW
represents wiring resistances.
that VSS (the negative power supply) must either be con-
nected to ground or must be in the range of –4.75V to
–5.25V. The voltage on VSS sets several bias points within
the converter. If VSS is not in one of these two configurations,
the bias values may be in error and proper operation of the
device may be affected.
The DAC7642 and DAC7643 offer a force and sense output
configuration for the high open-loop gain output amplifiers.
This feature allows the loop around the output amplifier to be
closed at the load (shown in Figure 4), thus ensuring an
accurate output voltage.
The current into the VREFH input and out of VREFL depends
on the DAC output voltages and can vary from a few
microamps to approximately 0.5mA. The reference input
appears as a varying load to the reference. If the references
applied can sink or source the required current, a reference
buffer is not required. The DAC7642 and DAC7643 feature
reference drive and sense connections such that the internal
errors caused by the changing reference current and the
circuit impedances can be minimized. Figures 5 through 13
show different reference configurations and the effect on the
linearity and differential linearity.
REFERENCE INPUTS
The reference inputs, VREFL and VREFH, can be any voltage
between VSS + 2.5V and VCC – 2.5V provided that VREFH is
at least 1.25V greater than VREFL. The minimum output of
each DAC is equal to VREFL plus a small offset voltage
(essentially, the offset of the output op amp). The maximum
output is equal to VREFH plus a similar offset voltage. Note
+V
OPA2234
VOUT
VOUT
OUTA Sense 31
REFL Sense 30
REFL 29
REFH 28
A
32
V
–2.5V
2200pF
100Ω
V
1000pF
1000pF
–V
V
DAC7642
DAC7643
+V
V
100Ω
V
REFH Sense 27
OUTB Sense 26
+2.5V
2200pF
V
VOUTB 25
VOUT
–V
FIGURE 5. Dual Supply Configuration-Buffered References, Used for Dual-Supply Characteristic Curves.
DAC7642, DAC7643
14
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+V
OPA2350
VOUT
VOUT
OUTA Sense 31
REFL Sense 30
REFL 29
REFH 28
A
32
V
2200pF
100Ω
2kΩ
V
1000pF
1000pF
+0.050V
V
DAC7642
DAC7643
98kΩ
+V
V
100Ω
V
REFH Sense 27
OUTB Sense 26
+2.5V
2200pF
V
VOUTB 25
VOUT
FIGURE 6. Single-Supply Buffered Reference with VREFL of 50mV.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
FIGURE 8. Integral Linearity and Differential Linearity Error
Curves for Figure 9.
FIGURE 7. Integral Linearity and Differential Linearity Error
Curves for Figure 6.
+V
+V
OPA2350
VOUT
VOUT
OUTA Sense 31
REFL Sense 30
REFL 29
REFH 28
A
32
V
+1.25V
2200pF
100Ω
V
1000pF
1000pF
V
DAC7642
DAC7643
+V
V
100Ω
V
REFH Sense 27
OUTB Sense 26
+2.5V
2200pF
V
V
OUTB 25
VOUT
FIGURE 9. Single-Supply Buffered Reference with VREFL = +1.25V and VREFH = +2.5V.
DAC7642, DAC7643
15
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VOUT
VOUT
VOUTA Sense 31
REFL Sense 30
VREF
29
REFH 28
VREFH Sense 27
OUTB Sense 26
VOUT
25
A
32
+V
V
OPA2350
L
DAC7642
DAC7643
+V
V
100Ω
1000pF
+2.5V
2200pF
V
B
VOUT
FIGURE 10. Single-Supply Buffered VREFH.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
FIGURE 11. Linearity and Differential Linearity Error Curves
for Figure 10.
FIGURE 13. Linearity and Differential Linearity Error Curves
for Figure 12.
DIGITAL INTERFACE
See Table I for the basic control logic of the DAC7642 and
DAC7643. Note that each internal register is edge triggered
and not level triggered. When the LOADDACS signal is
transitioned from LOW to HIGH, the digital word existing in
the input register is latched into the DAC register. The first
set of registers (the input registers) are triggered via the
DACSEL, R/W, and CS inputs. Only one of these registers
can be transparent at any given time.
VOUT
VOUT
OUTA Sense 31
REFL Sense 30
REFL 29
VREF
28
A
32
V
V
+V
DAC7642
DAC7643
V
H
+2.5V
V
REFH Sense 27
OUTB Sense 26
The double-buffered architecture is designed mainly so each
DAC input register can be written to at any time without
affecting the DAC outputs. All DAC voltages are updated
simultaneously by the rising edge of LOADDACS. It also
allows multiple devices to be updated simultaneously by
sharing the LOADDACS control from the host with each
device.
V
V
OUTB 25
VOUT
FIGURE 12. Low-Cost Single-Supply Configuration.
DAC7642, DAC7643
16
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INPUT
DAC
DACSEL
R/W
CS
RST
LOADDACS
REGISTER
REGISTER
MODE
DAC
L
H
L
H
X
X
X
L
L
L
L
L
L, H
L, H
L, H
L, H
L, H
L, H
↑
X
X
X
X
↑
Write
Write
Read
Read
Hold
Hold
Hold
Hold
Hold
Write
Hold
Reset
Write Input
Write Input
Read Input
Read Input
Update
A
B
A
H
H
X
X
X
L
B
H
H
X
All
All
All
L, H
L, H
Hold
Reset
Hold
Reset
TABLE I. DAC7642 and DAC7643 Logic Truth Table.
DIGITAL TIMING
Figure 14 and Table II provide detailed timing for the digital
interface of the DAC7642 and DAC7643.
V
REFH – VREFL •N
(
)
VOUT = VREFL +
65,536
(1)
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.
DIGITAL INPUT CODING
The DAC7642 and DAC7643 input data is in Straight Binary
format. The output voltage is given by Equation 1:
tWCS
CS
tWS
tWH
R/W
tRCS
tAH
CS
tAS
tRDH
tRDS
DACSEL
tLH
R/W
tLS
tLWD
tLX
tAS
tAH
±0.003% of FSR
Error Band
LOADDACS
Data In
DACSEL
Data Out
tDH
tDS
tDZ
tS
Data Valid
tCSD
VOUT
Data Read Timing
Data Write Timing
±0.003% of FSR
Error Band
tRSH
tRSS
RST
tS
+FS
(DAC7643)
(DAC7642)
VOUT
Zero-Scale
Midscale
–FS
+FS
VOUT
–FS
FIGURE 14. Digital Input and Output Timing.
DAC7642, DAC7643
17
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SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tRCS
tRDS
tRDH
tDZ
tCSD
tWCS
tWS
tWH
tAS
tAH
tLS
tLH
tLX
tDS
tDH
tLWD
tRSS
tRSH
tS
CS LOW for Read
R/W HIGH to CS LOW
R/W HIGH after CS HIGH
CS HIGH to Data Bus in High Impedance
CS LOW to Data Bus Valid
CS LOW for Write
150
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
10
100
150
100
40
0
10
0
10
30
100
100
0
10
100
10
10
R/W LOW to CS LOW
R/W LOW after CS HIGH
DACSEL Valid to CS LOW
DACSEL Valid after CS HIGH
CS LOW to LOADDACS HIGH
CS LOW after LOADDACS HIGH
LOADDACS HIGH
Data Valid to CS LOW
Data Valid after CS HIGH
LOADDACS LOW
RESET LOW
RESET HIGH
Settling Time
10
TABLE II. Timing Specifications (TA = –40°C to +85°C).
DIGITALLY-PROGRAMMABLE
CURRENT SOURCE
Figure 15 shows a DAC7642 and DAC7643 in a 4-20mA
current output configuration. The output current can be
determined by Equation 3:
The DAC7642 and DAC7643 offer a unique set of features
that allows a wide range of flexibility in designing applications
circuits, such as programmable current sources. The
DAC7642 and DAC7643 offer both a differential reference
input, as well as an open-loop configuration around the
output amplifier. The open-loop configuration around the
output amplifier allows a transistor to be placed within the
loop to implement a digitally-programmable, unidirectional
current source. The availability of a differential reference also
allows programmability for both the full-scale and zero-scale
currents. The output current is calculated as:
(3)
2.5V – 0.5V
125Ω
N Value
65,536
0.5V
IOUT
=
•
+
125Ω
At full-scale, the output current is 16mA plus the 4mA for the
zero current. At zero scale the output current is the offset
current of 4mA (0.5V/125Ω).
VREFH – VREF
L
N Value
65,536
IOUT
=
•
RSENSE
(2)
+ VREFL /RSENSE
(
)
IOUT
+V
VPROGRAMMED
125Ω
OPA2350
VOUT
OUTA Sense 31
REFL Sense 30
REFL 29
REFH 28
A
32
V
2200pF
100Ω
20kΩ
V
1000pF
1000pF
V
DAC7642
DAC7643
80kΩ
+V
V
100Ω
VREFH Sense 27
VOUTB Sense 26
+2.5V
2200pF
V
OUTB 25
IOUT
VPROGRAMMED
125Ω
FIGURE 15. 4-20mA Digitally Controlled Current Source.
18
DAC7642, DAC7643
SBAS233
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PACKAGE DRAWING
VF (S-PQFP-G32)
MTQF002B – JANUARY 1995 – REVISED MAY 2000
PLASTIC QUAD FLATPACK
0,45
0,25
0,20
M
0,80
24
17
25
16
32
9
0,13 NOM
1
8
5,60 TYP
7,20
SQ
6,80
Gage Plane
9,20
8,80
SQ
0,25
0,05 MIN
0°–7°
1,45
1,35
0,75
0,45
Seating Plane
0,10
1,60 MAX
4040172/D 04/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
DAC7642, DAC7643
19
SBAS233
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
DAC7642VFBT
DAC7642VFT
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
VF
32
32
32
32
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
DAC7642
B
ACTIVE
ACTIVE
VF
VF
VF
VF
250
250
Green (RoHS
& no Sb/Br)
-40 to 85
DAC7642
DAC7642VFTG4
DAC7643VFBR
DAC7643VFBRG4
Green (RoHS
& no Sb/Br)
-40 to 85
DAC7642
OBSOLETE
OBSOLETE
TBD
-40 to 85
DAC7643
B
TBD
Call TI
Call TI
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
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value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC7642VFBT
DAC7642VFT
LQFP
LQFP
VF
VF
32
32
250
250
330.0
330.0
16.4
16.4
9.6
9.6
9.6
9.6
1.9
1.9
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC7642VFBT
DAC7642VFT
LQFP
LQFP
VF
VF
32
32
250
250
367.0
367.0
367.0
367.0
38.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF002B – JANUARY 1995 – REVISED MAY 2000
VF (S-PQFP-G32)
PLASTIC QUAD FLATPACK
0,45
0,25
0,20
M
0,80
24
17
25
16
32
9
0,13 NOM
1
8
5,60 TYP
7,20
SQ
6,80
Gage Plane
9,20
8,80
SQ
0,25
0,05 MIN
0°–7°
1,45
1,35
0,75
0,45
Seating Plane
0,10
1,60 MAX
4040172/D 04/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
1
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