DAC43401DSGTQ1_技术文档

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

DACx3401-Q1 具有非易失性存储器和兼容PMBus™ 的I²C 接口且采用微型2 × 2

WSON 封装的汽车类10 位和8 位电压输出智能DAC

1 特性

3 说明

• 符合面向汽车应用的AEC-Q100 标准：

10 位 DAC53401-Q1 和 8 位 DAC43401-Q1

(DACx3401-Q1) 是具有引脚兼容性的汽车类缓冲电压

输出智能数模转换器 (DAC) 系列产品。这些器件功耗

极低且均可采用微型 8 引脚 WSON 封装。凭借这组特

性以及微型封装和低功耗，DACx3401-Q1 非常适合以

下应用：LED 和通用偏置点生成、电源控制和 PWM

信号生成。

– 温度等级1：–40°C 至+125°C，T_A

• 1 LSB INL 和DNL（10 位和8 位）

• 宽工作电压范围：

– 电源：1.8V 至5.5V

• 兼容PMBus^™的I²C 接口

– 标准模式、快速模式和快速+ 模式

– 由A0 引脚配置的四个从器件地址选项

– 1.62V V_IH(V_DD= 5.5V)

这些器件具有非易失性存储器 (NVM)、一个内部基准

和一个兼容 PMBus 的 I²C 接口。DACx3401-Q1 在内

部基准或电源基准下运行，提供 1.8V 至 5.5V 的满量

程输出。该器件通过 I²C 接口通信。这些器件支持 I²C

标准模式、快速模式和快速+ 模式。

• 用户可编程的非易失性存储器（NVM、EEPROM）

– 保存和撤销所有寄存器设置

• 可编程波形生成：方形、斜坡和锯齿状

• 使用三角波形和FB 引脚的脉宽调制(PWM) 输出

• 数字压摆率控制

DACx3401-Q1 是智能 DAC 器件，因为它们具有高级

集成特性。这些智能 DAC 具有强制检测输出、PWM

输出和 NVM 功能，无需使用软件即可实现系统性能和

控制功能。

• 内部基准

• 超低功耗：在1.8V 时为0.2 mA

• 灵活启动：高阻抗或10K-GND

• 微型封装：8 引脚WSON (2mm × 2mm)

器件信息

器件型号⁽¹⁾

DAC53401-Q1

DAC43401-Q1

封装尺寸（标称值）

封装

2 应用

WSON (8)

2.00mm × 2.00mm

• 汽车USB 充电

• 前灯

• 后灯

(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

VCC

LED

VDD

I_LED= I_SET

V_OUT

DACx3401-Q1

Q1

+

V_GS

V_FB

œ

V_DAC

R_SET

I_SET

功能方框图

使用DACx3401-Q1 的LED 偏置

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLASE30

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

Table of Contents

8.2 Functional Block Diagram.........................................18

8.3 Feature Description...................................................19

8.4 Device Functional Modes..........................................25

8.5 Programming............................................................ 27

8.6 Register Map.............................................................32

9 Application and Implementation..................................39

9.1 Application Information............................................. 39

9.2 Typical Applications.................................................. 39

10 Power Supply Recommendations..............................43

11 Layout...........................................................................43

11.1 Layout Guidelines................................................... 43

11.2 Layout Example...................................................... 43

12 Device and Documentation Support..........................44

12.1 Documentation Support.......................................... 44

12.2 接收文档更新通知................................................... 44

12.3 支持资源..................................................................44

12.4 Trademarks.............................................................44

12.5 静电放电警告.......................................................... 44

12.6 术语表..................................................................... 44

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 4

7.1 Absolute Maximum Ratings ....................................... 4

7.2 ESD Ratings .............................................................. 4

7.3 Recommended Operating Conditions ........................4

7.4 Thermal Information ...................................................4

7.5 Electrical Characteristics ............................................5

7.6 Timing Requirements: I²C Standard Mode ................ 7

7.7 Timing Requirements: I²C Fast Mode ........................8

7.8 Timing Requirements: I²C Fast Mode Plus ................8

7.9 Typical Characteristics: V_DD= 1.8 V (Reference

= V_DD) or V_DD= 2 V (Internal Reference)......................9

7.10 Typical Characteristics: V_DD= 5.5 V (Reference

= V_DD) or V_DD= 5 V (Internal Reference)....................11

7.11 Typical Characteristics............................................ 13

8 Detailed Description......................................................18

8.1 Overview...................................................................18

Information.................................................................... 44

4 Revision History

DATE

REVISION

NOTES

October 2020

*

Initial release.

2

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

5 Device Comparison Table

DEVICE

RESOLUTION

10-bit

DAC53401-Q1

DAC43401-Q1

8-bit

6 Pin Configuration and Functions

A0

SCL

SDA

CAP

1

2

3

4

8

7

6

5

OUT

FB

VDD

AGND

Not to scale

图6-1. DSG Package, 8-Pin WSON, Top View

表6-1. Pin Functions

TYPE

DESCRIPTION

NAME

A0

NO.

1

Input

Four-state address input

AGND

5

Ground

Ground reference point for all circuitry on the device

External capacitor for the internal LDO. Connect a capacitor (0.5 µF to 15 µF) between CAP and

AGND.

CAP

4

Input

FB

7

8

Input

Voltage feedback pin

OUT

Output

Analog output voltage from DAC

Serial interface clock. This pin must be connected to the supply voltage with an external pullup

resistor.

SCL

2

Input

Data are clocked into or out of the input register. This pin is a bidirectional, and must be connected to

the supply voltage with an external pullup resistor.

SDA

VDD

3

6

Input/output

Power

Analog supply voltage: 1.8 V to 5.5 V

Submit Document Feedback

3

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–10

–40

–65

MAX

6

UNIT

V

V_DD

Supply voltage, V_DDto A_GND

Digital input(s) to A_GND

CAP to A_GND

V_DD+ 0.3

1.65

V

V_FBto A_GND

V_DD+ 0.3

10

V

V_OUTto A_GND

V

Current into any pin

Junction temperature

Storage temperature

mA

°C

T_J

150

T_stg

150

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

HBM ESD classification level 2

±2000

Electrostatic

discharge

V_(ESD)

V

Charged device model (CDM), per AEC Q100-011

CDM ESD classification level C5

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.71

1.62

NOM

MAX UNIT

V_DD

V_IH

V_IL

T_A

Positive supply voltage to ground (A_GND

)

5.5

V

Digital input high voltage, 1.7 V < V_DD≤5.5 V

Digital input low voltage

0.4

Ambient temperature

125 °C

–40

7.4 Thermal Information

DACx3401-Q1

THERMAL METRIC⁽¹⁾

DSG (WSON)

UNIT

8 PINS

49

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

50

24.1

1.1

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Ψ_JT

24.1

8.7

Ψ_JB

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

4

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

7.5 Electrical Characteristics

all minimum/maximum specifications at T_A= –40°C to +125°C and typical specifications at T_A= 25°C, 1.8 V ≤V_DD≤5.5 V,

DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (R_L= 5 kΩto AGND) and capacitive

load (C_L= 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

STATIC PERFORMANCE

DAC53401-Q1

DAC43401-Q1

10

8

Resolution

Bits

INL Relative accuracy⁽¹⁾

1

LSB

–1

DNL Differential nonlinearity⁽¹⁾

Code 0d into DAC

6

12

15

Zero code error

mV

Internal V_REF, gain = 4x, V_DD= 5.5 V

Zero code error temperature

coefficient

±10

0.25

µV/°C

%FSR

Offset error⁽⁴⁾

0.6

0.5

–0.6

–0.5

Offset error temperature

coefficient⁽⁴⁾

±0.0003

0.25

%FSR/°C

%FSR

Gain error⁽⁴⁾

Gain error temperature

coefficient⁽⁴⁾

±0.0008

%FSR/°C

1.8 V ≤V_DD≺ 2.7 V, code 1023d into DAC,

0.5

0.25

1

–1

no headroom

Full scale error

%FSR

2.7 V ≤V_DD≤5.5 V, code 1023d into DAC,

no headroom

0.5

–0.5

Full scale error temperature

coefficient

±0.0008

%FSR/°C

OUTPUT CHARACTERISTICS

Output voltage

Reference tied to V_DD

0

5.5

1

V

R_L= Infinite, phase margin = 30°

R_L= 5 kΩ, phase margin = 30°

C_L

Capacitive load⁽²⁾

Load regulation

nF

2

DAC at midscale, –10 mA ≤I_OUT≤10 mA,

V_DD= 5.5 V

0.4

10

mV/mA

V_DD= 1.8 V, full-scale output shorted to A_GNDor

zero-scale output shorted to V_DD

V_DD= 2.7 V, full-scale output shorted to A_GNDor

zero-scale output shorted to V_DD

Short circuit current

25

mA

V_DD= 5.5 V, full-scale output shorted to A_GNDor

zero-scale output shorted to V_DD

50

To V_DD(DAC output unloaded, internal reference =

1.21 V), V_DD≥1.21 ☓ gain + 0.2 V

0.2

0.8

V

To V_DD

Output voltage headroom⁽¹⁾

(DAC output unloaded, reference tied to V_DD

)

%FSR

To V_DD(I_LOAD= 10 mA at V_DD= 5.5 V, I_LOAD= 3 mA at

V_DD= 2.7 V, I_LOAD= 1 mA at V_DD= 1.8 V), DAC code

= full scale

10

DAC output enabled and DAC code = midscale

DAC output enabled and DAC code = 4d

DAC output enabled and DAC code = 1016d

0.25

0.26

V_OUTdc output impedance

V_FBdc output impedance⁽³⁾

Ω

DAC output enabled, DAC reference tied to VDD (gain

= 1x) or internal reference (gain = 1.5x or 2x)

160

192

200

240

288

Z_O

kΩ

DAC output enabled, internal V_REF, gain = 3x or 4x

Submit Document Feedback

5

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

7.5 Electrical Characteristics (continued)

all minimum/maximum specifications at T_A= –40°C to +125°C and typical specifications at T_A= 25°C, 1.8 V ≤V_DD≤5.5 V,

DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (R_L= 5 kΩto AGND) and capacitive

load (C_L= 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OUT+ V_FBdc output

leakage⁽²⁾

At startup, measured when DAC output is disabled and

held at V_DD/ 2 for V_DD= 5.5 V

5

nA

Power supply rejection ratio

(dc)

Internal V_REF, gain = 2x, DAC at midscale;

V_DD= 5 V ±10%

0.25

8

mV/V

µs

DYNAMIC PERFORMANCE

1/4 to 3/4 scale and 3/4 to 1/4 scale settling to

10%FSR, V_DD= 5.5 V

t_settOutput voltage settling time

1/4 to 3/4 scale and 3/4 to 1/4 scale settling to

10%FSR, V_DD= 5.5 V, internal V_REF, gain = 4x

12

1

Slew rate

V_DD= 5.5 V

V/µs

mV

At startup (DAC output disabled), R_L= 5 kΩ,

C_L= 200 pF

75

Power-on glitch magnitude

200

250

34

At startup (DAC output disabled), R_L= 100 kΩ

DAC output disabled to enabled (DAC registers at zero

scale, R_L= 100 kΩ

Output enable glitch

magnitude

mV

0.1 Hz to 10 Hz, DAC at midscale, V_DD= 5.5 V

Output noise voltage (peak to

peak)

V_n

µV_PP

Internal V_REF, gain = 4x, 0.1 Hz to 10 Hz, DAC at

midscale, V_DD= 5.5 V

70

Measured at 1 kHz, DAC at midscale, V_DD= 5.5 V

0.2

0.7

Output noise density

µV/√Hz

Internal V_REF,gain = 4x,, measured at 1 kHz, DAC at

midscale, V_DD= 5.5 V

Internal V_REF, gain = 4x, 200-mV 50 or 60 Hz sine

wave superimposed on power supply voltage, DAC at

midscale

Power supply rejection ratio

(ac)⁽³⁾

dB

–71

±1 LSB change around mid code (including

feedthrough)

Code change glitch impulse

10

15

nV-s

mV

Code change glitch impulse

magnitude

±1 LSB change around mid code (including

feedthrough)

VOLTAGE REFERENCE

Initial accuracy

T_A= 25°C

1.212

V

Reference output temperature

coefficient⁽²⁾

50 ppm/°C

EEPROM

20000

1000

50

–40°C ≤T_A≤+85°C

T_A> 85°C

Endurance

Cycles

Years

Data retention⁽²⁾

T_A= 25°C

EEPROM programming write

cycle time⁽²⁾

10

20

ms

DIGITAL INPUTS

Digital feedthrough

Pin capacitance

DAC output static at midscale, fast mode plus, SCL

toggling

20

10

nV-s

pF

Per pin

6

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

7.5 Electrical Characteristics (continued)

all minimum/maximum specifications at T_A= –40°C to +125°C and typical specifications at T_A= 25°C, 1.8 V ≤V_DD≤5.5 V,

DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (R_L= 5 kΩto AGND) and capacitive

load (C_L= 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER

Load capacitor - CAP pin⁽²⁾

0.5

15

µF

mA

µA

Normal mode, DACs at full scale, digital pins static

DAC power-down, internal reference power down

0.5

80

0.8

I_DD

Current flowing into VDD

(1) Measured with DAC output unloaded. For external reference between end-point codes: 8d to 1016d for 10-bit resolution, 2d to 254d for

8-bit resolution. For internal reference V_DD≥1.21 x gain + 0.2 V, between end-point codes: 8d to 1016d for 10-bit resolution, 2d to

254d for 8-bit resolution.

(2) Specified by design and characterization, not production tested.

(3) Specified with 200-mV headroom with respect to reference value when internal reference is used.

(4) Measured with DAC output unloaded. For 10-bit resolution, between end-point codes: 8d to 1016d and for 8-bit resolution, between

end-point codes: 2d to 254d.

7.6 Timing Requirements: I²C Standard Mode

all input signals are timed from VIL to 70% of V_DD, 1.8 V ≤V_DD≤5.5 V, –40°C ≤T_A≤+125°C, and

1.8 V ≤V_pull-up≤V_DDV (unless otherwise noted)

MIN

NOM

MAX

UNIT

MHz

µs

f_SCLK

t_BUF

SCL frequency

0.1

Bus free time between stop and start conditions

Hold time after repeated start

Repeated start setup time

Stop condition setup time

Data hold time

4.7

4

t_HDSTA

t_SUSTA

t_SUSTO

t_HDDAT

t_SUDAT

t_LOW

t_HIGH

t_F

µs

4.7

4

µs

0

ns

Data setup time

250

4700

4000

ns

SCL clock low period

ns

SCL clock high period

Clock and data fall time

Clock and data rise time

ns

300

ns

t_R

1000

ns

Submit Document Feedback

7

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

7.7 Timing Requirements: I²C Fast Mode

all input signals are timed from VIL to 70% of V_DD, 1.8 V ≤V_DD≤5.5 V, –40°C ≤T_A≤+125°C, and

1.8 V ≤V_pull-up≤V_DDV (unless otherwise noted)

MIN

NOM

MAX

UNIT

MHz

µs

f_SCLK

t_BUF

SCL frequency

0.4

Bus free time between stop and start conditions

Hold time after repeated start

Repeated start setup time

Stop condition setup time

Data hold time

1.3

0.6

t_HDSTA

t_SUSTA

t_SUSTO

t_HDDAT

t_SUDAT

t_LOW

t_HIGH

t_F

µs

0.6

µs

0.6

µs

0

ns

Data setup time

100

1300

600

ns

SCL clock low period

ns

SCL clock high period

Clock and data fall time

Clock and data rise time

ns

300

ns

t_R

ns

7.8 Timing Requirements: I²C Fast Mode Plus

all input signals are timed from VIL to 70% of V_DD, 1.8 V ≤V_DD≤5.5 V, –40°C ≤T_A≤+125°C, and

1.8 V ≤V_pull-up≤V_DDV (unless otherwise noted)

MIN

NOM

MAX

UNIT

MHz

µs

f_SCLK

t_BUF

SCL frequency

1

Bus free time between stop and start conditions

Hold time after repeated start

Repeated start setup time

Stop condition setup time

Data hold time

0.5

0.26

0

t_HDSTA

t_SUSTA

t_SUSTO

t_HDDAT

t_SUDAT

t_LOW

t_HIGH

t_F

µs

ns

Data setup time

50

ns

SCL clock low period

0.5

µs

SCL clock high period

Clock and data fall time

Clock and data rise time

0.26

µs

120

ns

t_R

ns

8

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

7.9 Typical Characteristics: V_DD= 1.8 V (Reference = V_DD) or V_DD= 2 V (Internal Reference)

at T_A= 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)

1

0.8

0.6

0.4

0.2

0

1

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

Reference = VDD, gain = 1x

Internal reference, gain = 1.5x

Reference = VDD, gain = 1x

Internal reference, gain = 1.5x

0

128

256

384

512

Code

640

768

896 1023

0

128

256

384

512

Code

640

768

896 1023

图7-1. Integral Linearity Error vs Digital Input Code

图7-2. Differential Linearity Error vs Digital Input Code

0.25

0.2

1

INL max, reference = VDD, gain = 1x

INL min, reference = VDD, gain = 1x

INL max, internal reference, gain = 1.5x

0.8

0.15

0.1

0.6

INL min, internal reference, gain = 1.5x

0.4

0.05

0

0.2

0

-0.05

-0.1

-0.15

-0.2

-0.4

-0.6

-0.8

-1

Reference = VDD, gain = 1x

-0.2

Internal reference, gain = 1.5x

-0.25

0

128

256

384

512

Code

640

768

896 1023

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

图7-3. Total Unadjusted Error vs Digital Input Code

图7-4. Integral Linearity Error vs Temperature

1

0.8

0.6

0.4

0.2

0

DNL max, reference = VDD, gain = 1x

DNL min, reference = VDD, gain = 1x

DNL max, internal reference, gain = 1.5x

0.8

0.6

DNL min, internal reference, gain = 1.5x

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

TUE max, reference = VDD, gain = 1x

TUE min, reference = VDD, gain = 1x

TUE max, internal reference, gain = 1.5x

TUE min, internal reference, gain = 1.5x

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

图7-5. Differential Linearity Error vs Temperature

图7-6. Total Unadjusted Error vs Temperature

Submit Document Feedback

9

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

7.9 Typical Characteristics: V_DD= 1.8 V (Reference = V_DD) or V_DD= 2 V (Internal Reference)

(continued)

at T_A= 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)

8

7

6

5

4

3

2

1

0

0.5

0.3

0.1

-0.1

-0.3

-0.5

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (èC)

Reference = V_DD

图7-7. Zero Code Error vs Temperature

Reference = V_DD

图7-8. Offset Error vs Temperature

0.5

0.4

0.3

0.2

0.1

0

Reference = VDD, gain = 1x

Internal reference, gain = 1.5x

0.3

0.1

-0.1

-0.3

-0.5

-0.1

-0.2

-0.3

-0.4

-0.5

Reference = VDD, gain = 1x

Internal reference, gain = 1.5x

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (èC)

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (èC)

图7-9. Gain Error vs Temperature

图7-10. Full-Scale Error vs Temperature

10

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

7.10 Typical Characteristics: V_DD= 5.5 V (Reference = V_DD) or V_DD= 5 V (Internal Reference)

at T_A= 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)

1

0.8

0.6

0.4

0.2

0

1

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

Reference = VDD, gain = 1x

Internal reference, gain = 4x

Reference = VDD, gain = 1x

Internal reference, gain = 4x

0

128

256

384

512

Code

640

768

896 1023

0

128

256

384

512

Code

640

768

896 1023

图7-11. Integral Linearity Error vs Digital Input Code

图7-12. Differential Linearity Error vs Digital Input Code

0.5

1

Reference = VDD, gain = 1x

Internal reference, gain = 4x

INL min, reference = VDD, gain = 1x

INL max, reference = VDD, gain = 1x

INL min, internal reference, gain = 4x

0.4

0.8

0.3

0.2

0.1

0

0.6

INL max, internal reference, gain = 4x

0.4

0.2

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.2

-0.4

-0.6

-0.8

-1

0

128

256

384

512

Code

640

768

896 1023

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

图7-13. Total Unadjusted Error vs Digital Input Code

图7-14. Integral Linearity Error vs Temperature

1

0.5

DNL max, reference = VDD, gain = 1x

DNL min, reference = VDD, gain = 1x

DNL max, internal reference, gain = 4x

TUE max, reference = VDD, gain = 1x

TUE min, reference = VDD, gain = 1x

TUE max, internal reference, gain = 4x

TUE min, internal reference, gain = 4x

0.8

0.4

0.3

0.2

0.1

0

0.6

DNL min, internal reference, gain = 4x

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1

-0.1

-0.2

-0.3

-0.4

-0.5

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

图7-15. Differential Linearity Error vs Temperature

图7-16. Total Unadjusted Error vs Temperature

Submit Document Feedback

11

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

7.10 Typical Characteristics: V_DD= 5.5 V (Reference = V_DD) or V_DD= 5 V (Internal Reference)

(continued)

at T_A= 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)

2

1.5

1

0.5

0.3

0.5

0

0.1

-0.1

-0.3

-0.5

-1

-1.5

-2

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (èC)

Reference = V_DD

图7-17. Zero Code Error vs Temperature

Reference = V_DD

图7-18. Offset Error vs Temperature

0.5

Reference = VDD, gain = 1x

Internal reference, gain = 4x

Reference = VDD, gain 1x

Internal reference, gain 4x

0.3

0.1

-0.1

-0.3

-0.5

-0.1

-0.3

-0.5

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (èC)

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (èC)

图7-19. Gain Error vs Temperature

图7-20. Full-Scale Error vs Temperature

12

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

7.11 Typical Characteristics

at T_A= 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)

Reference = V_DD

图7-21. Integral Linearity Error

Reference = V_DD

图7-22. Differential Linearity Error

vs Supply Voltage

Reference = V_DD

图7-23. Total Unadjusted Error

图7-24. Zero-Code Error

vs Supply Voltage

Reference = V_DD

图7-25. Offset Error vs Supply Voltage

Reference = V_DD

图7-26. Gain Error vs Supply Voltage

Submit Document Feedback

13

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

7.11 Typical Characteristics (continued)

at T_A= 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)

0.4

0.35

0.3

Reference = VDD, gain = 1x

Internal reference, gain = 1.5x

0.25

0.2

0.15

0.1

0.05

0

128

256

384

512

Code

640

768

896 1023

V_DD= 1.8 V

Reference = V_DD

图7-27. Full-Scale Error vs Supply Voltage

图7-28. Supply Current vs Digital Input Code

0.4

0.35

0.3

0.4

0.35

0.3

Reference = VDD, gain = 1x

Internal reference, gain = 4x

I_DD, V_DD= 1.8 V

I_DD, V_DD= 3.3 V

I_DD, V_DD= 5.5 V

0.25

0.2

0.25

0.2

0.15

0.1

0.15

0.1

0.05

0

0.05

0

128

256

384

512

Code

640

768

896 1023

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

V_DD= 5.5 V

图7-29. Supply Current vs Digital Input Code

Reference = V_DD, DAC at midscale

图7-30. Supply Current vs Temperature

0.4

0.35

0.3

I_DD, V_DD= 3.3 V

I_DD, V_DD= 5.5 V

0.25

0.2

0.15

0.1

0.05

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

DAC at midscale

Internal reference (gain = 4x), DAC at midscale

图7-32. Supply Current vs Supply Voltage

图7-31. Supply Current vs Temperature

14

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

7.11 Typical Characteristics (continued)

at T_A= 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)

0.1

0.0875

0.075

0.0625

0.05

6

5

4

3

2

0.0375

0.025

0.0125

0

1

0

I_DD, V_DD= 1.8 V

I_DD, V_DD= 3.3 V

I_DD, V_DD= 5.5 V

-1

-2

Reference = V_DD= 1.8 V

Reference = V_DD= 5.5 V

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

-20

-15

-10

-5

0

5

Load Current (mA)

10

15

20

Reference = V_DD, DAC powered down

图7-33. Power-Down Current vs Temperature

图7-34. Source and Sink Capability

Reference = V_DD= 5.5 V, DAC code transition from midscale

to midscale + 1 LSB, DAC load = 5kΩ|| 200pF

to midscale –1 LSB, DAC load = 5kΩ|| 200pF

图7-35. Glitch Impulse, Rising Edge,

图7-36. Glitch Impulse, Falling Edge,

1-LSB Step

Reference = V_DD= 5.5 V, DAC load = 5kΩ|| 200pF

图7-37. Full-Scale Settling Time, Rising Edge

Reference = V_DD= 5.5 V, DAC load = 5kΩ|| 200pF

图7-38. Full-Scale Settling Time, Falling Edge

Submit Document Feedback

15

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

7.11 Typical Characteristics (continued)

at T_A= 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)

V_DD(1 V / div)

V_OUTunloaded (500 mV / div)

V_OUT10K-GND (15 mV / div)

V_DD(1 V / div)

V_OUTunloaded (500 mV / div)

V_OUT10K-GND (15 mV / div)

0

5

10

15

20

25

Time (ms)

30

35

40

45

50

0

5

10

15

20

25

Time (ms)

30

35

40

45

50

Reference = V_DD= 5.5 V

图7-39. Power-on Glitch

Reference = V_DD= 5.5 V

图7-40. Power-off Glitch

-40

V_OUT(6 mV / div)

SCL (4 V / div)

-50

-60

-70

-80

-90

-100

0

1

2

3

4

5

10

20 30 50 70100 200

500 1000 2000 5000 10000

Time (ms)

Frequency (Hz)

Reference = V_DD= 5.5 V, Fast+ mode, DAC at midscale, DAC

Internal reference (gain = 4x), V_DD= 5.25 V + 0.25 V_PP, DAC

load = 5kΩ|| 200pF

at midscale, DAC load = 5kΩ|| 200pF

图7-41. Clock Feedthrough

图7-42. DAC Output AC PSRR vs Frequency

Reference = V_DD= 5.5 V

Internal reference (gain = 4x), V_DD= 5.5 V

图7-43. DAC Output Noise Spectral Density

图7-44. DAC Output Noise Spectral Density

16

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

7.11 Typical Characteristics (continued)

at T_A= 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)

Reference = V_DD= 5.5 V, DAC at midscale

Internal reference (gain = 4x), V_DD= 5.5 V, DAC at midscale

图7-45. DAC Output Noise: 0.1 Hz to 10 Hz

图7-46. DAC Output Noise: 0.1 Hz to 10 Hz

Submit Document Feedback

17

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

8 Detailed Description

8.1 Overview

The 10-bit DAC53401-Q1 and 8-bit DAC43401-Q1 (DACx3401-Q1) are a pin-compatible family of automotive,

buffered voltage-output, smart digital-to-analog converters (DACs). These smart DACs contain nonvolatile

memory (NVM), an internal reference, a PMBus-compatible I²C interface, and a force-sense output. The

DACx3401-Q1 operate with either an internal reference or with a power supply as the reference, and provide a

full-scale output of 1.8 V to 5.5 V.

The devices communicate through an I²C interface and support I²C standard mode (100 kbps), fast mode (400

kbps), and fast mode plus (1 Mbps). These devices also support specific PMBus commands such as turn on/off,

margin high or low, and more. The DACx3401-Q1 also include digital slew rate control, and support basic signal

generation such as square, ramp, and sawtooth waveforms. These devices can generate pulse-width modulation

(PWM) output with the combination of the triangular or sawtooth waveform and the FB pin. These features

enable DACx3401-Q1 to go beyond the limitations of a conventional DAC that depends on a processor to

function. Because of processor-less operation and the smart feature set, the DACx3401-Q1 are called smart

DACs.

The DACx3401-Q1 devices have a power-on-reset (POR) circuit that makes sure all the registers start with

default or user-programmed settings using NVM. The DAC output powers on in high-impedance mode (default);

this setting can be programmed to 10kΩ-GND using NVM.

8.2 Functional Block Diagram

18

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

8.3 Feature Description

8.3.1 Digital-to-Analog Converter (DAC) Architecture

The DACx3401-Q1 family of devices consists of string architecture with an output buffer amplifier. 节 8.2 shows

the DAC architecture within the block diagram. This DAC architecture operates from a 1.8-V to 5.5-V power

supply. These devices consume only 0.2 mA of current when using a 1.8-V power supply. The DAC output pin

starts up in high impedance mode making it an excellent choice for power-supply control applications. To change

the power-up mode to 10kΩ-GND, program the DAC_PDN bit (address: D1h), and load these bits in the device

NVM. The DACx3401-Q1 devices include a smart feature set to enable processor-less operation and high-

integration. The NVM enables a predictable startup. The integrated functions and the FB pin enable PWM output

for control applications. The FB pin enables this device to be used as a programmable comparator. The digital

slew rate control and the Hi-Z power-down modes enable a hassle-free voltage margining and function.

8.3.1.1 Reference Selection and DAC Transfer Function

The device writes the input data to the DAC data registers in straight-binary format. After a power-on or a reset

event, the device sets all DAC registers to the values set in the NVM.

8.3.1.1.1 Power Supply as Reference

By default, the DACx3401-Q1 operate with the power-supply pin (VDD) as a reference. 方程式 1 shows DAC

transfer function when the power-supply pin is used as reference.

DAC _DATA

2^N

V_OUT

=

ì V_DD

(1)

where

• N is the resolution in bits, either 8 (DAC43401-Q1) or 10 (DAC53401-Q1).

• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC register.

• DAC_DATA ranges from 0 to 2^N–1.

• V_DDis used as the DAC reference voltage.

8.3.1.1.2 Internal Reference

The DACx3401-Q1 also contain an internal reference that is disabled by default. Enable the internal reference

by writing 1 to REF_EN (address D1h). The internal reference generates a fixed 1.21-V voltage (typical). Using

DAC_SPAN (address D1h) bits, gain of 1.5x, 2x, 3x, 4x can be achieved for the DAC output voltage (V_OUT) 方程

式2 shows DAC transfer function when the internal reference is used.

DAC_DATA

2^N

V_OUT

=

ì V_REFìGAIN

(2)

where

• N is the resolution in bits, either 8 (DAC43401-Q1) or 10 (DAC53401-Q1).

• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC register

• DAC_DATA ranges from 0 to 2^N–1.

• V_REFis the internal reference voltage = 1.21 V.

• GAIN = 1.5x, 2x, 3x, 4x based on DAC_SPAN (address D1h) bits.

Submit Document Feedback

19

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

8.3.2 DAC Update

The DAC output pin (OUT) is updated at the end of I²C DAC write frame.

8.3.2.1 DAC Update Busy

The DAC_UPDATE_BUSY bit (address D0h) is set to 1 by the device when certain DAC update operations,

such as function generation, transition to margin high or low, or any of the medical alarms are in progress. When

the DAC_UPDATE_BUSY bit is set to 1, do not write to any of the DAC registers. After the DAC update

operation is completed (DAC_UPDATE_BUSY = 0), any of the DAC registers can be written.

8.3.3 Nonvolatile Memory (EEPROM or NVM)

The DACx3401-Q1 contain nonvolatile memory (NVM) bits. These memory bits are user programmable and

erasable, and retain the set values in the absence of a power supply. All the register bits, as shown in 表 8-1,

can be stored in the device NVM by setting NVM_PROG = 1 (address D3h). The NVM_BUSY bit (address D0h)

is set to 1 by device when a NVM write or reload operation is ongoing. During this time, the device blocks all

write operations to the device. The NVM_BUSY bit is set to 0 after the write or reload operation is complete; at

this point, all write operations to the device are allowed. The default value for all the registers in the DACx3401-

Q1 is loaded from NVM as soon as a POR event is issued. Do not perform a read operation from the DAC

register while NVM_BUSY = 1.

表8-1. NVM Programmable Registers

REGISTER ADDRESS

REGISTER NAME

BIT ADDRESS

BIT NAME

FUNC_CONFIG

15:14

13

DEVICE_LOCK

11:9

8:5

4:3

2

CODE_STEP

D1h

GENERAL_CONFIG

SLEW_RATE

DAC_PDN

REF_EN

1:0

8

DAC_SPAN

D3h

10h

25h

26h

TRIGGER

START_FUNC_GEN

DAC_DATA

11:2

11:4

DAC_MARGIN_HIGH

DAC_MARGIN_LOW

MARGIN_HIGH (8 most significant bits)

MARGIN_LOW (8 most significant bits)

The DACx3401-Q1 also implement NVM_RELOAD bit (address D3h). Set this bit to 1 for the device to start an

NVM reload operation. After the operation is complete, the device autoresets this bit to 0. During the

NVM_RELOAD operation, the NVM_BUSY bit is set to 1.

8.3.3.1 NVM Cyclic Redundancy Check

The DACx3401-Q1 implement a cyclic redundancy check (CRC) feature for the device NVM to make sure that

the data stored in the device NVM is uncorrupted. There are two types of CRC alarm bits implemented in

DACx3401-Q1:

• NVM_CRC_ALARM_USER

• NVM_CRC_ALARM_INTERNAL

The NVM_CRC_ALARM_USER bit indicates the status of user-programmable NVM bits, and the

NVM_CRC_ALARM_INTERNAL bit indicates the status of internal NVM bits The CRC feature is implemented by

storing a 10-Bit CRC (CRC-10-ATM) along with the NVM data each time NVM program operation (write or

reload) is performed and during the device start up. The device reads the NVM data and validates the data with

the stored CRC. The CRC alarm bits (NVM_CRC_ALARM_USER and NVM_CRC_ALARM_INTERNAL address

D0h) report any errors after the data are read from the device NVM.

20

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

8.3.3.2 NVM_CRC_ALARM_USER Bit

A logic 1 on NVM_CRC_ALARM_USER bit indicates that the user-programmable NVM data is corrupt. During

this condition, all registers in the DAC are initialized with factory reset values, and any DAC registers can be

written to or read from. To reset the alarm bits to 0, issue a software reset (see 节 8.3.6) command, or cycle

power to the DAC. Alternatively, cycle the power to reload the user-programmable NVM bits.

8.3.3.3 NVM_CRC_ALARM_INTERNAL Bit

A logic 1 on NVM_CRC_ALARM_INTERNAL bit indicates that the internal NVM data is corrupt. During this

condition, all registers in the DAC are initialized with factory reset values, and any DAC registers can be written

to or read from. To reset the alarm bits to 0, issue a software reset (see 节8.3.6) command or cycle power to the

DAC.

8.3.4 Programmable Slew Rate

When the DAC data registers are written, the voltage on DAC output (V_OUT) immediately transitions to the new

code following the slew rate and settling time specified in 节 7.5. The slew rate control feature allows the user to

control the rate at which the output voltage (V_OUT) changes. When this feature is enabled (using

SLEW_RATE[3:0] bits), the DAC output changes from the current code to the code in MARGIN_HIGH (address

25h) or MARGIN_LOW (address 26h) registers (when margin high or low commands are issued to the DAC)

using the step and rate set in CODE_STEP and SLEW_RATE bits. With the default slew rate control setting

(CODE_STEP and SLEW_RATE bits, address D1h), the output changes smoothly at a rate limited by the output

drive circuitry and the attached load. Using this feature, the output steps digitally at a rate defined by bits

CODE_STEP and SLEW_RATE on address D1h. SLEW_RATE defines the rate at which the digital slew

updates; CODE_STEP defines the amount by which the output value changes at each update. 表8-2 and 表8-3

show different settings for CODE_STEP and SLEW_RATE.

When the slew rate control feature is used, the output changes happen at the programmed slew rate. This

configuration results in a staircase formation at the output. Do not write to CODE_STEP, SLEW_RATE, or

DAC_DATA during the output slew.

表8-2. Code Step

REGISTER ADDRESS

CODE_STEP[2]

CODE_STEP[1]

CODE_STEP[0]

COMMENT

AND NAME

Code step size = 1 LSB

(default)

0

1

0

1

0

1

0

1

0

1

0

1

Code step size = 2 LSB

Code step size = 3 LSB

Code step size = 4 LSB

Code step size = 6 LSB

Code step size = 8 LSB

Code step size = 16 LSB

Code step size = 32 LSB

D1h, GENERAL_CONFIG

Submit Document Feedback

21

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

COMMENT

表8-3. Slew Rate

REGISTER

ADDRESS AND

NAME

SLEW_RATE[3]

SLEW_RATE[2]

SLEW_RATE[1]

SLEW_RATE[0]

25.6 µs

(per step)

0

1

0

1

0

1

0

1

0

1

0

1

0

25.6 µs × 1.25

(per step)

25.6 µs × 1.50

(per step)

25.6 µs × 1.75

(per step)

204.8 µs

(per step)

204.8 µs × 1.25

(per step)

204.8 µs × 1.50

(per step)

D1h,

GENERAL_CONFIG

204.8 µs × 1.75

(per step)

0

1

0

1

0

1

0

1

1.6384 ms (per step)

1.6384 ms × 1.25

(per step)

1.6384 ms × 1.50

(per step)

1

0

1

0

1

1.6384 ms × 1.75

(per step)

1

0

1

0

1

0

1

12 µs (per step)

8 µs (per step)

4 µs (per step)

No slew (default)

22

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

8.3.5 Power-on-Reset (POR)

The DACx3401-Q1 family of devices includes a power-on reset (POR) function that controls the output voltage at

power up. After the V_DDsupply has been established, a POR event is issued. The POR causes all registers to

initialize to default values, and communication with the device is valid only after a 30-ms, POR delay. The default

value for all the registers in the DACx3401-Q1 is loaded from NVM as soon as the POR event is issued.

When the device powers up, a POR circuit sets the device to the default mode. The POR circuit requires specific

V_DDlevels, as indicated in 图 8-1, in order to make sure that the internal capacitors discharge and reset the

device on power up. To make sure that a POR occurs, V_DDmust be less than 0.7 V for at least 1 ms. When V_DD

drops to less than 1.65 V, but remains greater than 0.7 V (shown as the undefined region), the device may or

may not reset under all specified temperature and power-supply conditions. In this case, initiate a POR. When

V_DDremains greater than 1.65 V, a POR does not occur.

V_DD(V)

5.5 V

Specified supply

voltage range

No power-on reset

1.71 V

1.65 V

Undefined

0.7 V

Power-on reset

0 V

图8-1. Threshold Levels for V_DDPOR Circuit

8.3.6 Software Reset

To initiate a device software reset event, write the reserved code 1010 to the SW_RESET (address D3h). A

software reset initiates a POR event.

8.3.7 Device Lock Feature

The DACx3401-Q1 implement a device lock feature that prevents an accidental or unintended write to the DAC

registers. The device locks all the registers when the DEVICE_LOCK bit (address D1h) is set to 1. To bypass the

DEVICE_LOCK setting, write 0101 to the DEVICE_UNLOCK_CODE bits (address D3h).

Submit Document Feedback

23

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

8.3.8 PMBus Compatibility

The PMBus protocol is an I²C-based communication standard for power-supply management. PMBus contains

standard command codes tailored to power supply applications. The DACx3401-Q1 implement some PMBus

commands such as Turn Off, Turn On, Margin Low, Margin High, Communication Failure Alert Bit (CML), as well

as PMBUS revision. 图8-2 shows typical PMBus connections. The EN_PMBus bit (Bit 12, address D1h) must be

set to 1 to enable the PMBus protocol.

PMBus-compatible device #1

ALERT

CONTROL

DATA

CLOCK

Alert signal

PMBus-compatible device #2

ALERT

Control signal

CONTROL

Data

DATA

Clock

CLOCK

Optional

Required

PMBus-compatible device #3

ALERT

CONTROL

DATA

CLOCK

图8-2. PMBus Connections

Similar to I²C, PMBus is a variable length packet of 8-bit data bytes, each with a receiver acknowledge, wrapped

between a start and stop bit. The first byte is always a 7-bit slave address followed by a write bit, sometimes

called the even address that identifies the intended receiver of the packet. The second byte is an 8-bit command

byte, identifying the PMBus command being transmitted using the respective command code. After the

command byte, the transmitter either sends data associated with the command to write to the receiver command

register (from most significant byte to least significant byte), or sends a new start bit indicating the desire to read

the data associated with the command register from the receiver. After, the receiver transmits the data following

the same most significant byte first format (see 表8-7).

24

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

8.4 Device Functional Modes

8.4.1 Power Down Mode

The DACx3401-Q1 output amplifier and internal reference can be independently powered down through the

DAC_PDN bits (address D1h). At power up, the DAC output and the internal reference are disabled by default.

In power-down mode, the DAC output (OUT pin) is in a high-impedance state. To change this state to 10kΩ-

A_GND(at power up), use the DAC_PDN bits (address D1h).

The DAC power-up state can be programmed to any state (power-down or normal mode) using the NVM. 表 8-4

shows the DAC power-down bits.

表8-4. DAC Power-Down Bits

REGISTER ADDRESS AND NAME

DAC_PDN[1]

DAC_PDN[0]

DESCRIPTION

Power up

0

1

Power down to 10 kΩ

D1h, GENERAL_CONFIG

Power down to high impedance (Hi-Z)

(default)

1

0

1

Power down to 10 kΩ

8.4.2 Continuous Waveform Generation (CWG) Mode

The DACx3401-Q1 implement a continuous waveform generation feature. To set the device to this mode, set the

START_FUNC_GEN (address D3h) to 1. In this mode, the DAC output pin (OUT) generates a continuous

waveform based on the FUNC_CONFIG bits (address D1h). 表8-5 shows the continuous waveforms that can be

generated in this mode. The frequency of the waveform depends on the resistive and capacitive load on the

OUT pin, high and low codes, and slew rate settings as shown in the following equations.

1

f_SQUARE-WAVE

=

2ìSLEW _RATE

(3)

(4)

(5)

1

f_{TRIANGLE-WAVE}

=

≈ MARGIN_HIGH -MARGIN_LOW +1’

CODE _STEP

2ìSLEW _RATEì

∆

÷

«

◊

1

f_{SAWTOOTH-WAVE}

=

≈MARGIN_HIGH-MARGIN_LOW +1’

CODE_STEP

SLEW _RATEì

∆

÷

«

◊

where:

• SLEW_RATE is the programmable DAC slew rate specified in 表8-3.

• MARGIN_HIGH and MARGIN_LOW are the programmable DAC codes.

• CODE_STEP is the programmable DAC step code in 表8-2.

Submit Document Feedback

25

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

表8-5. FUNC_CONFIG bits

REGISTER ADDRESS AND NAME

FUNC_CONFIG[1]

FUNC_CONFIG[0]

DESCRIPTION

Generates a triangle wave between

MARGIN_HIGH (address 25h) code to

MARGIN_LOW (address 26h) code with

slope defined by SLEW_RATE (address

D1h) bits

0

Generates Saw-Tooth wave between

MARGIN_HIGH (address 25h) code to

MARGIN_LOW (address 26h) code, with

rising slope defined by SLEW_RATE

(address D1h) bits and immediate falling

edge

0

1

D1h, GENERAL_CONFIG

Generates Saw-Tooth wave between

MARGIN_HIGH (address 25h) code to

MARGIN_LOW (address 26h) code, with

falling slope defined by SLEW_RATE

(address D1h) bits and immediate rising

edge

1

0

1

Generates a square wave between

MARGIN_HIGH (address 25h) code to

MARGIN_LOW (address 26h) code with

pulse high and low period defined by

SLEW_RATE (address D1h) bits

8.4.3 PMBus Compatibility Mode

The DACx3401-Q1 I²C interface implements some of the PMBus commands. 表 8-6 shows the supported

PMBus commands that are implemented in DACx3401-Q1.The DAC uses MARGIN_LOW (address 26h),

MARGIN_HIGH (address 25h) bits, SLEW_RATE, and CODE_STEP bits (address D1h) for

PMBUS_OPERATION_CMD. The EN_PMBus bit (Bit 12, address D1h) must be set to 1 to enable the PMBus

protocol.

表8-6. PMBus Operation Commands

REGISTER ADDRESS AND NAME

PMBUS_OPERATION_CMD[15:8]

DESCRIPTION

Turn off

00h

80h

94h

A4h

Turn on

01h, PMBUS_OPERATION

Margin low

Margin high

The DACx3401-Q1 also implement PMBus features such as group command protocol and communication time-

out failure. The CML bit (address 78h) indicates a communication fault in the PMBus. This bit is reset by writing

1. In case of timeout, if the SDA line is held low, the SDA line stays low during the time-out event until next SCL

pulse is received.

To get the PMBus version, read the PMBUS_VERSION bits (address 98h).

26

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

8.5 Programming

The DACx3401-Q1 devices have a 2-wire serial interface (SCL and SDA), and one address pin (A0), as shown

in the pin diagram of 节 6. The I²C bus consists of a data line (SDA) and a clock line (SCL) with pullup

structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C-compatible devices connect

to the I²C bus through the open drain I/O pins, SDA and SCL.

The I²C specification states that the device that controls communication is called a master, and the devices that

are controlled by the master are called slaves. The master device generates the SCL signal. The master device

also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus

to indicate the start or stop of a data transfer. Device addressing is completed by the master. The master device

on an I²C bus is typically a microcontroller or digital signal processor (DSP). The DACx3401-Q1 family operates

as a slave device on the I²C bus. A slave device acknowledges master commands, and upon master control,

receives or transmits data.

Typically, theDACx3401-Q1 family operates as a slave receiver. A master device writes to the DACx3401-Q1, a

slave receiver. However, if a master device requires the DACx3401-Q1 internal register data, the DACx3401-Q1

operate as a slave transmitter. In this case, the master device reads from the DACx3401-Q1. According to I²C

terminology, read and write refer to the master device.

The DACx3401-Q1 family is a slave and supports the following data transfer modes:

• Standard mode (100 kbps)

• Fast mode (400 kbps)

• Fast mode plus (1.0 Mbps)

The data transfer protocol for standard and fast modes is exactly the same; therefore, both modes are referred

to as F/S-mode in this document. The fast mode plus protocol is supported in terms of data transfer speed, but

not output current. The low-level output current would be 3 mA; similar to the case of standard and fast modes.

The DACx3401-Q1 family supports 7-bit addressing. The 10-bit addressing mode is not supported. The device

supports the general call reset function. Sending the following sequence initiates a software reset within the

device: start or repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the rising edge of the

ACK bit, following the second byte.

Other than specific timing signals, the I²C interface works with serial bytes. At the end of each byte, a ninth clock

cycle generates and detects an acknowledge signal. An acknowledge is when the SDA line is pulled low during

the high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the high

period of the ninth clock cycle, as shown in 图8-3.

Data output

by transmitter

Not acknowledge

Data output

by receiver

Acknowledge

2

9

1

8

SCL from

master

S

Clock pulse for

acknowledgement

Start

condition

图8-3. Acknowledge and Not Acknowledge on the I²C Bus

Submit Document Feedback

27

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

8.5.1 F/S Mode Protocol

The following steps explain a complete transaction in F/S mode.

1. The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high, as shown in 图8-4. All I²C-compatible devices

recognize a start condition.

2. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit

(R/W) on the SDA line. During all transmissions, the master makes sure that data are valid. A valid data

condition requires the SDA line to be stable during the entire high period of the clock pulse, as shown in 图

8-5. All devices recognize the address sent by the master and compare the address to the respective

internal fixed address. Only the slave device with a matching address generates an acknowledge by pulling

the SDA line low during the entire high period of the 9th SCL cycle, as shown in Figure 8-3. When the

master detects this acknowledge, the communication link with a slave has been established.

3. The master generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the slave. In

either case, the receiver must acknowledge the data sent by the transmitter. The acknowledge signal can be

generated by the master or by the slave, depending on which is the receiver. The 9-bit valid data sequences

consists of 8-data bits and 1 acknowledge-bit, and can continue as long as necessary.

4. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from

low-to-high while the SCL line is high, as shown in 图8-4. This action releases the bus and stops the

communication link with the addressed slave. All I²C-compatible devices recognize the stop condition. Upon

receipt of a stop condition, the bus is released, and all slave devices then wait for a start condition followed

by a matching address.

SDA

SCL

S

P

Start

condition

Stop

condition

Change of data

allowed

Data line stable

Data valid

图8-4. Start and Stop Conditions

图8-5. Bit Transfer on the I²C Bus

28

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

8.5.2 I²C Update Sequence

For a single update, the DACx3401-Q1 require a start condition, a valid I²C address byte, a command byte, and

two data bytes, as listed in 表8-7.

表8-7. Update Sequence

MSB

....

LSB

ACK

MSB

...

LSB

ACK

MSB

...

LSB

ACK

MSB

...

LSB

ACK

Address (A) byte

Command byte

节8.5.2.2

Data byte - MSDB

DB [15:8]

Data byte - LSDB

DB [7:0]

节8.5.2.1

DB [31:24]

DB [23:16]

After each byte is received, the DACx3401-Q1 family acknowledges the byte by pulling the SDA line low during

the high period of a single clock pulse, as shown in 图 8-6. These four bytes and acknowledge cycles make up

the 36 clock cycles required for a single update to occur. A valid I²C address byte selects the DACx3401-Q1

devices.

Recognize

START or

REPEATED

Recognize

STOP or

REPEATED

Generate ACKNOWLEDGE

START

signal

condition

P

SDA

Sr

MSB

Acknowledgement

signal from Slave

Address

R/W

1

SCL

1

7

8

9

2 - 8

9

Sr

or

P

S

or

Sr

ACK

START or

REPEATED

START or

STOP

REPEATED

START

condition

Clock line held low while

interrupts are serviced

condition

图8-6. I²C Bus Protocol

The command byte sets the operating mode of the selected DACx3401-Q1 device. For a data update to occur

when the operating mode is selected by this byte, the DACx3401-Q1 device must receive two data bytes: the

most significant data byte (MSDB) and least significant data byte (LSDB). The DACx3401-Q1 device performs

an update on the falling edge of the acknowledge signal that follows the LSDB.

When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 10 kSPS. Using the fast

mode plus (clock = 1 MHz), the maximum DAC update rate is limited to 25 kSPS. When a stop condition is

received, the DACx3401-Q1 device releases the I²C bus and awaits a new start condition.

Submit Document Feedback

29

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

8.5.2.1 Address Byte

The address byte, as shown in 表 8-8, is the first byte received from the master device following the start

condition. The first four bits (MSBs) of the address are factory preset to 1001. The next three bits of the address

are controlled by the A0 pin. The A0 pin input can be connected to VDD, AGND, SCL, or SDA. The A0 pin is

sampled during the first byte of each data frame to determine the address. The device latches the value of the

address pin, and consequently responds to that particular address according to 表8-9.

表8-8. Address Byte

COMMENT

MSB

LSB

AD6

1

AD5

0

AD4

0

AD3

AD2

AD1

AD0

R/ W

—

See 表8-9

General address

1

0

0 or 1

0

(slave address column)

Broadcast address

1

0

1

1 1

The DACx3401-Q1 supports broadcast addressing, which is used for synchronously updating or powering down

multiple DACx3401-Q1 devices. When the broadcast address is used, the DACx3401-Q1 responds regardless of

the address pin state. Broadcast is supported only in write mode.

表8-9. Address Format

SLAVE ADDRESS

A0 PIN

AGND

VDD

000

001

010

011

SDA

SCL

8.5.2.2 Command Byte

表8-10 lists the command byte.

表8-10. Command Byte (Register Names)

ADDRESS

REGISTER NAME

D0h

STATUS

D1h

GENERAL_CONFIG

TRIGGER

D3h

21h

DAC_DATA

25h

DAC_MARGIN_HIGH

DAC_MARGIN_LOW

PMBUS_OP

26h

01h

78h

PMBUS_STATUS_BYTE

PMBUS_VERSION

98h

30

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

8.5.3 I²C Read Sequence

To read any register the following command sequence must be used:

1. Send a start or repeated start command with a slave address and the R/ W bit set to 0 for writing. The device

acknowledges this event.

2. Send a command byte for the register to be read. The device acknowledges this event again.

3. Send a repeated start with the slave address and the R/ W bit set to 1 for reading. The device acknowledges

this event.

4. The device writes the MSDB byte of the addressed register. The master must acknowledge this byte.

5. Finally, the device writes out the LSDB of the register.

An alternative reading method allows for reading back the value of the last register written. The sequence is a

start or repeated start with the slave address and the R/ W bit set to 1, and the two bytes of the last register are

read out.

The broadcast address cannot be used for reading.

表8-11. Read Sequence

R/ W

(0)

R/ W

(1)

S

MSB

ACK MSB

LSB ACK Sr MSB

ACK MSB

LSB

ACK

MSB

LSB

ACK

…

ADDRESS

BYTE

节8.5.2.1

COMMAND

BYTE

节8.5.2.2

ADDRESS

BYTE

节8.5.2.1

Sr

MSDB

From Slave

LSDB

From Master

Slave

From Master

Slave

From Master

Slave

Master

From Slave

Master

Submit Document Feedback

31

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

8.6 Register Map

表8-12. Register Map

MOST SIGNIFICANT DATA BYTE (MSDB)

LEAST SIGNIFICANT DATA BYTE (LSDB)

ADDR

BIT15

BIT14

BIT13

BIT12

BIT11 BIT10

BIT9

BIT8

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

NVM_

CRC_

ALARM_

USER

NVM_

CRC_

ALARM_

INTERNAL

DAC_

UPDATE_

BUSY

NVM_

BUSY

D0h

X⁽¹⁾

DEVICE_ID

VERSION_ID

DAC_SPAN

DEVICE_

LOCK

EN_

PMBUS

REF_

EN

D1h

D3h

FUNC_CONFIG

CODE_STEP

SLEW_RATE

DAC_PDN

NVM_

DEVICE_

CONFIG_

RESET

START_

FUNC_

GEN

PMBUS_ PMBUS_

MARGIN_ MARGIN_

NVM_

DEVICE_UNLOCK_CODE

X

SW_RESET

RELOAD PROG

HIGH

LOW

21h

25h

26h

01h

78h

98h

X

DAC_DATA[9:0] (10-Bit) or DAC_DATA[7:0] (8-Bit)

X

MARGIN_HIGH[9:0] (10-Bit) or MARGIN_HIGH[7:0] (8-Bit)

MARGIN_LOW[9:0] (10-Bit) or MARGIN_LOW[7:0] (8-Bit)

PMBUS_OPERATION_CMD

N/A

X

CML

N/A

PMBUS_VERSION

N/A

(1) X = Don't care.

表8-13. Register Names

ADDRESS

D0h

REGISTER NAME

SECTION

节8.6.1

节8.6.2

节8.6.3

节8.6.4

节8.6.5

节8.6.6

节8.6.7

节8.6.8

节8.6.9

STATUS

D1h

GENERAL_CONFIG

TRIGGER

D3h

21h

DAC_DATA

25h

DAC_MARGIN_HIGH

DAC_MARGIN_LOW

PMBUS_OPERATION

PMBUS_STATUS_BYTE

PMBUS_VERSION

26h

01h

78h

98h

表8-14. Access Type Codes

Access Type

Code

Description

X

Don't care

Read Type

R

Read

Write

Write Type

W

Reset or Default Value

-n

Value after reset or the default

value

32

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

8.6.1 STATUS Register (address = D0h) [reset = 000Ch or 0014h]

图8-7. STATUS Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

NVM_CRC_

ALARM_

USER

NVM_CRC_

ALARM_

INTERNAL

NVM_

BUSY

DAC_

UPDATE_

BUSY

X

DEVICE_ID

VERSION_ID

R-0h

X-00h

10-bit: R-0Ch

8-bit: R-14h

表8-15. STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

15

NVM_CRC_ALARM_USER

NVM_CRC_ALARM_INTERNAL

NVM_BUSY

R

0

0 : No CRC error in user NVM bits

1: CRC error in user NVM bits

14

13

R

0

0 : No CRC error in internal NVM

1: CRC error in internal NVM bits

0 : NVM write or load completed,write to DAC registers

allowed

1 : NVM write or load in progress, write to DAC registers

not allowed

12

DAC_UPDATE_BUSY

R

0

0 : DAC outputs updated, write to DAC registers allowed

1 : DAC outputs update in progress, write to DAC

registers not allowed

11 - 6

5 - 2

1 - 0

X

R

00h

Don't care

DEVICE_ID

VERSION_ID

DAC53401-Q1:

0Ch

DAC43401-Q1:

14h

DAC53401-Q1: 0Ch

DAC43401-Q1: 14h

8.6.2 GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]

图8-8. GENERAL_CONFIG Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FUNC_

DEVICE_

LOCK

EN_

PMBUS

CODE_STEP

SLEW_RATE

R/ W-Fh

DAC_PDN

REF_EN DAC_SPAN

CONFIG

R/ W-0h

W-0h

R/ W-0h

R/ W-2h

R/ W-0h R/ W-0h

表8-16. GENERAL_CONFIG Register Field Descriptions

Bit

Field

Type

Reset

Description

15 - 14 FUNC_CONFIG

R/ W

00

00 : Generates a triangle wave between MARGIN_HIGH

(address 25h) code to MARGIN_LOW (address 26h) code with

slope defined by SLEW_RATE (address D1h) bits.

01: Generates Saw-Tooth wave between MARGIN_HIGH

(address 25h) code to MARGIN_LOW (address 26h) code, with

rising slope defined by SLEW_RATE (address D1h) bits and

immediate falling edge.

10: Generates Saw-Tooth wave between MARGIN_HIGH

(address 25h) code to MARGIN_LOW (address 26h) code, with

falling slope defined by SLEW_RATE (address D1h) bits and

immediate rising edge.

11: Generates a square wave between MARGIN_HIGH (address

25h) code to MARGIN_LOW (address 26h) code with pulse high

and low period defined by SLEW_RATE (address D1h) bits.

13

12

DEVICE_LOCK

EN_PMBUS

W

0

0 : Device not locked

1: Device locked, the device locks all the registers. This bit can be

reset (unlock device) by writing 0101 to the

DEVICE_UNLOCK_CODE bits (address D3h)

R/ W

0: PMBus mode disabled

1: PMBus mode enabled

Submit Document Feedback

33

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

表8-16. GENERAL_CONFIG Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

11 - 9

CODE_STEP

R/ W

000

Code step for programmable slew rate control.

000: Code step size = 1 LSB (default)

001: Code step size = 2 LSB

010: Code step size = 3 LSB

011: Code step size = 4 LSB

100: Code step size = 6 LSB

101: Code step size = 8 LSB

110: Code step size = 16 LSB

111: Code step size = 32 LSB

8 - 5

SLEW_RATE

R/ W

1111

Slew rate for programmable slew rate control.

0000: 25.6 µs (per step)

0001: 25.6 µs × 1.25 (per step)

0010: 25.6 µs × 1.50 (per step)

0011: 25.6 µs × 1.75 (per step)

0100: 204.8 µs (per step)

0101: 204.8 µs × 1.25 (per step)

0110: 204.8 µs × 1.50 (per step)

0111: 204.8 µs × 1.75 (per step)

1000: 1.6384 ms (per step)

1001: 1.6384 ms × 1.25 (per step)

1010: 1.6384 ms × 1.50 (per step)

1011: 1.6384 ms × 1.75 (per step)

1100: 12 µs (per step)

1101: 8 µs (per step)

1110: 4 µs (per step)

1111: No slew (default)

4 - 3

DAC_PDN

R/ W

10

00: Power up

01: Power down to 10K

10: Power down to high impedance (default)

11: Power down to 10K

2

REF_EN

R/ W

0

0: Internal reference disabled, V_DDis DAC reference voltage,

DAC output range from 0 to V_DD

1: Internal reference enabled, DAC reference = 1.21 V

.

1 - 0

DAC_SPAN

00

Only applicable when internal reference is enabled.

00: Reference to V_OUTgain 1.5X

01: Reference to V_OUTgain 2X

10: Reference to V_OUTgain 3X

11: Reference to V_OUTgain 4X

34

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

8.6.3 TRIGGER Register (address = D3h) [reset = 0008h]

图8-9. TRIGGER Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DEVICE_UNLOCK_CODE

X

DEVICE_ START_

PMBUS_

NVM_

SW_RESET

CONFIG_

RESET

FUNC_

GEN

MARGIN_ MARGIN_ RELOAD PROG

HIGH

LOW

W-0h

R/ W-0h

W-0h

W-8h

表8-17. TRIGGER Register Field Descriptions

Bit

Field

Type

Reset

0000

0h

Description

15 - 12 DEVICE_UNLOCK_CODE

W

Write 0101 to unlock the device to bypass DEVICE_LOCK bit.

Don't care

11 - 10

9

X

DEVICE_CONFIG_RESET

W

0

0: Device configuration reset not initiated

1: Device configuration reset initiated. All registers loaded with

factory reset values.

8

START_FUNC_GEN

W

0

0: Continuous waveform generation mode disabled

1: Continuous waveform generation mode enabled, device

generates continuous waveform based on FUNC_CONFIG (D1h),

MARGIN_LOW (address 18h), and SLEW_RATE (address D1h)

bits.

7

6

5

4

PMBUS_MARGIN_HIGH

PMBUS_MARGIN_LOW

NVM_RELOAD

R/ W

W

0

0: PMBus margin high command not initiated

1: PMBus margin high command initiated, DAC output margins

high to MARGIN_HIGH code (address 25h). This bit automatically

resets to 0 after the DAC code reaches MARGIN_HIGH value.

0: PMBus margin low command not initiated

1: PMBus margin low command initiated, DAC output margins

low to MARGIN_LOW code (address 26h). This bit automatically

resets to 0 after the DAC code reaches MARGIN_LOW value.

0: NVM reload not initiated

1: NVM reload initiated, applicable DAC registers loaded with

corresponding NVM. NVM_BUSY bit set to 1 while this operation

is in progress. This bit is self-resetting.

NVM_PROG

W

0: NVM write not initiated

1: NVM write initiated, NVM corresponding to applicable DAC

registers loaded with existing register settings. NVM_BUSY bit

set to 1 while this operation is in progress. This bit is self-

resetting.

3 - 0

SW_RESET

W

1000

1000: Software reset not initiated

1010: Software reset initiated, DAC registers loaded with

corresponding NVMs, all other registers loaded with default

settings.

Submit Document Feedback

35

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

8.6.4 DAC_DATA Register (address = 21h) [reset = 0000h]

图8-10. DAC_DATA Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

DAC_DATA[9:0] / DAC_DATA[7:0] –MSB Left aligned

X-0h

W-000h

X-0h

表8-18. DAC_DATA Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-2

X

0h

Don't care

DAC_DATA[9:0] / DAC_DATA[7:0]

W

000h

Writing to the DAC_DATA register forces the respective DAC

channel to update the active register data to the DAC_DATA.

Data are in straight binary format and use the following format:

DACx3401-Q1: { DATA[9:0] }

DACx3401-Q1: { DATA[7:0], X, X }

X = Don’t care bits

1-0

X

0h

Don't care

8.6.5 DAC_MARGIN_HIGH Register (address = 25h) [reset = 0000h]

图8-11. DAC_MARGIN_HIGH Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

MARGIN_HIGH[9:0] / MARGIN_HIGH[7:0] –MSB Left aligned

X-0h

W-000h

X-0h

表8-19. DAC_MARGIN_HIGH Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-2

X

0h

Don't care

MARGIN_HIGH[9:0] /

MARGIN_HIGH[7:0] –MSB Left

aligned

W

000h

Margin high code for DAC output.

Data are in straight binary format and use the following format:

DACx3401-Q1: { MARGIN_HIGH[[9:0] }

DACx3401-Q1: { MARGIN_HIGH[[7:0], X, X }

X = Don’t care bits

1-0

X

0h

Don't care

36

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

8.6.6 DAC_MARGIN_LOW Register (address = 26h) [reset = 0000h]

图8-12. DAC_MARGIN_LOW Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

MARGIN_LOW[9:0] / MARGIN_LOW[7:0] –MSB Left aligned

X-0h

W-000h

X-0h

表8-20. DAC_MARGIN_LOW Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-2

X

0h

Don't care

MARGIN_LOW[9:0] /

MARGIN_LOW[7:0] –MSB Left

aligned

W

000h

Margin low code for DAC output.

Data are in straight binary format and follows the format below:

DACx3401-Q1: { MARGIN_LOW[[9:0] }

DACx3401-Q1: { MARGIN_LOW[[7:0], X, X }

X = Don’t care bits

1-0

X

0h

Don't care

8.6.7 PMBUS_OPERATION Register (address = 01h) [reset = 0000h]

图8-13. PMBUS_OPERATION Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PMBUS_OPERATION_CMD

R/ W-00h

X

X-00h

表8-21. PMBUS_OPERATION Register Field Descriptions

Bit

15 - 8

Field

Type

Reset

Description

PMBUS_OPERATION_CMD

R/W

00h

PMBus operation commands

00h: Turn off

80h: Turn on

A4h: Margin high, DAC output margins high to MARGIN_HIGH

code (address 25h)

94h: Margin low, DAC output margins low to MARGIN_LOW code

(address 26h)

7 - 0

X

00h

Not applicable

8.6.8 PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]

图8-14. PMBUS_STATUS_BYTE Register

15

14

13

12

11

10

9

8

7

6

5

4

X

3

2

1

0

X

CML

X-00h

R/W-0h

X-000h

表8-22. PMBUS_STATUS_BYTE Register Field Descriptions

Bit

Field

Type

Reset

00h

0

Description

15 - 10

9

X

Don't care

CML

R/W

0: No communication Fault

1: PMBus communication fault for timeout, write with incorrect

number of clocks, read before write command, and so more;

reset this bit by writing 1.

8 - 0

X

000h

Not applicable

Submit Document Feedback

37

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

8.6.9 PMBUS_VERSION Register (address = 98h) [reset = 2200h]

图8-15. PMBUS_VERSION Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PMBUS_VERSION

R-22h

X

X-00h

表8-23. PMBUS_VERSION Register Field Descriptions

Bit

Field

Type

Reset

Description

15 - 8

7 - 0

PMBUS_VERSION

X

R

22h

PMBus version

Not applicable

X

00h

38

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

9 Application and Implementation

Note

以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适

用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The DACx3401-Q1 are buffered, force-sense output, single-channel, DACs that include an NVM and internal

reference and are available in a tiny 3 mm × 3 mm package. This device interfaces to a processor using I²C.

There are 4 I²C addresses possible by configuring the A0 pin as shown in Table 7-5. The NVM allows processor-

less operation of this device after programming at factory. The force-sense output can work with a transitor to

create a programmable current sink that can bias LEDs. These digipots are designed for general-purpose

applications in a wide range of end equipment. Some of the most common applications for these devices are

power-supply margining and control, adaptive voltage scaling (AVS), set-and-forget LED biasing in automotive

applications and mobile projectors, general-purpose function generation, and programmable comparator

applications (such as standalone PWM control loops and offset and gain trimming in precision circuits).

9.2 Typical Applications

This section explains the design details of three primary applications of DACx3401-Q1: programmable LED

biasing, and power-supply margining.

9.2.1 Programmable LED Biasing

LED and laser biasing or driving circuits often require accuracy and stability of the luminosity with respect to

variation in temperature, electrical conditions, and physical characteristics. This accuracy and stability are most

effectively achieved using a precision DAC, such as the DACx3401-Q1. The DACx3401-Q1 have additional

features, such as the V_FBpin that compensates for the gate-to-source voltage of the transistor (V_GS) drop and

the drift of the MOSFET. The NVM allows the microprocessor to set-and-forget the LED biasing value, even

during a power cycle. 图9-1 shows the circuit diagram for LED biasing.

VCC

LED

VDD

I_LED= I_SET

V_OUT

DACx3401-Q1

Q1

+

V_GS

V_FB

œ

V_DAC

R_SET

I_SET

图9-1. LED Biasing

9.2.1.1 Design Requirements

• DAC output range: 0 V to 2.4 V

• LED current range: 0 mA to 20 mA

9.2.1.2 Detailed Design Procedure

The DAC sets the source current of a MOSFET using the integrated buffer, as shown in 图9-1. Connect the LED

between the power supply and the drain of the MOSFET. This configuration allows the DAC to control or set the

Submit Document Feedback

39

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

amount of current through the LED. The integrated buffer controls the gate-source voltage of the MOSFET inside

the feedback loop, thus compensating this drop and corresponding drift due to temperature, current, and ageing

of the MOSFET. Calculate the value of the LED current set by the DAC using 方程式 6. In order to generate 0

mA to 20 mA from a 0-V to 2.4-V DAC output range, the value of R_SETresistor is 120-Ω. Select the internal

reference with a span of 2x. Given a V_GSof 1.2 V, the V_DDof the DAC must be at least 3.6 V. Select a V_DDof 5 V

to allow variation of V_GSacross temperature. When the V_DDheadroom is a constraint, use a bipolar junction

transistor (BJT) in place of the MOSFET. BJTs have much less V_BEdrop as compared to a V_GSof a MOSFET. A

MOSFET provides a much better match between the current through the set register and the LED current, as

compared to a BJT.

V_DAC

I_SET

=

R_SET

(6)

The pseudocode for getting started with an LED biasing application is as follows:

//SYNTAX: WRITE <REGISTER NAME (Hex code)>, <MSB DATA>, <LSB DATA>

//Power-up the device, enable internal reference with 2x output span

WRITE GENERAL_CONFIG(0xD1), 0x11, 0xE5

//Write DAC code (12-bit aligned)

WRITE DAC_DATA(0x21), 0x07, 0xFC

//Write settings to the NVM

WRITE TRIGGER(0xD3), 0x00, 0x10

9.2.1.3 Application Curves

LED breathing effect in triangular pattern

LED breathing effect in sawtooth pattern

图9-2. Triangular Waveform

图9-3. Sawtooth Waveform

40

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

9.2.2 Power-Supply Margining

A power-supply margining circuit is used to test and trim the output of a power converter. This circuit is used to

test a system by margining the power supplies, for adaptive voltage scaling, or to program a desired value at the

output. Adjustable power supplies, such as LDOs and DC/DC converters, provide a feedback or adjust input that

is used to set the desired output. A precision voltage-output DAC is an excellent choice to control the power-

supply output linearly. 图 9-4 shows a control circuit for a switch-mode power supply (SMPS) using the

DACx3401-Q1. Typical applications include communications equipment, enterprise servers, test and

measurement, automotive processor modules,and general-purpose power-supply modules.

图9-4. Power-Supply Margining

9.2.2.1 Design Requirements

• Power supply nominal output: 3.3 V

• Reference voltage of the converter (V_FB): 0.6 V

• Margin: ±10% (that is, 2.97 V to 3.63 V)

• DAC output range: 1.8 V

• Nominal current through R₁and R₂: 100 µA

9.2.2.2 Detailed Design Procedure

The DACx3401-Q1 features a Hi-Z power-down mode that is set by default at power-up, unless the device is

programmed otherwise using NVM. When the DAC output is at Hi-Z, the current through R₃is zero and the

SMPS is set at the nominal output voltage of 3.3 V. To have the same nominal condition when the DAC powers

up, bring up the device at the same output as V_FB(that is, 0.6 V). This configuration makes sure there is no

current through R₃even at power-up. Calculate R₁as (V_OUT–V_FB) / 100 µA = 27 kΩ.

To achieve ±10% margin-high and margin-low conditions, the DAC must sink or source additional current

through R₁. Calculate the current from the DAC (I_MARGIN) using 方程式7 as 12 µA.

≈

∆

«

’

÷

◊

V_OUTì(1+ MARGIN) - V_FB

R₁

I_MARGIN

=

-I

NOMINAL

(7)

where:

• I_MARGINis the margin current sourced or sinked from the DAC.

• MARGIN is the percentage margin value divided by 100.

• I_NOMINALis the nominal current through R₁and R₂.

To calculate the value of R₃, first decide the DAC output range; for safe operation in the linear region, avoid the

codes near zero-scale and full-scale. A DAC output of 20 mV is a safe consideration as the minimum output, and

(1.8 V –0.6 V –20 mV = 1.18 V) as the maximum output. When the DAC output is at 20 mV, the power supply

goes to margin high, and when the DAC output is at 1.18 V, the power supply goes to margin low. Calculate the

value of R₃using 方程式 8 as 48.3 kΩ. Choose a standard resistor value and adjust the DAC outputs. Choosing

R₃= 47 kΩgives the DAC margin high code as 1.164 V and the DAC margin low code as 36 mV.

V_DAC- V_FB

R₃

=

I_MARGIN

(8)

Submit Document Feedback

41

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

The DACx3401-Q1 have a slew rate feature that is used to toggle between margin high, margin low, and

nominal outputs with a defined slew rate. See 表8-16 for the slew rate setting details.

Note

The MARGIN HIGH register value in DACx3401-Q1 results in the MARGIN LOW value at the power

supply output. Similarly, the MARGIN LOW register value in DACx3401-Q1 results in the MARGIN

HIGH value at the power-supply output.

The pseudocode for getting started with a power-supply control application is as follows:

//SYNTAX: WRITE <REGISTER NAME (Hex code)>, <MSB DATA>, <LSB DATA>

//Write DAC code (12-bit aligned) for nominal output

//For

a 1.8-V output range, the 10-bit hex code for 0.6 V is 0x0155. With 12-bit alignment, it

becomes 0x0554

WRITE DAC_DATA(0x21), 0x05, 0x54

//Write DAC code (12-bit aligned) for margin-low output at the power supply

//For a 1.8-V output range, the 10-bit hex code for 1.164 V is 0x0296. With 12-bit alignment, it

becomes 0x0A58

WRITE DAC_MARGIN_HIGH(0x25), 0x0A, 0x58

//Write DAC code (12-bit aligned) for margin-high output at the power supply

//For

a 1.8-V output range, the 10-bit hex code for 36 mV is 0x14. With 12-bit alignment, it

becomes 0x50

WRITE DAC_MARGIN_LOW(0x26), 0x00, 0x50

//Power-up the device with enable internal reference with 1.5x output span. This will output the

nominal voltage (0.6 V)

//CODE_STEP: 2 LSB, SLEW_RATE: 25.6 µs

WRITE GENERAL_CONFIG(0xD1), 0x12, 0x14

//Trigger margin-low output at the power supply

WRITE TRIGGER(0xD3), 0x00, 0x80

//Trigger margin-high output at the power supply

WRITE TRIGGER(0xD3), 0x00, 0x40

//Write back DAC code (12-bit aligned) for nominal output

WRITE DAC_DATA(0x21), 0x05, 0x54

9.2.2.3 Application Curves

图9-5. Power-Supply Margin High

图9-6. Power Supply Margin Low

42

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

www.ti.com.cn

ZHCSOM0 –OCTOBER 2020

10 Power Supply Recommendations

The DACx3401-Q1 family of devices does not require specific supply sequencing. These devices require a

single power supply, V_DD. Use a 0.1-µF decoupling capacitor for the V_DDpin. Use a bypass capacitor with a

value around 1.5-µF for the CAP pin.

11 Layout

11.1 Layout Guidelines

The DACx3401-Q1 pin configuration separates the analog, digital, and power pins for an optimized layout. For

signal integrity, separate the digital and analog traces, and place decoupling capacitors close to the device pins.

11.2 Layout Example

图11-1 shows an example layout drawing with decoupling capacitors and pullup resistors.

图11-1. Layout Example

Submit Document Feedback

43

Product Folder Links: DAC53401-Q1 DAC43401-Q1

DAC53401-Q1, DAC43401-Q1

ZHCSOM0 –OCTOBER 2020

www.ti.com.cn

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

Texas, Instruments DAC53401EVM user's guide

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

PMBus^™is a trademark of SMIF, Inc.

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

44

Submit Document Feedback

Product Folder Links: DAC53401-Q1 DAC43401-Q1

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Jul-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DAC43401DSGRQ1

DAC43401DSGTQ1

DAC53401DSGRQ1

DAC53401DSGTQ1

WSON

DSG

8

3000

250

180.0

8.4

2.3

1.15

4.0

8.0

Q2

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Jul-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DAC43401DSGRQ1

DAC43401DSGTQ1

DAC53401DSGRQ1

DAC53401DSGTQ1

WSON

DSG

8

3000

250

210.0

185.0

35.0

3000

250

Pack Materials-Page 2

GENERIC PACKAGE VIEW

DSG 8

2 x 2, 0.5 mm pitch

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224783/A

www.ti.com

PACKAGE OUTLINE

DSG0008A

WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

B

A

0.32

0.18

PIN 1 INDEX AREA

2.1

1.9

0.4

0.2

ALTERNATIVE TERMINAL SHAPE

TYPICAL

0.8

0.7

C

SEATING PLANE

0.05

0.00

SIDE WALL

0.08 C

METAL THICKNESS

DIM A

OPTION 1

0.1

OPTION 2

0.2

EXPOSED

THERMAL PAD

(DIM A) TYP

0.9 0.1

5

4

6X 0.5

2X

1.5

9

1.6 0.1

8

1

0.32

0.18

PIN 1 ID

(45 X 0.25)

8X

0.4

0.2

8X

0.1

C A B

C

0.05

4218900/E 08/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(0.9)

(

0.2) VIA

8X (0.5)

TYP

1

8

8X (0.25)

(0.55)

SYMM

9

(1.6)

6X (0.5)

5

4

SYMM

(1.9)

(R0.05) TYP

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218900/E 08/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

8X (0.5)

METAL

8

SYMM

1

8X (0.25)

(0.45)

SYMM

9

(0.7)

6X (0.5)

5

4

(R0.05) TYP

(0.9)

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:

87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4218900/E 08/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DAC43401DSGTQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有 NVM、缓冲电压输出和 I2C 接口的汽车类 8 位单通道智能 DAC \| DSG \| 8 \| -40 to 125
文件：	总53页 (文件大小：4078K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC43401DSGTQ1 [TI]

相关型号：

DAC43508

DAC43508RTER

DAC43608

DAC43608RTER

DAC43608RTET

DAC43701

DAC43701-Q1

DAC43701DSGR

DAC43701DSGRQ1

DAC43701DSGT

DAC43701DSGTQ1

DAC4813