DAC43701 [TI]
具有 GPIO 触发器和函数发生器的单通道输出电压、8 位智能 DAC;型号: | DAC43701 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 GPIO 触发器和函数发生器的单通道输出电压、8 位智能 DAC 触发器 |
文件: | 总58页 (文件大小:3278K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
DACx3701 具有非易失性存储器和兼容PMBus™ 且具有GPI 控制功能的I2C 接
口的10 位和8 位电压输出智能DAC
1 特性
3 说明
• 1 LSB INL 和DNL(10 位和8 位)
• 宽工作范围
10 位 DAC53701 和 8 位 DAC43701 (DACx3701) 是
引脚兼容的缓冲电压输出智能数模转换器 (DAC) 系列
产品。这些器件功耗极低且均可采用微型 8 引脚
WSON 封装。DACx3701 的功能集与微型封装和低功
耗相结合,非常适合家用电器门逐渐变亮或变暗、带
PWM 输入的无处理器 LED 调光、通用偏置点生成、
电压裕量和调节、PWM 信号生成以及医用警报音调生
成等应用。
– 电源:1.8V 至5.5V
– 温度范围:–40°C 至+125°C
• 基于通用输入(GPI) 的功能触发
• 兼容PMBus™ 的I2C 接口
– 标准模式、快速模式和快速+ 模式
– 使用广播地址配置的四个器件地址选项
– 1.62V VIH (VDD = 5.5V)
这些器件具有非易失性存储器 (NVM)、一个内部基
准、一个兼容 PMBus 的 I2C 接口和一个通用输入。
DACx3701 使用内部基准或以电源作为基准运行,并
提供1.8V 至5.5V 的满量程输出。
• 用户可编程的非易失性存储器(NVM/EEPROM)
– 保存和撤销所有寄存器设置
• 可编程波形生成:方形、三角形和锯齿形
• 使用三角波形和FB 引脚的脉宽调制(PWM) 输出
• 预编程医用警报音调生成模式:低、中和高优先级
警报
DACx3701 是智能 DAC 器件,因为它们具有高级集成
特性。凭借强制检测输出、基于 GPI 的功能触发、医
用警报、PWM 输出和 NVM 功能,智能 DAC 无需使
用软件即可实现系统性能和控制。
• 数字压摆率控制
• 内部基准
• 功耗极低:在1.8V 时为0.2 mA
• 灵活启动:高阻抗或10K-GND
• 微型封装:8 引脚WSON (2mm × 2mm)
器件信息
封装(1)
封装尺寸(标称值)
器件型号
DAC53701
DAC43701
WSON (8)
2.00mm × 2.00mm
2 应用
• 烤箱
• 呼吸机
• 输液泵
(1) 如需了解所有可用封装,请参阅数据表末尾的封装选项附录。
• 麻醉给药系统
• 外科手术设备
• 机架式服务器
• 出口和紧急照明
VCC
VDD
VDD
Bright
CAP
LDO
VDD
Dim
Dim
ON
LED
Driver
RP
LADDER
+
OUT
OFF
OFF
GPI
ICTRL
OUT
SCL
SDA
Non Volatile
Memory
Internal
Reference
œ
Mechanical Switch
Coupled to
Appliance Door
FB
DAC53701
DAC
Buffer
DAC
Register
DAC
+
OUT
FB
GPI
LEDs
BUF
œ
R1
Function
Generation
Power Down Logic
电器照明淡入淡出
Power On Reset
AGND
功能方框图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
Table of Contents
8.1 Overview...................................................................18
8.2 Functional Block Diagram.........................................18
8.3 Feature Description...................................................19
8.4 Device Functional Modes..........................................26
8.5 Programming............................................................ 29
8.6 Register Map.............................................................35
9 Application and Implementation..................................43
9.1 Application Information............................................. 43
9.2 Typical Applications.................................................. 43
10 Power Supply Recommendations..............................50
11 Layout...........................................................................50
11.1 Layout Guidelines................................................... 50
11.2 Layout Example...................................................... 50
12 Device and Documentation Support..........................51
12.1 Documentation Support.......................................... 51
12.2 接收文档更新通知................................................... 51
12.3 支持资源..................................................................51
12.4 Trademarks.............................................................51
12.5 静电放电警告.......................................................... 51
12.6 术语表..................................................................... 51
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings ....................................... 4
7.2 ESD Ratings .............................................................. 4
7.3 Recommended Operating Conditions ........................4
7.4 Thermal Information ...................................................4
7.5 Electrical Characteristics ............................................5
7.6 Timing Requirements: I2C Standard Mode ................ 7
7.7 Timing Requirements: I2C Fast Mode ........................7
7.8 Timing Requirements: I2C Fast Mode Plus ................8
7.9 Timing Requirements: GPI .........................................8
7.10 Timing Diagram.........................................................8
7.11 Typical Characteristics: VDD = 5.5 V (Reference
= VDD) or VDD = 5 V (Internal Reference)......................9
7.12 Typical Characteristics: VDD = 1.8 V (Reference
= VDD) or VDD = 2 V (Internal Reference)....................11
7.13 Typical Characteristics............................................13
8 Detailed Description......................................................18
Information.................................................................... 51
4 Revision History
DATE
REVISION
NOTES
December 2020
*
Initial release.
Copyright © 2023 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
5 Device Comparison Table
DEVICE
RESOLUTION
DAC53701
DAC43701
10-bit
8-bit
6 Pin Configuration and Functions
GPI
SCL
SDA
CAP
1
2
3
4
8
7
6
5
OUT
FB
VDD
AGND
Not to scale
图6-1. DSG Package, 8-Pin WSON, Top View
表6-1. Pin Functions
DESCRIPTION
PIN
TYPE
NAME
NO.
AGND
5
Ground
Input
Ground reference point for all circuitry on the device
External capacitor for the internal LDO. Connect a capacitor (approximately 1.5 µF) between CAP and
AGND.
CAP
4
FB
7
1
8
Input
Input
Voltage-feedback pin
GPI
OUT
General-purpose input
Output
Analog output voltage from DAC
Serial interface clock. This pin must be connected to the supply voltage with an external pullup
resistor.
SCL
2
Input
Data are clocked into or out of the input register. This pin is a bidirectional, and must be connected to
the supply voltage with an external pullup resistor.
SDA
VDD
3
6
Input/output
Power
Analog supply voltage: 1.8 V to 5.5 V
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–10
–40
–65
MAX
6
UNIT
V
VDD
Supply voltage, VDD to AGND
Digital input(s) to AGND
CAP to AGND
VDD + 0.3
1.65
V
V
VFB to AGND
VDD + 0.3
VDD + 0.3
10
V
VOUT to AGND
V
Current into any pin except the power pins and the OUT pin
Junction temperature
mA
°C
°C
TJ
150
Tstg
Storage temperature
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Electrostatic
discharge
V(ESD)
pins 1, 4, 5, 8(2)
V
Charged device model (CDM), per JEDEC
pins 2, 3, 6, 7(2)
±500
specification JESD22-C101
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.71
1.62
NOM
MAX UNIT
VDD
VIH
VIL
TA
Positive supply voltage to ground (AGND
)
5.5
V
V
V
Digital input high voltage, 1.7 V < VDD ≤5.5 V
Digital input low voltage
0.4
Ambient temperature
125 °C
–40
7.4 Thermal Information
DACx3701
THERMAL METRIC(1)
DSG (WSON)
UNIT
8 PINS
49
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
50
24.1
1.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJT
24.1
8.7
ΨJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
4
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
7.5 Electrical Characteristics
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤VDD ≤5.5 V,
DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩto AGND) and capacitive
load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
DAC53701
DAC43701
10
8
Resolution
Bits
INL Relative accuracy(1)
1
1
LSB
LSB
–1
–1
DNL Differential nonlinearity(1)
Code 0d into DAC, external reference, VDD = 5.5 V
6
6
12
Zero-code error
mV
Code 0d into DAC, internal reference, gain = 4x, VDD
5.5 V
=
15
Zero-code-error temperature
coefficient
±10
0.25
µV/°C
%FSR
Offset error(4)
0.5
0.5
–0.5
–0.5
Offset-error temperature
coefficient(4)
±0.0003
0.25
%FSR/°C
%FSR
Gain error(4)
Gain-error temperature
coefficient(4)
±0.0008
%FSR/°C
1.8 V ≤VDD ≺ 2.7 V, code 1023d into DAC for 10-bit
resolution, code 255d into DAC for 8-bit resolution, no
headroom
0.5
1
–1
Full-scale error
%FSR
2.7 V ≤VDD ≤5.5 V, code 1023d into DAC for 10-bit
resolution, code 255d into DAC for 8-bit resolution, no
headroom
0.25
0.5
–0.5
Full-scale-error temperature
coefficient
±0.0008
%FSR/°C
OUTPUT CHARACTERISTICS
Output voltage
Reference tied to VDD
0
5.5
1
V
RL = Infinite, phase margin = 30°
RL = 5 kΩ, phase margin = 30°
CL
Capacitive load(2)
Load regulation
nF
2
DAC at midscale, –10 mA ≤IOUT ≤10 mA,
VDD = 5.5 V
0.4
10
25
50
mV/mA
VDD = 1.8 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
VDD = 2.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
Short circuit current
mA
VDD = 5.5 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
To VDD (DAC output unloaded, internal reference =
1.21 V), VDD ≥1.21 ☓ gain + 0.2 V
0.2
0.8
V
To VDD (DAC output unloaded, reference tied to VDD
)
Output voltage headroom(1) (2)
To VDD (ILOAD = 10 mA at VDD = 5.5 V, ILOAD = 3 mA at
VDD = 2.7 V, ILOAD = 1 mA at VDD = 1.8 V), DAC code
= full scale
%FSR
10
DAC output enabled and DAC code = midscale
0.25
0.25
DAC output enabled and DAC code = 8d for 10-bit
resolution and code = 2d for 8-bit resolution
VOUT dc output impedance
Ω
DAC output enabled and DAC code = 1016d for 10-bit
resolution and code = 254d for 8-bit resolution
0.26
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
7.5 Electrical Characteristics (continued)
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤VDD ≤5.5 V,
DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩto AGND) and capacitive
load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
160
192
TYP
200
240
MAX
240
288
7
UNIT
DAC output enabled, DAC reference tied to VDD (gain
= 1x) or internal reference (gain = 1.5x or 2x)
ZO
VFB dc output impedance(3)
kΩ
DAC output enabled, internal VREF, gain = 3x or 4x
VOUT + VFB dc output
leakage(2)
At start up, measured when DAC output is disabled
and held at VDD / 2 for VDD = 5.5 V
nA
Power supply rejection ratio
(dc)
Internal VREF, gain = 2x, DAC at midscale;
VDD = 5 V ±10%
0.25
8
mV/V
DYNAMIC PERFORMANCE
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, VDD = 5.5 V
tsett Output voltage settling time
µs
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, VDD = 5.5 V, internal VREF, gain = 4x
12
1
Slew rate
VDD = 5.5 V
V/µs
mV
At startup (DAC output disabled), RL = 5 kΩ,
CL = 200 pF
75
Power-on glitch magnitude
200
250
34
At startup (DAC output disabled), RL = 100 kΩ
DAC output disabled to enabled (DAC registers at zero
scale, RL = 100 kΩ
Output enable glitch
magnitude
mV
0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V
Output noise voltage (peak to
peak)
Vn
µVPP
Internal VREF, gain = 4x, 0.1 Hz to 10 Hz, DAC at
midscale, VDD = 5.5 V
70
Measured at 1 kHz, DAC at midscale, VDD = 5.5 V
0.2
0.7
Output noise density
µV/√Hz
Internal VREF, gain = 4x, measured at 1 kHz, DAC at
midscale, VDD = 5.5 V
Internal VREF, gain = 4x, 200-mV 50-Hz or 60-Hz sine
wave superimposed on power supply voltage, DAC at
midscale
Power supply rejection ratio
(ac)(3)
dB
–71
±1 LSB change around mid code (including
feedthrough)
Code change glitch impulse
10
15
nV-s
mV
Code change glitch impulse
magnitude
±1 LSB change around mid code (including
feedthrough)
VOLTAGE REFERENCE
Initial accuracy
TA = 25°C
1.212
V
Reference output temperature
coefficient(2)
65 ppm/°C
EEPROM
20000
1000
50
–40°C ≤TA ≤+85°C
TA > 85°C
Endurance(2)
Cycles
Years
TA = 25°C
Data retention(2)
TA = 125°C
20
EEPROM programming write
cycle time(2)
10
20
ms
DIGITAL INPUTS
Digital feedthrough
Pin capacitance
DAC output static at midscale, fast mode plus, SCL
toggling
20
10
nV-s
pF
Per pin
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
6
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
7.5 Electrical Characteristics (continued)
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤VDD ≤5.5 V,
DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩto AGND) and capacitive
load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER
Load capacitor - CAP pin(2)
0.5
15
µF
mA
µA
Normal mode, DACs at full scale, digital pins static
DAC power-down, internal reference power down
0.225
80
0.55
IDD
Current flowing into VDD
(1) Measured with DAC output unloaded. For external reference between end-point codes: 8d to 1016d for 10-bit resolution, 2d to 254d for
8-bit resolution. For internal reference VDD ≥1.21 x gain + 0.2 V, between end-point codes: 8d to 1016d for 10-bit resolution, 2d to
254d for 8-bit resolution.
(2) Specified by design and characterization, not production tested.
(3) Specified with 200-mV headroom with respect to reference value when internal reference is used.
(4) Measured with DAC output unloaded. For 10-bit resolution, between end-point codes: 8d to 1016d and for 8-bit resolution, between
end-point codes: 2d to 254d.
7.6 Timing Requirements: I2C Standard Mode
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and 1.8 V ≤Vpull-up
≤VDD
V
MIN
NOM
MAX
UNIT
MHz
µs
fSCLK
tBUF
SCL frequency
0.1
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
4.7
4
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
tHIGH
tF
µs
4.7
4
µs
µs
0
ns
Data setup time
250
4700
4000
ns
SCL clock low period
ns
SCL clock high period
Clock and data fall time
Clock and data rise time
ns
300
ns
tR
1000
ns
7.7 Timing Requirements: I2C Fast Mode
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and 1.8 V ≤Vpull-up
≤VDD
V
MIN
NOM
MAX
UNIT
MHz
µs
fSCLK
tBUF
SCL frequency
0.4
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
1.3
0.6
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
tHIGH
tF
µs
0.6
µs
0.6
µs
0
ns
Data setup time
100
1300
600
ns
SCL clock low period
ns
SCL clock high period
Clock and data fall time
Clock and data rise time
ns
300
300
ns
tR
ns
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
7.8 Timing Requirements: I2C Fast Mode Plus
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and 1.8 V ≤Vpull-up
≤VDD
V
MIN
NOM
MAX
UNIT
MHz
µs
fSCLK
tBUF
SCL frequency
1
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
0.5
0.26
0.26
0.26
0
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
tHIGH
tF
µs
µs
µs
ns
Data setup time
50
ns
SCL clock low period
0.5
µs
SCL clock high period
Clock and data fall time
Clock and data rise time
0.26
µs
120
120
ns
tR
ns
7.9 Timing Requirements: GPI
all input signals are timed from VIL to 70% of VDD. VDD = 1.8 V to 5.5 V and TA = –40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
GPI edge to start of operation delay, 1.7 V ≤VDD ≤5.5 V(1)
tGPIDELAY
2
µs
(1) The value specified for tGPIDELAY in the timing table is in addition to 2x SLEW_RATE for margin-high, low and function generation
operations. The typical value for the total delay is (2xSLEW_RATE + tGPIDELAY).
7.10 Timing Diagram
Low byte ACK cycle
tR
tLOW
tF
SCL
tSUSTA
tHDSTA
tHIGH
tSUSTO
tHDDAT
tSUDAT
tHDSTA
SDA
tBUF
S
P
S
P
图7-1. I2C Timing Diagram
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
8
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
7.11 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
INL min, reference = VDD, gain = 1x
INL max, reference = VDD, gain = 1x
INL min, internal reference, gain = 4x
INL max, internal reference, gain = 4x
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
Reference = VDD, gain = 1x
Internal reference, gain = 4x
0
128
256
384
512
Code
640
768
896 1023
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
图7-2. Integral Linearity Error vs Digital Input Code
图7-3. Integral Linearity Error vs Temperature
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
DNL max, reference = VDD, gain = 1x
DNL min, reference = VDD, gain = 1x
DNL max, internal reference, gain = 4x
DNL min, internal reference, gain = 4x
-0.2
-0.4
-0.6
-0.2
-0.4
-0.6
-0.8
-1
Reference = VDD, gain = 1x
-0.8
Internal reference, gain = 4x
-1
0
128
256
384
512
Code
640
768
896 1023
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
图7-4. Differential Linearity Error vs Digital Input Code
图7-5. Differential Linearity Error vs Temperature
0.5
0.5
Reference = VDD, gain = 1x
Internal reference, gain = 4x
TUE max, reference = VDD, gain = 1x
TUE min, reference = VDD, gain = 1x
TUE max, internal reference, gain = 4x
TUE min, internal reference, gain = 4x
0.4
0.4
0.3
0.2
0.1
0
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
0
128
256
384
512
Code
640
768
896 1023
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
图7-6. Total Unadjusted Error vs Digital Input Code
图7-7. Total Unadjusted Error vs Temperature
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
7.11 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
(continued)
at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)
2
1.5
1
0.5
0.3
0.5
0
0.1
-0.1
-0.3
-0.5
-0.5
-1
-1.5
-2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
Reference = VDD
图7-8. Zero Code Error vs Temperature
Reference = VDD
图7-9. Offset Error vs Temperature
0.5
0.5
Reference = VDD, gain = 1x
Internal reference, gain = 4x
Reference = VDD, gain 1x
Internal reference, gain 4x
0.3
0.3
0.1
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
图7-10. Gain Error vs Temperature
图7-11. Full-Scale Error vs Temperature
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
10
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
7.12 Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
INL max, reference = VDD, gain = 1x
INL min, reference = VDD, gain = 1x
INL max, internal reference, gain = 1.5x
INL min, internal reference, gain = 1.5x
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
Reference = VDD, gain = 1x
Internal reference, gain = 1.5x
0
128
256
384
512
Code
640
768
896 1023
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
图7-12. Integral Linearity Error vs Digital Input Code
图7-13. Integral Linearity Error vs Temperature
1
0.8
0.6
0.4
0.2
0
1
DNL max, reference = VDD, gain = 1x
DNL min, reference = VDD, gain = 1x
DNL max, internal reference, gain = 1.5x
DNL min, internal reference, gain = 1.5x
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.2
-0.4
-0.6
-0.8
-1
Reference = VDD, gain = 1x
-0.8
Internal reference, gain = 1.5x
-1
0
128
256
384
512
Code
640
768
896 1023
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
图7-14. Differential Linearity Error vs Digital Input Code
图7-15. Differential Linearity Error vs Temperature
1
0.8
0.6
0.4
0.2
0
0.25
0.2
0.15
0.1
0.05
0
-0.2
-0.05
-0.1
-0.15
-0.4
TUE max, reference = VDD, gain = 1x
TUE min, reference = VDD, gain = 1x
TUE max, internal reference, gain = 1.5x
-0.6
-0.8
Reference = VDD, gain = 1x
-0.2
TUE min, internal reference, gain = 1.5x
-1
Internal reference, gain = 1.5x
-0.25
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0
128
256
384
512
Code
640
768
896 1023
图7-17. Total Unadjusted Error vs Temperature
图7-16. Total Unadjusted Error vs Digital Input Code
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
7.12 Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
(continued)
at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)
8
7
6
5
4
3
2
1
0
0.5
0.3
0.1
-0.1
-0.3
-0.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
Reference = VDD
图7-18. Zero Code Error vs Temperature
Reference = VDD
图7-19. Offset Error vs Temperature
0.5
0.5
0.4
0.3
0.2
0.1
0
Reference = VDD, gain = 1x
Internal reference, gain = 1.5x
0.3
0.1
-0.1
-0.3
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Reference = VDD, gain = 1x
Internal reference, gain = 1.5x
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
图7-20. Gain Error vs Temperature
图7-21. Full-Scale Error vs Temperature
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
12
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
7.13 Typical Characteristics
at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
INL min
INL max
DNL min
DNL max
1.8
2.725
3.65
Supply Voltage, VDD (V)
4.575
5.5
1.8
2.725
3.65
Supply Voltage, VDD (V)
4.575
5.5
Reference = VDD
Reference = VDD
图7-22. Integral Linearity Error vs Supply Voltage
图7-23. Differential Linearity Error vs Supply Voltage
0.25
0.2
12
11
10
9
0.15
0.1
8
7
0.05
0
6
5
-0.05
-0.1
-0.15
4
3
2
1
TUE max
TUE min
-0.2
0
-0.25
-1
1.8
2.725
3.65
Supply Voltage, VDD (V)
4.575
5.5
1.8
2.3
2.8
3.3
3.8
Supply Voltage, VDD (V)
4.3
4.8
5.3
Reference = VDD
Reference = VDD
图7-25. Zero-Code Error vs Supply Voltage
图7-24. Total Unadjusted Error vs Supply Voltage
0.5
0.5
0.3
0.1
0.3
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
1.8
2.3
2.8
3.3
Supply Voltage, VDD (V)
3.8
4.3
4.8
5.3
1.8
2.3
2.8
3.3
Supply Voltage, VDD (V)
3.8
4.3
4.8
5.3
Reference = VDD
图7-26. Offset Error vs Supply Voltage
Reference = VDD
图7-27. Gain Error vs Supply Voltage
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
7.13 Typical Characteristics (continued)
at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)
0.2
0.16
0.12
0.08
0.04
0
-0.04
-0.08
-0.12
-0.16
-0.2
1.8
2.725
3.65
Supply Voltage, VDD (V)
4.575
5.5
Reference = VDD
VDD = 1.8 V
图7-29. Supply Current vs Digital Input Code
图7-28. Full-Scale Error vs Supply Voltage
VDD = 5.5 V
Reference = VDD, DAC at midscale
图7-31. Supply Current vs Temperature
图7-30. Supply Current vs Digital Input Code
0.5
0.4
0.3
0.2
0.1
0
Reference = VDD, gain = 1x
Internal reference, gain = 1.5x
1.8
2.3
2.8
3.3
3.8
4.3
Supply Voltage, VDD (V)
4.8
5.3
DAC at midscale
图7-33. Supply Current vs Supply Voltage
Internal reference (gain = 4x), DAC at midscale
图7-32. Supply Current vs Temperature
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
14
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
7.13 Typical Characteristics (continued)
at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)
0.1
0.0875
0.075
0.0625
0.05
6
5
4
3
2
1
0.0375
0.025
0.0125
0
0
IDD, VDD = 1.8 V
IDD, VDD = 3.3 V
IDD, VDD = 5.5 V
-1
-2
Reference = VDD = 1.8 V
Reference = VDD = 5.5 V
-20
-15
-10
-5
0
5
Load Current (mA)
10
15
20
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Reference = VDD, DAC powered down
图7-35. Source and Sink Capability
图7-34. Power-Down Current vs Temperature
Reference = VDD = 5.5 V, DAC code transition from midscale
Reference = VDD = 5.5 V, DAC code transition from midscale
to midscale + 1 LSB, DAC load = 5kΩ|| 200pF
to midscale –1 LSB, DAC load = 5kΩ|| 200pF
图7-36. Glitch Impulse, Rising Edge, 1-LSB Step
图7-37. Glitch Impulse, Falling Edge, 1-LSB Step
Reference = VDD = 5.5 V, DAC load = 5kΩ|| 200pF
图7-38. Full-Scale Settling Time, Rising Edge
Reference = VDD = 5.5 V, DAC load = 5kΩ|| 200pF
图7-39. Full-Scale Settling Time, Falling Edge
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
7.13 Typical Characteristics (continued)
at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)
VDD (1 V / div)
VOUT unloaded (500 mV / div)
VOUT 10K-GND (15 mV / div)
VDD (1 V / div)
VOUT unloaded (500 mV / div)
VOUT 10K-GND (15 mV / div)
0
5
10
15
20
25
Time (ms)
30
35
40
45
50
0
5
10
15
20
25
Time (ms)
30
35
40
45
50
Reference = VDD = 5.5 V
图7-40. Power-on Glitch
Reference = VDD = 5.5 V
图7-41. Power-off Glitch
-40
-50
-60
-70
-80
-90
-100
10
20 30 50 70100 200
500 1000 2000 5000 10000
Frequency (Hz)
Internal reference (gain = 4x), VDD = 5.25 V + 0.25 VPP, DAC
Reference = VDD = 5.5 V, Fast+ mode, DAC at midscale, DAC
at midscale, DAC load = 5kΩ|| 200pF
load = 5kΩ|| 200pF
图7-43. DAC Output AC PSRR vs Frequency
图7-42. Clock Feedthrough
Reference = VDD = 5.5 V
Internal reference (gain = 4x), VDD = 5.5 V
图7-44. DAC Output Noise Spectral Density
图7-45. DAC Output Noise Spectral Density
Copyright © 2023 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
7.13 Typical Characteristics (continued)
at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)
Reference = VDD = 5.5 V, DAC at midscale
Internal reference (gain = 4x), VDD = 5.5 V, DAC at midscale
图7-46. DAC Output Noise: 0.1 Hz to 10 Hz
图7-47. DAC Output Noise: 0.1 Hz to 10 Hz
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8 Detailed Description
8.1 Overview
The 10-bit DAC53701 and 8-bit DAC43701 (DACx3701) are a pin-compatible family of buffered voltage-output,
smart digital-to-analog converters (DACs). These smart DACs contain nonvolatile memory (NVM), an internal
reference, a PMBus-compatible I2C interface, force-sense output, and a general-purpose input. The DACx3701
operate with either an internal reference or with a power supply as the reference, and provide a full-scale output
of 1.8 V to 5.5 V.
These devices communicate through an I2C interface, and support I2C standard mode (100 kbps), fast mode
(400 kbps), and fast mode plus (1 Mbps). These devices also support specific PMBus commands such as turn
on/off, margin high or low, and more. The GPI input can be configured as a power-down trigger, margin-high-low,
function trigger, and medical alarm trigger. The DACx3701 also include digital slew rate control, and support
basic signal generation such as square, ramp, and sawtooth waveforms. These devices can generate pulse-
width modulation (PWM) output with the combination of the triangular or sawtooth waveform and the FB pin.
These features enable the DACx3701 to go beyond the limitations of a conventional DAC that depends on a
processor to function. Because of processor-less operation and the smart feature set, the DACx3701 are called
smart DACs.
The DACx3701 have a power-on-reset (POR) circuit that makes sure all the registers start with default or user-
programmed settings using NVM. The DAC output powers on in high-impedance mode (default); this setting can
be programmed to 10kΩ-GND using NVM.
8.2 Functional Block Diagram
CAP
LDO
VDD
SCL
SDA
Non Volatile
Memory
Internal
Reference
DAC
Buffer
DAC
Register
DAC
+
OUT
FB
GPI
BUF
œ
R1
Function
Generation
Power Down Logic
Power On Reset
AGND
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
18
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.3 Feature Description
8.3.1 Digital-to-Analog Converter (DAC) Architecture
The DACx3701 family of devices consists of string architecture with an output buffer amplifier. 节 8.2 shows the
DAC architecture within the block diagram. This DAC architecture operates from a 1.8-V to 5.5-V power supply.
These devices consume only 0.2 mA of current when using a 1.8-V power supply. The DAC output pin starts up
in high-impedance mode, making these devices an excellent choice for power-supply control applications. To
change the power-up mode to 10kΩ-GND, program the DAC_PDN bit (address: D1h), and load these bits in the
device NVM. The DACx3701 devices include a smart feature set to enable processor-less operation and high-
integration. The NVM enables a predictable startup. The GPI triggers the DAC output without the I2C interface in
the absence of a processor or when the processor or software fails. The integrated functions and the FB pin
enable PWM output for control applications. The FB pin enables this device to be used as a programmable
comparator. The digital slew rate control and the Hi-Z power-down modes enable a hassle-free voltage
margining and function.
8.3.1.1 Reference Selection and DAC Transfer Function
The device writes the input data to the DAC data registers in straight-binary format. After a power-on or a reset
event, the device sets all DAC registers to the values set in the NVM.
8.3.1.1.1 Power Supply as Reference
By default, the DACx3701 operate with the power-supply pin (VDD) as a reference. 方程式 1 shows DAC
transfer function when the power-supply pin is used as reference. The gain at the output stage is always 1x.
DAC _DATA
2N
VOUT
=
ì VDD
(1)
where:
• N is the resolution in bits, either 8 (DAC43701) or 10 (DAC53701).
• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC register.
• DAC_DATA ranges from 0 to 2N –1.
• VDD is used as the DAC reference voltage.
8.3.1.1.2 Internal Reference
The DACx3701 also contain an internal reference that is disabled by default. Enable the internal reference by
writing 1 to REF_EN (address D1h). The internal reference generates a fixed 1.21-V voltage (typical). Using
DAC_SPAN (address D1h) bits, gain of 1.5x, 2x, 3x, 4x can be achieved for the DAC output voltage (VOUT) 方程
式2 shows DAC transfer function when the internal reference is used.
DAC_DATA
2N
VOUT
=
ì VREF ìGAIN
(2)
where:
• N is the resolution in bits, either 8 (DAC43701) or 10 (DAC53701).
• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC register
• DAC_DATA ranges from 0 to 2N –1.
• VREF is the internal reference voltage = 1.21 V.
• GAIN = 1.5x, 2x, 3x, 4x, based on DAC_SPAN (address D1h) bits.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.3.2 General-Purpose Input (GPI)
The GPI pin of DACx3701 enables processorless operation. The GPI pin can be configured to trigger various
functions, as shown in 表 8-1. The GPI_EN bit in the TRIGGER (节 8.6.4) register enables or disables the GPI
input. The GPI_CONFIG field in the CONFIG2 (节8.6.3) register maps the GPI pin to various functions. The GPI
operations are edge-triggered once the device boots up. Once the power supply ramps up, the device registers
the GPI level and executes the associated command. This feature allows the user to configure the initial output
state at power-on. By default, the GPI pin is not mapped to any operation. Pull the GPI pin to high or low when
not used. When the GPI pin is mapped to a specific function, the corresponding software bit functionality is
disabled to avoid a race condition. When the GPI is mapped to margin-high or low trigger function, the output
changes dynamically, unlike the behavior with I2C-based programming. This behavior is shown in 节 9.2.1.3. All
other constraints of the functions are applied to the GPI-based trigger.
表8-1. GPI Configuration
REGISTER NAME
GPI_EN
GPI_CONFIG
PIN FUNCTION
PIN EDGE
COMMAND
No Operation (Default)
0
X
None
X
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Power-Up
Power-Up, Down
(Hi-Z)
1
1
1
1
1
1
1
1
000
001
010
011
100
101
110
111
Hi-Z Power-Down
Power-Up
Power-Up, Down
(10-kΩ)
10-kΩPower-Down
Margin High Trigger
Margin-High, Low
Margin Low Trigger
Start Function Generation
Stop Function Generation
Start High-Priority Medical Alarm
Stop High-Priority Medical Alarm
Start Medium-Priority Medical Alarm
Stop Medium-Priority Medical Alarm
Start Low-Priority Medical Alarm
Stop Low-Priority Medical Alarm
Enable I2C Slave Address Update
Disable I2C Slave Address Update
Function
Generation
D2h, CONFIG2 and
D3h, TRIGGER
High-Priority
Medical Alarm
Medium-Priority
Medical Alarm
Low-Priority
Medical Alarm
I2C Slave Address
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
20
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.3.3 DAC Update
The DAC output pin (OUT) is updated at the end of I2C DAC write frame.
8.3.3.1 DAC Update Busy
The DAC_UPDATE_BUSY bit (address D0h) is set to 1 by the device when certain DAC update operations,
such as function generation, transition to margin high or low, or any of the medical alarms are in progress. When
the DAC_UPDATE_BUSY bit is set to 1, do not write to any of the DAC registers. After the DAC update
operation is completed (DAC_UPDATE_BUSY = 0), any of the DAC registers can be written.
8.3.4 Nonvolatile Memory (EEPROM or NVM)
The DACx3701 contain nonvolatile memory (NVM) bits. These memory bits are user programmable and
erasable, and retain the set values in the absence of a power supply. All the register bits, as shown in 表 8-2,
can be stored in the device NVM by setting NVM_PROG = 1 (address D3h). The NVM_BUSY bit (address D0h)
is set to 1 by device when a NVM write or reload operation is ongoing. During this time, the device blocks all
write operations to the device. The NVM_BUSY bit is set to 0 after the write or reload operation is complete; at
this point, all write operations to the device are allowed. The default value for all the registers in the DACx3701 is
loaded from NVM as soon as a POR event is issued. Do not perform a read operation from the DAC register
while NVM_BUSY = 1.
The DACx3701 also implement NVM_RELOAD bit (address D3h). Set this bit to 1 for the device to start an NVM
reload operation. After the operation is complete, the device autoresets this bit to 0. During the NVM_RELOAD
operation, the NVM_BUSY bit is set to 1.
表8-2. NVM Programmable Registers
REGISTER ADDRESS
REGISTER NAME
BIT ADDRESS
BIT NAME
DEVICE_LOCK
13
11:9
8:5
CODE_STEP
SLEW_RATE
D1h
GENERAL_CONFIG
4:3
DAC_PDN
2
REF_EN
1:0
DAC_SPAN
15:14
13:11
5:4
SLAVE_ADDRESS
GPI_CONFIG
D2h
CONFIG2
INTERBURST_TIME
PULSE_OFF_TIME
PULSE_ON_TIME
GPI_EN
3:2
1:0
D3h
21h
25h
26h
TRIGGER
10
DAC_DATA
11:2
11:4
11:4
DAC_DATA
DAC_MARGIN_HIGH
DAC_MARGIN_LOW
MARGIN_HIGH (8 most significant bits)
MARGIN_LOW (8 most significant bits)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.3.4.1 NVM Cyclic Redundancy Check
The DACx3701 implement a cyclic redundancy check (CRC) feature for the device NVM to make sure that the
data stored in the device NVM is uncorrupted. There are two types of CRC alarm bits implemented in
DACx3701:
• NVM_CRC_ALARM_USER
• NVM_CRC_ALARM_INTERNAL
The NVM_CRC_ALARM_USER bit indicates the status of user-programmable NVM bits, and the
NVM_CRC_ALARM_INTERNAL bit indicates the status of internal NVM bits The CRC feature is implemented by
storing a 10-Bit CRC (CRC-10-ATM) along with the NVM data each time NVM program operation (write or
reload) is performed and during the device start up. The device reads the NVM data and validates the data with
the stored CRC. The CRC alarm bits (NVM_CRC_ALARM_USER and NVM_CRC_ALARM_INTERNAL address
D0h) report any errors after the data are read from the device NVM.
8.3.4.2 NVM_CRC_ALARM_USER Bit
A logic 1 on NVM_CRC_ALARM_USER bit indicates that the user-programmable NVM data are corrupt. During
this condition, all registers in the DAC are initialized with factory reset values, and any DAC registers can be
written to or read from. To reset the alarm bits to 0, issue a software reset (see 节 8.3.7) command, or cycle
power to the DAC. A power cycle also reloads the user-programmable NVM bits. In case of NVM data
corruption, program the NVM again.
8.3.4.3 NVM_CRC_ALARM_INTERNAL Bit
A logic 1 on NVM_CRC_ALARM_INTERNAL bit indicates that the internal NVM data are corrupt. During this
condition, all registers in the DAC are initialized with factory reset values, and any DAC registers can be written
to or read from. In case of a temporary failure, to reset the alarm bits to 0, issue a software reset (see 节 8.3.7)
command or cycle power to the DAC.
8.3.5 Programmable Slew Rate
When the DAC data registers are written, the voltage on DAC output (VOUT) immediately transitions to the new
code following the slew rate and settling time specified in 节 7.5. The slew rate control feature allows the user to
control the rate at which the output voltage (VOUT) changes. When this feature is enabled (using
SLEW_RATE[3:0] bits), the DAC output changes from the current code to the code in MARGIN_HIGH (address
25h) or MARGIN_LOW (address 26h) registers (when margin high or low commands are issued to the DAC)
using the step and rate set in CODE_STEP and SLEW_RATE bits. With the default slew rate control setting
(CODE_STEP and SLEW_RATE bits, address D1h), the output changes smoothly at a rate limited by the output
drive circuitry and the attached load. Using this feature, the output steps digitally at a rate defined by bits
CODE_STEP and SLEW_RATE on address D1h. SLEW_RATE defines the rate at which the digital slew
updates; CODE_STEP defines the amount by which the output value changes at each update. 表8-3 and 表8-4
show different settings for CODE_STEP and SLEW_RATE.
When the slew rate control feature is used, the output changes happen at the programmed slew rate. This
configuration results in a staircase formation at the output. Do not write to CODE_STEP, SLEW_RATE, or
DAC_DATA during the output slew.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
22
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
表8-3. Code Step
REGISTER ADDRESS
AND NAME
CODE_STEP[2]
CODE_STEP[1]
CODE_STEP[0]
COMMENT
Code step size = 1 LSB
(default)
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Code step size = 2 LSB
Code step size = 3 LSB
Code step size = 4 LSB
Code step size = 6 LSB
Code step size = 8 LSB
Code step size = 16 LSB
Code step size = 32 LSB
D1h, GENERAL_CONFIG
表8-4. Slew Rate
REGISTER ADDRESS
AND NAME
TIME PERIOD (PER
STEP)
SLEW_RATE[3]
SLEW_RATE[2]
SLEW_RATE[1]
SLEW_RATE[0]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
25.6 µs
32 µs
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
38.4 µs
44.8 µs
204.8 µs
256 µs
307.2 µs
819.2 µs
1638.4 µs
2457.6 µs
3276.8 µs
4915.2 µs
12 µs
D1h, GENERAL_CONFIG
8 µs
4 µs
0 µs, no slew (default)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.3.6 Power-on-Reset (POR)
The DACx3701 family of devices includes a power-on reset (POR) function that controls the output voltage at
power up. After the VDD supply has been established, a POR event is issued. The POR causes all registers to
initialize to default values, and communication with the device is valid only after a 30-ms, POR delay. The default
value for all the registers in the DACx3701 is loaded from NVM as soon as the POR event is issued.
When the device powers up, a POR circuit sets the device to the default mode. The POR circuit requires specific
VDD levels, as indicated in 图 8-1, in order to make sure that the internal capacitors discharge and reset the
device on power up. To make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms. When VDD
drops to less than 1.65 V, but remains greater than 0.7 V (shown as the undefined region), the device may or
may not reset under all specified temperature and power-supply conditions. In this case, initiate a POR. When
VDD remains greater than 1.65 V, a POR does not occur.
VDD (V)
5.5 V
Specified supply
voltage range
No power-on reset
1.71 V
1.65 V
Undefined
0.7 V
Power-on reset
0 V
图8-1. Threshold Levels for VDD POR Circuit
8.3.7 Software Reset
To initiate a device software reset event, write the reserved code 1010 to the SW_RESET (address D3h). A
software reset initiates a POR event.
8.3.8 Device Lock Feature
The DACx3701 implement a device lock feature that prevents an accidental or unintended write to the DAC
registers. The device locks all the registers when the DEVICE_LOCK bit (address D1h) is set to 1. To bypass the
DEVICE_LOCK setting, write 0101 to the DEVICE_UNLOCK_CODE bits (address D3h).
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
24
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.3.9 PMBus Compatibility
The PMBus protocol is an I2C-based communication standard for power-supply management. PMBus contains
standard command codes tailored to power supply applications. The DACx3701 implement some PMBus
commands such as Turn Off, Turn On, Margin Low, Margin High, Communication Failure Alert Bit (CML), as well
as PMBUS revision. 图 8-2 shows typical PMBus connections. The EN_PMBUS bit (Bit 12, address D1h) must
be set to 1 to enable the PMBus protocol.
PMBus-compatible device #1
ALERT
CONTROL
DATA
CLOCK
Alert signal
PMBus-compatible device #2
ALERT
Control signal
CONTROL
Data
DATA
Clock
CLOCK
Optional
Required
PMBus-compatible device #3
ALERT
CONTROL
DATA
CLOCK
图8-2. PMBus Connections
Similar to I2C, PMBus is a variable length packet of 8-bit data bytes, each with a receiver acknowledge, wrapped
between a start and stop bit. The first byte is always a 7-bit slave address followed by a write bit, sometimes
called the even address that identifies the intended receiver of the packet. The second byte is an 8-bit command
byte, identifying the PMBus command being transmitted using the respective command code. After the
command byte, the transmitter either sends data associated with the command to write to the receiver command
register (from most significant byte to least significant byte), or sends a new start bit indicating the desire to read
the data associated with the command register from the receiver. Then the receiver transmits the data following
the same most significant byte first format (see 表8-11).
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.4 Device Functional Modes
8.4.1 Power Down Mode
The DACx3701 output amplifier and internal reference can be independently powered down through the
DAC_PDN bits (address D1h). At power up, the DAC output and the internal reference are disabled by default.
In power-down mode, the DAC output (OUT pin) is in a high-impedance state. To change this state to 10kΩ-
AGND (at power up), use the DAC_PDN bits (address D1h).
The DAC power-up state can be programmed to any state (power-down or normal mode) using the NVM. 表 8-5
shows the DAC power-down bits.
表8-5. DAC Power-Down Bits
REGISTER ADDRESS AND NAME
DAC_PDN[1]
DAC_PDN[0]
DESCRIPTION
Power up
0
0
0
1
Power down to 10 kΩ
D1h, GENERAL_CONFIG
Power down to high impedance (HiZ)
(default)
1
1
0
1
Power down to 10 kΩ
8.4.2 Continuous Waveform Generation (CWG) Mode
The DACx3701 implement a continuous waveform generation feature. To set the device to this mode, set the
START_FUNC_GEN (address D3h) to 1. In this mode, the DAC output pin (OUT) generates a continuous
waveform based on the FUNC_CONFIG bits (address D1h). 表8-6 shows the continuous waveforms that can be
generated in this mode. The frequency of the waveform depends on the resistive and capacitive load on the
OUT pin, high and low codes, and slew rate settings as shown in the following equations.
1
fSQUARE-WAVE
=
2ìSLEW _RATE
(3)
(4)
(5)
1
fTRIANGLE-WAVE
=
≈ MARGIN_HIGH -MARGIN_LOW +1’
CODE _STEP
2ìSLEW _RATEì
∆
÷
«
◊
1
fSAWTOOTH-WAVE
=
≈MARGIN_HIGH-MARGIN_LOW +1’
CODE_STEP
SLEW _RATEì
∆
÷
«
◊
where:
• SLEW_RATE is the programmable DAC slew rate specified in 表8-4.
• MARGIN_HIGH and MARGIN_LOW are the programmable DAC codes.
• CODE_STEP is the programmable DAC step code in 表8-3.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
26
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
表8-6. FUNC_CONFIG bits
REGISTER ADDRESS AND NAME
FUNC_CONFIG[1]
FUNC_CONFIG[0]
DESCRIPTION
Generates a triangle wave between
MARGIN_HIGH (address 25h) code to
MARGIN_LOW (address 26h) code with slope
defined by SLEW_RATE and CODE_STEP
(address D1h) bits
0
0
1
1
0
Generates Saw-Tooth wave between
MARGIN_HIGH (address 25h) code to
MARGIN_LOW (address 26h) code, with rising
slope defined by SLEW_RATE and CODE_STEP
(address D1h) bits and immediate falling edge
1
0
1
D1h, GENERAL_CONFIG
Generates Saw-Tooth wave between
MARGIN_HIGH (address 25h) code to
MARGIN_LOW (address 26h) code, with falling
slope defined by SLEW_RATE and CODE_STEP
(address D1h) bits and immediate rising edge
Generates a square wave between
MARGIN_HIGH (address 25h) code to
MARGIN_LOW (address 26h) code with pulse
high and low period defined by SLEW_RATE
(address D1h) bits
8.4.3 PMBus Compatibility Mode
The DACx3701 I2C interface implements some of the PMBus commands. 表 8-7 shows the supported PMBus
commands that are implemented in DACx3701.The DAC uses MARGIN_LOW (address 26h), MARGIN_HIGH
(address 25h) bits, SLEW_RATE, and CODE_STEP bits (address D1h) for PMBUS_OPERATION_CMD. The
EN_PMBUS bit (Bit 12, address D1h) must be set to 1 to enable the PMBus protocol.
表8-7. PMBus Operation Commands
REGISTER ADDRESS AND NAME
PMBUS_OPERATION_CMD[15:8]
DESCRIPTION
Turn off
00h
80h
94h
A4h
Turn on
01h, PMBUS_OPERATION
Margin low
Margin high
The DACx3701 also implement PMBus features such as group command protocol and communication time-out
failure. The CML bit (address 78h) indicates a communication fault in the PMBus. This bit is reset by writing 1.
To get the PMBus version, read the PMBUS_VERSION bits (address 98h).
8.4.4 Medical Alarm Generation Mode
The DACx3701 are also used to generate continuous alarm tones for medical devices. Use a suitable analog
mixer, audio amplifier, and a speaker to generate low, medium, or high priority alarm tones. See the Application
and Implementation section for more details. The DACx3701 allow tunability and configurability to support
different alarm generation. Using this approach, configurable medical alarm tones can be generated with a
simple circuit, and with no need for runtime software. The GPI pin can be used for trigerring an alarm directly
without using the I2C interface. This feature helps when the processor fails or the software crashes. This feature
is also helpful when there is a power failure and the alarm circuit is driven by a battery or a super capacitor.
8.4.4.1 Low-Priority Alarm
The MED_ALARM_LP bit (address D2h) is used to trigger a medical low-priority alarm generation. The DAC
generates a continuous-alarm signal until this bit is set back to 0. After the bit is set to 0, the device does not
abruptly end the alarm generation; the device stops only after completing the ongoing burst.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.4.4.2 Medium-Priority Alarm
The MED_ALARM_MP bit (address D2h) is used to trigger a medical medium-priority alarm generation. The
DAC generates a continuous-alarm signal until this bit is set back to 0. After the bit is set to 0, the device does
not abruptly end the alarm generation; the device stops only after completing the ongoing burst.
8.4.4.3 High-Priority Alarm
The MED_ALARM_HP bit (address D2h) is used to trigger a medical high-priority alarm generation. The DAC
generates a continuous-alarm signal until this bit is set back to 0. After the bit is set to 0, the device does not
abruptly end the alarm generation; the device stops only after completing the ongoing burst.
8.4.4.4 Interburst Time
The INTERBURST_TIME bit (address D2h) is used set the time between two adjacent bursts. 表 8-8 lists the
INTERBURST_TIME settings.
表8-8. Interburst Time
MEDIUM PRIORITY
ALARM INTERBURST
TIME
REGISTER ADDRESS
AND NAME
HIGH PRIORITY ALARM
INTERBURST TIME
LOW PRIORITY ALARM
INTERBURST TIME
INTERBURST_TIME[1:0]
00
01
10
11
2.55 s
2.96 s
3.38 s
3.80 s
2.60 s
3.06 s
3.52 s
4.00 s
D2h, CONFIG2
16 s
8.4.4.5 Pulse Off Time
The PULSE_OFF_TIME bit (address D2h) is used to control the low period of trapezoid in a medical alarm
waveform. 表8-9 lists the PULSE_OFF_TIME settings.
表8-9. Pulse Off Time
MEDIUM PRIORITY
ALARM PULSE OFF
TIME
REGISTER ADDRESS
AND NAME
HIGH PRIORITY ALARM
PULSE OFF TIME
LOW PRIORITY ALARM
PULSE OFF TIME
PULSE_OFF_TIME[1:0]
00
01
10
11
15 ms
36 ms
58 ms
80 ms
40 ms
60 ms
80 ms
100 ms
40 ms
60 ms
80 ms
100 ms
D2h, CONFIG2
8.4.4.6 Pulse On Time
The PULSE_ON_TIME bit (address D2h) controls the high period of trapezoid in a medical alarm waveform. 表
8-10 lists the PULSE_ON_TIME settings.
表8-10. Pulse On Time
REGISTER ADDRESS
AND NAME
HIGH PRIORITY ALARM
PULSE ON TIME
MEDIUM PRIORITY
ALARM PULSE ON TIME
LOW PRIORITY ALARM
PULSE ON TIME
PULSE_ON_TIME[1:0]
00
01
10
11
80 ms
103 ms
126 ms
150 ms
130 ms
153 ms
176 ms
200 ms
130 ms
153 ms
176 ms
200 ms
D2h, CONFIG2
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
28
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.5 Programming
The DACx3701 devices have a 2-wire serial interface (SCL and SDA) as shown in the pin diagram of 节 6. The
I2C bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both
SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through the open drain
I/O pins, SDA and SCL.
The I2C specification states that the device that controls communication is called a master, and the devices that
are controlled by the master are called slaves. The master device generates the SCL signal. The master device
also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus
to indicate the start or stop of a data transfer. Device addressing is completed by the master. The master device
on an I2C bus is typically a microcontroller or digital signal processor (DSP). The DACx3701 family operates as a
slave device on the I2C bus. A slave device acknowledges master commands, and upon master control,
receives or transmits data.
Typically, theDACx3701 family operates as a slave receiver. A master device writes to the DACx3701, a slave
receiver. However, if a master device requires the DACx3701 internal register data, the DACx3701 operate as a
slave transmitter. In this case, the master device reads from the DACx3701. According to I2C terminology, read
and write refer to the master device.
The DACx3701 family is a slave and supports the following data transfer modes:
• Standard mode (100 kbps)
• Fast mode (400 kbps)
• Fast mode plus (1.0 Mbps)
The data transfer protocol for standard and fast modes is exactly the same; therefore, both modes are referred
to as F/S-mode in this document. The fast mode plus protocol is supported in terms of data transfer speed, but
not output current. The low-level output current would be 3 mA; similar to the case of standard and fast modes.
The DACx3701 family supports 7-bit addressing. The 10-bit addressing mode is not supported. The device
supports the general call reset function. Sending the following sequence initiates a software reset within the
device: start or repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the rising edge of the
ACK bit, following the second byte.
Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a ninth clock
cycle generates and detects an acknowledge signal. An acknowledge is when the SDA line is pulled low during
the high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the high
period of the ninth clock cycle, as shown in 图8-3.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
Data output
by transmitter
Not acknowledge
Data output
by receiver
Acknowledge
2
9
1
8
SCL from
master
S
Clock pulse for
acknowledgement
Start
condition
图8-3. Acknowledge and Not Acknowledge on the I2C Bus
8.5.1 F/S Mode Protocol
The following steps explain a complete transaction in F/S mode.
1. The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in 图8-4. All I2C-compatible devices
recognize a start condition.
2. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
(R/W) on the SDA line. During all transmissions, the master makes sure that data are valid. A valid data
condition requires the SDA line to be stable during the entire high period of the clock pulse, as shown in 图
8-5. All devices recognize the address sent by the master and compare the address to the respective
internal fixed address. Only the slave device with a matching address generates an acknowledge by pulling
the SDA line low during the entire high period of the 9th SCL cycle, as shown in Figure 8-3. When the
master detects this acknowledge, the communication link with a slave has been established.
3. The master generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the slave. In
either case, the receiver must acknowledge the data sent by the transmitter. The acknowledge signal can be
generated by the master or by the slave, depending on which is the receiver. The 9-bit valid data sequences
consists of 8-data bits and 1 acknowledge-bit, and can continue as long as necessary.
4. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from
low-to-high while the SCL line is high, as shown in 图8-4. This action releases the bus and stops the
communication link with the addressed slave. All I2C-compatible devices recognize the stop condition. Upon
receipt of a stop condition, the bus is released, and all slave devices then wait for a start condition followed
by a matching address.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
30
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
SDA
SDA
SCL
SCL
S
P
Start
condition
Stop
condition
Change of data
allowed
Data line stable
Data valid
图8-4. Start and Stop Conditions
图8-5. Bit Transfer on the I2C Bus
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.5.2 I2C Update Sequence
For a single update, the DACx3701 require a start condition, a valid I2C address byte, a command byte, and two
data bytes, as listed in 表8-11.
表8-11. Update Sequence
MSB
....
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
Address (A) byte
Command byte
节8.5.2.2
Data byte - MSDB
DB [15:8]
Data byte - LSDB
DB [7:0]
节8.5.2.1
DB [31:24]
DB [23:16]
After each byte is received, the DACx3701 family acknowledges the byte by pulling the SDA line low during the
high period of a single clock pulse, as shown in 图 8-6. These four bytes and acknowledge cycles make up the
36 clock cycles required for a single update to occur. A valid I2C address byte selects the DACx3701 devices.
Recognize
START or
REPEATED
Recognize
STOP or
REPEATED
Generate ACKNOWLEDGE
START
START
signal
condition
condition
P
SDA
Sr
MSB
Acknowledgement
signal from Slave
Address
R/W
1
SCL
1
7
8
9
2 - 8
9
Sr
or
P
S
or
Sr
ACK
ACK
START or
REPEATED
START or
STOP
REPEATED
START
condition
Clock line held low while
interrupts are serviced
condition
图8-6. I2C Bus Protocol
The command byte sets the operating mode of the selected DACx3701 device. For a data update to occur when
the operating mode is selected by this byte, the DACx3701 device must receive two data bytes: the most
significant data byte (MSDB) and least significant data byte (LSDB). The DACx3701 device performs an update
on the falling edge of the acknowledge signal that follows the LSDB.
When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 10 kSPS. Using the fast
mode plus (clock = 1 MHz), the maximum DAC update rate is limited to 25 kSPS. When a stop condition is
received, the DACx3701 device releases the I2C bus and awaits a new start condition.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
32
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.5.2.1 Address Byte
The address byte, as shown in the following table, is the first byte received following the start condition from the
master device. The first five bits (MSBs) of the address are factory preset to 10010. The next two bits of the
address are controlled by the SLAVE_ADDRESS field in the CONFIG2 register. Follow the procedure described
in the next section to configure the slave address. The possible slave addresses using these bits are also shown
in the next section.
表8-12. Address Byte
COMMENT
MSB
LSB
AD6
1
AD5
0
AD4
0
AD3
AD2
0
AD1
AD0
R/ W
—
See 表8-13
(slave address column)
General address
1
0
0 or 1
0
Broadcast address
1
0
0
1
1
1
The DACx3701 family supports broadcast addressing, which can be used for synchronously updating or
powering down multiple DACx3701 devices. The DACx3701 family is designed to work with other members of
the family to support multichip synchronous updates. Using the broadcast address, the DACx3701 devices
respond regardless of the states of the SLAVE_ADDRESS bits. Broadcast is supported only in write mode.
8.5.2.1.1 Slave Address Configuration
This section provides the step by step procedure to configure the I2C slave addresses for up to four DACs. Use
the broadcast address for all the steps.
1. Set GPI pin to 0b for all devices.
2. Set GPI_CONFIG in the CONFIG2 register to 111b.
3. Set GPI_EN in the TRIGGER register to 1b.
4. Set the GPI pin to logic HIGH for the device that needs to be configured.
5. Write data to SLAVE_ADDRESS bit field in the CONFIG2 register. Only the device with GPI pin logic HIGH
updates the SLAVE_ADDRESS setting passed in the command. Make sure that the rest of the devices on
the same I2C bus have their respective GPI pins set to logic LOW during this process.
6. Toggle the GPI pin of the device bring programmed to logic LOW.
7. Repeat steps (1) through (6) above to program the I2C slave addresses to all the devices on the bus.
8. Set GPI_EN to 0b.
9. Change GPI_CONFIG to 000b.
10. Trigger NVM write operation.
The devices are now ready for use.
表8-13. Address Format
SLAVE_ADDRESS FIELD
IN CONFIG2 REGISTER
SLAVE ADDRESS
1001000
1001001
1001010
1001011
00 (default)
01
10
11
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.5.2.2 Command Byte
表8-14 lists the command byte addresses.
表8-14. Command Byte (Register Names)
ADDRESS
REGISTER NAME
D0h
STATUS
D1h
GENERAL_CONFIG
CONFIG2
D2h
D3h
TRIGGER
21h
DAC_DATA
25h
DAC_MARGIN_HIGH
DAC_MARGIN_LOW
PMBUS_OPERATION
PMBUS_STATUS_BYTE
PMBUS_VERSION
26h
01h
78h
98h
8.5.3 I2C Read Sequence
To read any register the following command sequence must be used:
1. Send a start or repeated start command with a slave address and the R/ W bit set to 0 for writing. The device
acknowledges this event.
2. Send a command byte for the register to be read. The device acknowledges this event again.
3. Send a repeated start with the slave address and the R/ W bit set to 1 for reading. The device acknowledges
this event.
4. The device writes the MSDB byte of the addressed register. The master must acknowledge this byte.
5. Finally, the device writes out the LSDB of the register.
An alternative reading method allows for reading back the value of the last register written. The sequence is a
start or repeated start with the slave address and the R/ W bit set to 1, and the two bytes of the last register are
read out.
The broadcast address cannot be used for reading.
表8-15. Read Sequence
R/ W
(0)
R/ W
(1)
S
MSB
ACK MSB
LSB ACK Sr MSB
ACK MSB
LSB
ACK
MSB
LSB
ACK
…
…
…
…
…
ADDRESS
BYTE
节8.5.2.1
COMMAND
BYTE
节8.5.2.2
ADDRESS
BYTE
节8.5.2.1
Sr
MSDB
From Slave
LSDB
From Master
Slave
From Master
Slave
From Master
Slave
Master
From Slave
Master
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
34
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.6 Register Map
表8-16. Register Map
MOST SIGNIFICANT DATA BYTE (MSDB)
LEAST SIGNIFICANT DATA BYTE (LSDB)
ADDRESS
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
NVM_CRC_ NVM_CRC_
DAC_
UPDATE_
BUSY
D0h
ALARM_
USER
ALARM_
INTERNAL
NVM_BUSY
X(1)
DEVICE_ID
VERSION_ID
DEVICE_
LOCK
D1h
D2h
FUNC_CONFIG
EN_PMBUS
CODE_STEP
MED_
SLEW_RATE
DAC_PDN
REF_EN
DAC_SPAN
MED_
MED_
SLAVE_ADDRESS
GPI_CONFIG
RESERVED
INTERBURST_TIME
PULSE_OFF_TIME
PULSE_ON_TIME
ALARM_HP ALARM_MP ALARM_LP
DEVICE_
CONFIG_
RESET
START_
FUNC_
GEN
PMBUS_
MARGIN_
HIGH
PMBUS_
MARGIN_
LOW
NVM_
RELOAD
NVM_
PROG
D3h
DEVICE_UNLOCK_CODE
X
GPI_EN
SW_RESET
21h
25h
26h
01h
78h
98h
X
X
X
DAC_DATA[9:0] (10-Bit) or DAC_DATA[7:0] (8-Bit)
MARGIN_HIGH[9:0] (10-Bit) or MARGIN_HIGH[7:0] (8-Bit)
MARGIN_LOW[9:0] (10-Bit) or MARGIN_LOW[7:0] (8-Bit)
X
X
X
PMBUS_OPERATION_CMD
N/A
N/A
N/A
X
CML
X
PMBUS_VERSION
(1) X = Don't care.
表8-17. Register Names
ADDRESS
D0h
REGISTER NAME
SECTION
节8.6.1
节8.6.2
节8.6.3
节8.6.4
节8.6.5
节8.6.6
节8.6.7
节8.6.8
节8.6.9
节8.6.10
STATUS
GENERAL_CONFIG
CONFIG2
D1h
D2h
D3h
TRIGGER
21h
DAC_DATA
25h
DAC_MARGIN_HIGH
DAC_MARGIN_LOW
PMBUS_OPERATION
PMBUS_STATUS_BYTE
PMBUS_VERSION
26h
01h
78h
98h
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
表8-18. Access Type Codes
Access Type
Code
Description
X
X
Don't care
Read Type
R
R
W
Read
Write Type
W
Write
Reset or Default Value
-n
Value after reset or the default value
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
36
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.6.1 STATUS Register (address = D0h) [reset = 000Ch or 0014h]
图8-7. STATUS Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NVM_CRC_
ALARM_
USER
NVM_CRC_
ALARM_
INTERNAL
NVM_
BUSY
DAC_
UPDATE_
BUSY
X
DEVICE_ID
VERSION_ID
R-0h
R-0h
R-0h
R-0h
X-00h
10-bit: R-3h
8-bit: R-5h
R-0h
表8-19. STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15
NVM_CRC_ALARM_USER
NVM_CRC_ALARM_INTERNAL
NVM_BUSY
R
0
0 : No CRC error in user NVM bits
1: CRC error in user NVM bits
14
13
R
R
0
0
0 : No CRC error in internal NVM
1: CRC error in internal NVM bits
0 : NVM write or load completed, Write to DAC registers
allowed
1 : NVM write or load in progress, Write to DAC register
map not allowed
12
DAC_UPDATE_BUSY
R
0
0 : DAC outputs updated, Write to DAC registers allowed
1 : DAC outputs update in progress, Write to DAC
register map not allowed
11 - 6
5 - 2
X
X
R
00h
Don't care
DEVICE_ID
DAC53701: 3h
DAC43701: 5h
Device identifier:
DAC53701: 3h
DAC43701: 5h
1 - 0
VERSION_ID
R
0h
Silicon version identifier. This field may have a different
value based on the silicon revision.
8.6.2 GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]
图8-8. GENERAL_CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FUNC_
DEVICE_
LOCK
EN_
PMBUS
CODE_STEP
SLEW_RATE
R/W-Fh
DAC_PDN
REF_EN DAC_SPAN
CONFIG
R/ W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-2h
R/W-0h R/W-0h
表8-20. GENERAL_CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15 - 14 FUNC_CONFIG
R/W
00
00: Generates a triangle wave between MARGIN_HIGH (address
25h) code to MARGIN_LOW (address 26h) code with slope
defined by SLEW_RATE and CODE_STEP bits.
01: Generates Saw-Tooth wave between MARGIN_HIGH
(address 25h) code to MARGIN_LOW (address 26h) code, with
rising slope defined by SLEW_RATE and CODE_STEP bits and
immediate falling edge.
10: Generates Saw-Tooth wave between MARGIN_HIGH
(address 25h) code to MARGIN_LOW (address 26h) code, with
falling slope defined by SLEW_RATE and CODE_STEP bits and
immediate rising edge.
11: Generates a square wave between MARGIN_HIGH (address
25h) code to MARGIN_LOW (address 26h) code with pulse high
and low period defined by SLEW_RATE bits.
13
DEVICE_LOCK
R/W
0
0: Device not locked
1: Device locked, the device locks all the registers. This bit can be
overwritten (unlock device) by writing 0101 to the
DEVICE_UNLOCK_CODE bits (address D3h)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
表8-20. GENERAL_CONFIG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
12
EN_PMBUS
R/W
0
0: PMBus mode disabled
1: PMBus mode enabled
11 - 9
CODE_STEP
R/W
000
Code step for programmable slew rate control.
000: Code step size = 1 LSB (default)
001: Code step size = 2 LSB
010: Code step size = 3 LSB
011: Code step size = 4 LSB
100: Code step size = 6 LSB
101: Code step size = 8 LSB
110: Code step size = 16 LSB
111: Code step size = 32 LSB
8 - 5
SLEW_RATE
R/W
1111
Slew rate for programmable slew rate control.
0000: 25.6 µs (per step)
0001: 32 µs (per step)
0010: 38.4 µs (per step)
0011: 44.8 µs (per step)
0100: 204.8 µs (per step)
0101:256 µs (per step)
0110: 307.2 µs (per step)
0111: 819.2 µs (per step)
1000: 1.6384 ms (per step)
1001: 2.4576 ms (per step)
1010: 3.2768 ms (per step)
1011: 4.9152 ms (per step)
1100: 12 µs (per step)
1101: 8 µs (per step)
1110: 4 µs (per step)
1111: No slew (default)
4 - 3
DAC_PDN
R/W
10
00: Power up
01: Power down to 10 kΩ
10: Power down to high impedance (default)
11: Power down to 10 kΩ
2
REF_EN
R/W
R/W
0
0: Internal reference disabled, VDD is DAC reference voltage,
DAC output range from 0 to VDD
1: Internal reference enabled, DAC reference = 1.21 V, DAC
output range is a function of DAC_SPAN.
.
1 - 0
DAC_SPAN
00
Only applicable when internal reference is enabled.
00: Reference to VOUT gain = 1.5x
01: Reference to VOUT gain = 2x
10: Reference to VOUT gain = 3x
11: Reference to VOUT gain = 4x
Copyright © 2023 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.6.3 CONFIG2 Register (address = D2h) [reset = 0000h]
图8-9. CONFIG2 Register
15
14 13 12 11
10
9
8
7
6
5
4
3
2
1
0
SLAVE_
ADDRESS
GPI_
CONFIG
MED_
ALARM_
HP
MED_
ALARM_
MP
MED_
ALARM_
LP
RESERVED
MED_ALARM_
DEAD_TIME
PULSE_
OFF_TIME
PULSE_
ON_TIME
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
RESERVED
R/W-0h
R/W-0h
R/W-0h
表8-21. CONFIG2 Register Field Descriptions
Bit
Field
Type
R/W
R/W
R/W
Reset
Description
15 - 14 SLAVE_ADDRESS
0h
AD1-AD0 of device address as per 表8-13
Refer to 表8-1 for the GPI configuration
13-11
10
GPI_CONFIG
0h
MED_ALARM_HP
0
0: No medical alarm waveform generated
1: High priority medical alarm waveform generated
9
8
MED_ALARM_MP
MED_ALARM_LP
R/W
R/W
0
0
0: No medical alarm waveform generated
1: Medium priority medical alarm waveform generated
0: No medical alarm waveform generated
1: Low priority medical alarm waveform generated
7 - 6
5 - 4
RESERVED
Reserved 0
RESERVED
INTERBURST_TIME
R/W
R/W
R/W
00
High priority alarm
00: 2.55 s
01: 2.96 s
10: 3.38 s
11: 3.80 s
Medium priority
alarm
00: 2.60 s
01: 3.06 s
10: 3.52 s
11: 4.00 s
Low priority alarm
00: 16 s
01: 16 s
10: 16 s
11: 16 s
3 - 2
PULSE_OFF_TIME
PULSE_ON_TIME
00
00
High priority alarm
00: 15 ms
01: 36 ms
10: 58 ms
11: 80 ms
Medium priority
alarm
00: 40 ms
01: 60 ms
10: 80 ms
11: 100 ms
Low priority alarm
00: 40 ms
01: 60 ms
10: 80 ms
11: 100 ms
1 - 0
High priority alarm
00: 80 ms
Medium priority
alarm
Low priority alarm
00: 130 ms
01: 103 ms
10: 126 ms
11: 150 ms
00: 130 ms
01: 153 ms
10: 176 ms
11: 200 ms
01: 153 ms
10: 176 ms
11: 200 ms
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.6.4 TRIGGER Register (address = D3h) [reset = 0008h]
图8-10. TRIGGER Register
15
14
13
12
11
X
10
9
8
7
6
5
4
3
2
1
0
DEVICE_UNLOCK_CODE
GPI_
EN
DEVICE_ START_
CONFIG_
RESET
PMBUS_
PMBUS_
NVM_
NVM_
SW_RESET
FUNC_
GEN
MARGIN_ MARGIN_ RELOAD PROG
HIGH
LOW
W-0h
X-0h R/W-0h
W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h R/W-0h
W-8h
表8-22. TRIGGER Register Field Descriptions
Bit
Field
Type
Reset
0000
0h
Description
15 - 12 DEVICE_UNLOCK_CODE
W
Write 0101 to unlock the device to bypass DEVICE_LOCK bit.
Don't care
11
10
X
X
GPI_EN
R/W
0
0: GPI disabled
1: GPI enabled
9
8
DEVICE_CONFIG_RESET
START_FUNC_GEN
W
0
0
0: Device configuration reset not initiated
1: Device configuration reset initiated. All registers loaded with
factory reset values.
R/W
0: Continuous waveform generation mode disabled
1: Continuous waveform generation mode enabled, device
generates continuous waveform based on FUNC_CONFIG
(address D1h), MARGIN_LOW (address 26h), MARGIN_HIGH
(address 25h), and SLEW_RATE and CODE_STEP (address
D1h) bits.
7
6
5
4
PMBUS_MARGIN_HIGH
PMBUS_MARGIN_LOW
NVM_RELOAD
R/W
R/W
R/W
R/W
0
0
0
0
0: PMBus margin high command not initiated
1: PMBus margin high command initiated, DAC output margins
high to MARGIN_HIGH code (address 25h). This bit automatically
resets to 0 after the DAC code reaches MARGIN_HIGH value.
0: PMBus margin low command not initiated
1: PMBus margin low command initiated, DAC output margins
low to MARGIN_LOW code (address 26h). This bit automatically
resets to 0 after the DAC code reaches MARGIN_LOW value.
0: NVM reload not initiated
1: NVM reload initiated, applicable DAC registers loaded with
corresponding NVM. NVM_BUSY bit set to 1 which this operation
is in progress.. This bit is self-resetting.
NVM_PROG
0: NVM write not initiated
1: NVM write initiated, NVM corresponding to applicable DAC
registers loaded with existing register settings. NVM_BUSY bit
set to 1 which this operation is in progress. This bit is self-
resetting.
3 - 0
SW_RESET
W
1000
1000: Software reset not initiated
1010: Software reset initiated, DAC registers loaded with
corresponding NVMs, all other registers loaded with default
settings.
Copyright © 2023 Texas Instruments Incorporated
40
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.6.5 DAC_DATA Register (address = 21h) [reset = 0000h]
图8-11. DAC_DATA Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
DAC_DATA[9:0] / DAC_DATA[7:0] –MSB Left aligned
X-0h
R/W-000h
X-0h
表8-23. DAC_DATA Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11-2
X
X
0h
Don't care
DAC_DATA[9:0] / DAC_DATA[7:0]
R/W
000h
Writing to the DAC_DATA register forces the respective DAC
channel to update the active register data to the DAC_DATA.
Data are in straight binary format and use the following format:
DACx3701: { DATA[9:0] }
DACx3701: { DATA[7:0], X, X }
X = Don’t care bits
1-0
X
X
0h
Don't care
8.6.6 DAC_MARGIN_HIGH Register (address = 25h) [reset = 0000h]
图8-12. DAC_MARGIN_HIGH Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
MARGIN_HIGH[9:0] / MARGIN_HIGH[7:0] –MSB Left aligned
X-0h
R/W-000h
X-0h
表8-24. DAC_MARGIN_HIGH Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11-2
X
X
0h
Don't care
MARGIN_HIGH[9:0] /
MARGIN_HIGH[7:0] –MSB Left
aligned
R/W
000h
Margin high code for DAC output.
Data are in straight binary format and use the following format:
DACx3701: { MARGIN_HIGH[[9:0] }
DACx3701: { MARGIN_HIGH[[7:0], X, X }
X = Don’t care bits
1-0
X
X
0h
Don't care
8.6.7 DAC_MARGIN_LOW Register (address = 26h) [reset = 0000h]
图8-13. DAC_MARGIN_LOW Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
MARGIN_LOW[9:0] / MARGIN_LOW[7:0] –MSB Left aligned
X-0h
R/W-000h
X-0h
表8-25. DAC_MARGIN_LOW Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11-2
X
X
0h
Don't care
MARGIN_LOW[9:0] /
MARGIN_LOW[7:0] –MSB Left
aligned
R/W
000h
Margin low code for DAC output.
Data are in straight binary format and follows the format below:
DACx3701: { MARGIN_LOW[[9:0] }
DACx3701: { MARGIN_LOW[[7:0], X, X }
X = Don’t care bits
1-0
X
X
0h
Don't care
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
8.6.8 PMBUS_OPERATION Register (address = 01h) [reset = 0000h]
图8-14. PMBUS_OPERATION Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PMBUS_OPERATION_CMD
R/ W-00h
X
X-00h
表8-26. PMBUS_OPERATION Register Field Descriptions
Bit
15 - 8
Field
Type
Reset
Description
PMBUS_OPERATION_CMD
R/W
00h
PMBus operation commands
00h: Turn off
80h: Turn on
A4h: Margin high, DAC output margins high to MARGIN_HIGH
code (address 25h)
94h: Margin low, DAC output margins low to MARGIN_LOW code
(address 26h)
7 - 0
X
X
00h
Not applicable
8.6.9 PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]
图8-15. PMBUS_STATUS_BYTE Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
CML
X
N/A
X-00h
R/W-0h
X-0h
X-00h
表8-27. PMBUS_STATUS_BYTE Register Field Descriptions
Bit
Field
Type
Reset
00h
0
Description
15 - 10
9
X
X
Don't care
CML
R/W
0: No communication Fault
1: PMBus communication fault for write with incorrect number of
clocks, read before write command, invalid command address,
and invalid or unsupported data value; reset this bit by writing 1.
8
X
X
X
X
0h
Don't care
7 - 0
00h
Not applicable
8.6.10 PMBUS_VERSION Register (address = 98h) [reset = 2200h]
图8-16. PMBUS_VERSION Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PMBUS_VERSION
R-22h
X
X-00h
表8-28. PMBUS_VERSION Register Field Descriptions
Bit
Field
Type
Reset
Description
15 - 8
7 - 0
PMBUS_VERSION
X
R
22h
PMBus version
Not applicable
X
00h
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
42
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
9.1 Application Information
The DACx3701 are buffered, force-sense output, single-channel, DACs that include an NVM and internal
reference and are available in a tiny 2-mm × 2-mm package . These DACs are designed for general-purpose
applications in a wide range of end equipment. Some of the most common applications for these devices are
power-supply margining and control, adaptive voltage scaling (AVS), set-and-forget LED biasing in mobile
projectors, general-purpose function generation, medical alarm generation, and programmable comparator
applications (such as smoke detectors, standalone PWM control loops, and offset and gain trimming in precision
circuits).
9.2 Typical Applications
This section explains the design details of three primary applications of DACx3701: programmable LED biasing,
power-supply margining. and medical alarm generation.
9.2.1 Appliance Light Fade-In Fade-Out
Appliances such as toaster ovens, microwave ovens, refrigerators, cloth dryers, and more implement door lights
for monitoring the status of the function. These door lights dim and brighten when the door closes and opens,
respectively. Appliance manufacturers prefer to provide a smooth-dimming transition for a better user
experience. However, a microcontroller is required for such an operation, and implementing a separate
microcontroller and associated software is a big overhead. For this reason, only high-end appliances have such
features. The DACx3701 provides a simpler way to control the slew of such lights without software. 图9-1 shows
the simplified circuit diagram of light fade-in fade-out using MOSFET based control and 图 9-2 shows the circuit
with an external LED driver. For high-power LEDs, external LED drivers with headroom control are preferred
over MOSFET-based LED control.
图9-1. Appliance Light Fade-In Fade-Out
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
VCC
VDD
VDD
Bright
Dim
Dim
ON
LED
Driver
RP
LADDER
+
OUT
OFF
OFF
GPI
ICTRL
OUT
œ
Mechanical Switch
Coupled to
Appliance Door
FB
DAC53701
LEDs
图9-2. Fade-In Fade-Out with Switching LED Driver
9.2.1.1 Design Requirements
• Slew time: approximately, 1.5 s
• Bright LED current: 20 mA
• Dim LED current: 10 mA
9.2.1.2 Detailed Design Procedure
Choose a small VSET so that the power dissipation across RSET is minimum. Choose 1 V for the bright condition,
which results in an RSET of (1 V / 20 mA) = 50 Ω. Set the DACx3701 output span to 1.8 V. The output buffer of
the DAC is connected in a force-sense configuration to the MOSFET, as shown in 图9-1. This configuration
compensates the gate-source voltage drop caused by temperature, drain current, and ageing of the MOSFET.
Considering a typical gate-source voltage of 1.2 V and a power supply headroom of 200 mV, the VDD for the
DAC must be a minimum of (1 V + 1.2 V + 200 mV) = 2.4 V. Use a standard 3.3-V or 5-V power supply for the
DAC. A bipolar junction transistor (BJT) provides a much smaller base-emitter voltage drop, but a MOSFET has
better matching between the drain and source currents. Choose a BJT over the MOSFET in case there is a less
than 2.4-V supply voltage available for the DAC. Configure the MARGIN HIGH value to the code equivalent of 1
V; that is (1 V / 1.8 V) × 1024 = 569d or 0x239. The MARGIN LOW value should be the equivalent of the dim
LED current that is 10 mA, which corresponds to a DAC voltage of (10 mA × 50 Ω) = 500 mV. The code for
MARGN LOW is (500 mV / 1.8 V) × 1024 = 284d or 0x11C.
For control without the use of software, map the GPI to margin high-low operation as listed in 表 8-1. The rising
edge of the GPI maps to the MARGIN HIGH value of the 20-mA LED current, and the falling edge maps to the
MARGIN LOW value of the 10-mA LED current. When the DAC output is in the slewing condition, any change in
the GPI state changes the direction of the slew after the ongoing SLEW_RATE time, as shown in the Application
Curves section.
The slew time is given by (MARGIN_HIGH – MARGIN_LOW) × CODE_STEP × SLEW_RATE. For a 1.5-s slew
time, CODE_STEP × SLEW_RATE = 1.5 / (569 – 284) = ~ 5 ms. Choose the CODE_STEP as 1 LSB and
SLEW_RATE of 4.9152 ms. This configuration provides a slew time of 1.4 s. Adjust the MARGIN HIGH and
MARGIN LOW values for more granular control.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
44
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
The following pseudocode helps to get started with a light fade-in fade-out application:
//SYNTAX: WRITE <REGISTER NAME (Hex code)>, <MSB DATA>, <LSB DATA>
//Write MARGIN-HIGH code (12-bit aligned) for bright LED light
//For a 1.8-V output range, the 10-bit hex code for 1 V is 0x0239.
//With 12-bit alignment, it becomes 0x08E4
WRITE DAC_MARGIN_HIGH(0x25), 0x08, 0xE4
//Write MARGIN-LOW code (12-bit aligned) for dim LED light
//For a 1.8-V output range, the 10-bit hex code for 500 mV is 0x11C.
//With 12-bit alignment, it becomes 0x0470
WRITE DAC_MARGIN_LOW(0x26), 0x04, 0x70
//Map GPI to margin high-low function
WRITE CONFIG2(0xD2), 0x10, 0x00
//Enable GPI
WRITE TRIGGER(0xD3), 0x04, 0x08
//Configure internal reference with 1.5x output span, and slew time and power-up the device
//CODE_STEP: 1 LSB, SLEW_RATE: 4.9152 ms
WRITE GENERAL_CONFIG(0xD1), 0x01, 0x64
//Program the EEPROM
WRITE TRIGGER(0xD3), 0x04, 0x18
9.2.1.3 Application Curves
图9-3. Light Fade-In-Fade-Out With GPI
9.2.2 Power-Supply Margining
A power-supply margining or scaling circuit is used to test and trim the output of a power converter. This
example circuit is used to test a system by margining the power supplies, for adaptive voltage scaling, or to
program a desired value at the output. Adjustable power supplies, such as LDOs and DC/DC converters provide
a feedback or adjust input that is used to set the desired output. A precision voltage-output DAC is the best
choice for controlling the power-supply output linearly. 图 9-4 shows a control circuit for a switch-mode power
supply (SMPS) using the DACx3701. Typical applications of power-supply margining are communications
equipment, enterprise servers, test and measurement, and general-purpose power-supply modules.
图9-4. Power-Supply Margining
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
9.2.2.1 Design Requirements
• Power-supply nominal output: 3.3 V
• Reference voltage of the converter (VFB): 0.6 V
• Margin: ±10% (that is, 2.97 V to 3.63 V)
• DAC output range: 1.8 V
• Nominal current through R1 and R2: 100 µA
9.2.2.2 Detailed Design Procedure
The DACx3701 features a Hi-Z power-down mode that is set by default at power-up, unless the device is
programmed otherwise using the NVM. When the DAC output is at Hi-Z, the current through R3 is zero and the
SMPS is set at the nominal output voltage of 3.3 V. To have the same nominal condition when the DAC powers
up, bring up the device at the same output as VFB (that is 0.6 V). This configuration makes sure there is no
current through R3 even at power-up. Calculate R1 as (VOUT –VFB) / 100 µA = 27 kΩ.
To achieve ±10% margin-high and margin-low conditions, the DAC must sink or source additional current
through R1. Calculate the current from the DAC (IMARGIN) using 方程式6 as 12 µA.
≈
∆
«
’
÷
◊
VOUT ì(1+ MARGIN) - VFB
R1
IMARGIN
=
-I
NOMINAL
(6)
where
• IMARGIN is the margin current sourced or sinked from the DAC.
• MARGIN is the percentage margin value divided by 100.
• INOMINAL is the nominal current through R1 and R2.
To calculate the value of R3, first decide the DAC output range, and make sure to avoid the codes near zero-
scale and full-scale for safe operation in the linear region. A DAC output of 20 mV is a safe consideration as the
minimum output, and (1.8 V – 0.6 V –20 mV = 1.18 V) as the maximum output. When the DAC output is at 20
mV, the power supply goes to margin high, and when the DAC output is at 1.18 V, the power supply goes to
margin low. Calculate the value of R3 using 方程式 7 as 48.3 kΩ. Choose a standard resistor value and adjust
the DAC outputs. Choosing R3 = 47 kΩ makes the DAC margin high code as 1.164 V and the DAC margin low
code as 36 mV.
VDAC - VFB
R3 =
IMARGIN
(7)
The DACx3701 have a slew rate feature that is used to toggle between margin high, margin low, and nominal
outputs with a defined slew rate. See the 节8.6.2 for the slew rate setting details.
备注
The MARGIN HIGH register value in DACx3701 results in the MARGIN LOW value at the power
supply output. Similarly, the MARGIN LOW register value in DACx3701 results in the MARGIN HIGH
value at the power-supply output.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
46
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
The pseudocode for getting started with a power-supply control application is as follows:
//SYNTAX: WRITE <REGISTER NAME (Hex code)>, <MSB DATA>, <LSB DATA>
//Write DAC code (12-bit aligned) for nominal output
//For a 1.8-V output range, the 10-bit hex code for 0.6 V is 0x0155. With 12-bit alignment, it
becomes 0x0554
WRITE DAC_DATA(0x21), 0x05, 0x54
//Write DAC code (12-bit aligned) for margin-low output at the power supply
//For a 1.8-V output range, the 10-bit hex code for 1.164 V is 0x0296. With 12-bit alignment, it
becomes 0x0A58
WRITE DAC_MARGIN_HIGH(0x25), 0x0A, 0x58
//Write DAC code (12-bit aligned) for margin-high output at the power supply
//For a 1.8-V output range, the 10-bit hex code for 36 mV is 0x14. With 12-bit alignment, it
becomes 0x50
WRITE DAC_MARGIN_LOW(0x26), 0x00, 0x50
//Power-up the device with enable internal reference with 1.5x output span. This will output the
nominal voltage (0.6 V)
//CODE_STEP: 2 LSB, SLEW_RATE: 25.6 µs
WRITE GENERAL_CONFIG(0xD1), 0x12, 0x14
//Trigger margin-low output at the power supply
WRITE TRIGGER(0xD3), 0x00, 0x80
//Trigger margin-high output at the power supply
WRITE TRIGGER(0xD3), 0x00, 0x40
//Write back DAC code (12-bit aligned) for nominal output
WRITE DAC_DATA(0x21), 0x05, 0x54
9.2.2.3 Application Curves
图9-5. Power-Supply Margin High
图9-6. Power Supply Margin Low
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
47
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
9.2.3 Medical Alarm Generation
All medical devices implementing an alarm system shall comply to IEC60601-1-8 standard for medical alarms,
as per IEC60601-1 Ed 3.1. The regulatory tests are done at a system level; therefore, system level acoustics
play a major role in compliance. A medical alarm is a common functional block in many medical devices. A
portable implementation is needed that can also be customized to fit mechanical and audio or acoustic
requirements. The DACx3701-based design is aimed at providing a programmable, standalone, and robust
implementation.
There are three types of alarms with different timing requirements: low priority, medium priority, and high priority.
Usually, for easy identification, different timings are employed for different equipment. Medical device
manufacturers prefer using their signature melodies within the limits of the standard.
图9-7. Medical Alarm
9.2.3.1 Design Requirements
• Alarm envelope rise and fall time: 26 ms
• Alarm pulse frequency: 610 Hz
9.2.3.2 Detailed Design Procedure
For the auditory alarm implementation, two DAC53701 devices are required: one device to generate the pulse
envelope and the burst, and the second device to generate the pulse frequency, as shown in 图 9-7. The signals
coming from both DACs are combined together using amplifier OP1 that has a shutdown pin, for example, the
TLV9002S or OPA363. The combined signal is then ac-coupled to an audio amplifier, such as the TPA6211A1, to
drive the speaker. The TPA6211A1 is an integrated Class-AB amplifier that can drive up to 3 W of output power
with very little distortion. As per medical alarm standard IEC60601-1-8, the pulse frequency must be greater than
150 Hz, and must have at least four harmonic components that are within ±15 dB of each other. As a result of
the square-wave pulse frequency and the mixing done by OP1, the speaker output generates multiple harmonics
of the fundamental pulse frequency. The DACx3701 provide a range of timing options for the pulse frequency
and envelope, and various options to program the pulse frequency and envelope timings. See 节 8.4.4 for the
alarm configuration options. Calculate the frequency of a square wave or pulse frequency using 方程式 3. The
square-wave function has a limited number of frequencies because this function is programmed by the
SLEW_RATE bit alone. To get a higher number of frequencies, generate a triangular waveform with comparator
mode output. Generate the triangular waveform using 方程式 4. Set the DAC output in the comparator mode by
fixing the FB pin to the midscale of the DAC using a resistive voltage divider from VDD. Select VDD as the
reference in this case using the GENERAL_CONFIG register (see 节8.6.2).
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
48
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
The following pseudocode helps to get started with a medical alarm application using two DACs:
//SYNTAX: WRITE <REGISTER NAME (Hex code)>, <MSB DATA>, <LSB DATA>
//Power-up the first DAC, enable VDD reference
//SLEW_RATE: 1.6384 ms (Square wave frequency: 610 Hz)
WRITE GENERAL_CONFIG(0xD1), 0xD1, 0x58
//Set MARGIN_HIGH on the first DAC
WRITE DAC_MARGIN_HIGH(0x25), 0x0F, 0xFC
//Set MARGIN_LOW on the first DAC
WRITE DAC_MARGIN_LOW(0x26), 0x00, 0x00
//Trigger square wave generation on the first DAC
WRITE TRIGGER(0xD3), 0x01, 0x00
//Power-up the second DAC, enable VDD reference
//CODE_STEP: 8 LSB, SLEW_RATE: 204.8 µs x 1.75 = 358.4 µs (Envelope rise/fall times for full-scale:
~26 ms)
WRITE GENERAL_CONFIG(0xD1), 0x1A, 0xE8
//OPTION-1: Configure the second DAC for low-priority alarm with minimum time settings and trigger
WRITE CONFIG2(0xD2), 0x01, 0x00
//OPTION-2: Configure the second DAC for medium-priority alarm with minimum time settings and
trigger
WRITE CONFIG2(0xD2), 0x02, 0x00
//OPTION-3: Configure the second DAC for high-priority alarm with minimum time settings and trigger
WRITE CONFIG2(0xD2), 0x04, 0x00
//Set MARGIN_HIGH on the second DAC
WRITE DAC_MARGIN_HIGH(0x25), 0x0F, 0xFC
//Set MARGIN_LOW on the second DAC
WRITE DAC_MARGIN_LOW(0x26), 0x00, 0x00
9.2.3.3 Application Curves
图9-8. Low Priority Alarm
图9-9. Medium Priority Alarm
图9-10. High-Priority Alarm
图9-11. Pulse Frequency
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
49
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
10 Power Supply Recommendations
The DACx3701 family of devices does not require specific supply sequencing. These devices require a single
power supply, VDD. Use a 0.1-µF decoupling capacitor for the VDD pin. Use a bypass capacitor with a value
approximately 1.5 µF for the CAP pin.
11 Layout
11.1 Layout Guidelines
The DACx3701 pin configuration separates the analog, digital, and power pins for an optimized layout. For
signal integrity, separate the digital and analog traces, and place decoupling capacitors close to the device pins.
11.2 Layout Example
图11-1 shows an example layout drawing with decoupling capacitors and pullup resistors.
图11-1. Layout Example
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEY5
50
Submit Document Feedback
Product Folder Links: DAC53701 DAC43701
DAC53701, DAC43701
ZHCSM38 –DECEMBER 2020
www.ti.com.cn
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Texas, Instruments DAC53701EVM user's guide
12.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
12.4 Trademarks
PMBus™ is a trademark of SMIF, Inc.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
51
Product Folder Links: DAC53701 DAC43701
English Data Sheet: SLASEY5
PACKAGE OPTION ADDENDUM
www.ti.com
19-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC43701DSGR
DAC43701DSGT
DAC53701DSGR
DAC53701DSGT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
8
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
4371
4371
5371
5371
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Aug-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC43701, DAC53701 :
Automotive : DAC43701-Q1, DAC53701-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023,德州仪器 (TI) 公司
相关型号:
©2020 ICPDF网 联系我们和版权申明