CSD88537NDT [TI]
CSD88537ND, Dual 60 V N-Channel NexFET Power MOSFETs; CSD88537ND ,双路60V的N通道NexFET功率MOSFET型号: | CSD88537NDT |
厂家: | TEXAS INSTRUMENTS |
描述: | CSD88537ND, Dual 60 V N-Channel NexFET Power MOSFETs |
文件: | 总13页 (文件大小:1006K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CSD88537ND
www.ti.com
SLPS455 –JANUARY 2014
CSD88537ND, Dual 60 V N-Channel NexFET™ Power MOSFETs
Check for Samples: CSD88537ND
PRODUCT SUMMARY
1
FEATURES
TA = 25°C
TYPICAL VALUE
UNIT
V
2
•
•
•
•
•
Ultra-Low Qg and Qgd
Avalanche Rated
Pb Free
VDS
Qg
Drain-to-Source Voltage
60
14
Gate Charge Total (10 V)
Gate Charge Gate to Drain
nC
nC
mΩ
mΩ
V
Qgd
2.3
VGS = 6 V
VGS = 10 V
3.0
15.0
12.5
RoHS Compliant
Halogen Free
RDS(on) Drain-to-Source On Resistance
VGS(th) Threshold Voltage
APPLICATIONS
ORDERING INFORMATION
•
•
Half Bridge for Motor Control
Synchronous Buck Converter
Device
Qty
2500
250
Media
Package
Ship
CSD88537ND
CSD88537NDT
13-Inch Reel
7-Inch Reel
SO-8 Plastic
Package
Tape and
Reel
DESCRIPTION
This dual SO-8, 60 V, 12.5 mΩ NexFET™ power
MOSFET is designed to serve as a half bridge in low
current motor control applications.
ABSOLUTE MAXIMUM RATINGS
TA = 25°C
VALUE
UNIT
V
VDS
VGS
Drain to Source Voltage
60
±20
15
Gate to Source Voltage
V
Top View
Continuous Drain Current (Package limited)
Continuous Drain Current (Silicon limited),
TC = 25°C
Continuous Drain Current (1)
Pulsed Drain Current, TA = 25°C(2)
Power Dissipation(1)
ID
16
A
1
8
S1
D1
8.0
62
IDM
PD
TJ,
A
2
3
7
6
G1
S2
D1
D2
2.1
W
Operating Junction and
TSTG Storage Temperature Range
–55 to 150
51
°C
Avalanche Energy, single pulse
EAS
mJ
ID = 32, L = 0.1 mH, RG = 25 Ω
4
5
G2
D2
(1) Typical RθJA = 60°C/W on a 1-inch2, 2-oz. Cu pad on a 0.06-
inch thick FR4 PCB.
(2) Pulse duration ≤ 300 μs, duty cycle ≤ 2%
.
.
RDS(on) vs VGS
GATE CHARGE
30
27
24
21
18
15
12
9
10
TC = 25°C,I D = 8A
TC = 125°C,I D = 8A
ID = 8A
VDS = 30V
9
8
7
6
5
4
3
2
1
0
6
3
0
0
2
4
6
8
10
12
14
16
18
20
0
3
6
9
12
15
Qg - Gate Charge (nC)
VGS - Gate-to- Source Voltage (V)
G001
G001
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2014, Texas Instruments Incorporated
CSD88537ND
SLPS455 –JANUARY 2014
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
Static Characteristics
TEST CONDITIONS
MIN
TYP
MAX UNIT
BVDSS
IDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 250 μA
60
V
Drain-to-Source Leakage Current
Gate-to-Source Leakage Current
Gate-to-Source Threshold Voltage
VGS = 0 V, VDS = 48 V
VDS = 0 V, VGS = 20 V
VDS = VGS, ID = 250 μA
VGS = 6 V, ID = 8 A
1
100
3.6
μA
nA
V
IGSS
VGS(th)
2.6
3.0
15.0
12.5
42
19.0
15.0
mΩ
mΩ
S
RDS(on)
Drain-to-Source On Resistance
VGS = 10 V, ID = 8 A
VDS = 30 V, ID = 8 A
gfs
Transconductance
Dynamic Characteristics
Ciss
Coss
Crss
RG
Input Capacitance
1080
133
4.0
5.5
14
1400
173
5.2
pF
pF
pF
Ω
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Gate Charge Total (10 V)
Gate Charge Gate to Drain
Gate Charge Gate to Source
Gate Charge at Vth
Output Charge
VGS = 0 V, VDS = 30 V, f = 1 MHz
11.0
18
Qg
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
2.3
4.6
3.4
25
VDS = 30 V, ID = 8 A
VDS = 30 V, VGS = 0 V
Turn On Delay Time
Rise Time
6
15
VDS = 30 V, VGS = 10 V, IDS = 8 A, RG = 0 Ω
td(off)
tf
Turn Off Delay Time
Fall Time
5
19
Diode Characteristics
VSD
Qrr
trr
Diode Forward Voltage
ISD = 8 A, VGS = 0 V
0.8
50
30
1
V
Reverse Recovery Charge
Reverse Recovery Time
nC
ns
VDS= 30 V, IF = 8 A, di/dt = 300 A/μs
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
Thermal Resistance Junction to Lead(1)
Thermal Resistance Junction to Ambient(1)(2)
MIN
TYP
MAX
UNIT
°C/W
°C/W
RθJL
RθJA
20
75
(1)
R
θJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
2
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Product Folder Links: CSD88537ND
CSD88537ND
www.ti.com
SLPS455 –JANUARY 2014
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
VDS = 5V
VGS =10V
VGS =8V
VGS =6V
TC = 125°C
TC = 25°C
TC = −55°C
0
0
0
0.3
0.6
0.9
1.2
1.5
0
1
2
3
4
5
6
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
G001
G001
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
Copyright © 2014, Texas Instruments Incorporated
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3
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SLPS455 –JANUARY 2014
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TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
10
9
8
7
6
5
4
3
2
1
0
100000
10000
1000
100
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
ID = 8A
VDS = 30V
10
1
0
3
6
9
12
15
0
6
12
18
24
30
36
42
48
54
60
Qg - Gate Charge (nC)
VDS - Drain-to-Source Voltage (V)
G001
G001
Figure 4. Gate Charge
Figure 5. Capacitance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
3.6
3.4
3.2
3
30
27
24
21
18
15
12
9
ID = 250uA
TC = 25°C,I D = 8A
TC = 125°C,I D = 8A
2.8
2.6
2.4
2.2
2
6
3
0
−75
−25
25
75
125
175
0
2
4
6
8
10
12
14
16
18
20
TC - Case Temperature (ºC)
VGS - Gate-to- Source Voltage (V)
G001
G001
Figure 6. Threshold Voltage vs Temperature
TEXT ADDED FOR SPACING
Figure 7. On-State Resistance vs Gate-to-Source Voltage
TEXT ADDED FOR SPACING
2.2
2
100
VGS = 6V
VGS = 10V
TC = 25°C
TC = 125°C
10
1.8
1.6
1.4
1.2
1
1
0.1
0.01
0.8
0.6
0.4
0.001
0.0001
ID = 8A
175
−75
−25
25
75
125
0
0.2
0.4
0.6
0.8
1
TC - Case Temperature (ºC)
VSD − Source-to-Drain Voltage (V)
G001
G001
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
4
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Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: CSD88537ND
CSD88537ND
www.ti.com
SLPS455 –JANUARY 2014
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1000
100
10
100
TC = 25ºC
TC = 125ºC
10us
1ms
DC
100us
10ms
1
Single Pulse
Max RthetaJL = 20ºC/W
0.1
0.1
10
0.01
1
10
100
0.1
1
VDS - Drain-to-Source Voltage (V)
TAV - Time in Avalanche (mS)
G001
G001
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
21
18
15
12
9
6
3
0
−50 −25
0
25
50
75
100 125 150 175
TC - Case Temperature (ºC)
G001
Figure 12. Maximum Drain Current vs Temperature
Copyright © 2014, Texas Instruments Incorporated
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CSD88537ND
SLPS455 –JANUARY 2014
www.ti.com
MECHANICAL DATA
SO-8 Package Dimensions
1. All linear dimensions are in inches (millimeters).
2. This drawing is subject to change without notice.
3. Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs
shall not exceed 0.006 (0.15) each side.
4. Body width does not include interlead flash. Interlead flash shall not exceed 0.017 (0.43) each side.
5. Reference JEDEC MS-012 variation AA.
6
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Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: CSD88537ND
CSD88537ND
www.ti.com
SLPS455 –JANUARY 2014
Recommended PCB Pattern and Stencil Opening
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.
3. Publication IPC-7351 is recommended for alternate designs.
4. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release.
Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525
for other stencil recommendations.
5. Customers should contact their board fabrication site for solder mask tolerances between and around signal
pads.
Copyright © 2014, Texas Instruments Incorporated
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Product Folder Links: CSD88537ND
PACKAGE OPTION ADDENDUM
www.ti.com
14-Feb-2014
PACKAGING INFORMATION
Orderable Device
CSD88537ND
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
D
8
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CSD88537NDT
PREVIEW
D
250
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Feb-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD88537ND
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 41.3
CSD88537ND
D
8
2500
Pack Materials-Page 2
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