CSD17575Q3T [TI]
采用 3mm x 3mm SON 封装的单路、3.2mΩ、30V、N 沟道 NexFET™ 功率 MOSFET | DQG | 8 | -55 to 150;
| 型号： | CSD17575Q3T |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 3mm x 3mm SON 封装的单路、3.2mΩ、30V、N 沟道 NexFET™ 功率 MOSFET | DQG | 8 | -55 to 150 局域网 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总16页 (文件大小：782K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CSD17575Q3
ZHCSCP7A –JUNE 2014–REVISED AUGUST 2014
CSD17575Q3 30V N 通道 NexFET™ 功率金属氧化物半导体场效应晶体管
(MOSFET)
1 特性
产品概要
1
•
•
•
•
•
•
•
•
低 Qg 和 Qgd
低 RDS(on)
低热阻
TA = 25°C
VDS
典型值
30
单位
V
漏源电压
Qg
栅极电荷总量 (4.5V)
栅漏栅极电荷
23
nC
nC
雪崩级
Qgd
5.4
VGS = 4.5 V
VGS = 10V
2.6
1.9
无铅端子镀层
符合 RoHS 标准
无卤素
RDS(on)
Vth
漏源导通电阻
阀值电压
mΩ
1.4
V
小外形尺寸无引线 (SON) 3.3mm × 3.3mm 塑料封
装
。
订购信息(1)
数量
器件
介质
封装
出货
卷带封装
2 应用
CSD17575Q3
CSD17575Q3T
13 英寸卷带
13 英寸卷带
2500
250
SON 3.3mm x
3.3mm
塑料封装
•
用于网络互联，电信和计算系统的负载点同步降压
转换器
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
•
已针对同步场效应晶体管 (FET) 应用进行优化
最大绝对额定值
3 说明
TA = 25°C
值
30
单位
V
VDS
VGS
漏源电压
这款 1.9mΩ，30V，SON 3×3 NexFET™ 功率
MOSFET 被设计成在功率转换应用中最大限度地降低
功率损耗。
栅源电压
±20
60
V
持续漏极电流（受封装限制）
持续漏极电流（受芯片限制），
TC = 25°C 时测得
持续漏极电流(1)
脉冲漏极电流(2)
功率耗散(1)
ID
182
A
顶视图
27
240
2.8
IDM
PD
A
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
W
功率耗散，TC = 25°C
108
TJ， 运行结温和
Tstg
-55 至 150
°C
储存温度范围
雪崩能量，单脉冲
ID = 48，L = 0.1mH，RG = 25Ω
EAS
115
mJ
D
D
(1) RθJA = 45°C/W，这是在一块厚度为 0.060 英寸的 FR4 印刷电
路板 (PCB) 上的 1 平方英寸 2 盎司铜过渡垫片上测得的典型
值。
P0095-01
(2) 最大 RθJC = 1.5°C/W，脉冲持续时间 ≤ 100μs，占空比 ≤ 1%
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLPS489
CSD17575Q3
ZHCSCP7A –JUNE 2014–REVISED AUGUST 2014
www.ti.com.cn
RDS(on) 与 VGS 间的关系
栅极电荷
8
10
9
8
7
6
5
4
3
2
1
0
TC = 25°C,I D = 25A
TC = 125°C,I D = 25A
7
6
5
4
3
2
1
0
0
2
4
6
8
10
12
14
16
18
20
0
5
10 15 20 25 30 35 40 45 50 55
Qg - Gate Charge (nC)
VGS - Gate-to- Source Voltage (V)
G001
G001
2
版权 © 2014, Texas Instruments Incorporated
CSD17575Q3
www.ti.com.cn
ZHCSCP7A –JUNE 2014–REVISED AUGUST 2014
目录
1
2
3
4
5
特性.......................................................................... 1
6
7
器件和文档支持........................................................ 8
6.1 Trademarks............................................................... 8
6.2 Electrostatic Discharge Caution................................ 8
6.3 术语表 ....................................................................... 8
机械封装和可订购信息............................................. 9
7.1 Q3 封装尺寸.............................................................. 9
7.2 建议 PCB 布局 ........................................................ 10
7.3 建议模板开口........................................................... 10
7.4 Q3 卷带信息............................................................ 11
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 3
Specifications......................................................... 4
5.1 Electrical Characteristics........................................... 4
5.2 Thermal Information.................................................. 4
5.3 Typical MOSFET Characteristics.............................. 5
4 修订历史记录
Changes from Original (June 2014) to Revision A
Page
•
在机械信息表中增加了 b1、d、d1 和 K 尺寸 ......................................................................................................................... 9
Copyright © 2014, Texas Instruments Incorporated
3
CSD17575Q3
ZHCSCP7A –JUNE 2014–REVISED AUGUST 2014
www.ti.com.cn
5 Specifications
5.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 250 μA
30
V
μA
nA
V
Drain-to-Source Leakage Current
Gate-to-Source Leakage Current
Gate-to-Source Threshold Voltage
VGS = 0 V, VDS = 24 V
VDS = 0 V, VGS = ±20 V
VDS = VGS, ID = 250 μA
VGS = 4.5 V, ID = 25 A
VGS = 10 V, ID = 25 A
VDS = 3 V, ID = 25 A
1
100
1.8
3.2
2.3
IGSS
VGS(th)
1.1
1.4
2.6
mΩ
RDS(on)
gƒs
Drain-to-Source On-Resistance
Transconductance
1.9
118
S
DYNAMIC CHARACTERISTICS
CISS
COSS
CRSS
Rg
Input Capacitance
3400
393
157
0.9
23
4420
511
204
1.8
pF
pF
pF
Ω
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Gate Charge Total (4.5 V)
Gate Charge Gate-to-Drain
Gate Charge Gate-to-Source
Gate Charge at Vth
Output Charge
VGS = 0 V, VDS = 15 V, ƒ = 1 MHz
Qg
30
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qgd
Qgs
Qg(th)
QOSS
td(on)
tr
5.4
8.5
4.6
11.6
4
VDS = 15 V, ID = 25 A
VDS = 15 V, VGS = 0 V
Turn On Delay Time
Rise Time
10
VDS = 15 V, VGS = 4.5 V ID = 25 A
RG = 2 Ω
td(off)
tƒ
Turn Off Delay Time
Fall Time
20
3
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode Forward Voltage
Reverse Recovery Charge
Reverse Recovery Time
IS = 25 A, VGS = 0 V
0.8
15
13
1
V
nC
ns
VDD = 15 V, IF = 25 A, di/dt = 300 A/μs
5.2 Thermal Information
(TA = 25°C unless otherwise stated)
THERMAL METRIC
MIN
TYP
MAX
UNIT
RθJC
RθJA
Junction-to-Case Thermal Resistance(1)
Junction-to-Ambient Thermal Resistance(1)(2)
1.5
55
°C/W
(1)
R
θJC is determined with the device mounted on a 1-inch2 (6.45-cm2), Cu pad on a 1.5-inches × 1.5-inches thick FR4 PCB. RθJC is
specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-inch2 2-oz.Cu.
4
Copyright © 2014, Texas Instruments Incorporated
CSD17575Q3
www.ti.com.cn
ZHCSCP7A –JUNE 2014–REVISED AUGUST 2014
GATE
Source
GATE
Source
Max RθJA = 160°C/W
when mounted on
minimum pad area of
2 oz. Cu.
Max RθJA = 55°C/W
when mounted on
1 inch2 of 2 oz. Cu.
DRAIN
DRAIN
M0161-02
M0161-01
5.3 Typical MOSFET Characteristics
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
Copyright © 2014, Texas Instruments Incorporated
5
CSD17575Q3
ZHCSCP7A –JUNE 2014–REVISED AUGUST 2014
www.ti.com.cn
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
200
200
180
160
140
120
100
80
180
160
140
120
100
80
60
60
VGS =10V
VGS =6V
VGS =4.5V
TC = 125°C
TC = 25°C
TC = −55°C
40
20
0
40
20
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
G001
G001
VDS = 5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
10
9
8
7
6
5
4
3
2
1
0
10000
1000
100
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
0
5
10 15 20 25 30 35 40 45 50 55
Qg - Gate Charge (nC)
3
6
9
12
15
18
21
24
27
30
VDS - Drain-to-Source Voltage (V)
G001
G001
ID = 25 A
VDS = 15 V
Figure 4. Gate Charge
Figure 5. Capacitance
2
1.8
1.6
1.4
1.2
1
8
7
6
5
4
3
2
1
0
TC = 25°C,I D = 25A
TC = 125°C,I D = 25A
0.8
0.6
0.4
−75 −50 −25
0
25
50
75 100 125 150 175
2
4
6
8
10
12
14
16
18
20
TC - Case Temperature (ºC)
VGS - Gate-to- Source Voltage (V)
G001
G001
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
6
Copyright © 2014, Texas Instruments Incorporated
CSD17575Q3
www.ti.com.cn
ZHCSCP7A –JUNE 2014–REVISED AUGUST 2014
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
2
100
10
VGS = 4.5V
VGS = 10V
TC = 25°C
TC = 125°C
1.8
1.6
1.4
1.2
1
1
0.1
0.01
0.001
0.0001
0.8
0.6
0.4
−75 −50 −25
0
25
50
75 100 125 150 175
0
0.2
0.4
0.6
0.8
1
TC - Case Temperature (ºC)
VSD − Source-to-Drain Voltage (V)
G001
G001
ID = 25 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
1000
100
TC = 25ºC
TC = 125ºC
100
10
1
10us
1ms
DC
100us
10ms
0.1
0.1
10
0.01
1
10
100
0.1
1
VDS - Drain-to-Source Voltage (V)
TAV - Time in Avalanche (mS)
G001
G001
Single Pulse
Max RθJC = 1.5°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
80
70
60
50
40
30
20
10
0
−50 −25
0
25
50
75 100 125 150 175 200
TC - Case Temperature (ºC)
G001
Figure 12. Maximum Drain Current vs Temperature
Copyright © 2014, Texas Instruments Incorporated
7
CSD17575Q3
ZHCSCP7A –JUNE 2014–REVISED AUGUST 2014
www.ti.com.cn
6 器件和文档支持
6.1 Trademarks
NexFET is a trademark of Texas Instruments.
6.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
8
Copyright © 2014, Texas Instruments Incorporated
CSD17575Q3
www.ti.com.cn
ZHCSCP7A –JUNE 2014–REVISED AUGUST 2014
7 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
7.1 Q3 封装尺寸
毫米
标称值
1.000
英寸
标称值
0.039
DIM
最小值
0.950
0.000
0.280
最大值
1.100
0.050
0.400
最小值
0.037
0.000
0.011
最大值
0.043
0.002
0.016
A
A1
b
0.000
0.000
0.340
0.013
b1
c
0.310（标称值）
0.200
0.012（标称值）
0.008
0.150
3.200
1.650
0.150
0.300
3.200
2.350
0.250
3.400
1.800
0.250
0.400
3.400
2.550
0.006
0.126
0.065
0.006
0.012
0.126
0.093
0.010
0.134
0.071
0.010
0.016
0.134
0.100
D
3.300
0.130
D2
d
1.750
0.069
0.200
0.008
d1
E
0.350
0.014
3.300
0.130
E2
e
2.450
0.096
0.650 典型值
0.450
0.026
H
0.35
0.550
0.014
0.018
0.022
K
0.650 典型值
0.450
0.026 典型值
0.018
L
0.35
0
0.550
0.014
0.022
L1
θ
—
0
0
0
0
—
0
0
0
—
—
Copyright © 2014, Texas Instruments Incorporated
9
CSD17575Q3
ZHCSCP7A –JUNE 2014–REVISED AUGUST 2014
www.ti.com.cn
7.2 建议 PCB 布局
要获得与印刷电路板 (PCB) 设计相关的建议电路布局布线，请参见《应用说明》SLPA005 - 通过 PCB 布局布线技
巧来减少振铃。
7.3 建议模板开口
全部尺寸单位为 mm，除非另外注明。
10
Copyright © 2014, Texas Instruments Incorporated
CSD17575Q3
www.ti.com.cn
ZHCSCP7A –JUNE 2014–REVISED AUGUST 2014
7.4 Q3 卷带信息
4.00 0.ꢀ0 ꢁ(SS ꢂNoS ꢀ1
8.00 0.ꢀ0
2.00 0.0ꢃ
+0.ꢀ0
–0.00
Ø ꢀ.ꢃ0
3.60
M0ꢀ44-0ꢀ
注释：
1. 10 链轮孔距累积容差为 ±0.2
2. 每 100mm 长度的翘曲不能超过 1mm，在 250mm 长度上不累积
3. 材料：黑色抗静电聚苯乙烯
4. 全部尺寸单位为 mm（除非另外注明）。
5. 厚度：0.30 ± 0.05mm
6. MSL1 260°C（红外 (IR) 和传导）无铅 (PbF) 回流焊兼容
Copyright © 2014, Texas Instruments Incorporated
11
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
CSD17575Q3
CSD17575Q3T
ACTIVE
VSON-CLIP
VSON-CLIP
DQG
8
8
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
CSD17575
CSD17575
ACTIVE
DQG
RoHS-Exempt
& Green
SN
-55 to 150
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD17575Q3T
VSON-
CLIP
DQG
8
250
330.0
12.4
3.6
3.6
1.2
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VSON-CLIP DQG
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 41.3
CSD17575Q3T
8
250
Pack Materials-Page 2
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