CSD17576Q5B [TI]

采用 5mm x 6mm SON 封装的单路、2.9mΩ、30V、N 沟道 NexFET™ 功率 MOSFET;
CSD17576Q5B
型号: CSD17576Q5B
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

采用 5mm x 6mm SON 封装的单路、2.9mΩ、30V、N 沟道 NexFET™ 功率 MOSFET

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中文:  中文翻译
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CSD17576Q5B  
ZHCSCL0A JUNE 2014REVISED MAY 2017  
CSD17576Q5B 30V N 通道 NexFET™功率金属氧化物半导体场效应晶体  
(MOSFET)  
1 特性  
产品概要  
1
Qg Qgd  
RDS(on)  
TA = 25°C  
VDS  
典型值  
30  
单位  
V
漏源电压  
低热阻  
Qg  
栅极电荷总量 (4.5V)  
栅极电荷(栅极到漏极)  
25  
nC  
nC  
mΩ  
mΩ  
V
雪崩级  
Qgd  
5.4  
VGS = 4.5V  
VGS = 10V  
1.4  
2.4  
1.7  
无铅引脚镀层  
符合 RoHS 标准  
无卤素  
RDS(on) 漏源导通电阻  
VGS(th) 阈值电压  
SON 5mm × 6mm 塑料封装  
订购信息(1)  
器件  
数量  
2500 13 英寸卷带  
250 7 英寸卷带  
介质  
封装  
出货  
卷带封装  
2 应用范围  
CSD17576Q5B  
CSD17576Q5BT  
SON 5mm x 6mm  
塑料封装  
用于网络互联、电信和计算系统的 负载点 同步降  
压转换器  
(1) 要了解所有可用封装,请参阅数据表末尾的可订购产品附录。  
已针对同步 FET 应用进行 优化  
绝对最大额定值  
3 说明  
TA = 25°C  
30  
单位  
V
VDS  
VGS  
漏源电压  
这款 30V1.7mΩSON 5 x 6mm NexFET™功率  
MOSFET 的设计旨在追求以最大限度降低功率转换应  
用中的功率 损耗。  
栅源电压  
±20  
100  
V
持续漏极电流(受封装限制)  
持续漏极电流(受芯片限制),TC = 25°C  
时测得  
ID  
184  
A
顶视图  
持续漏极电流(1)  
30  
400  
3.1  
IDM  
PD  
脉冲漏极电流,TA = 25°C 时测得(2)  
功率耗散(1)  
A
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
W
功率耗散,TC = 25°C  
125  
TJ, 运行结温和  
-55 150  
°C  
Tstg  
储存温度范围  
雪崩能量,单脉冲  
ID = 48L = 0.1mHRG = 25Ω  
EAS  
115  
mJ  
D
(1) RθJA = 40°C/W,这是在一个厚度 0.06 英寸环氧树脂 (FR4) 印  
刷电路板 (PCB) 上的 1 英寸22 盎司的铜过渡垫片上测得的  
典型值。  
D
P0093-01  
(2) 最大 RθJC = 1.3°C/W,脉冲持续时间 100μs,占空比 1%。  
RDS(on) VGS 对比  
栅极电荷  
8
7
6
5
4
3
2
1
0
10  
9
TC = 25°C,I D = 25A  
TC = 125°C,I D = 25A  
8
7
6
5
4
3
2
ID = 25A  
VDS = 15V  
1
0
0
2
4
6
8
10  
12  
14  
16  
18  
20  
0
5
10 15 20 25 30 35 40 45 50 55  
Qg - Gate Charge (nC)  
VGS - Gate-to- Source Voltage (V)  
G001  
G001  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
English Data Sheet: SLPS497  
 
 
 
 
 
 
CSD17576Q5B  
ZHCSCL0A JUNE 2014REVISED MAY 2017  
www.ti.com.cn  
目录  
6.1 接收文档更新通知 ..................................................... 7  
6.2 社区资源.................................................................... 7  
6.3 ........................................................................... 7  
6.4 静电放电警告............................................................. 7  
6.5 Glossary.................................................................... 7  
机械、封装和可订购信息 ......................................... 8  
7.1 Q5B 封装尺寸............................................................ 8  
7.2 建议 PCB 布局 .......................................................... 9  
7.3 建议模板布局........................................................... 10  
7.4 Q5B 卷带信息.......................................................... 10  
1
2
3
4
5
特性.......................................................................... 1  
应用范围................................................................... 1  
说明.......................................................................... 1  
修订历史记录 ........................................................... 2  
Specifications......................................................... 3  
5.1 Electrical Characteristics........................................... 3  
5.2 Thermal Information.................................................. 3  
5.3 Typical MOSFET Characteristics.............................. 4  
器件和文档支持........................................................ 7  
7
6
4 修订历史记录  
Changes from Original (June 2014) to Revision A  
Page  
已添加 接收文档更新通知社区资源部分添加到了器件和文档支持............................................................................ 7  
已更改 将建议 PCB 布局 部分方框图中.................................................................................................................................. 9  
2
版权 © 2014–2017, Texas Instruments Incorporated  
 
CSD17576Q5B  
www.ti.com.cn  
ZHCSCL0A JUNE 2014REVISED MAY 2017  
5 Specifications  
5.1 Electrical Characteristics  
(TA = 25°C unless otherwise stated)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
STATIC CHARACTERISTICS  
BVDSS  
IDSS  
Drain to Source Voltage  
VGS = 0 V, ID = 250 μA  
30  
V
Drain to Source Leakage Current  
Gate to Source Leakage Current  
Gate to Source Threshold Voltage  
VGS = 0 V, VDS = 24 V  
VDS = 0 V, VGS = 20 V  
VDS = VGS, ID = 250 μA  
VGS = 4.5 V, ID = 25 A  
VGS = 10 V, ID = 25 A  
VDS = 3 V, ID = 25 A  
1
100  
1.8  
2.9  
2.0  
μA  
nA  
V
IGSS  
VGS(th)  
1.1  
1.4  
2.4  
1.7  
120  
mΩ  
mΩ  
S
RDS(on)  
gfs  
Drain to Source On Resistance  
Transconductance  
DYNAMIC CHARACTERISTICS  
Ciss  
Coss  
Crss  
RG  
Input Capacitance  
3410  
389  
151  
1.0  
25  
4430  
506  
196  
2.0  
pF  
pF  
pF  
Output Capacitance  
Reverse Transfer Capacitance  
Series Gate Resistance  
Gate Charge Total (4.5 V)  
Gate Charge Total (10 V)  
Gate Charge Gate to Drain  
Gate Charge Gate to Source  
Gate Charge at Vth  
Output Charge  
VGS = 0V, VDS = 15 V, ƒ = 1 MHz  
Qg  
32  
nC  
nC  
nC  
nC  
nC  
nC  
ns  
ns  
ns  
ns  
Qg  
53  
68  
Qgd  
Qgs  
Qg(th)  
Qoss  
td(on)  
tr  
VDS = 15 V, ID = 25 A  
VDS = 30 V, VGS = 0 V  
5.4  
8.9  
4.7  
12.3  
5
Turn On Delay Time  
Rise Time  
16  
VDS = 15 V, VGS = 10 V,  
IDS = 25 A, RG = 0 Ω  
td(off)  
tf  
Turn Off Delay Time  
Fall Time  
23  
3
DIODE CHARACTERISTICS  
VSD  
Qrr  
trr  
Diode Forward Voltage  
Reverse Recovery Charge  
Reverse Recovery Time  
ISD = 25 A, VGS = 0V  
0.8  
14.7  
14  
1
V
nC  
ns  
VDS= 15 V, IF = 25 A,  
di/dt = 300 A/μs  
5.2 Thermal Information  
(TA = 25°C unless otherwise stated)  
THERMAL METRIC  
MIN  
TYP  
MAX  
UNIT  
(1)  
RθJC  
RθJA  
Junction-to-Case Thermal Resistance  
Junction-to-Ambient Thermal Resistance  
1.3  
50  
°C/W  
(1)(2)  
(1)  
R
θJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inches × 1.5-inches (3.81-  
cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.  
(2) Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.  
Copyright © 2014–2017, Texas Instruments Incorporated  
3
CSD17576Q5B  
ZHCSCL0A JUNE 2014REVISED MAY 2017  
www.ti.com.cn  
GATE  
Source  
GATE  
Source  
Max RθJA = 50°C/W  
when mounted on  
1 inch2 (6.45 cm2) of  
2-oz. (0.071-mm thick)  
Cu.  
Max RθJA = 125°C/W  
when mounted on a  
minimum pad area of  
2-oz. (0.071-mm thick)  
Cu.  
DRAIN  
DRAIN  
M0137-02  
M0137-01  
5.3 Typical MOSFET Characteristics  
(TA = 25°C unless otherwise stated)  
Figure 1. Transient Thermal Impedance  
4
Copyright © 2014–2017, Texas Instruments Incorporated  
CSD17576Q5B  
www.ti.com.cn  
ZHCSCL0A JUNE 2014REVISED MAY 2017  
Typical MOSFET Characteristics (continued)  
(TA = 25°C unless otherwise stated)  
200  
200  
180  
160  
140  
120  
100  
80  
180  
160  
140  
120  
100  
80  
60  
60  
VGS =10V  
VGS =6V  
VGS =4.5V  
TC = 125°C  
TC = 25°C  
TC = −55°C  
40  
20  
0
40  
20  
0
0
0.1  
0.2  
0.3  
0.4  
0.5  
0.6  
0.7  
0.8  
0
0
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
VDS - Drain-to-Source Voltage (V)  
VGS - Gate-to-Source Voltage (V)  
G001  
G001  
VDS = 5 V  
Figure 2. Saturation Characteristics  
Figure 3. Transfer Characteristics  
10  
9
8
7
6
5
4
3
2
1
0
10000  
1000  
100  
Ciss = Cgd + Cgs  
Coss = Cds + Cgd  
Crss = Cgd  
0
5
10 15 20 25 30 35 40 45 50 55  
Qg - Gate Charge (nC)  
3
6
9
12  
15  
18  
21  
24  
27  
30  
VDS - Drain-to-Source Voltage (V)  
G001  
G001  
VDS = 15 V  
ID = 25 A  
Figure 4. Gate Charge  
Figure 5. Capacitance  
2
1.8  
1.6  
1.4  
1.2  
1
8
7
6
5
4
3
2
1
0
TC = 25°C,I D = 25A  
TC = 125°C,I D = 25A  
0.8  
0.6  
−75 −50 −25  
0
25  
50  
75 100 125 150 175  
2
4
6
8
10  
12  
14  
16  
18  
20  
TC - Case Temperature (ºC)  
VGS - Gate-to- Source Voltage (V)  
G001  
G001  
ID = 250 µA  
Figure 6. Threshold Voltage vs Temperature  
Figure 7. On-State Resistance vs Gate-to-Source Voltage  
Copyright © 2014–2017, Texas Instruments Incorporated  
5
CSD17576Q5B  
ZHCSCL0A JUNE 2014REVISED MAY 2017  
www.ti.com.cn  
Typical MOSFET Characteristics (continued)  
(TA = 25°C unless otherwise stated)  
2
100  
10  
VGS = 4.5V  
VGS = 10V  
TC = 25°C  
TC = 125°C  
1.8  
1.6  
1.4  
1.2  
1
1
0.1  
0.01  
0.001  
0.0001  
0.8  
0.6  
−75 −50 −25  
0
25  
50  
75 100 125 150 175  
0
0.2  
0.4  
0.6  
0.8  
1
TC - Case Temperature (ºC)  
VSD − Source-to-Drain Voltage (V)  
G001  
G001  
ID = 25 A  
Figure 8. Normalized On-State Resistance vs Temperature  
Figure 9. Typical Diode Forward Voltage  
5000  
100  
TC = 25ºC  
TC = 125ºC  
10us  
100us  
1ms  
10ms  
DC  
1000  
100  
10  
1
0.1  
0.1  
10  
0.01  
1
10  
100  
0.1  
1
VDS - Drain-to-Source Voltage (V)  
TAV - Time in Avalanche (mS)  
G001  
G001  
Single Pulse Max RθJC = 1.3°C/W  
Figure 10. Maximum Safe Operating Area  
Figure 11. Single Pulse Unclamped Inductive Switching  
120  
100  
80  
60  
40  
20  
0
−50 −25  
0
25  
50  
75 100 125 150 175 200  
TC - Case Temperature (ºC)  
G001  
Figure 12. Maximum Drain Current vs Temperature  
6
Copyright © 2014–2017, Texas Instruments Incorporated  
CSD17576Q5B  
www.ti.com.cn  
ZHCSCL0A JUNE 2014REVISED MAY 2017  
6 器件和文档支持  
6.1 接收文档更新通知  
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我进行注册,即可收到任意产品  
信息更改每周摘要。有关更改的详细信息,请查看任意已修订文档中包含的修订历史记录。  
6.2 社区资源  
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective  
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of  
Use.  
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration  
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help  
solve problems with fellow engineers.  
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and  
contact information for technical support.  
6.3 商标  
NexFET, E2E are trademarks of Texas Instruments.  
6.4 静电放电警告  
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损  
伤。  
6.5 Glossary  
SLYZ022 TI Glossary.  
This glossary lists and explains terms, acronyms, and definitions.  
版权 © 2014–2017, Texas Instruments Incorporated  
7
CSD17576Q5B  
ZHCSCL0A JUNE 2014REVISED MAY 2017  
www.ti.com.cn  
7 机械、封装和可订购信息  
以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据发生变化时,  
我们可能不会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本,请参见左侧的导航栏。  
7.1 Q5B 封装尺寸  
K
c1  
H
L
E1  
d1  
d2  
Top View  
Side View  
Bottom View  
Front View  
毫米  
标称值  
1.00  
DIM  
最小值  
最大值  
A
b
0.80  
0.36  
0.15  
0.15  
0.20  
4.90  
4.12  
3.90  
0.20  
1.05  
0.46  
0.25  
0.25  
0.30  
5.10  
4.32  
4.10  
0.30  
0.41  
c
0.20  
c1  
c2  
D1  
D2  
D3  
d
0.20  
0.25  
5.00  
4.22  
4.00  
0.25  
d1  
d2  
E
0.085 典型值  
0.369  
5.00  
0.319  
4.90  
5.90  
3.48  
0.419  
5.10  
6.10  
3.68  
E1  
E2  
e
6.00  
3.58  
1.27 典型值  
0.46  
H
0.36  
0.46  
0.57  
0°  
0.56  
0.66  
0.77  
-
L
0.56  
L1  
θ
0.67  
-
K
1.40 典型值  
8
版权 © 2014–2017, Texas Instruments Incorporated  
CSD17576Q5B  
www.ti.com.cn  
ZHCSCL0A JUNE 2014REVISED MAY 2017  
7.2 建议 PCB 布局  
,焊盘 3 4 之间的尺寸从 0.028 英寸更改为了 0.050 英寸  
要获得与印刷电路板 (PCB) 设计相关的建议电路布局布线,请参见《应用说明》SLPA005 - 通过 PCB 布局布线技  
巧来减少振铃。  
版权 © 2014–2017, Texas Instruments Incorporated  
9
CSD17576Q5B  
ZHCSCL0A JUNE 2014REVISED MAY 2017  
www.ti.com.cn  
7.3 建议模板布局  
(0.020)  
0.508  
(0.014)  
0.350  
(0.022)  
0.562 x 4  
(0.029)  
0.746 x 8  
(0.011)  
0.286  
x4  
(0.086)  
2.186  
1.270  
4.318  
(0.170)  
0.300  
(0.012)  
(0.050)  
1.270  
(0.050)  
(0.051)  
1.294  
x 8  
(0.030)  
0.766  
(0.060)  
1.525  
(0.042)  
1.072  
(0.259)  
6.586  
7.4 Q5B 卷带信息  
K0  
4.00 0.10 ꢀ(SS ꢁNoS 1ꢂ  
0.30 0.05  
2.00 0.05  
+0.10  
–0.00  
Ø 1.50  
B0  
A0  
8.00 0.10  
R 0.30 MAX  
Ø 1.50 MIꢁ  
R 0.30 TYP  
A0 = 6.50 0.10  
B0 = 5.30 0.10  
K0 = 1.40 0.10  
M0138-01  
注释:  
1. 10 个链齿孔的累积容差为 ±0.2。  
2. 100mm 长度的翘曲不能超过 1mm,在 250mm 长度上不累积。  
3. 材料:黑色抗静电聚苯乙烯。  
4. 全部尺寸单位为 mm(除非另外注明)。  
5. 高于孔眼底部 0.3mm 的平面上测量得到 A0 B0 .  
10  
版权 © 2014–2017, Texas Instruments Incorporated  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
2500  
250  
(1)  
(2)  
(3)  
(4/5)  
(6)  
CSD17576Q5B  
CSD17576Q5BT  
ACTIVE  
VSON-CLIP  
VSON-CLIP  
DNK  
8
8
RoHS-Exempt  
& Green  
NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
CSD17576  
CSD17576  
ACTIVE  
DNK  
RoHS-Exempt  
& Green  
NIPDAU  
-55 to 150  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
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