CLVTH162373MDLREP [TI]
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS; 具有三态输出的3.3V ABT 16位透明D型锁存器
| 型号： | CLVTH162373MDLREP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS |
| 文件： | 总10页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVTH162373-EP
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCBS811A–JULY 2006–REVISED JULY 2006
FEATURES
•
Controlled Baseline
•
•
•
Flow-Through Architecture Optimizes PCB
Layout
– One Assembly/Test Site, One Fabrication
Site
Latch-Up Performance Exceeds 500 mA Per
JESD 17
•
•
Extended Temperature Performance of –55°C
to 125°C
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
xxxxxxxxxxxx
Enhanced Diminishing Manufacturing
Sources (DMS) Support
•
•
•
Enhanced Product-Change Notification
(1)
Qualification Pedigree
DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments Widebus™
Family
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1
2
3
4
5
6
7
8
9
48 1LE
47 1D1
•
Output Ports Have Equivalent 22-Ω Series
Resistors, So No External Resistors Are
Required
46
1D2
45 GND
44 1D3
•
•
•
•
•
•
Supports Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC
)
43
1D4
42 VCC
41 1D5
40 1D6
39 GND
38 1D7
37 1D8
Supports Unregulated Battery Operation
Down to 2.7 V
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
GND 10
1Q7
1Q8
11
12
Ioff and Power-Up 3-State Support Hot
Insertion
2Q1 13
2Q2
36
2D1
14
35 2D2
34 GND
33 2D3
32 2D4
31 VCC
30 2D5
29 2D6
28 GND
27 2D7
26 2D8
25 2LE
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
GND 15
2Q3 16
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
2Q4
17
VCC 18
2Q5 19
2Q6 20
GND 21
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
2Q7
22
2Q8 23
2OE 24
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
xxxx
DESCRIPTION/ORDERING INFORMATION
The SN74LVTH162373 is a 16-bit transparent D-type latch with 3-state outputs designed for low-voltage (3.3-V)
VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. This device is
particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
LVTH162373EP
–55°C to 125°C
SSOP – DL
Tape and reel
CLVTH162373MDLREP
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVTH162373-EP
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCBS811A–JULY 2006–REVISED JULY 2006
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors to
reduce overshoot and undershoot.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D
inputs.
FUNCTION TABLE
(EACH 8-BIT SECTION)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q0
Z
H
X
LOGIC DIAGRAM (POSITIVE LOGIC)
1
24
2OE
1OE
1LE
25
48
2LE
C1
1D
C1
1D
2
13
2Q1
1Q1
47
36
2D1
1D1
To Seven Other Channels
To Seven Other Channels
2
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SN74LVTH162373-EP
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCBS811A–JULY 2006–REVISED JULY 2006
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
V
VCC Supply voltage range
4.6
VI
Input voltage range(2)
7
V
VO
VO
IO
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high state(2)
Current into any output in the low state
7
VCC + 0.5
30
V
V
mA
mA
mA
mA
°C/W
°C
IO
Current into any output in the high state(3)
30
IIK
Input clamp current
VI < 0
–50
IOK
θJA
Tstg
Output clamp current
VO < 0
–50
Package thermal impedance(4)
Storage temperature range(5)
63
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This current flows only when the output is in the high state and VO > VCC
.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
Recommended Operating Conditions(1)
MIN
2.7
2
MAX UNIT
VCC
VIH
VIL
Supply voltage
3.6
V
V
High-level input voltage
Low-level input voltage
Input voltage
0.8
5.5
–12
12
V
VI
V
IOH
IOL
High-level output current
Low-level output current
Input transition rise or fall rate
mA
mA
ns/V
µs/V
°C
∆t/∆v
Outputs enabled
10
∆t/∆VCC Power-up ramp rate
TA Operating free-air temperature
200
–55
125
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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SN74LVTH162373-EP
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCBS811A–JULY 2006–REVISED JULY 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
II = –18 mA
IOH = –12 mA
IOL = 12 mA
VI = 5.5 V
MIN TYP(1)
MAX
UNIT
VIK
VCC = 2.7 V,
VCC = 3 V,
–1.2
V
V
V
VOH
VOL
2
VCC = 3 V,
0.8
10
±1
1
VCC = 0 or 3.6 V,
VCC = 3.6 V,
Control inputs
Data inputs
VI = VCC or GND
VI = VCC
II
µA
VCC = 3.6 V
VCC = 3 V
VI = 0
–5
VI = 0.8 V
75
II(hold) Data inputs
µA
VI = 2 V
–75
IOZH
VCC = 3.6 V,
VCC = 3.6 V,
VO = 3 V
5
–5
±100(1)
±100(1)
0.19
µA
µA
µA
µA
IOZL
VO = 0.5 V
IOZPU
IOZPD
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care
VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care
Outputs high
VCC = 3.6 V,
ICC
IO = 0,
Outputs low
5
mA
VI = VCC or GND
Outputs disabled
0.19
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
(2)
∆ICC
0.2
mA
Ci
VI = 3 V or 0
VO = 3 V or 0
3
9
pF
pF
Co
(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.
(2) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN MAX
MIN
3
MAX
tw
tsu
th
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
3
1.3
1
ns
ns
ns
0.6
1.1
4
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SN74LVTH162373-EP
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCBS811A–JULY 2006–REVISED JULY 2006
Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN MAX
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
1.8
1.8
2.1
2.1
1.7
1.7
2.3
1
5
4.4
5.4
4.9
5.6
5.3
6.3
7.4
5.7
4.8
6.2
4.7
7
D
Q
Q
Q
Q
ns
ns
ns
ns
LE
OE
OE
5.9
6.6
6.4
5
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SN74LVTH162373-EP
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCBS811A–JULY 2006–REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION
6 V
Open
S1
500 W
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
6 V
From Output
Under Test
GND
CL = 50 pF
(see Note A)
500 W
GND
2.7 V
LOAD CIRCUIT
tw
Timing Input
Data Input
1.5 V
th
0 V
tsu
1.5 V
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
Output
Control
1.5 V
1.5 V
tPLZ
1.5 V
1.5 V
Input
0 V
tPZL
tPHL
tPLH
Output
Waveform 1
S1 at 6 V
VOH
VOL
3 V
1.5 V
1.5 V
1.5 V
1.5 V
Output
VOL + 0.3 V
VOL
(see Note B)
tPZH
tPHZ
tPHL
tPLH
Output
Waveform 2
S1 at GND
VOH
VOL
VOH
OH - 0.3 V
V
1.5 V
1.5 V
Output
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
CLVTH162373MDLREP
V62/06654-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DL
48
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
48
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVTH162373-EP :
Catalog: SN74LVTH162373
Military: SN54LVTH162373
•
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Military - QML certified for Military and Defense Applications
•
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CLVTH162373MDLREP
SSOP
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DL 48
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 49.0
CLVTH162373MDLREP
1000
Pack Materials-Page 2
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