CDC509PWR [TI]
3.3-V PHASE-LOCK LOOP CLOCK DRIVER;
| 型号： | CDC509PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER 驱动 光电二极管 逻辑集成电路 |
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CDC509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS576B – JULY 1996 – REVISED JANUARY 1998
PW PACKAGE
(TOP VIEW)
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
Distributes One Clock Input to One Bank of
Five and One Bank of Four Outputs
AGND
CLK
AV
1
24
23
22
21
20
19
18
17
16
15
14
13
V
2
CC
CC
Separate Output Enable for Each Output
Bank
1Y0
1Y1
1Y2
GND
GND
1Y3
V
3
CC
2Y0
2Y1
GND
GND
2Y2
2Y3
4
External Feedback (FBIN) Pin Is Used to
Synchronize the Outputs to the Clock Input
5
6
7
No External RC Network Required
8
Operates at 3.3-V V
CC
1Y4
9
Packaged in Plastic 24-Pin Thin Shrink
Small-Outline Package
V
10
11
12
V
CC
CC
1G
FBOUT
2G
FBIN
description
The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to
precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It
is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3-V V and is designed
CC
to drive up to five clock loads per output.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output
signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can
be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs
switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low
state.
Unlike many products containing PLLs, the CDC509 does not require external RC networks. The loop filter for
the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC509 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL can be bypassed for test purposes by strapping AV
to ground.
CC
The CDC509 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
2G
OUTPUTS
2Y
1Y
(0:4)
1G
CLK
FBOUT
(0:3)
X
L
X
L
L
H
H
H
H
L
L
L
L
L
H
H
H
H
L
H
L
L
H
H
H
H
H
L
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS576B – JULY 1996 – REVISED JANUARY 1998
functional block diagram
11
1G
3
4
5
8
9
1Y0
1Y1
1Y2
1Y3
1Y4
14
2G
21
20
2Y0
2Y1
17
16
24
2Y2
CLK
PLL
13
2Y3
FBIN
12
FBOUT
23
AV
CC
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(PW)
0°C to 70°C
CDC509PWR
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS576B – JULY 1996 – REVISED JANUARY 1998
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME
NO.
Clock input. CLK provides the clock signal to be distributed by the CDC509 clock driver. CLK is used
toprovidethereferencesignaltotheintegratedPLLthatgeneratestheclockoutputsignals. CLKmust
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.
CLK
24
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
FBIN
1G
13
11
14
I
I
I
Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are
disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same
frequency as CLK.
Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are
disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same
frequency as CLK.
2G
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL.
FBOUT
1Y(0:4)
2Y(0:3)
12
O
O
O
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via
the 1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input.
3, 4, 5, 8, 9
16, 17, 20 21
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via
the 2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input.
Analog power supply. AV
CC
provides the power reference for the analog circuitry. In addition, AV
CC
AV
CC
23
Power
can be used to bypass the PLL for test purposes. When AV
is strapped to ground, PLL is bypassed
CC
and CLK is buffered directly to the device outputs.
AGND
1
Ground Analog ground. AGND provides the ground reference for the analog circuitry.
Power Power supply
Ground Ground
V
CC
GND
2, 10, 15, 22
6, 7, 18, 19
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
I
Voltage range applied to any output in the high
or low state, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V
Maximum power dissipation at T = 55°C (in still air) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, T
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation, refertothePackageThermalConsiderationsapplicationnoteintheABTAdvancedBiCMOSTechnologyData
Book, literature number SCBD002.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS576B – JULY 1996 – REVISED JANUARY 1998
recommended operating conditions (see Note 4)
MIN
3
MAX
UNIT
V
V
V
V
V
Supply voltage
3.6
CC
High-level input voltage
Low-level input voltage
Input voltage
2
V
IH
0.8
V
IL
0
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Operating free-air temperature
–20
20
mA
mA
°C
OH
OL
T
A
70
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP
MAX
UNIT
V
IK
I = –18 mA
I
3 V
–1.2
V
I
I
I
I
= –100 µA
= –20 mA
= 100 µA
= 20 mA
MIN to MAX
3 V
V
CC
–0.2
2.4
OH
OH
OL
OL
V
V
V
OH
MIN to MAX
3 V
0.2
0.55
±5
V
OL
I
I
V = V
or GND
or GND,
3.6 V
µA
µA
µA
pF
pF
I
I
CC
CC
‡
V = V
I = 0, Outptus high or low
O
3.6 V
10
CC
I
∆I
CC
One input at V
CC
– 0.6 V,
Other inputs at V
or GND
3.3 V to 3.6 V
3.3 V
500
CC
C
C
V = V
or GND
4
6
i
I
CC
= V or GND
CC
V
3.3 V
o
O
†
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
For I of AV , see Figure 5.
CC
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
25
MAX
125
60%
1
UNIT
f
Clock frequency
MHz
clock
Input clock duty cycle
40%
§
Stabilization time
ms
§
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phasereferencesignalmustbepresentatCLK. Untilphaselockisobtained, thespecificationsforpropagationdelay, skew,
and jitter parameters given in the switching characteristics table are not applicable.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS576B – JULY 1996 – REVISED JANUARY 1998
switching characteristics over recommended ranges of supply voltage and operating free-air
†
temperature, C = 30 pF (see Note 5 and Figures 1 and 2)
L
V
= 3.3 V
± 0.165 V
V
= 3.3 V
CC
CC
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
t
, reference
(see Figure 3)
66 MHz < CLKIN↑ < 100
phase error
FBIN↑
FBIN↑
100...480
340
ps
ps
MHz
t
, – jitter,
phase error
(see Note 6)
CLKIN↑ = 100 MHz
220
480
‡
t
Any Y or FBOUT
F(clkin > 66 MHz)
F(clkin ≤ 66 MHz)
F(clkin > 66 MHz)
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
200
100
55%
57%
1.6
ps
ps
sk(o)
Jitter
–100
45%
43%
0.7
(pk-pk)
Duty cycle, reference
(see Figure 4)
t
r
1.1
0.8
1.5
1.3
ns
ns
t
f
0.5
1.5
†
‡
This parameters are not production tested.
The t specification is only valid for equal loading of all outputs.
sk(o)
NOTES: 5. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
6. Phase error does not include jitter. The total phase error is 120 ps to 580 ps for the 5% V range.
CC
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
Input
50% V
CC
t
pd
From Output
Under Test
V
V
OH
2 V
0.4 V
2 V
Output
500
50% V
CC
0.4 V
30 pF
OL
t
t
f
r
LOAD CIRCUIT FOR OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, Z = 50 Ω, t ≤ 1.2 ns, t ≤ 1.2 ns.
O
r
f
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS576B – JULY 1996 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
CLKIN
FBIN
t
phase error
FBOUT
Any Y
t
sk(o)
Any Y
Any Y
t
sk(o)
Figure 2. Phase Error and Skew Calculations
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS576B – JULY 1996 – REVISED JANUARY 1998
TYPICAL CHARACTERISTICS
PHASE ERROR
vs
OUTPUT DUTY CYCLE
vs
CLOCK FREQUENCY
CLOCK FREQUENCY
1.2
1
57%
55%
V
T
= 3.3 V
V
C
= 3.3 V
DD
= 25°C
DD
= 30 pF
A
L
0.8
0.6
0.4
0.2
53%
51%
49%
47%
45%
43%
0
–0.2
35 45 55 65 75 85 95 105 115 125 135
30
50
70
90
110
130
f
– Clock Frequency – MHz
f
– Clock Frequency – MHz
clk
clk
Figure 3
Figure 4
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
9
V
T
A
= 3.3 V
= 25°C
DD
8
7
6
5
4
3
2
1
0
25 35 45 55 65 75 85 95 105 115 125
f
– Clock Frequency – MHz
clk
Figure 5
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS576B – JULY 1996 – REVISED JANUARY 1998
MECHANICAL INFORMATION
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,30
0,19
0,65
M
0,10
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
0,75
A
0,50
Seating Plane
0,10
1,20 MAX
0,05 MIN
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/E 08/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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