CDC391DR [TI]
1-To-6 Clock Driver With Selectable Polarity 16-SOIC;
| 型号： | CDC391DR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1-To-6 Clock Driver With Selectable Polarity 16-SOIC 驱动 信息通信管理 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢄ ꢅꢆ ꢇꢈꢉ ꢊ ꢋ ꢌ ꢅꢆ ꢇꢈꢉ ꢀꢆ ꢋ ꢀꢍ ꢁ ꢎꢇ ꢏ ꢉꢎ
ꢐ ꢇꢊ ꢑ ꢒꢉ ꢆꢉ ꢀꢊꢓꢔꢆ ꢉ ꢕꢋ ꢆ ꢓꢎꢇ ꢊꢖ ꢓꢈꢁ ꢂ ꢅꢒꢊꢓꢊ ꢉ ꢋ ꢗꢊ ꢕ ꢗꢊꢒ
SCAS334A − DECEMBER 1992 − REVISED NOVEMBER 1995
D PACKAGE
(TOP VIEW)
D Low Output Skew for Clock-Distribution
and Clock-Generation Applications
D TTL-Compatible Inputs and Outputs
1Y1
1T/C
GND
1Y2
1Y3
GND
2Y1
2Y2
GND
3Y1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D Distributes One Clock Input to Six Clock
Outputs
V
CC
D Polarity Control Selects True or
2T/C
A
Complementary Outputs
V
D Distributed V
and GND Pins Reduce
CC
CC
Switching Noise
3T/C
OE
D High-Drive Outputs (−48-mA I
,
OH
48-mA I
)
OL
D State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
D Packaged in Plastic Small-Outline Package
description
The CDC391 contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew
for clock distribution. Through the use of the polarity-control (T/C) inputs, various combinations of true and
complementary outputs can be obtained. The output-enable (OE) input is provided to disable the outputs to a
high-impedance state.
The CDC391 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUT
Y
Z
L
OE
H
L
T/C
X
A
X
L
L
L
L
H
L
H
H
L
L
H
L
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
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Copyright 1995, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢀꢂ ꢃ ꢄ
ꢄꢅ ꢆ ꢇ ꢈꢉ ꢊꢋ ꢌ ꢅꢆ ꢇ ꢈ ꢉ ꢀꢆ ꢋꢀ ꢍ ꢁꢎ ꢇ ꢏꢉ ꢎ
ꢐꢇ ꢊ ꢑ ꢒꢉ ꢆ ꢉꢀ ꢊꢓꢔ ꢆꢉ ꢕ ꢋꢆ ꢓꢎꢇ ꢊ ꢖ ꢓꢈ ꢁ ꢂ ꢅꢒ ꢊꢓꢊ ꢉ ꢋ ꢗꢊ ꢕꢗꢊ ꢒ
SCAS334A − DECEMBER 1992 − REVISED NOVEMBER 1995
†
logic symbol
9
OE
EN
16
2
1
1Y1
1Y2
1Y3
2Y1
2Y2
3Y1
12
A
1
1
2
2
3
15
3
N1
N2
N3
1T/C
13
5
2T/C
10
6
3T/C
8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
9
OE
15
1T/C
16
2
1Y1
1Y2
1Y3
3
5
6
8
12
A
2Y1
2Y2
13
10
2T/C
3T/C
3Y1
2
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ꢀ ꢁꢀ ꢂꢃ ꢄ
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ꢐ ꢇꢊ ꢑ ꢒꢉ ꢆꢉ ꢀꢊꢓꢔꢆ ꢉ ꢕꢋ ꢆ ꢓꢎꢇ ꢊꢖ ꢓꢈꢁ ꢂ ꢅꢒꢊꢓꢊ ꢉ ꢋ ꢗꢊ ꢕꢗ ꢊꢒ
SCAS334A − DECEMBER 1992 − REVISED NOVEMBER 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state, V
. . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Maximum power dissipation at T = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.77 W
A
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 300 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
MIN NOM
MAX
UNIT
V
V
V
V
V
Supply voltage
4.75
2
5
5.25
CC
High-level input voltage
Low-level input voltage
Input voltage
V
IH
0.8
V
IL
0
V
V
I
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Input clock frequency
Operating free-air temperature
−48
48
mA
mA
ns/V
MHz
°C
OH
OL
∆t/∆v
5
f
100
85
clock
T
−40
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
I = −18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
V
V
= 4.75 V,
= 4.75 V,
= 4.75 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
−1.2
IK
CC
CC
CC
CC
CC
CC
I
I
= − 48 mA
= 48 mA
2
V
OH
OL
OH
OL
I
0.5
1
V
I
I
I
V = V
CC
or GND
or GND
µA
µA
mA
I
I
V
= V
CC
50
OZ
O
O
§
V
= 2.5 V
−15
−100
10
O
Outputs high
Outputs low
V
= 5.25 V,
I
O
= 0,
CC
40
I
mA
CC
V = V
or GND
I
CC
Outputs disabled
10
C
C
V = 2.5 V or 0.5 V
3
5
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
o
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
3
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢀꢂ ꢃ ꢄ
ꢄꢅ ꢆ ꢇ ꢈꢉ ꢊꢋ ꢌ ꢅꢆ ꢇ ꢈ ꢉ ꢀꢆ ꢋꢀ ꢍ ꢁꢎ ꢇ ꢏꢉ ꢎ
ꢐꢇ ꢊ ꢑ ꢒꢉ ꢆ ꢉꢀ ꢊꢓꢔ ꢆꢉ ꢕ ꢋꢆ ꢓꢎꢇ ꢊ ꢖ ꢓꢈ ꢁ ꢂ ꢅꢒ ꢊꢓꢊ ꢉ ꢋ ꢗꢊ ꢕꢗꢊ ꢒ
SCAS334A − DECEMBER 1992 − REVISED NOVEMBER 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 and 2)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
t
t
t
t
t
t
t
t
1.5
1.5
1.5
1.5
1.5
3
5
5
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Any Y
Any Y
Any Y
Any Y
ns
5
T/C
OE
OE
ns
5
5
ns
7
5
ns
5
Any Y (same phase)
Any Y (any phase)
Any Y
0.5
1
t
t
A
A
ns
ns
sk(o)
1
sk(p)
t
t
1.5
1.5
ns
ns
r
f
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢀ ꢂꢃ ꢄ
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ꢐ ꢇꢊ ꢑ ꢒꢉ ꢆꢉ ꢀꢊꢓꢔꢆ ꢉ ꢕꢋ ꢆ ꢓꢎꢇ ꢊꢖ ꢓꢈꢁ ꢂ ꢅꢒꢊꢓꢊ ꢉ ꢋ ꢗꢊ ꢕꢗ ꢊꢒ
SCAS334A − DECEMBER 1992 − REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
7 V
TEST
S1
S1
500 Ω
Open
GND
t
t
/t
Open
7 V
Open
PLH PHL
/t
From Output
Under Test
PLZ PZL
t
/t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
3 V
0 V
Output
Control
(low-level
enabling)
LOAD CIRCUIT FOR OUTPUTS
1.5 V
1.5 V
t
t
PZL
t
PLZ
3 V
0 V
Input
3.5 V
1.5 V
1.5 V
Output
Waveform 1
S1 at 7 V
1.5 V
V
+ 0.3 V
OL
t
PLH
V
OL
t
PHL
(see Note B)
t
PHZ
V
OH
PZH
2 V
0.8 V
2 V
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
Output
1.5 V
t
0.8 V
V
− 0.3 V
V
OL
OH
1.5 V
≈ 0 V
t
f
r
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
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ꢄꢅ ꢆ ꢇ ꢈꢉ ꢊꢋ ꢌ ꢅꢆ ꢇ ꢈ ꢉ ꢀꢆ ꢋꢀ ꢍ ꢁꢎ ꢇ ꢏꢉ ꢎ
ꢐꢇ ꢊ ꢑ ꢒꢉ ꢆ ꢉꢀ ꢊꢓꢔ ꢆꢉ ꢕ ꢋꢆ ꢓꢎꢇ ꢊ ꢖ ꢓꢈ ꢁ ꢂ ꢅꢒ ꢊꢓꢊ ꢉ ꢋ ꢗꢊ ꢕꢗꢊ ꢒ
SCAS334A − DECEMBER 1992 − REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
A
1T/C
1Y1
t
t
t
t
t
t
t
t
PLH1
PLH2
PHL1
PHL2
PLH5
PLH6
PHL5
PHL6
1Y2
2T/C
2Y1
2Y2
t
t
t
t
t
t
t
t
PHL7
PHL8
PLH7
PLH8
PLH3
PLH4
PHL3
PHL4
NOTES: A. Output skew, t
from A to any Y (same phase), can be measured only between outputs for which the respective polarity-control
inputs (T/C) are at the same logic level. It is calculated as the greater of:
sk(o),
− The difference between the fastest and slowest of t
− The difference between the fastest and slowest of t
− The difference between the fastest and slowest of t
− The difference between the fastest and slowest of t
from A↑ to any Y (e.g., t
from A↓ to any Y (e.g., t
from A↓ to any Y (e.g., t
from A↑ to any Y (e.g., t
, n = 1 to 4; or t
, n = 1 to 4; or t
, n = 7 to 8)
, n = 5 to 6)
, n = 5 to 6)
PLH
PHL
PLH
PHL
PLHn
PHLn
PLHn
PHLn
PLHn
PHLn
, n = 7 to 8)
B. Output skew, t
from A to any Y (any phase), can be measured between outputs for which the respective polarity-control inputs
(T/C) are at the same or different logic levels. It is calculated as the greater of:
sk(o),
− The difference between the fastest and slowest of t
from A↑ to any Y or t
from A↑ to any Y (e.g., t
, n = 1 to 4;
PLH
PHL
PLHn
or t
, n = 5 to 6, and t , n = 7 to 8)
PLHn
PHLn
− The difference between the fastest and slowest of t
or t , n = 5 to 6, and t , n = 7 to 8)
from A↓ to any Y or t
from A↓ to any Y (e.g., t
, n = 1 to 4;
PHL
PLH
PHLn
PHLn PLHn
Figure 2. Waveforms for Calculation of t
sk(o)
6
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