CD74HCT533E [TI]
High Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs; 高速CMOS逻辑八路反相透明锁存器，三态输出
| 型号： | CD74HCT533E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs |
| 文件： | 总9页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC533, CD74HCT533,
CD74HC563, CD74HCT563
Data sheet acquired from Harris Semiconductor
SCHS187
High Speed CMOS Logic Octal Inverting
Transparent Latch, Three-State Outputs
January 1998
Features
Description
• Common Latch-Enable Control
• Common Three-State Output Enable Control
• Buffered Inputs
The Harris CD74HC533, CD74HCT533, CD74HC563, and
CD74HCT563 are high speed Octal Transparent Latches
manufactured with silicon gate CMOS technology. They pos-
sess the low power consumption of standard CMOS inte-
grated circuits, as well as the ability to drive 15 LSTTL
devices.
[ /Title
(CD74H
C533,
CD74H
CT533,
CD74H
C563,
CD74H
CT563)
/Subject
(High
• Three-State Outputs
• Bus Line Driving Capacity
The outputs are transparent to the inputs when the latch
enable (LE) is high. When the latch enable (LE) goes low the
data is latched. The output enable (OE) controls the three-
state outputs. When the output enable (OE) is high the
outputs are in the high impedance state. The latch operation
• Typical Propagation Delay = 13ns at V
CC
= 5V,
o
C = 15pF, T = 25 C (Data to Output)
L
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
is independent to the state of the output enable.
The CD74HC533 and CD74HCT533 are identical in function
to the CD74HC563 and CD74HCT563 but have different
pinouts. The CD74HC533 and CD74HCT533 are similar to
the CD74HC373 and CD74HCT373; the latter are non-
inverting types.
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Speed
• Significant Power Reduction Compared to LSTTL
Logic ICs
Ordering Information
• HC Types
- 2V to 6V Operation
TEMP. RANGE
PKG.
NO.
o
PART NUMBER
CD74HC533E
CD74HCT533E
CD74HC563E
CD74HCT563E
CD74HCT563M
NOTES:
( C)
PACKAGE
20 Ld PDIP
20 Ld PDIP
20 Ld PDIP
20 Ld PDIP
20 Ld SOIC
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
F20.3
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
E20.3
E20.3
E20.3
M20.3
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number are available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1599.1
Copyright © Harris Corporation 1998
1
CD74HC533, CD74HCT533, CD74HC563, CD74HCT563
Pinouts
CD74HC533, CD74HCT533
(PDIP, SOIC)
CD74HC563, CD74HCT563
(PDIP, SOIC)
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
9
V
1
2
3
4
5
6
7
8
9
V
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
20
19
OE
D0
D1
D2
D3
D4
D5
D6
D7
20
19
CC
CC
Q7
Q0
18 D7
17 D6
16 Q6
18 Q1
17 Q2
16 Q3
15
Q5
15
Q4
14 D5
13 D4
14 Q5
13 Q6
12
12
Q4
Q7
GND 10
11 LE
GND 10
11 LE
Functional Block Diagram
CD74HC/HCT533
D
D
D
D
D
D
D
D
7
0
1
2
3
4
5
6
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
LE
OE
O
O
O
O
O
O
O
O
7
0
1
2
3
4
5
6
TRUTH TABLE
OUTPUT ENABLE
LATCH ENABLE
DATA
Q OUTPUT
L
L
L
L
H
H
H
L
H
L
l
L
H
H
L
L
h
X
X
Z
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance State, l = Low voltage level one set-up time prior
to the high to low latch enable transition, h = High voltage level one set-up time prior to the high to low latch enable transition.
2
CD74HC533, CD74HCT533, CD74HC563, CD74HCT563
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
120
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-6
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-7.8
Low Level Output
Voltage
CMOS Loads
V
or
0.02
0.02
0.02
6
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
V
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
7.8
Input Leakage
Current
I
V
or
-
6
6
-
-
-
-
±0.1
-
-
±1
-
-
±1
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
0
8
80
160
CC
CC
GND
3
CD74HC533, CD74HCT533, CD74HC563, CD74HCT563
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
Three-State Leakage
Current
-
V
V
or
V
=
or
6
-
-
±0.5
-
±5
-
±10
µA
IL
O
V
IH
CC
GND
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
V
IL
High Level Output
Voltage
TTL Loads
-6
0.02
6
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IH
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
-
5.5
5.5
5.5
-
-
-
-
-
-
±0.1
8
-
-
-
±1
80
±5
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
0
160
±10
CC
CC
GND
Three-State Leakage
Current
-
V
or
V
V
=
or
±0.5
IL
V
O
IH
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆I
CC
V
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
CC
-2.1
NOTE:
4. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
0.15
D0 - D7
LE
OE
0.30
0.55
NOTE: Unit Load is ∆I
tions table, e.g., 360µA max at 25 C.
limit specified in DC Electrical Specifica-
CC
o
4
CD74HC533, CD74HCT533, CD74HC563, CD74HCT563
Prerequisite For Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
LE Pulse Width
t
-
-
-
-
2
80
16
14
50
10
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100
20
17
65
13
11
45
9
-
-
-
-
-
-
-
-
-
-
-
-
120
24
20
75
15
13
55
11
7
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
W
4.5
6
Set-up Time Data to LE
t
2
SU
4.5
6
Hold Time, Data to LE
(533)
t
t
2
35
7
H
H
4.5
6
6
8
Hold Time, Data to LE
(563)
2
4
4
4
4.5
6
4
4
4
4
4
4
HCT TYPES
LE Pulse Width
t
t
t
t
-
-
-
-
4.5
4.5
4.5
4.5
16
10
8
-
-
-
-
-
-
-
-
20
13
10
5
-
-
-
-
24
15
12
5
-
-
-
-
ns
ns
ns
ns
w
w
H
H
Set-up Time Data to LE
Hold Time, Data to LE (533)
Hold Time, Data to LE (563)
5
Switching Specifications Input t , t = 6ns
r
f
o
-55 C TO
125 C
o
o
o
o
25 C
-40 C TO 85 C
MAX
TEST
PARAMETER
HC TYPES
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
MAX
UNITS
CC
Propagation Delay,
Data to Qn
(HC533)
t
, t
C = 50pF
2
4.5
6
-
-
165
33
28
-
205
41
35
-
250
50
43
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PLH PHL
L
-
C = 15pF
5
13
-
L
Propagation Delay,
Data to Qn
(HC563)
t
t
t
t
C = 50pF
2
150
30
26
-
190
38
33
-
225
45
38
-
PLH, PHL
L
4.5
6
-
-
C = 15pF
5
12
-
L
Propagation Delay,
LE to Qn
(HC533)
t
C = 50pF
2
175
35
30
-
220
44
37
-
265
53
45
-
PLH, PHL
L
4.5
6
-
-
C = 15pF
5
14
-
L
Propagation Delay,
LE to Qn
(HC563)
t
C = 50pF
2
165
33
28
-
205
41
35
-
250
50
43
-
PLH, PHL
L
4.5
6
-
-
C = 15pF
5
13
L
5
CD74HC533, CD74HCT533, CD74HC563, CD74HCT563
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
-55 C TO
125 C
o
o
o
o
25 C
-40 C TO 85 C
TEST
PARAMETER
Enable Times
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
150
30
26
-
MAX
190
38
33
-
MAX
225
45
38
-
UNITS
ns
CC
t
t
C = 50pF
2
-
-
PZH, PZL
L
(HC533)
4.5
ns
6
5
2
-
ns
C = 15pF
12
-
ns
L
Disable Times
(HC533)
t
t
C = 50pF
150
30
26
-
190
38
33
-
225
45
38
-
ns
PHZ, PLZ
L
4.5
6
-
ns
-
ns
C = 15pF
5
12
-
ns
L
Enable and Disable Times
(HC563)
t
t
C = 50pF
2
150
30
26
-
190
38
33
-
225
45
38
-
ns
PZH, PZL,
L
t
t
PHZ, PLZ
4.5
6
-
ns
-
ns
C = 15pF
L
5
12
-
ns
Input Capacitance
C
-
-
-
10
20
10
20
10
20
pF
pF
I
Three-State Output
Capacitance
C
-
-
O
Power Dissipation
Capacitance
C
-
5
42
-
-
-
pF
PD
(Notes 5, 6)
HCT TYPES
Propagation Delay,
Data to Qn
(HC/HCT533)
t
t
t
, t
C = 50pF
4.5
5
-
34
-
43
-
51
-
ns
ns
PLH PHL
L
C = 15pF
14
L
Propagation Delay,
Data to Qn
(HC/HCT563)
, t
PLH PHL
C = 50pF
4.5
5
-
30
-
38
-
45
-
ns
ns
L
C = 15pF
12
L
Propagation Delay,
LE to Qn
(HC/HCT533)
, t
PLH PHL
C = 50pF
4.5
5
-
38
-
48
-
57
-
ns
ns
L
C = 15pF
16
L
Propagation Delay,
LE to Qn
(HC/HCT563)
t , t
PZL PZH
C = 50pF
4.5
5
-
35
-
44
-
53
-
ns
ns
L
C = 15pF
14
L
Enable Times
(HC/HCT533)
t
, t
PLZ PZH
C = 50pF
4.5
5
-
14
-
35
-
44
-
53
-
ns
ns
ns
ns
ns
ns
pF
pF
L
C = 15pF
L
Disable Times
(HC/HCT533)
t
, t
TLH THL
C = 50pF
4.5
5
30
-
38
-
45
-
L
C = 15pF
12
-
L
Enable and Disable Times
(HC/HCT563)
t
t
C = 50pF
4.5
5
35
-
44
-
53
-
PZH, PZL,
L
t
t
PHZ, PLZ
C = 15pF
L
14
-
Input Capacitance
C
-
-
-
10
-
10
-
10
-
I
Power Dissipation
Capacitance
C
5
42
PD
(Notes 5, 6)
NOTES:
5. C
PD
is used to determine the no-load dynamic power consumption, per latch.
2
2
6. P (total power per latch) = C
V
f + Σ C V f where f = Input Frequency, f = Output Frequency, C = Output Load
CC o i o L
D
PD CC
i
L
Capacitance, V
= Supply Voltage.
CC
6
CD74HC533, CD74HCT533, CD74HC563, CD74HCT563
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
fC
t C
f
L
L
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%. accordance with device truth table. For f , input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
7
CD74HC533, CD74HCT533, CD74HC563, CD74HCT563
Test Circuits and Waveforms (Continued)
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 7. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 8. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
PLZ
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
V
, C = 50pF.
CC
L
FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
8
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