CD74HCT534 [TI]
High Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggered; 高速CMOS逻辑八路D类触发器，三态反相上升沿触发
| 型号： | CD74HCT534 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggered |
| 文件： | 总9页 (文件大小：55K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC534, CD74HCT534,
CD74HC564, CD74HCT564
Data sheet acquired from Harris Semiconductor
SCHS188
High Speed CMOS Logic Octal D-Type Flip-Flop,
Three-State Inverting Positive-Edge Triggered
January 1998
Features
Description
• Buffered Inputs
The Harris CD74HC534, CD74HCT534, CD74HC564 and
CD74HCT564 are high speed Octal D-Type Flip-Flops manu-
• Common Three-State Output-Enable Control
• Three-State Outputs
[ /Title
(CD74
HC534
,
factured with silicon gate CMOS technology. They possess
the low power consumption of standard CMOS integrated cir-
cuits, as well as the ability to drive 15 LSTTL loads. Due to the
large output drive capability and the three-state feature, these
devices are ideally suited for interfacing with bus lines in a bus
organized system. The two types are functionally identical and
differ only in their pinout arrangements.
• Bus Line Driving Capability
• Typical Propagation Delay = 13ns at V
CC
= 5V,
CD74
HCT53
4,
CD74
HC564
,
o
C = 15pF, T = 25 C (Clock to Output)
L
A
• Fanout (Over Temperature Range)
The CD74HC534, CD74HCT534, CD74HC564 and
CD74HCT564 are positive edge triggered flip-flops. Data at
the D inputs, meeting the setup and hold time requirements,
are inverted and transferred to the Q outputs on the positive
going transition of the CLOCK input. When a high logic level is
applied to the OUTPUT ENABLE input, all outputs go to a
high impedance state, regardless of what signals are present
at the other inputs and the state of the storage elements.
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
CD74
HCT56
• Significant Power Reduction Compared to LSTTL
Logic ICs
The CD74HCT logic family is speed, function, and pin
compatible with the standard 74LS logic family.
• HC Types
- 2V to 6V Operation
Ordering Information
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
PKG.
CC
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
NO.
E20.3
E20.3
E20.3
E20.3
• HCT Types
CD74HC534E
CD74HCT534E
CD74HC564E
CD74HCT564E
CD74HC564M
CD74HCT564M
NOTES:
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
20 Ld PDIP
20 Ld PDIP
20 Ld PDIP
20 Ld PDIP
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
20 Ld SOIC M20.3
20 Ld SOIC M20.3
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
Pinouts
CD74HC534, CD74HCT534 (PDIP)
CD74HC564, CD74HCT564 (PDIP, SOIC)
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
9
V
1
2
3
4
5
6
7
8
9
V
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
20
19
OE
D0
D1
D2
D3
D4
D5
D6
D7
20
19
CC
CC
Q7
Q0
18 D7
17 D6
16 Q6
18 Q1
17 Q2
16 Q3
15
Q5
15
Q4
14 D5
13 D4
14 Q5
13 Q6
12
12
Q4
Q7
GND 10
11 CP
GND 10
11 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1640.1
Copyright © Harris Corporation 1998
1
CD74HC534, CD74HCT534, CD74HC564, CD74HCT564
Functional Diagram
D
D
D
D
D
D
D
D
7
0
1
2
3
4
5
6
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
CP
OE
Q
Q
Q
Q
Q
Q
Q
O
7
0
1
2
3
4
5
6
TRUTH TABLE
INPUTS
OUTPUT
OE
L
CP
↑
Dn
Qn
L
H
L
L
↑
H
L
L
X
X
No Change
Z
H
X
NOTE:
H = High Level (Steady State)
L
X
↑
= Low Level (Steady State)
= Don’t Care
= Transition from Low to High Level
= High Impedance State
Z
2
CD74HC534, CD74HCT534, CD74HC564, CD74HCT564
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
120
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-6
4.5
6
3.98
-
3.84
-
3.7
-
-7.8
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
6
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
7.8
-
Input Leakage
Current
I
V
or
6
I
CC
GND
3
CD74HC534, CD74HCT534, CD74HC564, CD74HCT564
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
I
O
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
Three- State Leakage
Current
V
or V
V
=V
CC
-
6
-
-
±0.5
-
±5.0
-
±10
µA
IL
IH
O
or GND
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-6
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
6
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
5.5
-
-
-
-
±0.1
8
-
-
-
-
±1
80
-
-
-
-
±1
µA
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
-
160
±10
490
CC
CC
GND
Three- State Leakage
Current
V
or V
V
=V
±0.5
360
±5.0
450
IL
IH
O
CC
or GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
V
-
4.5 to
5.5
100
CC
CC
-2.1
NOTE: For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
0.15
D0 - D7
CP
OE
0.30
0.55
NOTE: Unit load is ∆I
Table, e.g., 360µA max. at 25 C.
limit specific in DC Electrical Specifications
o
CC
4
CD74HC534, CD74HCT534, CD74HC564, CD74HCT564
Prerequisite for Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V) MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX UNITS
CC
Maximum Clock
Frequency
f
MAX
2
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
25
29
100
20
17
75
15
13
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
20
23
120
24
20
90
18
15
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
ns
4.5
6
30
35
80
16
14
60
12
10
5
Clock Pulse Width
t
2
W
4.5
6
ns
ns
Setup Time
Data to Clock
t
2
ns
SU
4.5
6
ns
ns
Hold Time
Data to Clock
t
2
ns
H
4.5
6
5
5
5
ns
5
5
5
ns
HCT TYPES
Maximum Clock
Frequency
f
MAX
4.5
25
-
-
20
-
-
16
-
-
MHz
Clock Pulse Width
t
4.5
4.5
20
20
-
-
-
-
25
25
-
-
-
-
30
30
-
-
-
-
ns
ns
W
Setup Time
t
SU
Data to Clock
Hold Time
Data to Clock (534)
t
4.5
4.5
5
3
-
-
-
-
5
3
-
-
-
-
5
3
-
-
-
-
ns
ns
H
H
Hold Time
t
Data to Clock (564)
Switching Specifications C = 50pF, Input t , t = 6ns
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay
Clock to Output
t
, t
PLH PHL
C = 50pF
L
2
-
-
-
165
33
-
-
-
-
-
-
-
-
-
205
41
-
-
-
-
-
-
-
-
-
250
50
-
ns
ns
ns
ns
ns
ns
ns
ns
4.5
5
-
-
-
-
-
-
-
C = 15pF
13
-
L
C = 50pF
6
28
150
30
-
35
190
38
-
43
225
45
-
L
Output Disable to Q (534)
t
, t
PLZ PHZ
C
= 50pF
2
-
L
4.5
5
-
C
= 15pF
12
-
L
C = 50pF
6
26
33
38
L
5
CD74HC534, CD74HCT534, CD74HC564, CD74HCT564
Switching Specifications C = 50pF, Input t , t = 6ns (Continued)
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Output Disable to Q (564)
t
, t
PLZ PHZ
C
= 50pF
2
-
-
-
135
27
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
170
34
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
205
41
-
ns
ns
L
4.5
5
-
-
C
= 15pF
12
-
ns
L
C = 50pF
6
-
23
150
30
-
29
190
38
-
35
225
45
-
ns
L
Output Enable to Q
t
, t
PZL PZH
C
= 50pF
2
-
-
ns
L
4.5
5
-
-
ns
C
= 15pF
-
12
-
ns
L
C = 50pF
6
-
26
-
33
-
38
-
ns
L
Maximum Clock Frequency
Output Transition Time
f
C
= 15pF
= 50pF
5
-
60
-
MHz
ns
MAX
, t
L
L
t
C
2
-
60
12
10
10
20
75
15
13
10
20
90
18
15
10
20
THL TLH
4.5
6
-
-
ns
-
-
ns
Input Capacitance
C
C
L
= 50pF
-
-
10
20
-
pF
pF
I
Three-State Output
Capacitance
C
-
-
O
Power Dissipation Capacitance
(Notes 4, 5)
C
-
5
-
32
-
-
-
-
-
pF
PD
HCT TYPES
Propagation Delay
Clock to Output
t
t
PHL, PLH
C
L
= 50pF
4.5
5
-
-
-
14
-
35
-
-
-
-
-
-
-
-
-
-
-
44
-
-
-
-
-
-
-
-
-
-
-
53
-
ns
ns
C = 15pF
L
Output Disable to Q
Output Enable to Q
t
t
, t
PLZ PHZ
C
= 50pF
4.5
5
-
30
-
38
-
45
-
ns
L
C = 15pF
-
12
-
ns
L
, t
PZL PZH
C
= 50pF
4.5
5
-
35
-
44
-
53
-
ns
L
C = 15pF
-
14
50
-
ns
L
Maximum Clock Frequency
f
C
C
C
= 15pF
= 50pF
= 50pF
-
5
-
-
-
-
MHz
ns
MAX
, t
L
L
L
t
4.5
-
-
12
10
20
15
10
20
18
10
20
TLH THL
Output Transition Time
Input Capacitance
C
10
20
-
pF
pF
I
Three-State Output
Capacitance
C
-
-
O
Power Dissipation Capacitance
(Notes 4, 5)
C
-
5
-
36
-
-
-
-
-
pF
PD
NOTES:
4. C
is used to determine the dynamic power consumption, per package.
PD
5. P = C
2
2
V
f + ∑ C V
f
where f = Input Frequency, f = Output Frequency, C = Output Load Capacitance, V
= Supply
CC
D
PD CC
i
L
CC
O
i
O
L
Voltage.
6
CD74HC534, CD74HCT534, CD74HC564, CD74HCT564
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
fC
t C
f
L
L
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%. accordance with device truth table. For f , input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
7
CD74HC534, CD74HCT534, CD74HC564, CD74HCT564
Test Circuits and Waveforms (Continued)
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 7. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 8. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
PLZ
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
V
, C = 50pF.
CC
L
FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
8
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号：
CD74HCT534E
High Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggered
TI
CD74HCT534EE4
High-Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggered
TI
©2020 ICPDF网 联系我们和版权申明