CD74HC40105MG4 [TI]
High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register; 高速CMOS逻辑4位x 16字FIFO寄存器
| 型号： | CD74HC40105MG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register |
| 文件： | 总21页 (文件大小：461K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC40105, CD74HC40105,
CD54HCT40105, CD74HCT40105
Data sheet acquired from Harris Semiconductor
SCHS222C
High-Speed CMOS Logic
4-Bit x 16-Word FIFO Register
February 1998 - Revised October 2003
Features
Description
• Independent Asynchronous Inputs and Outputs
• Expandable in Either Direction
• Reset Capability
The ’HC40105 and ’HCT40105 are high-speed silicon-gate
CMOS devices that are compatible, except for “shift-out”
circuitry, with the CD40105B. They are low-power first-in-out
(FIFO) “elastic” storage registers that can store 16 four-bit
words. The 40105 is capable of handling input and output
data at different shifting rates. This feature makes it
particularly useful as a buffer between asynchronous
systems.
[ /Title
(CD74
HC401
05,
CD74
HCT40
105)
/Sub-
ject
(High
Speed
CMOS
• Status Indicators on Inputs and Outputs
• Three-State Outputs
• Shift-Out Independent of Three-State Control
• Fanout (Over Temperature Range)
Each work position in the register is clocked by a control flip-
flop, which stores a marker bit. A “1” signifies that the posi-
tion’s data is filled and a “0” denotes a vacancy in that posi-
tion. The control flip-flop detects the state of the preceding
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
flip-flop and communicates its own status to the succeeding
o
• Wide Operating Temperature Range . . . -55 C to 125 C flip-flop. When a control flip-flop is in the “0” state and sees a
“1” in the preceeding flip-flop, it generates a clock pulse that
transfers data from the preceding four data latches into its
• Balanced Propagation Delay and Transition Times
own four data latches and resets the preceding flip-flop to
“0”. The first and last control flip-flops have buffered outputs.
Since all empty locations “bubble” automatically to the input
end, and all valid data ripple through to the output end, the
status of the first control flip-flop (DATA-IN READY) indicates
if the FIFO is full, and the status of the last flip-flop (DATA-
OUT READY) indicates if the FIFO contains data. As the
earliest data are removed from the bottom of the data stack
(the output end), all data entered later will automatically
propagate (ripple) toward the output.
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
Ordering Information
IL
IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
o
PART NUMBER
CD54HC40105F3A
CD54HCT40105F3A
CD74HC40105E
TEMP. RANGE ( C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
Applications
• Bit-Rate Smoothing
• CPU/Terminal Buffering
• Data Communications
• Peripheral Buffering
• Line Printer Input Buffers
• Auto-Dialers
CD74HC40105M
CD74HC40105MT
CD74HC40105M96
CD74HCT40105E
CD74HCT40105M
CD74HCT40105MT
CD74HCT40105M96
• CRT Buffer Memories
• Radar Data Acquisition
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
Three-State Outputs
Pinout
In order to facilitate data busing, three-state outputs (Q0 to
CD54HC40105, CD54HCT40105
(CERDIP)
CD74HC40105, CD74HCT40105
(PDIP, SOIC)
Q3) are provided on the data output lines, while the load
condition of the register can be detected by the state of the
DOR output. A HIGH on the three-state control flag (output
enable input OE) forces the outputs into the high-impedance
OFF-state mode. Note that the shift-out signal, unlike that in
the CD40105B, is independent of the three-state output
control. In the CD40105B, the three-state control must not
be shifted from High to Low when the shift-out signal is Low
(data loss would occur). In the high-speed CMOS version
this restriction has been eliminated.
TOP VIEW
THREE-STATE
1
2
3
4
5
6
7
8
16 V
CC
CONTROL
DIR
15 SO
14 DOR
13 Q0
12 Q1
11 Q2
10 Q3
SI
D0
D1
Cascading
D2
The 40105 can be cascaded to form longer registers simply
by connecting the DIR to SO and DOR to SI. In the cascaded
mode, a MASTER RESET pulse must be applied after the
supply voltage is turned on. For words wider than four bits, the
DIR and the DOR outputs must be gated together with AND
gates. Their outputs drive the SI and SO inputs in parallel, if
expanding is done in both directions (see Figures 12 and 13).
D3
9
MR
GND
Loading Data
Data can be entered whenever the DATA-IN READY (DIR)
flag is high, by a low to high transition on the SHIFT-IN (SI)
input. This input must go low momentarily before the next
word is accepted by the FIFO. The DIR flag will go low
momentarily, until the data have been transferred to the sec-
ond location. The flag will remain low when all 16-word loca-
tions are filled with valid data, and further pulses on the SI
input will be ignored until DIR goes high.
Functional Diagram
THREE-
STATE
CONTROL
1
13
4
Q0
D0
12
5
Q1
D1
11
Unloading Data
6
7
Q2
D2
10
As soon as the first word has rippled to the output, the data-
out ready output (DOR) goes HIGH and data of the first word
is available on the outputs. Data of other words can be
removed by a negative-going transition on the shift-out input
(SO). This negative-going transition causes the DOR signal
to go LOW while the next word moves to the output. As long
as valid data is available in the FIFO, the DOR signal will go
high again, signifying that the next word is ready at the
output. When the FIFO is empty, DOR will remain LOW, and
any further commands will be ignored until a “1” marker
ripples down to the last control register and DOR goes
HIGH. If during unloading SI is HIGH, (FIFO is full) data on
the data input of the FIFO is entered in the first location.
Q3
D3
3
14
2
DATA-OUT
READY
DATA-IN
READY
SHIFT IN
15
SHIFT OUT
GND = 8
= 16
9
MASTER
RESET
V
CC
Master Reset
A high on the MASTER RESET (MR) sets all the control
logic marker bits to “0”. DOR goes low and DIR goes high.
The contents of the data register are not changed, only
declared invalid, and will be superseded when the first word
is loaded. Thus, MR does not clear data within the register
but only the control logic. If the shift-in flag (SI) is HIGH
during the master reset pulse, data present at the input (D0
to D3) are immediately moved into the first location upon
completion of the reset process.
2
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
INPUT
BUFFERS
OUTPUT
BUFFERS
D0
D1
D2
D3
4
5
6
7
13 Q0
12 Q1
11 Q2
10 Q3
4 x 16
DATA
REGISTER
1
THREE-STATE CONTROL
DATA-OUT READY (DOR)
DATA-IN READY (DIR)
2
CONTROL LOGIC
14
SHIFT OUT (SO)
15
3
9
SHIFT IN (SI)
MASTER
RESET
(MR)
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
3
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
9
3
MR
SI
14
DOR
15
S0
F/Fs
2-15
F/F16
F/F1
R
S
Q
Q
R
Q
R
Q
Q
R
Q
†
† †
† †
S
† †
S
Q
S
Q
R
S
†
14 x
Q
2
DIR
14 x
4
5
13
Q0
Q1
Q2
Q3
D0
D1
D2
D3
CL
CL
CL
CL
CL
CL
12
11
10
THREE-
STATE
OUTPUT
BUFFERS
4
4 x 14
LATCHES
4
LATCHES
LATCHES
6
7
L1
14 x L1
L16
E
E
POSITION 1
POSITION 2-15
POSITIONS 16
1
OE
†
“S” overrides “R”.
†† “R” overrides “S”.
FIGURE 2. LOGIC DIAGRAM
4
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
67
73
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
5
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
O
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
I
Three-State Leakage
Current
I
V
or V
V
=
or
6
-
-
±0.5
-
±5
-
±10
µA
OZ
IL
IH
O
V
CC
GND
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
0.02
4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
5.5
5.5
5.5
-
-
-
-
-
-
±0.1
8
-
-
-
±1
80
±5
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
±10
CC
CC
GND
Three-State Leakage
Current
I
V
or V
V =
O
±0.5
OZ
IL
IH
V
or
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
CC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
OE
0.75
0.4
0.3
1.5
SI, SO
Dn
MR
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
6
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
Prerequisite for Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CC
SI Pulse Width
HIGH or LOW
t
t
t
t
t
2
80
16
14
120
24
20
200
40
34
200
40
34
120
24
20
50
10
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100
20
17
150
30
26
250
50
43
250
50
43
150
30
26
65
13
11
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
120
24
20
180
36
31
300
60
51
300
60
51
180
36
31
75
15
13
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
W
W
W
W
W
4.5
6
2
ns
SO Pulse Width
HIGH or LOW
ns
4.5
6
ns
ns
DIR Pulse Width
HIGH or LOW
2
ns
4.5
6
ns
ns
DOR Pulse Width
HIGH or LOW
2
ns
4.5
6
ns
ns
MR Pulse Width HIGH
2
ns
4.5
6
ns
ns
Removal Time
MR to SI
t
REM
2
ns
4.5
6
ns
ns
Set-Up Time
Dn to SI
t
2
5
ns
SU
4.5
6
5
5
5
ns
5
5
5
ns
Hold Time
Dn to SI
t
2
125
25
21
3
155
31
26
2
190
38
32
2
ns
H
4.5
6
ns
ns
Maximum Pulse Frequency
SI, SO
f
MAX
2
MHz
MHz
MHz
4.5
6
15
18
12
14
10
12
HCT TYPES
SI Pulse Width HIGH or LOW
t
t
4.5
4.5
16
16
-
-
20
20
-
-
24
24
-
-
ns
ns
W
SO Pulse Width HIGH or
LOW
W
DIR Pulse Width HIGH or
LOW
t
t
t
4.5
4.5
40
40
-
-
50
50
-
-
60
60
-
-
ns
ns
W
W
W
DOR Pulse Width HIGH or
LOW
MR Pulse Width HIGH
Removal Time MR to SI
Set-Up Time Dn to SI
Hold Time Dn to SI
4.5
4.5
4.5
4.5
4.5
24
15
0
-
-
-
-
-
30
19
0
-
-
-
-
-
36
22
0
-
-
-
-
-
ns
ns
t
f
REM
t
ns
SU
t
25
15
31
12
38
10
ns
H
Maximum Pulse Frequency
SI, SO
MHz
MAX
7
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
SYMBOL CONDITIONS
V
CC
(V)
PARAMETER
HC TYPES
MIN TYP MAX
MIN
MAX
MIN
MAX UNITS
Propagation Delay
MR to DIR, DOR
t
t
t
t
C = 50pF
2
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
175
35
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
220
44
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
265
53
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
pF
pF
PHL,
L
t
PLH
C = 50pF
L
C = 15pF
15
-
-
-
-
L
C = 50pF
6
30
37
45
L
SI to DIR
SO to DOR
SO to Qn
C = 50pF
2
-
210
42
265
53
315
63
PHL,
L
t
PLH
C = 50pF
4.5
5
-
L
C = 15pF
18
-
-
-
-
L
C = 50pF
6
36
45
54
L
C = 50pF
2
-
210
42
265
53
315
63
PHL,
L
t
PLH
C = 50pF
4.5
5
-
L
C = 15pF
18
-
-
-
-
L
C = 50pF
6
36
45
54
L
C = 50pF
2
-
400
80
500
100
-
600
120
-
PHL,
L
t
PLH
C = 50pF
4.5
5
-
L
C = 15pF
35
-
-
L
C = 50pF
6
68
85
102
3000
600
510
3750
750
638
2250
450
380
225
45
L
Propagation Delay/Ripple thru
Delay
SI to DOR
t
C = 50pF
2
-
2000
400
340
2500
500
425
1500
300
260
150
30
2500
500
425
3125
625
532
1900
380
330
190
38
PLH
PLH
PLH
L
4.5
6
-
-
Propagation Delay/Ripple thru
Delay
SO to DIR
t
t
C = 50pF
2
-
L
4.5
6
-
-
Propagation Delay/Ripple thru
Delay
SI to Qn
C = 50pF
2
-
L
4.5
6
-
-
Three-State Output Enable
t
t
t
t
C = 50pF
2
-
PZH, PZL
L
OE to Q
n
4.5
6
-
-
26
33
38
Three-State Output Disable
OE to Qn
t
C = 50pF
2
-
140
28
175
35
210
42
PHZ, PLZ
L
C = 50pF
4.5
6
-
L
C = 50pF
-
24
30
36
L
Output Transition Time
, t
TLH THL
C = 50pF
2
-
75
95
110
22
L
4.5
6
-
15
19
-
13
16
19
Maximum SI, SO Frequency
Input Capacitance
f
C = 15pF
5
32
-
-
-
-
MAX
L
C
C = 50pF
-
10
10
10
IN
L
Power Dissipation Capacitance
(Notes 3, 4)
C
C = 15pF
5
83
-
-
-
PD
L
8
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
(V)
PARAMETER
SYMBOL CONDITIONS
MIN TYP MAX
MIN
MAX
MIN
MAX UNITS
Three-State Output
Capacitance
C
C = 50pF
-
-
-
15
-
15
-
15
pF
O
L
HCT TYPES
Propagation Delay Time
t
t
t
t
C = 50pF
4.5
5
-
-
-
-
-
-
-
-
-
-
15
-
36
-
-
-
-
-
-
-
-
-
-
45
-
-
-
-
-
-
-
-
-
-
54
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
PLH,
L
t
PHL
MR to DIR, DOR
SI to DIR
C = 15pF
L
C = 50pF
4.5
5
42
-
53
-
63
-
PLH,
L
t
PHL
C =15pF
18
-
L
SO to DOR
SO to Qn
C = 50pF
4.5
5
42
-
53
-
63
-
PLH,
L
t
PHL
C =15pF
18
-
L
C = 50pF
4.5
5
80
-
100
-
120
-
PLH,
L
t
PHL
C =15pF
35
-
L
Propagation Delay/Ripple thru
t
C = 50pF
4.5
400
500
600
PLH
L
Delay
SI to DOR
Propagation Delay/Ripple thru
Delay
SO to DIR
t
t
C = 50pF
4.5
4.5
-
-
-
-
500
300
-
-
625
380
-
-
750
450
ns
ns
PLH
PLH
L
Propagation Delay/Ripple thru
C = 50pF
L
Delay
SI to Qn
Three-State Output Enable
t
t
t
t
C = 50pF
4.5
4.5
-
-
-
-
35
30
-
-
44
38
-
-
53
45
ns
ns
PZH, PZL
L
OE to Q
n
Three-State Output Disable
OE to Qn
t
C = 50pF
PHZ, PLZ L
Output Transition Time
Maximum CP Frequency
Input Capacitance
, t
TLH THL
C = 50pF
4.5
5
-
-
-
-
-
15
-
-
-
-
-
19
-
-
-
-
-
22
-
ns
MHz
pF
L
f
C =15pF
32
-
MAX
L
C
C = 50pF
-
10
-
10
-
10
-
IN
L
Power Dissipation Capacitance
(Notes 3, 4)
C
C =15pF
5
83
pF
PD
L
Three-State Output
Capacitance
C
C = 50pF
-
-
-
15
-
15
-
15
pF
O
L
NOTES:
3. C
is used to determine the dynamic power consumption, per package.
PD
4. P = C
2
2
V
f + Σ (C V
f ) where f = Input Frequency, f = Output Frequency, C = Output Load Capacitance, V
= Supply
D
PD CC
i
L
CC
o
i
o
L
CC
Voltage.
9
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
fC
t C
f
L
L
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%.
accordance with device truth table. For f
, input duty cycle = 50%.
MAX
MAX
FIGURE 3. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 4. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 5. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 6. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
10
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
Test Circuits and Waveforms (Continued)
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 7. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 8. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 9. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 10. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
PLZ
V
, C = 50pF.
CC
L
FIGURE 11. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
11
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
DATA OUT
READY
SHIFT IN
SI DOR
SI DOR
D0
Q0
D0
Q0
D1
D2
D1
D2
Q1
Q1
Q2
Q3
Q2
Q3
D3
DIR
D3
DIR
MR
MR
SO
SO
8-BIT
DATA
8-BIT
DATA
SI DOR
SI DOR
D0
Q0
D0
Q0
D1
D2
D1
D2
Q1
Q1
Q2
Q3
Q2
Q3
D3
DIR
D3
DIR
MR
MR
SO
SO
SHIFT OUT
DATA IN READY
MASTER RESET
(NOTE)
NOTE: Pulse must be applied for cascading by 16 N bits.
FIGURE 12. EXPANSION, 8-BITS WIDE BY 16 N-BITS LONG USING HC/HCT40105
12
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
MASTER
RESET
SHIFT IN
(DATA VALID)
INPUTS
SHIFT-IN PULSES
HAVE NO EFFECT
≈180ns
(NOTE 6)
SHIFT OUT
SHIFT-OUT PULSES
HAVE NO EFFECT
≈180ns
(NOTE 7)
INPUT READY
(CLEAR OUT)
(NOTE 5)
OUTPUTS
OUTPUT READY
(DATA VALID)
DATA IN
(Db)
INPUTS
THREE-STATE
(OUTPUT
1
0
1 1 1 0 0 1
(UNKNOWN)
1
0
1 0 1 0 1 0
ENABLE)
DATA OUT
(NOTE 5)
HIGH Z
1
0
1
1
1
0
INVALID
NOTES:
5. Data valid goes to high level in advance of the data out by a maximum of 38ns at V
o
= 4.5V for C = 50pF and T = 25 C.
CC
L
A
6. At V
7. At V
= 4.5V, ripple time from position 1 to position 16.
= 4.5V, ripple time from position 16 to position 1.
CC
CC
FIGURE 13. TIMING DIAGRAM FOR THE CD74HC/HCT40105
13
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
PDIP
Drawing
CD54HC40105F3A
CD54HCT40105F3A
CD74HC40105E
ACTIVE
ACTIVE
ACTIVE
J
J
16
16
16
1
1
TBD
TBD
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HC40105EE4
CD74HC40105M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
N
D
D
D
D
D
D
D
D
D
N
N
D
D
D
D
D
D
D
D
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC40105M96
CD74HC40105M96E4
CD74HC40105M96G4
CD74HC40105ME4
CD74HC40105MG4
CD74HC40105MT
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC40105MTE4
CD74HC40105MTG4
CD74HCT40105E
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HCT40105EE4
CD74HCT40105M
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HCT40105M96
CD74HCT40105M96E4
CD74HCT40105M96G4
CD74HCT40105ME4
CD74HCT40105MG4
CD74HCT40105MT
CD74HCT40105MTE4
CD74HCT40105MTG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2007
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
16
CD74HC40105M96
CD74HCT40105M96
D
D
16
16
SITE 27
SITE 27
6.5
6.5
10.3
10.3
2.1
2.1
8
8
16
16
Q1
Q1
330
16
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
CD74HC40105M96
CD74HCT40105M96
D
D
16
16
SITE 27
SITE 27
342.9
342.9
336.6
336.6
0.0
0.0
Pack Materials-Page 2
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