CD74HC4015E [TI]
High Speed CMOS Logic Dual 4-Stage Static Shift Register; 高速CMOS逻辑双路4级静态移位寄存器
| 型号： | CD74HC4015E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic Dual 4-Stage Static Shift Register |
| 文件： | 总6页 (文件大小：41K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC4015
Data sheet acquired from Harris Semiconductor
SCHS198
High Speed CMOS Logic
Dual 4-Stage Static Shift Register
November 1997
Features
Description
• Maximum Frequency, Typically 60MHz
o
The Harris CD74HC4015 consists of two identical,
independent, 4-stage serial-input/parallel-output registers.
Each register has independent Clock (CP) and Reset (MR)
inputs as well as a single serial Data input. “Q” outputs are
available from each of the four stages on both registers. All
register stages are D-type, master-slave flip-flops. The logic
level present at the Data input is transferred into the first
register stage and shifted over one stage at each positive-
going clock transition. Resetting of all stages is
accomplished by a high level on the reset line.
C = 15pF, V
= 5V, T = 25 C
A
L
CC
[ /Title
(CD74
HC401
5)
/Sub-
ject
• Positive-Edge Clocking
• Overriding Reset
• Buffered Inputs and Outputs
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
(High
Speed
CMOS
Logic
Dual
4-
The device can drive up to 10 low power Schottky equivalent
loads. The CD74HC4015 is an enhanced version of
equivalent CMOS types.
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
Ordering Information
PKG.
NO.
• HC Types
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
- 2V to 6V Operation
CD74HC4015E
NOTES:
-55 to 125
20 Ld PDIP
E16.3
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or
Harris customer service for ordering information.
Pinout
CD74HC4015
(PDIP)
TOP VIEW
2CP
1
2
3
4
5
6
7
8
16 V
CC
2Q
1Q
1Q
1Q
15 2D
3
2
1
0
14 2MR
13 2Q
12 2Q
11 2Q
10 1Q
0
1
2
3
1MR
1D
9
1CP
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1678.1
Copyright © Harris Corporation 1997
1
CD74HC4015
Functional Diagram
5
7
1D
1CP
1MR
1Q
1Q
1Q
1Q
0
1
2
3
4
9
6
3
10
13
12
11
2
15
1
2D
2CP
2MR
2Q
2Q
2Q
2Q
0
1
2
3
14
GND = 8
V
= 16
CC
TRUTH TABLE
INPUTS
OUTPUTS
CP
D
l
R
Q
Q
q’
q’
q’
Q
q’
q’
q’
Q
q’
q’
q’
0
1
2
1
1
2
3
2
2
3
↑
L
L
L
0
0
1
↑
h
X
X
H
↓
X
L
q’
0
H
L
L
L
L
NOTES:
H = High Voltage Level
h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition
L = Low Voltage Level
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition
X = Don’t Care.
↑ = Low to High Clock Transition
↓ = High to Low Clock Transition
q’ = Lower case letters indicate the state of the referenced output one set-up time prior to the Low to High
n
clock transition.
2
CD74HC4015
t6
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
90
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
o
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
DC Output Source or Sink Current per Output Pin, I
O
(SOIC - Lead Tips Only)
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
CC
I
O
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
f
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
V
O
High Level Input
Voltage
V
-
-
2
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
IH
4.5
6
3.15
-
-
3.15
-
-
3.15
V
4.2
4.2
4.2
-
V
Low Level Input
Voltage
V
-
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
V
IL
4.5
6
-
-
-
V
-
-
-
V
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
V
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
V
5.9
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
V
-4
4.5
6
3.98
-
3.84
-
3.7
-
V
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
V
OL
4.5
6
V
V
Low Level Output
Voltage
TTL Loads
-
V
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
V
5.2
-
V
Input Leakage
Current
I
V
or
6
µA
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
NOTE: For dual-supply systems theoretical worst case (V = 2.4V, V
= 5.5V) specification is 1.8mA.
I
CC
3
CD74HC4015
Prerequisite for Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
Maximum Clock
SYMBOL
f
V
(V)
MIN
6
MAX
MIN
5
MAX
MIN
4
MAX
UNITS
MHz
MHz
MHz
ns
CC
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
Frequency
4.5
30
35
80
16
14
150
30
26
50
10
9
24
28
100
20
17
190
38
33
65
13
11
75
15
13
0
20
24
120
24
20
225
45
38
75
15
13
90
18
15
0
6
2
Clock Pulse Width
t
t
W
W
4.5
6
ns
ns
MR Pulse Width
2
ns
4.5
6
ns
ns
MR Recovery Time
t
2
ns
REC
4.5
6
ns
ns
Set-up Time,
Data-In to CP
t
t
2
60
12
10
0
ns
SUL, SUH
4.5
6
ns
ns
Hold Time,
Data-In to CP
t
2
ns
H
4.5
6
0
0
0
ns
0
0
0
ns
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
MIN TYP MAX
-40 C TO 85 C -55 C TO 125 C
TEST
SYMBOL CONDITIONS
V
CC
(V)
PARAMETER
MIN
MAX
220
44
-
MIN
MAX UNITS
Propagation Delay (Figure 1)
t
t
t
C = 50pF
2
4.5
5
-
-
-
-
-
-
-
-
175
35
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
270
54
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
MHz
pF
PLH,
L
t
PHL
Clock to Q
n
C =15pF
14
-
L
C = 50pF
6
30
275
55
-
37
345
64
-
46
415
83
-
L
MR to Q , (Clock High)
C = 50pF
2
-
n
PLH,
L
t
PHL
4.5
-
C =15pF
25
-
L
C = 50pF
6
2
-
-
-
47
325
65
-
54
400
81
-
71
490
98
-
L
MR to Q , (Clock Low)
n
C = 50pF
-
PLH,
L
t
PHL
4.5
-
C =15pF
25
-
L
C = 50pF
6
2
-
-
-
-
-
-
-
55
75
15
13
10
-
69
95
19
16
10
-
83
110
22
19
10
-
L
Output Transition Time
(Figure 1)
t
, t
C = 50pF
-
TLH THL
L
4.5
6
-
-
Input Capacitance
C
C = 50pF
-
-
IN
L
Maximum Clock Frequency
f
C =15pF
5
60
43
MAX
L
Power Dissipation
Capacitance
(Notes 4, 5)
C
C =15pF
5
-
-
-
PD
L
NOTES:
4. C
is used to determine the dynamic power consumption, per shift register.
PD
5. P = V
2
2
f + ∑ C
V
where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
CC
i
L
CC
i
L
4
CD74HC4015
Test Circuit and Waveform
t C
t C
f
L
r
L
V
CC
90%
10%
CLOCK
INPUT
50%
GND
t
t
H(H)
H(L)
V
CC
DATA
INPUT
50%
GND
t
t
SU(H)
SU(L)
t
t
90%
50%
TLH
THL
90%
OUTPUT
10%
t
t
PHL
PLH
t
REM
V
CC
SET, RESET
OR PRESET
50%
GND
IC
C
L
50pF
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED
SEQUENTIAL LOGIC CIRCUITS
5
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