BQ51003YFPT [TI]
Highly Integrated Wireless Receiver Qi (WPC v1.1) Compliant Power Supply; 高度集成的无线接收器齐（ WPC V1.1 ）标准电源
| 型号： | BQ51003YFPT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Highly Integrated Wireless Receiver Qi (WPC v1.1) Compliant Power Supply |
| 文件： | 总34页 (文件大小：2162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq51003
www.ti.com
SLUSBC8 –DECEMBER 2013
Highly Integrated Wireless Receiver Qi (WPC v1.1) Compliant Power Supply
Check for Samples: bq51003
1
FEATURES
DESCRIPTION
The bq51003 is an advanced, integrated, receiver IC
for wireless power transfer in portable applications.
The device provides the AC/DC power conversion
while integrating the digital control required to comply
with the Qi v1.1 communication protocol. Together
with the bq500210 transmitter controller, the bq51003
•
Integrated Wireless Power Supply Receiver
Solution - Optimized for 2.5-W Applications
–
–
–
93% Overall Peak AC-DC Efficiency
Full Synchronous Rectifier
WPC v1.1 Compliant Communication
Control
enables
a complete contact-less power transfer
system for a wireless power supply solution. By using
near-field inductive power transfer, the receiver coil
embedded in the portable device receives the power
transmitted by the transmitter coil via mutually
coupled inductors. The AC signal from the receiver
coil is then rectified and regulated to be used as a
power supply for down-system electronics. Global
feedback is established from the secondary to the
transmitter in order to stabilize the power transfer
process via back-scatter modulation. This feedback is
established by using the Qi v1.1 communication
protocol supporting up to 2.5-W applications.
–
–
Output Voltage Conditioning
Only IC Required Between Rx coil and
Output
•
Wireless Power Consortium (WPC) v1.1
Compliant (FOD Enabled) Highly Accurate
Current Sense
•
•
Dynamic Rectifier Control for Improved Load
Transient Response
Dynamic Efficiency Scaling for Optimized
Performance Over wide Range of Output
Power
The device integrates
a
low-impedance full
synchronous rectifier, low-dropout regulator, digital
control, and accurate voltage and current loops.
•
Adaptive Communication Limit for Robust
Communication
•
•
Supports 20-V Maximum Input
Power
bq51003
Low-power Dissipative Rectifier Overvoltage
Clamp (VRECT-OVP = 15 V)
Voltage
Conditioning
AC to DC
Drivers
Rectification
Load
Communication
•
•
Thermal Shutdown
Multifunction NTC and Control Pin for
Temperature Monitoring, Charge Complete and
Fault Host Control
Controller
V/I
Sense
Controller
bq500210
Transmitter
•
1.9-mm x 3.0-mm DSBGA
Receiver
APPLICATIONS
Figure 1. Wireless Power Consortium (WPC or
Qi) Inductive Power System
•
•
•
•
•
•
WPC Compliant Receivers
Cell Phones, Smart Phones
Headsets
Digital Cameras
Portable Media Players
Hand-held Devices
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
bq51003
SLUSBC8 –DECEMBER 2013
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ORDERING INFORMATION
ORDERING NUMBER
(Tape and Reel)
PART NUMBER
MARKING
bq51003
FUNCTION
PACKAGE
QUANTITY
bq51003YFPR
bq51003YFPT
3000
250
bq51003
5V Regulated Power Supply
DSBGA-YFP
AVAILABLE OPTIONS
OVER
CURRENT
SHUTDOWN
WPC
VERSION
COMMUNICATION
DEVICE
FUNCTION
VRECT-OVP VOUT-(REG)
AD-OVP
TERMINATION
CURRENT LIMIT(1)(2)
5-V Power
Supply
bq51003
v1.1
15 V
5 V
Disabled
Disabled
Disabled
Adaptive + 1 s Hold-Off
(1) Enabled if EN2 is low and disabled if EN2 is high
(2) Communication current limit is disabled for 1 second at startup
ABSOLUTE MAXIMUM RATINGS(1)(2)
over operating free-air temperature range (unless otherwise noted)
VALUES
UNITS
MIN
MAX
AC1, AC2
–0.8
20
V
V
RECT, COMM1, COMM2, OUT, CHG, CLAMP1,
CLAMP2
–0.3
20
Input voltage
AD, AD-EN
–0.3
-0.3
–0.3
30
26
7
V
V
BOOT1, BOOT2
EN1, EN2, FOD, TS-CTRL, ILIM
AC1, AC2
V
Input current
1
A(RMS)
mA
mA
A
Output current
OUT
525
15
1
CHG
Output sink current
COMM1, COMM2
Junction temperature, TJ
Storage temperature, TSTG
–40
–65
2
150
150
°C
°C
Human Body Model (HBM)
Charge Device Model (CDM)
kV
ESD Rating (100 pF, 1.5 kΩ)
500
V
(1) All voltages are with respect to the VSS terminal, unless otherwise noted.
(2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
YFP
THERMAL METRIC(1)
UNITS
28 PINS
58.9
0.2
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
9.1
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.4
ψJB
8.9
θJCbot
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLUSBC8 –DECEMBER 2013
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
VIN
Input voltage range
Input Current
RECT
RECT
OUT
4
10
500
500
1
V
IIN
mA
mA
mA
mA
°C
IOUT
IAD-EN
ICOMM
TJ
Output Current
Sink Current
AD-EN
COMM
COMM Sink Current
Junction Temperature
500
125
0
TYPICAL APPLICATION SCHEMATICS
/AD-EN
System
Load
AD
OUT
CCOMM1
CBOOT1
C4
COMM1
BOOT1
AC1
ROS1
D1
ROS2
RECT
C1
R4
C3
HOST
bq51003
COIL
C2
TS-CTRL
AC2
NTC
BOOT2
COMM2
CBOOT2
/CHG
Tri-State
CCOMM2
CCLAMP2
CCLAMP1
Bi-State
Bi-State
CLAMP2
CLAMP1
ILIM
EN1
EN2
PGND
FOD
R1
RFOD
Figure 2. bq51003 Used as a Wireless Power Receiver and Power Supply for System Loads
Only One of ROS1 or ROS2 Needed
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System
Load
Q1
USB or
AC Adapter
Input
/AD-EN
AD
OUT
CCOMM1
CBOOT1
C4
COMM1
BOOT1
AC1
C5
ROS1
D1
ROS2
RECT
C1
R4
C3
bq51003
COIL
C2
TS-CTRL
AC2
NTC
BOOT2
COMM2
CBOOT2
HOST
/CHG
Tri-State
CCOMM2
CCLAMP2
CCLAMP1
CLAMP2
CLAMP1
ILIM
EN1
EN2
Bi-State
Bi-State
PGND
FOD
R1
RFOD
Figure 3. bq51003 Used as a Wireless Power Receiver and Power Supply for System Loads with Adapter
Power-Path Multiplexing
Only One of ROS1 or ROS2 Needed
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, 0°C to 125°C (unless otherwise noted)
PARAMETER
Undervoltage lock-out
Hysteresis on UVLO
TEST CONDITIONS
VRECT: 0 V → 3 V
MIN
TYP
2.7
MAX
UNIT
V
UVLO
2.6
2.8
VRECT: 3 V → 2 V
250
150
15
mV
mV
V
VHYS
Hysteresis on OVP
VRECT: 16 V → 5 V
VRECT-OVP
Input overvoltage threshold
Dynamic VRECT threshold 1
VRECT: 5 V → 16 V
14.5
15.5
ILOAD < 0.1 x IIMAX (ILOAD rising)
7.08
0.1 x IIMAX < ILOAD < 0.2 x IIMAX
(ILOAD rising)
Dynamic VRECT threshold 2
6.28
V
0.2 x IIMAX < ILOAD < 0.4 x IIMAX
(ILOAD rising)
VRECT-REG
Dynamic VRECT threshold 3
Dynamic VRECT threshold 4
VRECT TRACKING
5.53
5.11
ILOAD > 0.4 x IIMAX (ILOAD rising)
In current limit voltage above
VOUT
VO+0.25
ILOAD hysteresis for dynamic VRECT
thresholds as a % of IILIM
ILOAD
ILOAD falling
4%
3.1
8
Rectifier undervoltage protection, restricts
IOUT at VRECT-DPM
VRECT-DPM
VRECT-REV
3
3.2
9
V
V
Rectifier reverse voltage protection at the
output
VRECT-REV = VOUT - VRECT
VOUT = 10 V
,
QUIESCENT CURRENT
ILOAD = 0 mA, 0°C ≤ TJ ≤ 85°C
8
2
10
mA
mA
Active chip quiescent current consumption
from RECT
IRECT
ILOAD = 300 mA,
0°C ≤ TJ ≤ 85°C
3.0
Quiescent current at the output when
wireless power is disabled (Standby)
IOUT
VOUT = 5 V, 0°C ≤ TJ ≤ 85°C
20
35
µA
ILIM SHORT CIRCUIT
Highest value of ILIM resistor considered a
RILIM: 200 Ω → 50 Ω. IOUT
latches off, cycle power to reset
RILIM
120
Ω
fault (short). Monitored for IOUT > 100 mA
Deglitch time transition from ILIM short to IOUT
disable
tDGL
1
ms
ILIM-SHORT,OK enables the ILIM short
comparator when IOUT is greater than this
value
ILOAD: 0 mA → 200 mA
ILOAD: 0 mA → 200 mA
120
145
30
165
mA
mA
A
ILIM_SC
Hysteresis for ILIM-SHORT,OK comparator
Maximum ILOAD that will be
delivered for 1 ms when ILIM is
shorted
IOUT
Maximum output current limit, CL
2.45
OUTPUT
ILOAD = 500 mA
ILOAD = 10 mA
4.96
4.97
5.00
5.01
5.04
5.05
VOUT-REG
Regulated output voltage
V
RLIM = KILIM / IILIM, where IILIM is
the hardware current limit.
IOUT = 500 mA
Current programming factor for hardware
protection
KILIM
303
314
321
AΩ
IIMAX = KIMAX / RLIM where IMAX
is the maximum normal
operating current.
Current programming factor for the nominal
operating current
KIMAX
262
IOUT = 500 mA
AΩ
mA
mA
mA
IOUT
Current limit programming range
750
425
IOUT > 300 mA
IOUT < 300 mA
IOUT + 50
378
ICOMM
Current limit during WPC communication
343
Hold off time for the communication current
limit during startup
tHOLD
1
s
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, 0°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TS / CTRL
ITS-Bias < 100 µA (periodically
driven see tTS-CTRL)
VTS
Internal TS bias voltage
2
2.2
2.4
V
Rising threshold
VTS: 50% → 60%
56.5
58.7
2
60.8
VCOLD
Falling hysteresis
VTS: 60% → 50%
%VTS-Bias
Falling threshold
VTS: 20% → 15%
18.5
19.6
3
20.7
VHOT
Rising hysteresis
VTS: 15% → 20%
CTRL pin threshold for a high
CTRL pin threshold for a low
VTS-CTRL: 50 → 150 mV
VTS-CTRL: 150 → 50 mV
80
50
100
80
130
100
mV
mV
VCTRL
Time VTS-Bias is active when TS
measurements occur
Synchronous to the
communication period
tTS-CTRL
tTS
24
10
20
ms
ms
kΩ
Deglitch time for all TS comparators
Pull-up resistor for the NTC network. Pulled
up to the voltage bias.
RTS
18
22
THERMAL PROTECTION
Thermal shutdown temperature
Thermal shutdown hysteresis
OUTPUT LOGIC LEVELS ON CHG
155
20
°C
°C
TJ
VOL
Open drain CHG pin
ISINK = 5 mA
VCHG = 20 V
500
1
mV
µA
IOFF
CHG leakage current when disabled
COMM PIN
RDS(ON)
fCOMM
COMM1 and COMM2
VRECT = 2.6 V
1.5
Ω
Signaling frequency on COMM pin
Comm pin leakage current
2.00
Kb/s
µA
IOFF
VCOMM1 = 20 V, VCOMM2 = 20 V
1
CLAMP PIN
RDS(ON)
CLAMP1 and CLAMP2
0.8
Ω
ADAPTER ENABLE
VAD rising threshold voltage. EN-UVLO
VAD 0 V → 5 V
3.5
3.6
3.8
V
VAD-EN
IAD
RAD
VAD-EN hysteresis, EN-HYS
VAD 5 V → 0 V
400
mV
μA
Input leakage current
VRECT = 0 V, VAD = 5 V
60
Pull-up resistance from AD-EN to OUT when
adapter mode is disabled and VOUT > VAD
EN-OUT
,
VAD = 0 V, VOUT = 5 V
200
4.5
350
Ω
Voltage difference between VAD and VAD-EN
when adapter mode is enabled, EN-ON
VAD
VAD = 5 V, 0°C ≤ TJ ≤ 85°C
3
5
V
SYNCHRONOUS RECTIFIER
IOUT at which the synchronous rectifier
ILOAD : 200 mA → 0 mA
ILOAD : 0 mA → 200 mA
80
100
25
130
mA
mA
V
enters half synchronous mode, SYNC_EN
IOUT
Hysteresis for IOUT,RECT-EN (full-synchronous
mode enabled)
IAC-VRECT = 250 mA and
TJ = 25°C
High-side diode drop when the rectifier is in
half synchronous mode
VHS-DIODE
0.7
EN1 AND EN2
VIL
Input low threshold for EN1 and EN2
Input high threshold for EN1 and EN2
EN1 and EN2 pull down resistance
0.4
V
V
VIH
RPD
1.3
200
0%
kΩ
ADC (WPC Related Measurements and Coefficients)
Accuracy of the current sense over the load
IOUT SENSE
range
IOUT = 300 mA - 500 mA
–1.5%
0.9%
6
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SLUSBC8 –DECEMBER 2013
DEVICE INFORMATION
SIMPLIFIED BLOCK DIAGRAM
M1
RECT
,
OUT
VOUT,FB
VREF,ILIM
_
+
_
VILIM
+ VOUT,REG
VREF,IABS
VIABS,FB
+
_
ILIM
VIN,FB
+
_
VIN,DPM
AD
+
_
VREFAD,OVP
BOOT2
BOOT1
_
+
VREFAD,UVLO
/AD-EN
AC1
AC2
Sync
Rectifier
Control
VREF,TS-BIAS
VFOD
FOD
+
_
COMM1
COMM2
+
_
TS_COLD
TS_HOT
VBG,REF
VIN,FB
VOUT,FB
VILIM
+
_
DATA_
OUT
VIABS,FB
ADC
TS-CTRL
CLAMP1
CLAMP2
VIABS,REF
VIC,TEMP
VFOD
+
_
TS_DETECT
VREF_100MV
Digital Control
50uA
+
_
ILIM
/CHG
EN1
EN2
200k:
200k:
VRECT
VOVP,REF
+
_
OVP
PGND
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YFP Package
(TOP VIEW)
A1
A2
A3
A4
PGND
PGND
PGND
PGND
B1
B2
B3
B4
AC2
AC2
AC1
AC1
C1
C2
C3
C4
BOOT2
RECT
RECT
BOOT1
D1
D2
D3
D4
OUT
OUT
OUT
OUT
E2
CLAMP2
E3
CLAMP1
E4
COMM1
E1
COMM2
F1
F2
F3
F4
TS-CTRL
FOD
/AD-EN
/CHG
G1
ILIM
G2
EN2
G3
EN1
G4
AD
PIN FUNCTIONS
NAME
AC1
YFP
B3, B4
B1, B2
C4
I/O
I
DESCRIPTION
AC input from receiver coil antenna.
AC2
I
BOOT1
BOOT2
O
O
Bootstrap capacitors for driving the high-side FETs of the synchronous rectifier. Connect a 10 nF ceramic
capacitor from BOOT1 to AC1 and from BOOT2 to AC2.
C1
Filter capacitor for the internal synchronous rectifier. Connect a ceramic capacitor to PGND. Depending on
the power levels, the value may be 4.7 μF to 22 μF.
RECT
C2, C3
O
D1, D2,
D3, D4
OUT
O
O
Output pin, delivers power to the load.
COMM1
E4
E1
E2
E3
Open-drain output used to communicate with primary by varying reflected impedance. Connect COMM1
through a capacitor to either AC1 or AC2 for capacitive load modulation (COMM2 must be connected to the
alternate AC1 or AC2 pin). For resistive modulation connect COMM1 and COMM2 to RECT via a single
resistor; connect through separate capacitors for capacitive load modulation.
COMM2
CLAMP2
CLAMP1
O
O
O
Open drain FETs which are utilized for a non-power dissipative over-voltage AC clamp protection. When the
RECT voltage goes above 15 V, both switches will be turned on and the capacitors will act as a low
impedance to protect the IC from damage. If used, CLAMP1 is required to be connected to AC1, and
CLAMP2 is required to be connected to AC2 via 0.47 µF capacitors.
A1, A2,
A3, A4
PGND
Power ground
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NAME
SLUSBC8 –DECEMBER 2013
PIN FUNCTIONS (continued)
YFP
I/O
DESCRIPTION
Programming pin for the over current limit. Connect external resistor to VSS. Size RILIM with the following
equation: RILIM = 250 / IMAX where IMAX is the expected maximum output current of the wireless power
supply. The hardware current limit (IILIM) will be 20% greater than IMAX or 1.2 x IMAX. If the supply is meant to
operate in current limit use
ILIM
G1
I/O
RILIM = 314 / IILIM
RILIM = R1 + RFOD
Connect this pin to the wired adapter input. When a voltage is applied to this pin wireless charging is
disabled and AD_EN is driven low. Connect to GND through a 1 µF capacitor. If unused, capacitor is not
required and should be grounded directly.
AD
G4
F3
I
Push-pull driver for external PFET connecting AD and OUT. This node is pulled to the higher of OUT and
AD when turning off the external FET. This voltage tracks approximately 4 V below AD when voltage is
present at AD and provides a regulated VGS bias for the external FET. Float this pin if unused.
AD-EN
O
Must be connected to ground via a resistor. If an NTC function is not desired connect to GND with a 10-kΩ
resistor. As a CTRL pin pull to ground to send end power transfer (EPT) fault to the transmitter or pull-up to
an internal rail (i.e. 1.8 V) to send EPT termination to the transmitter. Note that a 3-state driver should be
used to interface this pin (see the 3-state Driver section for further description).
TS-CTRL
F1
I
EN1
EN2
G3
G2
I
I
Inputs that allow user to enable/disable wireless and wired charging <EN1 EN2>:
<00> Wireless charging is enabled
<01> Dynamic communication current limit disabled
<10> Wireless charging disabled
<11> Wireless charging disabled.
FOD
CHG
F2
F4
I
Input for the recieved power measurement. Connect to GND with a RFOD resistor.
Open-drain output – Active when the output of the wireless power supply is enabled.
O
Spacer
TYPICAL CHARACTERISTICS
100
90
80
70
60
50
40
80
70
60
50
40
30
20
10
RILIM = 524
-
0
0.5
1
1.5
2
2.5
3
0.000
0.500
1.000
1.500
2.000
2.500
Power (W)
Power (W)
C006
C001
Figure 4. Rectifier Efficiency
Figure 5. System Efficiency from DC Input to DC Output
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TYPICAL CHARACTERISTICS (continued)
80%
70%
60%
50%
40%
30%
20%
10%
0%
7.5
Load Current Rising
Load Current Falling
7
6.5
6
RILIM = 524
5.5
RILIM = 524
RILIM = 1048
5
0.00
0.50
1.00
1.50
2.00
2.50
0
0.1
0.2
0.3
0.4
0.5
0.6
Power (W)
Load Current (A)
C002
C003
Figure 6. Light Load System Efficiency Improvement Due to
Dynamic Efficiency Scaling Feature
Figure 7. VRECT vs. ILOAD at RILIM = 524 Ω
7.5
5.025
5.020
5.015
5.010
5.005
5.000
RILIM = 524
RILIM = 1048
7
6.5
6
5.5
Increasing Load Current
5
0
0.1
0.2
0.3
0.4
0.5
0.6
0
0.1
0.2
0.3
0.4
0.5
0.6
Load Current (A)
Output Current (A)
C004
C005
Figure 8. VRECT vs. ILOAD at RILIM = 524 Ω and 1048 Ω
Figure 9. ILOAD Sweep (I-V Curve)
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TYPICAL CHARACTERISTICS (continued)
60
50
40
30
20
10
0
5.004
5.002
5.000
4.998
0
20
40
60
80
100
120
0
0.1
0.2
0.3
0.4
0.5
0.6
Temperature (°C)
Load Current (A)
C007
Figure 10. Output Ripple vs. ILOAD (COUT = 1 µF) without
Communication
Figure 11. VOUT vs Temperature
Figure 12. 0.5-A Instantaneous Load Dump
Figure 13. 0.5-A Load Step Full System Response
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TYPICAL CHARACTERISTICS (continued)
VRECT
VOUT
Figure 14. 0.5-A Load Dump Full System Response
Figure 15. Rectifier Overvoltage Clamp (fop = 110 kHz)
VTS/CTRL
VRECT
Figure 16. TS Fault
Figure 17. Typical Startup with a 0.5-A System Load
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TYPICAL CHARACTERISTICS (continued)
IOUT
IOUT
VRECT
VRECT
VOUT
VOUT
Figure 18. Adaptive Communication Limit Event Where the
400-mA Current Limit is Enabled (IOUT-DC < 300 mA)
Figure 19. Adaptive Communication Limit Event Where the
Current Limit is IOUT + 50 mA (IOUT-DC > 300 mA)
Figure 20. Rx Communication Packet Structure
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PRINCIPLE OF OPERATION
Power
bq51003
Voltage
Conditioning
AC to DC
Drivers
Rectification
Load
Communication
Controller
V/I
Sense
Controller
bq500210
Transmitter
Receiver
Figure 21. WPC Wireless Power System Indicating the Functional Integration of the bq51003
A Brief Description of the Wireless System:
A wireless system consists of a charging pad (transmitter or primary) and the secondary-side equipment
(receiver or secondary). There is a coil in the charging pad and in the secondary equipment which are
magnetically coupled to each other when the secondary is placed on the primary. Power is then transferred from
the transmitter to the receiver via coupled inductors (e.g. an air-core transformer). Controlling the amount of
power transferred is achieved by sending feedback (error signal) communication to the primary (that is, to
increase or decrease power).
The receiver communicates with the transmitter by changing the load seen by the transmitter. This load variation
results in a change in the transmitter coil current, which is measured and interpreted by a processor in the
charging pad. The communication is digital - packets are transferred from the receiver to the transmitter.
Differential Bi-phase encoding is used for the packets. The bit rate is 2-kbps.
Various types of communication packets have been defined. These include identification and authentication
packets, error packets, control packets, end power packets, and power usage packets.
The transmitter coil stays powered off most of the time. It occasionally wakes up to see if a receiver is present.
When a receiver authenticates itself to the transmitter, the transmiter will remain powered on. The receiver
maintains full control over the power transfer using communication packets.
Using the bq51003 as a Wireless Power Supply: (See Figure 2)
Figure 2 is the schematic of a system which uses the bq51003 as a power supply.
When the system shown in Figure 2 is placed on the charging pad, the receiver coil is inductively coupled to the
magnetic flux generated by the coil in the charging pad which consequently induces a voltage in the receiver coil.
The internal synchronous rectifier feeds this voltage to the RECT pin which has the filter capacitor C3.
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The bq51003 identifies and authenticates itself to the primary using the COM pins by switching on and off the
COM FETs and hence switching in and out CCOMM. If the authentication is successful, the transmitter will remain
powered on. The bq51003 measures the voltage at the RECT pin, calculates the difference between the actual
voltage and the desired voltage VRECT-REG, (threshold 1 at no load) and sends back error packets to the primary.
This process goes on until the input voltage settles at VRECT-REG. During a load transient, the dynamic rectifier
algorithm will set the targets specified by VRECT-REG thresholds 1, 2, 3, and 4. This algorithm is termed Dynamic
Rectifier Control and is used to enhance the transient response of the power supply.
During power-up, the LDO is held off until the VRECT-REG threshold 1 converges. The voltage control loop ensures
that the output voltage is maintained at VOUT-REG to power the system. The bq51003 meanwhile continues to
monitor the input voltage, and maintains sending error packets to the primary every 250 ms. If a large overshoot
occurs, the feedback to the primary speeds up to every 32 ms in order to converge on an operating point in less
time.
Details of a Qi Wireless Power System and bq51003 Power Transfer Flow Diagrams
The bq51003 integrates a fully compliant WPC v1.1 communication algorithm in order to streamline receiver
designs (no extra software development required). Other unique algorithms such as Dynamic Rectifier Control
are also integrated to provide best-in-class system performance. This section provides a high level overview of
these features by illustrating the wireless power transfer flow diagram from startup to active operation.
During startup operation, the wireless power receiver must comply with proper handshaking to be granted a
power contract from the Tx. The Tx will initiate the hand shake by providing an extended digital ping. If an Rx is
present on the Tx surface, the Rx will then provide the signal strength, configuration and identification packets to
the Tx (see volume 1 of the WPC specification for details on each packet). These are the first three packets sent
to the Tx. The only exception is if there is a true shutdown condition on the EN1/EN2, AD, or TS-CTRL pins
where the Rx will shut down the Tx immediately. See Table 4 for details. Once the Tx has successfully received
the signal strength, configuration and identification packets, the Rx will be granted a power contract and is then
allowed to control the operating point of the power transfer. With the use of the bq51003 Dynamic Rectifier
Control algorithm, the Rx will inform the Tx to adjust the rectifier voltage above 7 V prior to enabling the output
supply. This method enhances the transient performance during system startup. See Figure 22 for the startup
flow diagram details.
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Tx Powered
without Rx
Active
Tx Extended Digital Ping
Yes
Send EPT packet with
reason value
EN1/EN2/TS-CTRL
EPT Condition?
No
No
Identification and
Configuration and SS,
Received by Tx?
Yes
Power Contract
Established. All
proceeding control is
dictated by the Rx.
Yes
Send control error packet
to increase VRECT
VRECT< 7V?
No
Startup operating point
established. Enable the
Rx output.
Rx Active
Power Transfer
Stage
Figure 22. Wireless Power Startup Flow Diagram
Once the startup procedure has been established, the Rx will enter the active power transfer stage. This is
considered the “main loop” of operation. The Dynamic Rectifier Control algorithm will determine the rectifier
voltage target based on a percentage of the maximum output current level setting (set by KIMAX and the ILIM
resistance to GND). The Rx will send control error packets in order to converge on these targets. As the output
current changes, the rectifier voltage target will dynamically change. As a note, the feedback loop of the WPC
system is relatively slow where it can take up to 90 ms to converge on a new rectifier voltage target. It should be
understood that the instantaneous transient response of the system is open loop and dependent on the Rx coil
output impedance at that operating point. More details on this will be covered in the section Receiver Coil Load-
Line Analysis. The “main loop” will also determine if any conditions in Table 4 are true in order to discontinue
power transfer. See Figure 23 which illustrates the active power transfer loop.
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Rx Active
Power Transfer
Stage
Rx Shutdown
conditions per the EPT
Table?
Tx Powered
without Rx
Active
Yes
Send EPT packet with
reason value
No
VRECT target= 7V. Send
control error packets to
converge.
Yes
IOUT< 10% of IMAX?
No
VRECT target= 6.3V.
Send control error packets
to converge.
Yes
Yes
IOUT< 20% of IMAX?
No
VRECT target= 5.5V.
Send control error packets
to converge.
IOUT< 40% of IMAX?
No
VRECT target= 5.1V.
Send control error packets
to converge.
Measure Rectified Power
and Send Value to Tx
Figure 23. Active Power Transfer Flow Diagram
Another requirement of the WPC v1.1 specification is to send the measured recieved power. This task is enabled
on the IC by measuring the voltage on the FOD pin which is proportional to the output current and can be scaled
based on the choice of the resitor to ground on the FOD pin.
Dynamic Rectifier Control
The Dynamic Rectifier Control algorithm offers the end system designer optimal transient response for a given
max output current setting. This is achieved by providing enough voltage headroom across the internal regulator
at light loads in order to maintain regulation during a load transient. The WPC system has a relatively slow global
feedback loop where it can take more than 90 ms to converge on a new rectifier voltage target. Therefore, the
transient response is dependent on the loosely coupled transformers output impedance profile. The Dynamic
Rectifier Control allows for a 2 V change in rectified voltage before the transient response will be observed at the
output of the internal regulator (output of the bq51003).
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Dynamic Efficiency Scaling
The Dynamic Efficiency Scaling feature allows for the loss characteristics of the bq51003 to be scaled based on
the maximum expected output power in the end application. This effectively optimizes the efficiency for each
application. This feature is achieved by scaling the loss of the internal LDO based on a percentage of the
maximum output current. Note that the maximum output current is set by the KIMAX term and the RILIM resistance
(where RILIM = KIMAX / IMAX). The flow diagram show in Figure 23 illustrates how the rectifier is dynamically
controlled (Dynamic Rectifier Control) based on a fixed percentage of the IMAX setting. Table 1 summarizes how
the rectifier behavior is dynamically adjusted based on two different RILIM settings.
Table 1.
OUTPUT CURRENT
PERCENTAGE
RILIM = 1116 Ω
IMAX = 250 mA
RILIM = 488 Ω
IMAX = 500 mA
VRECT
0 to 10%
10 to 20%
20 to 40%
>40%
0 A to 0.025 A
0.025 A to 0.050 A
0.050 A to 0.100 A
> 0.100 A
0 A to 0.05 A
0.050 A to 0.100 A
0.100 A to 0.200 A
> 0.200 A
7.08 V
6.28 V
5.53 V
5.11 V
Figure 8 illustrates the shift in the Dynamic Rectifier Control behavior based on the two different RILIM settings.
With the rectifier voltage (VRECT) being the input to the internal LDO, this adjustment in the Dynamic Rectifier
Control thresholds will dynamically adjust the power dissipation across the LDO where:
P
= V
(
- V
× I
)
OUT OUT
DIS
RECT
(1)
Figure 6 illustrates how the system efficiency is improved due to the Dynamic Efficiency Scaling feature. Note
that this feature balances efficiency with optimal system transient response.
RILIM Calculations
The bq51003 includes a means of providing hardware overcurrent protection by means of an analog current
regulation loop. The hardware current limit provides an extra level of safety by clamping the maximum allowable
output current (that is, a current compliance). The RILIM resistor size also sets the thresholds for the dynamic
rectifier levels and thus providing efficiency tuning per each application’s maximum system current. The
calculation for the total RILIM resistance is as follows:
262
RILIM
=
IMAX
314
I
ILIM =1.2´IMAX
=
RILIM
R
ILIM = R1 + RFOD
(2)
Where IMAX is the expected maximum output current during normal operation and IILIM is the hardware over
current limit. When referring to the application diagram shown in Figure 2, RILIM is the sum of RFOD and the R1
resistance (that is, the total resistance from the ILIM pin to GND).
Input Overvoltage
If the input voltage suddenly increases in potential (that is, due to a change in position of the equipment on the
charging pad), the voltage-control loop inside the bq51003 becomes active, and prevents the output from going
beyond VOUT-REG. The receiver then starts sending back error packets to the transmitter every 30 ms until the
input voltage comes back to the VRECT-REG target, and then maintains the error communication every 250 ms.
If the input voltage increases in potential beyond VRECT-OVP, the IC switches off the LDO and communicates to
the primary to bring the voltage back to VRECT-REG. In addition, a proprietary voltage protection circuit is activated
by means of CCLAMP1 and CCLAMP2 that protects the IC from voltages beyond the maximum rating of the IC (that
is, 20 V).
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Adapter Enable Functionality and EN1/EN2 Control
Figure 3 is an example application that shows the bq51003 used as a wireless power receiver that can power
mutliplex between wired or wireless power for the down-system electronics. In the default operating mode pins
EN1 and EN2 are low, which activates the adapter enable functionality. In this mode, if an adapter is not present
the AD pin will be low, and AD-EN pin will be pulled to the higher of the OUT and AD pins so that the PMOS
between OUT and AD will be turned off. If an adapter is plugged in and the voltage at the AD pin goes above 3.6
V then wireless charging is disabled and the AD-EN pin will be pulled approximately 4 V below the AD pin to
connect AD to the secondary charger. The difference between AD and AD-EN is regulated to a maximum of 7 V
to ensure the VGS of the external PMOS is protected.
The EN1 and EN2 pins include internal 200-kΩ pull-down resistors, so that if these pins are not connected
bq51003 defaults to AD-EN control mode. However, these pins can be pulled high to enable other operating
modes as described in Table 2:
Table 2.
EN1
EN2
RESULT
Adapter control enabled. If adapter is present then secondary charger is powered by adapter, otherwise wireless
charging is enabled when wireless power is available. Communication current limit is enabled.
0
0
1
1
0
1
0
1
Disables communication current limit.
AD-EN is pulled low, whether or not adapter voltage is present. This feature can be used, e.g., for USB OTG
applications.
Adapter and wireless charging are disabled, i.e., power will never be delivered by the OUT pin in this mode.
Table 3.
WIRELESS
POWER
ADAPTIVE COMMUNICATION
LIMIT
EN1
EN2
WIRED POWER
OTG MODE
EPT
0
0
1
1
0
1
0
1
Enabled
Priority(1)
Disabled
Disabled
Priority(1)
Enabled
Enabled
Disabled
Disabled
Disabled
Enabled(2)
Disabled
Enabled
Disabled
N/A
Not Sent to Tx
Not Sent to Tx
No Response
Termination
N/A
(1) If both wired and wireless power are present, wired power is given priority.
(2) Allows for a boost-back supply to be driven from the output terminal of the Rx to the adapter port via the external back-to-back PMOS
FET.
As described in Table 3, pulling EN2 high disables the adapter mode and only allows wireless charging. In this
mode the adapter voltage will always be blocked from the OUT pin. An application example where this mode is
useful is when USB power is present at AD, but the USB is in suspend mode so that no power can be taken from
the USB supply. Pulling EN1 high enables the off-chip PMOS regardless of the presence of a voltage. This
function can be used in USB OTG mode to allow a charger connected to the OUT pin to power the AD pin.
Finally, pulling both EN1 and EN2 high disables both wired and wireless charging.
NOTE
It is required to connect a back-to-back PMOS between AD and OUT so that voltage is
blocked in both directions. Also, when AD mode is enabled no load can be pulled from the
RECT pin as this could cause an internal device overvoltage in bq51003.
End Power Transfer Packet (WPC Header 0x02)
The WPC allows for a special command for the receiver to terminate power transfer from the transmitter termed
End Power Transfer (EPT) packet. Table 4 specifies the v1.1 reasons column and their corresponding data field
value. The condition column corresponds to the methodology used by bq51003 to send equivalent message.
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Table 4.
MESSAGE
VALUE
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
CONDITION
Charge Complete
Internal Fault
TS-CTRL = 1, or EN1 = 1, or <EN1 EN2> = <11>
TJ > 150°C or RILIM < 100 Ω
Over Temperature
Over Voltage
TS < VHOT, TS > VCOLD, or TS-CTRL < 100 mV
Not Sent
NOT USED
Over Current
Battery Failure
Reconfigure
Not Sent
Not Sent
No Response
VRECT target does not converge
Status Outputs
The bq51003 has one status output, CHG. This output is an open-drain NMOS device that is rated to 20 V. The
open-drain FET connected to the CHG pin will be turned on whenever the output of the power supply is enabled.
Please note, the output of the power supply will not be enabled if the VRECT-REG does not converge at the no-load
target voltage.
WPC Communication Scheme
The WPC communication uses a modulation technique termed “backscatter modulation” where the receiver coil
is dynamically loaded in order to provide amplitude modulation of the transmitter's coil voltage and current. This
scheme is possible due to the fundamental behavior between two loosely coupled inductors (that is, between the
Tx and Rx coil). This type of modulation can be accomplished by switching in and out a resistor at the output of
the rectifier, or by switching in and out a capacitor across the AC1/AC2 net. Figure 24 shows how to implement
resistive modulation.
CRES1
AC1
VRECT
RMOD
COIL
CRES2
AC2
GND
Figure 24. Resistive Modulation
Figure 25 shows how to implement capacitive modulation.
CRES1
AC1
VRECT
CMOD
COIL
CRES2
AC2
GND
Figure 25. Capacitive Modulation
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The amplitude change in Tx coil voltage or current can be detected by the transmitters decoder. The resulting
signal observed by the Tx is shown in Figure 26.
Power
bq51003
Voltage
Conditioning
AC to DC
Drivers
Rectification
Communication
Controller
V/I
Sense
Controller
bq500210
Transmitter
Receiver
1
1
0
0
0
TX COIL VOLTAGE / CURRENT
Figure 26.
The WPC protocol uses a differential bi-phase encoding scheme to modulate the data bits onto the Tx coil
voltage/current. Each data bit is aligned at a full period of 0.5 ms (tCLK) or 2 kHz. An encoded ONE results in two
transitions during the bit period and an encoded ZERO results in a single transition. See Figure 27 for an
example of the differential bi-phase encoding.
Figure 27. Differential Bi-phase Encoding Scheme (WPC Volume 1: Low Power, Part 1 Interface
Definition)
The bits are sent LSB first and use an 11-bit asynchronous serial format for each portion of the packet. This
includes one start bit, n-data bytes, a parity bit, and a single stop bit. The start bit is always ZERO and the parity
bit is odd. The stop bit is always ONE. Figure 28 shows the details of the asynchronous serial format.
Figure 28. Asynchronous Serial Formatting (WPC volume 1: Low Power, Part 1 Interface Definition)
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Each packet format is organized as shown in Figure 29.
Preamble
Header
Message
Checksum
Figure 29. Packet Format (WPC Volume 1: Low Power, Part 1 Interface Definition)
Figure 20 above shows an example waveform of the receiver sending a rectified power packet (header 0x04).
Communication Modulator
The bq51003 provides two identical, integrated communication FETs which are connected to the pins COMM1
and COMM2. These FETs are used for modulating the secondary load current which allows bq51003 to
communicate error control and configuration information to the transmitter. Figure 30 shows how the COMM pins
can be used for resistive load modulation. Each COMM pin can handle at most a 24-Ω communication resistor.
Therefore, if a COMM resistor between 12 Ω and 24 Ω is required COMM1 and COMM2 pins must be connected
in parallel. The bq51003 does not support a COMM resistor less than 12 Ω.
RECTIFIER
24W
24W
COMM1
COMM2
COMM_DRIVE
Figure 30. Resistive Load Modulation
In addition to resistive load modulation, the bq51003 is also capable of capacitive load modulation as shown in
Figure 31. In this case, a capacitor is connected from COMM1 to AC1 and from COMM2 to AC2. When the
COMM switches are closed there is effectively a 22 nF capacitor connected between AC1 and AC2. Connecting
a capacitor in between AC1 and AC2 modulates the impedance seen by the coil, which will be reflected in the
primary as a change in current.
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Figure 31. Capacitive Load Modulation
Adaptive Communication Limit
The Qi communication channel is established via backscatter modulation as described in the previous sections.
This type of modulation takes advantage of the loosely coupled inductor relationship between the Rx and Tx coil.
Essentially the switching in-and-out of the communication capacitor or resistor adds a transient load to the Rx
coil in order to modulate the Tx coil voltage/current waveform (amplitude modulation). The consequence of this
technique is that a load transient (load current noise) from the mobile device has the same signature. In order to
provide noise immunity to the communication channel, the output load transients must be isolated from the Rx
coil. The proprietary feature Adaptive Communication Limit achieves this by dynamically adjusting the current
limit of the regulator. When the regulator is put in current limit, any load transients will be offloaded to the battery
in the system.
Note that this requires the battery charger IC to have input voltage regulation (weak adapter mode). The output
of the Rx appears as a weak supply if a transient occurs above the current limit of the regulator.
The Adaptive Communication Limit feature has two current limit modes and is detailed in Table 5:
Table 5.
IOUT
COMMUNICATION CURRENT LIMIT
Fixed 400 mA
< 300 mA
> 300 mA
IOUT + 50 mA
Synchronous Rectification
The bq51003 provides an integrated, self-driven synchronous rectifier that enables high-efficiency AC to DC
power conversion. The rectifier consists of an all NMOS H-Bridge driver where the backgates of the diodes are
configured to be the rectifier when the synchronous rectifier is disabled. During the initial startup of the WPC
system the synchronous rectifier is not enabled. At this operating point, the DC rectifier voltage is provided by the
diode rectifier. Once VRECT is greater than UVLO, half synchronous mode will be enabled until the load current
surpasses 120 mA. Above 120 mA the full synchronous rectifier stays enabled until the load current drops back
below 100 mA where half synchronous mode is enabled instead.
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Temperature Sense Resistor Network (TS)
bq51003 includes a ratiometric external temperature sense function. The temperature sense function has two
ratiometric thresholds which represent a hot and cold condition. An external temperature sensor is recommended
in order to provide safe operating conditions for the receiver product. This pin is best used for monitoring the
surface that can be exposed to the end user (that is, place the NTC resistor closest to the user).
Figure 32 allows for any NTC resistor to be used with the given VHOT and VCOLD thresholds.
VTSB (2.2V)
20kΩ
R2
TS-CTRL
R1
R3
NTC
Figure 32. NTC Circuit Used for Safe Operation of the Wireless Receiver Power Supply
The resistors R1 and R3 can be solved by resolving the system of equations at the desired temperature
thresholds. The two equations are:
æ
ç
ç
ö
÷
÷
÷
R
R
+ R
1
TCOLD
(
)
3
NTC
R + R
+ R
1
ç
(
NTC
)
3
NTC
TCOLD
è
ø
%V
=
=
´100
COLD
æ
ç
ç
ö
R
R
+ R
1
(
)
÷
÷
÷
3
TCOLD
+ R2
R + R
+ R
1
ç
(
)
3
NTC
TCOLD
è
ø
æ
ö
÷
÷
÷
R
R
+ R
1
THOT
(
)
ç
ç
3
NTC
R + R
+ R
ç
(
NTC
)
3
NTC
1
THOT
è
ø
%V
´100
HOT
æ
ç
ç
ö
R
R
+ R
1
(
)
÷
÷
÷
3
THOT
+ R2
R + R
+ R
1
ç
(
)
3
NTC
THOT
è
ø
(3)
(4)
Where:
ö
÷
÷
çæ 1
è
1
b
-
ç
TCOLD Toø
R
= R e
o
NTC
TCOLD
çæ 1
1
Toø
ö
÷
÷
b
-
ç
THOT
è
R
= R e
o
NTC
THOT
where, TCOLD and THOT are the desired temperature thresholds in degrees Kelvin. RO is the nominal resistance
and β is the temperature coefficient of the NTC resistor. RO is fixed at 20 kΩ. An example solution is provided:
•
•
R1 = 4.23 kΩ
R3 = 66.8 kΩ
where the chosen parameters are:
•
•
•
%VHOT = 19.6%
%VCOLD = 58.7%
TCOLD = –10°C
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•
•
•
THOT = 100°C
β = 3380
RO = 10 kΩ
The plot of the percent VTSB vs. temperature is shown in Figure 33:
Figure 33. Example Solution for an NTC resistor with RO = 10 kΩ and β = 4500
Figure 34 illustrates the periodic biasing scheme used for measuring the TS state. The TS_READ signal enables
the TS bias voltage for 24 ms. During this period the TS comparators are read (each comparator has a 10-ms
deglitch) and appropriate action is taken based on the temperature measurement. After this 24-ms period has
elapsed, the TS_READ signal goes low, which causes the TS-Bias pin to become high impedance. During the
next 35 ms (priority packet period) or 235 ms (standard packet period), the TS voltage is monitored and
compared to 100 mV. If the TS voltage is greater than 100 mV then a secondary device is driving the TS-CTRL
pin and a CTRL = ‘1’ is detected.
Figure 34. Timing Diagram for TS Detection Circuit
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3-State Driver Recommendations for the TS-CTRL Pin
The TS-CTRL pin offers three functions with one 3-state driver interface
1. NTC temperature monitoring,
2. Fault indication,
3. Charge done indication
A 3-state driver can be implemented with the circuit in Figure 35 and the use of two GPIO connections.
BATT
TERM
M3
TS-CTRL
FAULT
M4
Figure 35. 3-State Driver for TS-CTRL
Note that the signals “TERM” and “FAULT” are given by two GPIOs. The truth table for this circuit is found in
Table 6:
Table 6.
TERM
FAULT
F (Result)
1
0
1
0
0
1
Z (Normal Mode)
Charge Complete
System Fault
The default setting is TERM = 1 and FAULT = 0. In this condition, the TS-CTRL net is high impedance (hi-z) and;
therefore, the NTC is function is allowed to operate. When the TS-CTRL pin is pulled to GND by setting FAULT =
1, the Rx is shut down with the indication of a fault. When the TS-CTRL pin is pulled to the battery by setting
TERM = 1, the Rx is shut down with the indication of a charge complete condition. Therefore, the host controller
can indicate whether the Rx is system is turning off due to a fault or due to a charge complete condition.
Thermal Protection
The bq51003 includes a thermal shutdown protection. If the die temperature reaches TJ(OFF), the LDO is shut
off to prevent any further power dissipation. In this case bq51003 will send an EPT message of internal fault
(0x02).
WPC v1.1 Compliance – Foreign Object Detection
The bq51003 is a WPC v1.1 compatible device. In order to enable a Power Transmitter to monitor the power loss
across the interface as one of the possible methods to limit the temperature rise of Foreign Objects, the bq51003
reports its Received Power to the Power Transmitter. The Received Power equals the power that is available
from the output of the Power Receiver plus any power that is lost in producing that output power (the power loss
in the Secondary Coil and series resonant capacitor, the power loss in the Shielding of the Power Receiver, the
power loss in the rectifier). In WPC v1.1 specification, foreign object detection (FOD) is enforced. This means the
bq51003 will send received power information with known accuracy to the transmitter.
WPC v1.1 defines Received Power as “the average amount of power that the Power Receiver receives through
its Interface Surface, in the time window indicated in the Configuration Packet”.
26
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Product Folder Links: bq51003
bq51003
www.ti.com
SLUSBC8 –DECEMBER 2013
In order to receive certification as a WPC v1.1 receiver, the Device Under Test (DUT) is tested on a Reference
Transmitter whose transmitted power is calibrated, the receiver must send a received power such that:
0 mW < (Tx PWR)REF – (Rx PWR out)DUT < –250 mW
(5)
This 250-mW bias ensures that system will remain interoperable.
WPC v1.1 Transmitter will be tested to see if they can detect reference Foreign Objects with a Reference
receiver.
WPC v1.1 Specification will allow much more accurate sensing of Foreign Objects.
Series and Parallel Resonant Capacitor Selection
Shown in Figure 2, the capacitors C1 (series) and C2 (parallel) make up the dual resonant circuit with the
receiver coil. These two capacitors must be sized correctly per the WPC v1.1 specification. Figure 36 illustrates
the equivalent circuit of the dual resonant circuit:
C1
Ls’
C2
Figure 36. Dual Resonant Circuit with the Receiver Coil
Section 4.2 (Power Receiver Design Requirements) in Part 1 of the WPC v1.1 specification highlights in detail
the sizing requirements. To summarize, the receiver designer will be required take inductance measurements
with a fixed test fixture. The test fixture is shown in Figure 37:
Figure 37. WPC v1.1 Receiver Coil Test Fixture for the Inductance Measurement Ls’ (Copied from
System Description Wireless Power Transfer, Volume 1: Low Power, Part 1 Interface Definition, Version
1.1)
Copyright © 2013, Texas Instruments Incorporated
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27
Product Folder Links: bq51003
bq51003
SLUSBC8 –DECEMBER 2013
www.ti.com
The primary shield is to be 50 mm x 50 mm x 1 mm of Ferrite material PC44 from TDK Corp. The gap dZ is to be
3.4 mm. The receiver coil, as it will be placed in the final system (that is, the back cover and battery must be
included if the system calls for this), is to be placed on top of this surface and the inductance is to be measured
at 1-V RMS and a frequency of 100 kHz. This measurement is termed Ls’. The same measurement is to be
repeated without the test fixture shown in Figure 37. This measurement is termed Ls or the free-space
inductance. Each capacitor can then be calculated using Equation 6:
-1
é
ê
ù
ú
2
'
S
C = f ×2p ×L
( )
1
S
ê
ú
ë
û
-1
é
ù
ú
2
1
ê
C =
f ×2p ×L -
( )
D
S
C
2
ê
ú
1
ë
û
(6)
(7)
Where fS is 100 kHz +5/-10% and fD is 1 MHz ±10%. C1 must be chosen first prior to calculating C2.
The quality factor must be greater than 77 and can be determined by Equation 7:
2p× f ×LS
D
Q =
R
Where R is the DC resistance of the receiver coil. All other constants are defined above.
Package Summary
YFP Package
(Top View)
YFP Package Symbol
(Top Side Symbol for bq51003)
A1
B1
C1
D1
E1
F1
G1
A2
B2
C2
D2
E2
F2
G2
A3
B3
C3
D3
E3
F3
G3
A4
B4
C4
D4
E4
F4
G4
TI YMLLLLS
bq51003
D
0-Pin A1 Marker, TI-TI Letters, YM- Year Month Date Code,
LLLL-Lot Trace Code, S-Assembly Site Code
Figure 38. Chip Scale Packaging Dimensions
•
•
D = 3.0 mm ± 0.035 mm
E = 1.88 mm ± 0.035 mm
28
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Product Folder Links: bq51003
PACKAGE OPTION ADDENDUM
www.ti.com
31-Dec-2013
PACKAGING INFORMATION
Orderable Device
BQ51003YFPR
BQ51003YFPT
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
DSBGA
DSBGA
YFP
28
28
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
BQ51003
BQ51003
ACTIVE
YFP
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Dec-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Dec-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ51003YFPR
BQ51003YFPT
DSBGA
DSBGA
YFP
YFP
28
28
3000
250
180.0
180.0
8.4
8.4
2.0
2.0
3.13
3.13
0.6
0.6
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Dec-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ51003YFPR
BQ51003YFPT
DSBGA
DSBGA
YFP
YFP
28
28
3000
250
182.0
182.0
182.0
182.0
17.0
17.0
Pack Materials-Page 2
D: Max = 3.036 mm, Min =2.976 mm
E: Max = 1.913 mm, Min =1.852 mm
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