BQ40Z50RSMR-R2_技术文档

BQ40Z50-R2

ZHCSGX4C –JUNE 2017 –REVISED APRIL 2021

BQ40Z50-R2 1 节、2 节、3 节和4 节串联锂离子电池组管理器

1 特性

3 说明

• 完全集成的1 节、2 节、3 节和4 节串联锂离子或

锂聚合物电池组管理器和保护

• 获得专利的新一代Impedance Track^™技术可准确

测量锂离子和锂聚合物电池中的可用电量

• 高侧N 沟道保护FET 驱动器

• 充电或者静止状态时具有集成的电池平衡功能

• 适合于100mAh 和29Ah 之间的电池

• 全面的可编程保护功能

– 电压

BQ40Z50-R2 器件采用已获专利的 Impedance Track^™

技术，是一个全集成、单芯片、基于电池组的解决方

案，可为1 节、2 节、3 节和4 节串联锂离子和锂聚合

物电池组提供电量监测、保护和认证等各种特性。

BQ40Z50-R2 器件利用其集成的高性能模拟外设，测

量锂离子或锂聚合物电池的可用容量、电压、电流、温

度和其他关键参数，保留准确的数据记录，并通过

SMBus v1.1 兼容接口将这些信息报告给系统主机控制

器。

– 电流

– 温度

器件信息

– 充电终止时间

– CHG/DSG FET

封装尺寸（标称值）

器件型号

封装

VQFN (32)

BQ40Z50-R2

4.00mm × 4.00mm

– 模拟前端(AFE)

• 精密的充电算法

+

PACK

– JEITA

– 增强型充电

– 自适应充电

– 电池均衡

• 支持涡轮模式2.0

• 支持电池跳闸点(BTP)

• 诊断使用寿命数据监控器和黑盒记录器

• LED 显示屏

• 支持双线制SMBus v1.1 接口

• 安全散列算法(SHA-1) 认证

• IATA 支持

LEDCNTLA

BAT

VC4

LEDCNTLB

LEDCNTLC

VC3

VC2

OUT

VC3

VC2

VC1

Cell 3

Cell 2

DISP

SMBD

VDD

GND

SMBD

SMBC

VC1

PBI

SMBC

PRES

VSS SRP SRN TS1 TS2 TS3 TS4 BTP PRES

Cell 1

BTP

• 紧凑型封装：32 引线QFN (RSM)

–

PACK

Copyright

2 应用

简化版原理图

• 平板电脑

• 无人机

• UPS/电池备用系统

• 医疗设备

• 手持式真空吸尘器和扫地机器人

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSCS4

BQ40Z50-R2

ZHCSGX4C –JUNE 2017 –REVISED APRIL 2021

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Table of Contents

7.26 Low-Frequency Oscillator....................................... 16

7.27 Voltage Reference 1............................................... 16

7.28 Voltage Reference 2............................................... 16

7.29 Instruction Flash......................................................16

7.30 Data Flash...............................................................17

7.31 OLD, SCC, SCD1, SCD2 Current Protection

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Description (continued).................................................. 3

6 Pin Configuration and Functions...................................3

6.1 Pin Equivalent Diagrams.............................................5

7 Specifications.................................................................. 8

7.1 Absolute Maximum Ratings........................................ 8

7.2 ESD Ratings............................................................... 8

7.3 Recommended Operating Conditions.........................8

7.4 Thermal Information....................................................9

7.5 Supply Current............................................................9

7.6 Power Supply Control................................................. 9

7.7 AFE Power-On Reset............................................... 10

7.8 AFE Watchdog Reset and Wake Timer.................... 10

7.9 Current Wake Comparator........................................10

7.10 VC1, VC2, VC3, VC4, BAT, PACK.......................... 11

7.11 SMBD, SMBC..........................................................11

7.12 PRES, BTP_INT, DISP ...........................................11

7.13 LEDCNTLA, LEDCNTLB, LEDCNTLC................... 12

7.14 Coulomb Counter....................................................12

7.15 CC Digital Filter.......................................................12

7.16 ADC........................................................................ 12

7.17 ADC Digital Filter.................................................... 13

7.18 CHG, DSG FET Drive.............................................13

7.19 PCHG FET Drive.................................................... 14

7.20 FUSE Drive.............................................................14

7.21 Internal Temperature Sensor.................................. 15

7.22 TS1, TS2, TS3, TS4................................................15

7.23 PTC, PTCEN...........................................................15

7.24 Internal 1.8-V LDO..................................................15

7.25 High-Frequency Oscillator...................................... 16

Thresholds...................................................................17

7.32 Timing Requirements: OLD, SCC, SCD1,

SCD2 Current Protection Timing.................................18

7.33 Timing Requirements: SMBus................................ 19

7.34 Timing Requirements: SMBus XL...........................19

7.35 Typical Characteristics............................................20

8 Detailed Description......................................................24

8.1 Overview...................................................................24

8.2 Functional Block Diagram.........................................24

8.3 Feature Description...................................................25

8.4 Device Functional Modes..........................................28

9 Application and Implementation..................................29

9.1 Application Information............................................. 29

9.2 Typical Applications.................................................. 30

10 Power Supply Recommendations..............................41

11 Layout...........................................................................42

11.1 Layout Guidelines................................................... 42

11.2 Layout Example...................................................... 44

12 Device and Documentation Support..........................46

12.1 第三方产品免责声明................................................46

12.2 Documentation Support.......................................... 46

12.3 支持资源..................................................................46

12.4 Trademarks.............................................................46

12.5 Electrostatic Discharge Caution..............................46

12.6 Glossary..................................................................46

13 Mechanical, Packaging, and Orderable

Information.................................................................... 46

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (July 2018) to Revision C (April 2021)

Page

• 将整个数据表中出现的所有OCD 更改为OLD................................................................................................... 1

Changes from Revision A (October 2017) to Revision B (July 2018)

Page

• Changed Pin Configuration and Functions ........................................................................................................5

• Changed System Present ................................................................................................................................34

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5 Description (continued)

The BQ40Z50-R2 device supports TURBO Mode 2.0 by providing the available max power and max current to

the host system. The device also supports Battery Trip Point to send a BTP interrupt signal to the host system at

the preset state of charge thresholds.

The BQ40Z50-R2 provides software-based 1st- and 2nd-level safety protection against overvoltage,

undervoltage, overcurrent, short-circuit current, overload, and overtemperature conditions, as well as other pack-

and cell-related faults.

SHA-1 authentication, with secure memory for authentication keys, enables identification of genuine battery

packs.

The compact 32-lead QFN package minimizes solution cost and size for smart batteries while providing

maximum functionality and safety for battery gauging applications.

6 Pin Configuration and Functions

PBI

VC4

VC3

VC2

VC1

SRN

NC

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

PTCEN

PTC

LEDCNTLC

LEDCNTLB

LEDCNTLA

SMBC

Thermal

Pad

SMBD

SRP

DISP

Not to scale

表6-1. Pin Functions

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

1

PBI

P⁽¹⁾

Power supply backup input pin. Connect to the 2.2-µF capacitor to VSS.

Sense voltage input pin for the most positive cell, and balance current input

for the most positive cell. Should be connected to the positive terminal of the

fourth cell from the bottom of the stack with a 100-Ωseries resistor and a 0.1-

μF capacitor to VC3. If not used, connect to VC3.

2

3

VC4

IA

Sense voltage input pin for the third-most positive cell, balance current input

for the third-most positive cell, and return balance current for the most

positive cell. Should be connected to the positive terminal of the third cell from

the bottom of the stack with a 100-Ωseries resistor and a 0.1-μF capacitor

to VC2. If not used, connect to VC2.

VC3

VC2

VC1

IA

Sense voltage input pin for the second-most positive cell, balance current

input for the second-most positive cell, and return balance current for the

third-most positive cell. Should be connected to the positive terminal of the

second cell from the bottom of the stack with a 100-Ωseries resistor and a

0.1-μF capacitor to VC1. If not used, connect to VC1.

4

5

Sense voltage input pin for the least positive cell, balance current input for the

least positive cell, and return balance current for the second-most positive

cell. Should be connected to the positive terminal of the first cell from the

bottom of the stack with a 100-Ωseries resistor and a 0.1-μF capacitor to

VSS.

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表6-1. Pin Functions (continued)

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

Analog input pin connected to the internal coulomb counter peripheral for

integrating a small voltage between SRP and SRN where SRP is the top of

the sense resistor.

6

7

8

SRN

NC

I

Not internally connected. It is okay to leave floating or to tie to VSS.

—

Analog input pin connected to the internal coulomb counter peripheral for

integrating a small voltage between SRP and SRN where SRP is the top of

the sense resistor.

SRP

I

9

VSS

TS1

P

Device ground

Temperature sensor 1 thermistor input pin. Connect to thermistor-1. If not

used, connect directly to VSS and configure data flash accordingly.

10

IA

Temperature sensor 2 thermistor input pin. Connect to thermistor-2. If not

used, connect directly to VSS and configure data flash accordingly.

11

12

13

TS2

TS3

TS4

IA

Temperature sensor 3 thermistor input pin. Connect to thermistor-3. If not

used, connect directly to VSS and configure data flash accordingly.

Temperature sensor 4 thermistor input pin. Connect to thermistor-4. If not

used, connect directly to VSS and configure data flash accordingly.

14

15

NC

Not internally connected. It is okay to leave floating or to tie to VSS.

—

BTP_INT

O

Battery Trip Point (BTP) interrupt output. If not used, connect directly to VSS.

Host system present input for removable battery pack or emergency system

shutdown input for embedded pack. A pullup is not required for this pin. If not

used, connect directly to VSS.

16

PRES or SHUTDN

I

17

18

19

DISP

Display control for LEDs. If not used, connect directly to VSS.

—

SMBD

SMBC

I/OD

SMBus data pin

SMBus clock pin

LED display segment that drives the external LEDs depending on the

firmware configuration. If LEDs are not used, these pins can be left floating or

connected to VSS through a 20-kΩresistor.

20

21

22

LEDCNTLA

LEDCNTLB

LEDCNTLC

—

LED display segment that drives the external LEDs depending on the

firmware configuration. If LEDs are not used, these pins can be left floating or

connected to VSS through a 20-kΩresistor.

LED display segment that drives the external LEDs depending on the

firmware configuration. If LEDs are not used, these pins can be left floating or

connected to VSS through a 20-kΩresistor.

Safety PTC thermistor input pin. To disable, connect both PTC and PTCEN to

VSS.

23

24

PTC

IA

Safety PTC thermistor enable input pin. Connect to BAT. To disable, connect

both PTC and PTCEN to VSS.

PTCEN

25

26

27

FUSE

VCC

O

P

Fuse drive output pin. If not used, connect directly to VSS.

Secondary power supply input

PACK

IA

Pack sense input pin

NMOS Discharge FET drive output pin. If not used, it can be left floating or

connected to VSS through a 20-kΩresistor.

28

29

30

DSG

NC

O

Not internally connected. It is okay to leave floating or to tie to VSS.

—

PMOS Precharge FET drive output pin. If not used, it can be left floating or

connected to VSS through a 20-kΩresistor.

PCHG

O

NMOS Charge FET drive output pin. If not used, it can be left floating or

connected to VSS through a 20-kΩresistor.

31

32

CHG

BAT

O

P

Primary power supply input pin

(1) P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output

4

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6.1 Pin Equivalent Diagrams

VC4

CDEN4

CDEN3

BAT

VCC

PACK

VC3

+

–

BATDET

ENVCC

3.1 V

PACK

Detector

VC2

ADC Mux

ADC

PACKDET

PBI

SHUTDOWN

Shutdown

Latch

CDEN2

Reference

System

1.8 V

Domain

SHOUT

VC1

ENBAT

BAT

Control

CDEN1

Power Supply Control

Cell Balancing

VCC

CHGEN

BAT

2 kΩ

CHG

Pump

8 kΩ

PCHG

2 kΩ

CHGOFF

PCHGEN

Pre-Charge Drive

PACK

BAT

DSGEN

ZVCD

BAT

2 kΩ

DSG

CHGEN

Pump

BAT

CHG

Pump

VCC

DSGOFF

ZVCHGEN

CHG, DSG Drive

Zero-Volt Charge

图6-1. Pin Equivalent Diagram 1

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1.8 V

ADTHx

BAT

FUSEWKPUP

18 kΩ

2 kΩ

ADC Mux

ADC

150 nA

TS1,2,3,4

FUSEEN

2 kΩ

FUSE

1.8 V

100 kΩ

FUSEDIG

RCWKPUP

RCPUP

FUSE Drive

1 kΩ

RCIN

RCOUT

100 kΩ

SMBCIN

SMBC

Thermistor Inputs

SMBCOUT

SMBCEN

1 MΩ

PBI

100 kΩ

SMBDIN

SMBD

RHOEN

SMBDOUT

10 kΩ

SMBDEN

1 MΩ

PRES

SMBus Interface

RHOUT

100 kΩ

RHIN

High-Voltage GPIO

BAT

RLOEN

LED1, 2, 3

22.5 mA

RLOUT

100 kΩ

RLIN

LED Drive

图6-2. Pin Equivalent Diagram 2

6

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10 Ω

VC4

CHANx

Φ

2

3.8 kΩ

1.9 MΩ

0.1 MΩ

SRP

SRN

Φ

1

ADC Mux

ADC

Comparator

Array

Φ

2

1

3.8 kΩ

Φ

2

10 Ω

100 Ω

PACK

Φ

1

Coulomb

Counter

Φ

2

1

CHANx

100 Ω

Φ

1.9 MΩ

0.1 MΩ

ADC Mux

ADC

OLD , SCC, SCD Comparators and Coulomb Counter

VC4 and PACK Dividers

图6-3. Pin Equivalent Diagram 3

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7 Specifications

7.1 Absolute Maximum Ratings

Over-operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Supply voltage range,

BAT, VCC, PBI

V_CC

30

V

–0.3

PACK, SMBC, SMBD, PRES or SHUTDN, BTP_INT, DISP

TS1, TS2, TS3, TS4

30

V

–0.3

V_REG+ 0.3

V_BAT+ 0.3

0.3

PTC, PTCEN, LEDCNTLA, LEDCNTLB, LEDCNTLC

SRP, SRN

VC3 + 8.5, or

VSS + 30

VC4

V

VC3 –0.3

VC2 –0.3

VC1 –0.3

VSS –0.3

Input voltage range, V_IN

VC2 + 8.5, or

VSS + 30

VC3

VC2

VC1

VC1 + 8.5, or

VSS + 30

VSS + 8.5, or

VSS + 30

CHG, DSG

32

30

–0.3

Output voltage range,

V_O

PCHG, FUSE

V

Maximum VSS current, I_SS

50

mA

°C

Storage temperature, T_STG

150

300

–65

Lead temperature (soldering, 10 s), T_SOLDER

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Electrostatic

discharge

V_(ESD)

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

MIN

2.2

NOM

MAX

26

UNIT

V_CC

Supply voltage

BAT, VCC, PBI

V

V_SHUTDOWN–Shutdown voltage

V_PACK< V_{SHUTDOWN –}

V_PACK> V_SHUTDOWN–+ V_HYS

1.8

2.0

2.2

V_SHUTDOWN+

V_HYS

Start-up voltage

2.05

2.25

2.45

Shutdown voltage

hysteresis

250

mV

V

_SHUTDOWN+–V_SHUTDOWN–

8

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7.3 Recommended Operating Conditions (continued)

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

MIN

NOM

MAX

26

UNIT

PACK, SMBC, SMBD, PRES, BTP_IN, DISP

TS1, TS2, TS3, TS4

V_REG

PTC, PTCEN, LEDCNTLA, LEDCNTLB, LEDCNTLC

V_BAT

SRP, SRN

VC4

0.2

–0.2

V_VC3

V_VC2

V_VC1

V_VSS

V_IN

Input voltage range

V

V_VC3+ 5

V_VC2+ 5

V_VC1+ 5

V_VSS+ 5

VC3

VC2

VC1

Output voltage

range

V_O

CHG, DSG, PCHG, FUSE

26

V

External PBI

capacitor

C_PBI

T_OPR

2.2

µF

°C

Operating

temperature

85

–40

7.4 Thermal Information

BQ40Z50-R2

RSM (QFN)

32 PINS

47.4

THERMAL METRIC⁽¹⁾

UNIT

R_{θJA, High K}

R_θJC(top)

R_θJB

Junction-to-ambient thermal resistance

Junction-to-case(top) thermal resistance

°C/W

40.3

Junction-to-board thermal resistance

14.7

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

0.8

ψ_JT

14.4

ψ_JB

R_θJC(bottom)

3.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.5 Supply Current

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 20 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

336

75

MAX

UNIT

I_NORMAL

I_SLEEP

NORMAL mode

CHG on. DSG on, no Flash write

µA

CHG off, DSG on, no SBS communication

CHG off, DSG off, no SBS communication

SLEEP mode

µA

52

I_SHUTDOWN

SHUTDOWN mode

1.6

7.6 Power Supply Control

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BAT to V_CC

switchover voltage

V_{SWITCHOVER–}

V_SWITCHOVER+

V_BAT< V_{SWITCHOVER–}

1.95

2.1

2.2

V

V_CCto BAT

switchover voltage

V_BAT> V_{SWITCHOVER–}+ V_HYS

2.9

3.1

3.25

V

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7.6 Power Supply Control (continued)

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Switchover

voltage hysteresis

V_HYS

1000

mV

V

_SWITCHOVER+–V_{SWITCHOVER–}

BAT pin, BAT = 0 V, VCC = 25 V, PACK = 25 V

PACK pin, BAT = 25 V, VCC = 0 V, PACK = 0 V

1

Input Leakage

current

I_LKG

µA

BAT and PACK terminals, BAT = 0 V, VCC = 0 V, PACK =

0 V, PBI = 25 V

1

7.7 AFE Power-On Reset

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Negative-going

voltage input

V_REGIT–

V_HYS

V_REG

_REGIT+–V_REGIT–

1.51

1.55

1.59

V

Power-on reset

hysteresis

70

100

300

130

400

mV

µs

V

Power-on reset

time

t_RST

200

7.8 AFE Watchdog Reset and Wake Timer

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

372

TYP

500

MAX

628

UNIT

t_WDT= 500

t_WDT= 1000

t_WDT= 2000

t_WDT= 4000

t_WAKE= 250

t_WAKE= 500

t_WAKE= 1000

t_WAKE= 512

744

1000

2000

4000

250

1256

2512

5024

314

AFE watchdog

timeout

t_WDT

ms

1488

2976

186

372

500

628

t_WAKE

AFE wake timer

ms

744

1000

2000

1256

2512

1488

FET off delay after

reset

t_FETOFF

t_FETOFF= 512

409

512

614

7.9 Current Wake Comparator

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

±0.3

±0.6

±1.2

±2.4

TYP

±0.625

±1.25

±2.5

MAX UNIT

±0.9

V_WAKE= ±0.625 mV

V_WAKE= ±1.25 mV

V_WAKE= ±2.5 mV

V_WAKE= ±5 mV

±1.8

Wake voltage

threshold

V_WAKE

mV

±3.6

±7.2

±5.0

Temperature drift of

V_WAKEaccuracy

V_WAKE(DRIFT)

0.5%

°C

µs

Time from

application of

current to wake

interrupt

t_WAKE

700

10

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7.9 Current Wake Comparator (continued)

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

1000 µs

Wake comparator

startup time

t_WAKE(SU)

500

7.10 VC1, VC2, VC3, VC4, BAT, PACK

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3

BAT–VSS, PACK–VSS

MIN

TYP

MAX

0.2020

0.051

0.510

5

UNIT

0.1980 0.2000

K

Scaling factor

0.049

0.490

–0.2

0.050

0.500

—

V_REF2

VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3

BAT–VSS, PACK–VSS

V_IN

Input voltage range

Input leakage current

V

20

VC1, VC2, VC3, VC4, cell balancing off, cell detach

detection off, ADC multiplexer off

I_LKG

R_CB

I_CD

1

200

70

µA

Internal cell balance

resistance

R_DS(ON)for internal FET switch at 2 V < V_DS< 4 V

VCx > VSS + 0.8 V

Ω

Internal cell detach

check current

30

50

µA

7.11 SMBD, SMBC

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IH

Input voltage high

Input voltage low

Output low voltage

Input capacitance

Input leakage current

Pulldown resistance

SMBC, SMBD, V_REG= 1.8 V

1.3

V

V_IL

SMBC, SMBD, V_REG= 1.8 V

0.8

0.4

V

V_OL

C_IN

I_LKG

R_PD

SMBC, SMBD, V_REG= 1.8 V, I_OL= 1.5 mA

5

pF

µA

MΩ

1

0.7

1.0

1.3

7.12 PRES, BTP_INT, DISP

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

High-level input

Low-level input

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IH

V_IL

1.3

V

0.55

V

3.5

1.8

V_BAT> 5.5 V, I_OH= –0 µA

V_OH

Output voltage high

V

V_BAT> 5.5 V, I_OH= –10 µA

V_OL

C_IN

Output voltage low

Input capacitance

Input leakage current

I_OL= 1.5 mA

0.4

1

V

5

pF

µA

I_LKG

Output reverse

resistance

R_O

Between PRES or BTP_INT or DISP and PBI

8

kΩ

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7.13 LEDCNTLA, LEDCNTLB, LEDCNTLC

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

High-level input

Low-level input

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IH

V_IL

1.45

V

0.55

V

V_BAT

–

V_OH

V_OL

I_SC

Output voltage high

Output voltage low

V

V_BAT> 3.0 V, I_OH= –22.5 mA

1.6

I_OL= 1.5 mA

0.4

V

High level output

current protection

mA

–30

–45

–6 0

Low level output

current

I_OL

V_BAT> 3.0 V, V_OH= 0.4 V

V_BAT= V_LEDCNTLx+ 2.5 V

15.75

22.5

29.25

mA

Current matching

between LEDCNTLx

I_LEDCNTLx

±1%

20

C_IN

Input capacitance

pF

µA

I_LKG

Input leakage current

1

Frequency of LED

pattern

f_LEDCNTLx

124

Hz

7.14 Coulomb Counter

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

–0.1

TYP

MAX

0.1

UNIT

V

Input voltage range

Full scale range

Integral nonlinearity⁽¹⁾

Offset error

V_REF1/10

±22.3

±10

V

–V_REF1/10

16-bit, best fit over input voltage range

16-bit, Post-calibration

±5.2

±5

LSB

µV

Offset error drift

Gain error

15-bit + sign, Post-calibration

0.2

0.3 µV/°C

15-bit + sign, over input voltage range

±0.2%

±0.8%

FSR

150 PPM/°C

MΩ

Gain error drift

Effective input resistance

2.5

(1) 1 LSB = V_REF1/(10 × 2^N) = 1.215/(10 × 2¹⁵) = 3.71 µV

7.15 CC Digital Filter

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

ms

Bits

Conversion time

Effective resolution

Single conversion

250

15

7.16 ADC

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

–0.2

–V_FS

TYP

MAX UNIT

Internal reference (V_REF1

)

1

Input voltage range

Full scale range

V

External reference (V_REG

V_FS= V_REF1or V_REG

)

0.8 × V_REG

V_FS

V

12

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7.16 ADC (continued)

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

±6.6

16-bit, best fit, –0.1 V to 0.8 × V_REF1

Integral nonlinearity⁽¹⁾

LSB

±13.1

±157

3

16-bit, best fit, –0.2 V to –0.1 V

16-bit, Post-calibration, V_FS= V_REF1

16-bit, –0.1 V to 0.8 × V_FS

Offset error⁽²⁾

±67

0.6

µV

Offset error drift

Gain error

µV/°C

FSR

±0.2%

±0.8%

Gain error drift

Effective input resistance

150 PPM/°C

16-bit, –0.1 V to 0.8 × V_FS

8

MΩ

(1) 1 LSB = V_REF1/(2^N) = 1.225/(2¹⁵) = 37.4 µV (when t_CONV= 31.25 ms)

(2) For VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3, VC4–VSS, PACK–VSS, and V_REF1/2, the offset error is multiplied by (1/ADC

multiplexer scaling factor (K)).

7.17 ADC Digital Filter

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

Conversion time

Resolution

TEST CONDITIONS

MIN

TYP

31.25

15.63

7.81

MAX UNIT

Single conversion

ms

Single conversion

1.95

No missing codes

16

14

13

11

9

Bits

With sign, t_CONV= 31.25 ms

With sign, t_CONV= 15.63 ms

With sign, t_CONV= 7.81 ms

With sign, t_CONV= 1.95 ms

15

14

12

10

Effective resolution

7.18 CHG, DSG FET Drive

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Ratio_DSG= (V_DSG–V_BAT)/V_BAT, 2.2 V < V_BAT< 4.92 V,

10 MΩbetween PACK and DSG

2.133

2.333

2.433

Output voltage

ratio

—

Ratio_CHG= (V_CHG–V_BAT)/V_BAT, 2.2 V < V_BAT< 4.92 V,

10 MΩbetween BAT and CHG

2.133

10.5

2.333

11.5

2.433

12

V_DSG(ON)= V_DSG–V_BAT, V_BAT≥4.92 V, 10 MΩ

between PACK and DSG, V_BAT= 18 V

Output voltage,

CHG and DSG on

V_(FETON)

V

V_CHG(ON)= V_CHG–V_BAT, V_BAT≥4.92 V, 10 MΩ

between BAT and CHG, V_BAT= 18 V

10.5

11.5

12

V_DSG(OFF)= V_DSG–V_PACK, 10 MΩbetween PACK and

DSG

0.4

–0.4

Output voltage,

CHG and DSG off

V_(FETOFF)

V_CHG(OFF)= V_CHG–V_BAT, 10 MΩbetween BAT and

CHG

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7.18 CHG, DSG FET Drive (continued)

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_DSGfrom 0% to 35% V_{DSG (ON)(TYP)}, V_BAT≥2.2 V, C_L=

4.7 nF between DSG and PACK, 5.1 kΩbetween DSG

and C_L, 10 MΩbetween PACK and DSG

200

500

t_R

Rise time

µs

V_CHGfrom 0% to 35% V_{CHG (ON)(TYP)}, V_BAT≥2.2 V, C_L=

4.7 nF between CHG and BAT, 5.1 kΩbetween CHG

and C_L, 10 MΩbetween BAT and CHG

200

40

500

300

200

V_DSGfrom V_DSG(ON)(TYP)to 1 V, V_BAT≥2.2 V, C_L= 4.7

nF between DSG and PACK, 5.1 kΩbetween DSG and

C_L, 10 MΩbetween PACK and DSG

t_F

Fall time

µs

V_CHGfrom V_CHG(ON)(TYP)to 1 V, V_BAT≥2.2 V, C_L= 4.7

nF between CHG and BAT, 5.1 kΩbetween CHG and

C_L, 10 MΩbetween BAT and CHG

40

7.19 PCHG FET Drive

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Output voltage,

PCHG on

V_PCHG(ON)= VV_CC–V_PCHG, 10 MΩbetween V_CCand

PCHG

V_(FETON)

6

7

8

V

Output voltage,

PCHG off

V_PCHG(OFF)= VV_CC–V_PCHG, 10 MΩbetween V_CCand

PCHG

V_(FETOFF)

0.4

V

–0.4

V_PCHGfrom 10% to 90% V_{PCHG(ON)(TYP)}, VV_CC≥8 V, C_L

= 4.7 nF between PCHG and V_CC, 5.1 kΩbetween

PCHG and C_L, 10 MΩbetween V_CCand CHG

t_R

Rise time

Fall time

40

200

µs

V_PCHGfrom 90% to 10% V_{PCHG(ON)(TYP)}, V_CC≥8 V, C_L=

4.7 nF between PCHG and V_CC, 5.1 kΩbetween PCHG

and C_L, 10 MΩbetween V_CCand CHG

t_F

µs

7.20 FUSE Drive

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

_BAT≥8 V, C_L= 1 nF, I_AFEFUSE= 0 µA

V_BAT< 8 V, C_L= 1 nF, I_AFEFUSE= 0 µA

MIN

TYP

MAX UNIT

6

7

8.65

V

Output voltage

high

V_OH

V

V_BAT

2.5

V

_BAT–0.1

V_IH

High-level input

1.5

2.0

V

Internal pullup

current

I_AFEFUSE(PU)

150

330

3.2

nA

V

_BAT≥8 V, V_AFEFUSE= VSS

R_AFEFUSE

C_IN

Output impedance

Input capacitance

2

2.6

5

kΩ

pF

Fuse trip detection

delay

t_DELAY

t_RISE

128

256

20

µs

Fuse output rise

time

5

V

_BAT≥8 V, C_L= 1 nF, V_OH= 0 V to 5 V

14

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7.21 Internal Temperature Sensor

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Internal

temperature

sensor voltage drift

V_TEMPP

_TEMPP–V_TEMPN, assured by design

–1.9

–2.0

–2.1

V_TEMP

mV/°C

0.177

0.178

0.179

V

7.22 TS1, TS2, TS3, TS4

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

–0.2

TYP

MAX UNIT

TS1, TS2, TS3, TS4, V_BIAS= V_REF1

TS1, TS2, TS3, TS4, V_BIAS= V_REG

0.8 × V_REF1

Input voltage

range

V_IN

V

0.8 × V_REG

21.6

Internal pullup

resistance

R_NTC(PU)

TS1, TS2, TS3, TS4

14.4

18

kΩ

Resistance drift

over

R_NTC(DRIFT)

PPM/°C

–360

–280

–200

temperature

7.23 PTC, PTCEN

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

1.2

TYP

2.5

MAX UNIT

PTC trip

resistance

R_PTC(TRIP)

V_PTC(TRIP)

I_PTC

3.95

890

350

145

MΩ

mV

nA

PTC trip voltage

200

40

500

290

80

V_PTC(TRIP)= V_PTCEN–V_PTC

T_A= –40°C to 110°C

Internal PTC

current bias

t_PTC(DELAY)PTC delay time

ms

7.24 Internal 1.8-V LDO

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_REG

Regulator voltage

Regulator output

over temperature

Line regulation

Load regulation

1.6

1.8

2.0

V

±0.25%

ΔV_O(TEMP)

ΔV_REG/ΔT_A, I_REG= 10 mA

0.5%

1.5%

ΔV_O(LINE)

ΔV_O(LOAD)

ΔV_REG/ΔV_BAT, V_BAT= 10 mA

–0 .6%

–1.5%

ΔV_REG/ΔI_REG, I_REG= 0 mA to 10 mA

Regulator output

current limit

I_REG

V_REG= 0.9 × V_REG(NOM), V_IN> 2.2 V

V_REG= 0 × V_REG(NOM)

20

25

mA

dB

Regulator short-

circuit current limit

I_SC

40

55

Power supply

rejection ratio

PSRR_REG

ΔV_BAT/ΔV_REG, I_REG= 10 mA ,V_IN> 2.5 V, f = 10 Hz

Slew rate

V_SLEW

enhancement

voltage threshold

V_REG

1.58

1.65

V

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7.25 High-Frequency Oscillator

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

16.78

MAX UNIT

MHz

f_HFO

Operating frequency

±0.25%

2.5%

3.5%

T_A= –20°C to 70°C, includes frequency drift

–2.5%

–3.5%

f_HFO(ERR)

Frequency error

Start-up time

T_A= –40°C to 85°C, includes frequency drift

T_A= –20°C to 85°C, oscillator frequency within +/–

3% of nominal

4

ms

µs

t_HFO(SU)

100

oscillator frequency within +/–3% of nominal

7.26 Low-Frequency Oscillator

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

262.144

±0.25%

±0.25

MAX UNIT

kHz

f_LFO

Operating frequency

1.5%

2.5

T_A= –20°C to 70°C, includes frequency drift

T_A= –40°C to 85°C, includes frequency drift

–1.5%

–2.5

f_LFO(ERR)

Frequency error

Failure detection

frequency

f_LFO(FAIL)

30

80

100

kHz

7.27 Voltage Reference 1

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

1.22 V

Internal reference

voltage

V_REF1

T_A= 25°C, after trim

1.21

1.215

T_A= 0°C to 60°C, after trim

±50

±80

Internal reference

voltage drift

V_REF1(DRIFT)

PPM/°C

T_A= –40°C to 85°C, after trim

7.28 Voltage Reference 2

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

1.23 V

Internal reference

voltage

V_REF2

T_A= 25°C, after trim

1.22

1.225

T_A= 0°C to 60°C, after trim

±50

±80

Internal reference

voltage drift

V_REF2(DRIFT)

PPM/°C

T_A= –40°C to 85°C, after trim

7.29 Instruction Flash

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Years

Data retention

10

Flash programming

write cycles

1000

Cycles

µs

Word programming

time

t_PROGWORD

40

T_A= –40°C to 85°C

16

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7.29 Instruction Flash (continued)

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

t_MASSERASE

t_PAGEERASE

I_FLASHREAD

I_FLASHWRITE

I_FLASHERASE

TEST CONDITIONS

MIN

TYP

MAX UNIT

Mass-erase time

Page-erase time

Flash-read current

Flash-write current

Flash-erase current

40

2

ms

T_A= –40°C to 85°C

ms

mA

5

15

7.30 Data Flash

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Years

Data retention

10

Flash programming

write cycles

20000

Cycles

t_PROGWORD

t_MASSERASE

t_PAGEERASE

I_FLASHREAD

I_FLASHWRITE

I_FLASHERASE

Word programming time

Mass-erase time

40

1

µs

ms

mA

T_A= –40°C to 85°C

Page-erase time

Flash-read current

Flash-write current

Flash-erase current

5

15

7.31 OLD, SCC, SCD1, SCD2 Current Protection Thresholds

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_OLD= V_SRP–V_SRN,AFE PROTECTION

CONTROL[RSNS] = 1

–16.6

–100

OLD detection threshold

voltage range

V_OLD

mV

V_OLD= V_SRP–V_SRN,AFE PROTECTION

CONTROL[RSNS] = 0

–8.3

–50

V_OLD= V_SRP–V_SRN,AFE PROTECTION

CONTROL[RSNS] = 1

–5.56

–2.78

OLD detection threshold

voltage program step

mV

ΔV_OLD

V_OLD= V_SRP–V_SRN,AFE PROTECTION

CONTROL[RSNS] = 0

V_SCC= V_SRP–V_SRN,AFE PROTECTION

CONTROL[RSNS] = 1

44.4

22.2

200

100

SCC detection threshold

voltage range

V_SCC

V_SCC= V_SRP–V_SRN,AFE PROTECTION

CONTROL[RSNS] = 0

V_SCC= V_SRP–V_SRN,AFE PROTECTION

CONTROL[RSNS] = 1

22.2

11.1

SCC detection threshold

voltage program step

ΔV_SCC

V_SCC= V_SRP–V_SRN,AFE PROTECTION

CONTROL[RSNS] = 0

V_SCD1= V_SRP–V_SRN,AFE PROTECTION

CONTROL[RSNS] = 1

–44.4

–22.2

–200

–100

SCD1 detection

threshold voltage range

V_SCD1

V_SCD1= V_SRP–V_SRN,AFE PROTECTION

CONTROL[RSNS] = 0

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7.31 OLD, SCC, SCD1, SCD2 Current Protection Thresholds (continued)

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_SCD1= V_SRP–V_SRN,AFE PROTECTION

CONTROL[RSNS] = 1

–22.2

SCD1 detection

threshold voltage

program step

mV

ΔV_SCD1

V_SCD1= V_SRP–V_SRN,AFE PROTECTION

CONTROL[RSNS] = 0

–11.1

V_SCD2= V_SRP–V_SRN,AFE PROTECTION

CONTROL[RSNS] = 1

–44.4

–22.2

–200

–100

SCD2 detection

threshold voltage range

V_SCD2

mV

V_SCD2= V_SRP–V_SRN,AFE PROTECTION

CONTROL[RSNS] = 0

V_SCD2= V_SRP–V_SRN,AFE PROTECTION

CONTROL[RSNS] = 1

–22.2

–11.1

SCD2 detection

threshold voltage

program step

ΔV_SCD2

V_SCD2= V_SRP–V_SRN,AFE PROTECTION

CONTROL[RSNS] = 0

OLD, SCC, and SCDx

offset error

V_OFFSET

Post-trim

2.5

mV

–2.5

No trim

10%

5%

–10%

–5%

OLD, SCC, and SCDx

scale error

V_SCALE

—

Post-trim

7.32 Timing Requirements: OLD, SCC, SCD1, SCD2 Current Protection Timing

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

MIN

NOM

MAX UNIT

OLD detection

delay time

t_OLD

1

31

ms

OLD detection

delay time

program step

2

ms

µs

Δt_OLD

SCC detection

delay time

t_SCC

0

915

SCC detection

delay time

61

Δt_SCC

program step

AFE PROTECTION CONTROL[SCDDx2] = 0

AFE PROTECTION CONTROL[SCDDx2] = 1

AFE PROTECTION CONTROL[SCDDx2] = 0

0

915

SCD1 detection

delay time

t_SCD1

µs

1850

SCD1 detection

delay time

program step

61

Δt_SCD1

AFE PROTECTION CONTROL[SCDDx2] = 1

121

AFE PROTECTION CONTROL[SCDDx2] = 0

AFE PROTECTION CONTROL[SCDDx2] = 1

AFE PROTECTION CONTROL[SCDDx2] = 0

0

458

915

SCD2 detection

delay time

t_SCD2

SCD2 detection

delay time

program step

30.5

61

µs

Δt_SCD2

AFE PROTECTION CONTROL[SCDDx2] = 1

Current fault

detect time

V

_SRP–V_SRN= V_T–3 mV for OLD, SCD1, and SC2,

_SRP–V_SRN= V_T+ 3 mV for SCC

t_DETECT

t_ACC

160

Current fault delay

time accuracy

Max delay setting

10%

–10%

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7.33 Timing Requirements: SMBus

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

MIN

NOM

MAX

UNIT

SMBus operating

frequency

f_SMB

SLAVE mode, SMBC 50% duty cycle

10

100

kHz

SMBus master clock

frequency

f_MAS

MASTER mode, no clock low slave extend

51.2

kHz

µs

Bus free time between start

and stop

t_BUF

4.7

4.0

Hold time after (repeated)

start

t_HD(START)

µs

t_SU(START)

t_SU(STOP)

t_HD(DATA)

t_SU(DATA)

t_TIMEOUT

t_LOW

Repeated start setup time

Stop setup time

4.7

4.0

300

250

25

µs

ns

ms

µs

ns

Data hold time

Data setup time

Error signal detect time

Clock low period

Clock high period

Clock rise time

35

4.7

4.0

t_HIGH

50

1000

300

t_R

10% to 90%

90% to 10%

t_F

Clock fall time

Cumulative clock low slave

extend time

t_LOW(SEXT)

t_LOW(MEXT)

25

10

ms

Cumulative clock low

master extend time

7.34 Timing Requirements: SMBus XL

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

MIN

NOM

MAX UNIT

f_SMBXL

t_BUF

SMBus XL operating

frequency

SLAVE mode

40

400

kHz

Bus free time between start

and stop

4.7

µs

t_HD(START)

t_SU(START)

t_SU(STOP)

t_TIMEOUT

t_LOW

Hold time after (repeated) start

Repeated start setup time

Stop setup time

4.0

4.7

4.0

5

µs

ms

µs

Error signal detect time

Clock low period

20

t_HIGH

Clock high period

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Tt_R

Tt_F

Tt_R

Tt_HIGH

T

t_SU(STOP)p

t_HD(START)

Tt_BUFT

Tt_LOWT

SMBC

SMBD

P

S

t_HD(DATA)

T

Tt_SU(DATA)

Start and Stop Condition

Wait and Hold Condition

t_SU(START)

T

Tt_TIMEOUT

SMBC

SMBD

SMBC

SMBD

S

Repeated Start Condition

Timeout Condition

图7-1. SMBus Timing Diagram

7.35 Typical Characteristics

±8.

0.15

0.10

Max CC Offset Error

Min CC Offset Error

ꢀ8.

ꢁ8.

0.05

ꢂ8.

0.00

.8.

±ꢂ8.

±ꢁ8.

±ꢀ8.

±±8.

œ0.05

œ0.10

œ0.15

Max ADC Offset Error

Min ADC Offset Error

0

20

40

60

80

100

120

œ40

œ20

.

ꢂ.

ꢁ.

ꢀ.

±.

1..

1ꢂ.

±ꢁ.

±ꢂ.

Temperature (°C)

C001

Temperature (°C)

C..3

图7-2. CC Offset Error vs. Temperature

图7-3. ADC Offset Error vs. Temperature

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1.24

264

262

260

258

256

254

252

250

1.23

1.22

1.21

1.20

0

20

40

60

80

100

0

20

40

60

80

100

œ40

œ20

œ40

œ20

Temperature (°C)

C006

C007

图7-4. Reference Voltage vs. Temperature

图7-5. Low-Frequency Oscillator vs. Temperature

16.9

–24.6

–24.8

–25.0

–25.2

–25.4

–25.6

–25.8

16.8

16.7

16.6

0

20

40

60

80

100

120

0

20

40

60

80

100

120

œ40

œ20

–40

–20

Temperature (°C)

C008

C009

Threshold setting is –25 mV.

图7-6. High-Frequency Oscillator vs. Temperature

图7-7. Overcurrent Discharge Protection

Threshold vs. Temperature

87.4

87.2

87.0

86.8

86.6

86.4

86.2

œ86.0

œ86.2

œ86.4

œ86.6

œ86.8

œ87.0

œ87.2

0

20

40

60

80

100

120

0

20

40

60

80

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C010

C011

Threshold setting is 88.85 mV.

Threshold setting is –88.85 mV.

图7-8. Short Circuit Charge Protection Threshold

图7-9. Short Circuit Discharge 1 Protection

vs. Temperature

Threshold vs. Temperature

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11.00

10.95

10.90

10.85

10.80

10.75

10.70

œ172.9

œ173.0

œ173.1

œ173.2

œ173.3

œ173.4

œ173.5

œ173.6

0

20

40

60

80

100

120

0

20

40

60

80

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C012

C013

Threshold setting is 11 ms.

Threshold setting is –177.7 mV.

图7-11. Overcurrent Delay Time vs. Temperature

图7-10. Short Circuit Discharge 2 Protection

Threshold vs. Temperature

452

450

448

446

444

442

440

438

436

434

432

480

460

440

420

400

0

20

40

60

80

100

120

0

20

40

60

80

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C014

C015

Threshold setting is 465 µs.

Threshold setting is 465 µs (including internal delay).

图7-12. Short Circuit Charge Current Delay Time

图7-13. Short Circuit Discharge 1 Delay Time vs.

vs. Temperature

Temperature

2.4984

2.49835

2.4983

2.49825

2.4982

2.49815

2.4981

2.49805

2.498

3.49825

3.4982

3.49815

3.4981

3.49805

3.498

0

20

40

60

80

100

120

0

20

40

60

80

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C017

C016

This is the V_CELLaverage for single cell.

图7-14. V_CELLMeasurement at 2.5-V vs.

Temperature

图7-15. V_CELLMeasurement at 3.5-V vs.

Temperature

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4.24805

99.25

99.20

99.15

99.10

99.05

99.00

4.248

4.24795

4.2479

4.24785

4.2478

0

20

40

60

80

100

120

œ40

œ20

0

20

40

60

80

100

120

œ40

œ20

Temperature (°C)

C018

C019

This is the V_CELLaverage for single cell.

I_SET= 100 mA

图7-16. V_CELLMeasurement at 4.25-V vs.

图7-17. I measured vs. Temperature

Temperature

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8 Detailed Description

8.1 Overview

The BQ40Z50-R2 device, incorporating patented Impedance Track^™technology, provides cell balancing while

charging or at rest. This fully integrated, single-chip, pack-based solution, including a diagnostic lifetime data

monitor and black box recorder, provides a rich array of features for gas gauging, protection, and authentication

for 1-series, 2-series, 3-series, and 4-series cell Li-ion and Li-polymer battery packs.

8.2 Functional Block Diagram

Cell, Stack,

Pack

Voltage

High Side

N-CH FET

Drive

Cell

Balancing

Cell Detach

Detection

Power Mode

Control

P-CH

FET Drive

Zero Volt

Charge

Control

PTCEN

PTC

Wake

Comparator

Power On

Reset

PTC

Overtemp

Short Circuit

Comparator

FUSE

Control

FUSE

SRP

SRN

BTP_INT

Over

Current

Comparator

High

Voltage

I/O

Voltage

Reference2

PRES or SHUTDN

DISP

Random

Number

Generator

Watchdog

Timer

NTC Bias

TS1

TS2

TS3

TS4

LEDCNTLC

LEDCNTLB

LEDCNTLA

Internal

Temp

Sensor

LED Display

Drive I/O

Voltage

Reference1

ADC MUX

AFE Control

Low

Frequency

Oscillator

SBS High

Voltage

Translation

SMBD

SMBC

ADC/CC

FRONTEND

1.8V LDO

Regulator

AFE COM

Engine

High

Frequency

Oscillator

Low Voltage

I/O

I/O &

Interrupt

Controller

ADC/CC

Digital Filter

Timers&

PWM

AFE COM

Engine

SBS COM

Engine

Data (8bit)

DMAddr (16bit)

bqBMP

CPU

PMInstr

(8bit)

PMAddr

(16bit)

Program

Flash

EEPROM

Data Flash

EEPROM

Data

SRAM

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8.3 Feature Description

8.3.1 Primary (1st Level) Safety Features

The BQ40Z50-R2 supports a wide range of battery and system protection features that can easily be configured.

See the BQ40Z50-R2 Technical Reference Manual (SLUUBK0) for detailed descriptions of each protection

function.

The primary safety features include:

• Cell Overvoltage Protection

• Cell Undervoltage Protection

• Cell Undervoltage Protection Compensated

• Overcurrent in Charge Protection

• Overcurrent in Discharge Protection

• Overload in Discharge Protection

• Short Circuit in Charge Protection

• Short Circuit in Discharge Protection

• Overtemperature in Charge Protection

• Overtemperature in Discharge Protection

• Undertemperature in Charge Protection

• Undertemperature in Discharge Protection

• Overtemperature FET protection

• Precharge Timeout Protection

• Host Watchdog Timeout Protection

• Fast Charge Timeout Protection

• Overcharge Protection

• Overcharging Voltage Protection

• Overcharging Current Protection

• Over Precharge Current Protection

8.3.2 Secondary (2nd Level) Safety Features

The secondary safety features of the BQ40Z50-R2 can be used to indicate more serious faults via the FUSE pin.

This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or

discharging. See the BQ40Z50-R2 Technical Reference Manual (SLUUBK0) for detailed descriptions of each

protection function.

The secondary safety features provide protection against:

• Safety Overvoltage Permanent Failure

• Safety Undervoltage Permanent Failure

• Safety Overtemperature Permanent Failure

• Safety FET Overtemperature Permanent Failure

• Qmax Imbalance Permanent Failure

• Impedance Imbalance Permanent Failure

• Capacity Degradation Permanent Failure

• Cell Balancing Permanent Failure

• Fuse Failure Permanent Failure

• PTC Permanent Failure

• Voltage Imbalance At Rest Permanent Failure

• Voltage Imbalance Active Permanent Failure

• Charge FET Permanent Failure

• Discharge FET Permanent Failure

• AFE Register Permanent Failure

• AFE Communication Permanent Failure

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• Second Level Protector Permanent Failure

• Instruction Flash Checksum Permanent Failure

• Open Cell Connection Permanent Failure

• Data Flash Permanent Failure

• Open Thermistor Permanent Failure

8.3.3 Charge Control Features

The BQ40Z50-R2 charge control features include:

• Supports JEITA temperature ranges. Reports charging voltage and charging current according to the active

temperature range

• Handles more complex charging profiles. Allows for splitting the standard temperature range into two sub-

ranges and allows for varying the charging current according to the cell voltage

• Reports the appropriate charging current needed for constant current charging and the appropriate charging

voltage needed for constant voltage charging to a smart charger using SMBus broadcasts

• Reduces the charge difference of the battery cells in a fully charged state of the battery pack gradually using

a voltage-based cell balancing algorithm during charging. A voltage threshold can be set up for cell balancing

to be active. This prevents fully charged cells from overcharging and causing excessive degradation and also

increases the usable pack energy by preventing premature charge termination.

• Supports precharging/0-volt charging

• Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range

• Reports charging fault and also indicates charge status via charge and discharge alarms

8.3.4 Gas Gauging

The BQ40Z50-R2 uses the Impedance Track algorithm to measure and calculate the available capacity in

battery cells. The BQ40Z50-R2 accumulates a measure of charge and discharge currents and compensates the

charge current measurement for the temperature and state-of-charge of the battery. The BQ40Z50-R2 estimates

self-discharge of the battery and also adjusts the self-discharge estimation based on temperature. The device

also has TURBO Mode 2.0 support, which enables the BQ40Z50-R2 to provide the necessary data for the MCU

to determine what level of peak power consumption can be applied without causing a system reset or transient

battery voltage level spike to trigger termination flags. See the BQ40Z50-R2 Technical Reference Manual

(SLUUBK0) for further details.

8.3.5 Configuration

8.3.5.1 Oscillator Function

The BQ40Z50-R2 fully integrates the system oscillators and does not require any external components to

support this feature.

8.3.5.2 System Present Operation

The BQ40Z50-R2 checks the PRES pin periodically (1 s). If PRES input is pulled to ground by the external

system, the BQ40Z50-R2 detects this as system present.

8.3.5.3 Emergency Shutdown

For battery maintenance, the emergency shutdown feature enables a push button action connecting the

SHUTDN pin to shut down an embedded battery pack system before removing the battery. A high-to-low

transition of the SHUTDN pin signals the BQ40Z50-R2 to turn off the CHG and DSG FETs, disconnecting the

power from the system to safely remove the battery pack. The CHG and DSG FETs can be turned on again by

another high-to-low transition detected by the SHUTDN pin or when a data flash configurable timeout is reached.

8.3.5.4 1-Series, 2-Series, 3-Series, or 4-Series Cell Configuration

In a 1-series cell configuration, VC4 is shorted to VC, VC2, and VC1. In a 2-series cell configuration, VC4 is

shorted to VC3 and VC2. In a 3-series cell configuration, VC4 is shorted to VC3.

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8.3.5.5 Cell Balancing

The device supports cell balancing by bypassing the current of each cell during charging or at rest. If the

device's internal bypass is used, up to 10 mA can be bypassed and multiple cells can be bypassed at the same

time. Higher cell balance current can be achieved by using an external cell balancing circuit. In external cell

balancing mode, only one cell at a time can be balanced.

The cell balancing algorithm determines the amount of charge needed to be bypassed to balance the capacity of

all cells.

8.3.6 Battery Parameter Measurements

8.3.6.1 Charge and Discharge Counting

The BQ40Z50-R2 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement,

and a second delta-sigma ADC for individual cell and battery voltage and temperature measurement.

The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage

drop across a small-value sense resistor between the SRP and SRN terminals. The integrating ADC measures

bipolar signals from –0.1 V to 0.1 V. The BQ40Z50-R2 detects charge activity when V_SR= V_(SRP)– V_(SRN)is

positive, and discharge activity when V_SR= V_(SRP)– V_(SRN)is negative. The BQ40Z50-R2 continuously

integrates the signal over time, using an internal counter. The fundamental rate of the counter is 0.26 nVh.

8.3.7 Battery Trip Point (BTP)

Required for WIN8 OS, the battery trip point (BTP) feature indicates when the RSOC of a battery pack has

depleted to a certain value set in a DF register. This feature enables a host to program two capacity-based

thresholds that govern the triggering of a BTP interrupt on the BTP_INT pin, and the setting or clearing of the

OperationStatus[BTP_INT] on the basis of RemainingCapacity().

An internal weak pullup is applied when the BTP feature is active. Depending on the system design, an external

pullup may be required to put on the BTP_INT pin. See 节7.12 for details.

8.3.8 Lifetime Data Logging Features

The BQ40Z50-R2 offers lifetime data logging for several critical battery parameters. The following parameters

are updated every 10 hours if a difference is detected between values in RAM and data flash:

• Maximum and Minimum Cell Voltages

• Maximum Delta Cell Voltage

• Maximum Charge Current

• Maximum Discharge Current

• Maximum Average Discharge Current

• Maximum Average Discharge Power

• Maximum and Minimum Cell Temperature

• Maximum Delta Cell Temperature

• Maximum and Minimum Internal Sensor Temperature

• Maximum FET Temperature

• Number of Safety Events Occurrences and the Last Cycle of the Occurrence

• Number of Valid Charge Termination and the Last Cycle of the Valid Charge Termination

• Number of Qmax and Ra Updates and the Last Cycle of the Qmax and Ra Updates

• Number of Shutdown Events

• Cell Balancing Time for Each Cell

(This data is updated every 2 hours if a difference is detected.)

• Total FW Runtime and Time Spent in Each Temperature Range

(This data is updated every 2 hours if a difference is detected.)

8.3.9 Authentication

The BQ40Z50-R2 supports authentication by the host using SHA-1.

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8.3.10 LED Display

The BQ40Z50-R2 can drive a 3-, 4-, or 5- segment LED display for remaining capacity indication and/or a

permanent fail (PF) error code indication.

8.3.11 IATA Support

The BQ40Z50-R2 supports IATA with several new commands and procedures. See the BQ40Z50-R2 Technical

Reference Manual (SLUUBK0) for further details.

8.3.12 Voltage

The BQ40Z50-R2 updates the individual series cell voltages at 0.25-s intervals. The internal ADC of the

BQ40Z50-R2 measures the voltage, and scales and calibrates it appropriately. This data is also used to

calculate the impedance of the cell for the Impedance Track gas gauging.

8.3.13 Current

The BQ40Z50-R2 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge

current using a 1-mΩto 3-mΩtyp. sense resistor.

8.3.14 Temperature

The BQ40Z50-R2 has an internal temperature sensor and inputs for four external temperature sensors. All five

temperature sensor options can be individually enabled and configured for cell or FET temperature usage. Two

configurable thermistor models are provided to allow the monitoring of cell temperature in addition to FET

temperature, which use a different thermistor profile.

8.3.15 Communications

The BQ40Z50-R2 uses SMBus v1.1 with MASTER mode and packet error checking (PEC) options per the SBS

specification.

8.3.15.1 SMBus On and Off State

The BQ40Z50-R2 detects an SMBus off state when SMBC and SMBD are low for two or more seconds. Clearing

this state requires that either SMBC or SMBD transition high. The communication bus will resume activity within

1 ms.

8.3.15.2 SBS Commands

See the BQ40Z50-R2 Technical Reference Manual (SLUUBK0) for further details.

8.4 Device Functional Modes

The BQ40Z50-R2 supports three power modes to reduce power consumption:

• In NORMAL mode, the BQ40Z50-R2 performs measurements, calculations, protection decisions, and data

updates in 250-ms intervals. Between these intervals, the BQ40Z50-R2 is in a reduced power stage.

• In SLEEP mode, the BQ40Z50-R2 performs measurements, calculations, protection decisions, and data

updates in adjustable time intervals. Between these intervals, the BQ40Z50-R2 is in a reduced power stage.

The BQ40Z50-R2 has a wake function that enables exit from SLEEP mode when current flow or failure is

detected.

• In SHUTDOWN mode, the BQ40Z50-R2 is completely disabled.

See the BQ40Z50-R2 Technical Reference Manual (SLUUBK0) for further details.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The BQ40Z50-R2 is a gas gauge with primary protection support, and can be used with 1-series to 4-series Li-

ion/Li-polymer battery packs. To implement and design a comprehensive set of parameters for a specific battery

pack, users need the Battery Management Studio (BQSTUDIO) graphical user-interface tool installed on a PC

during development. The firmware installed on the BQSTUDIO tool has default values for this product, which are

summarized in the BQ40Z50-R2 Technical Reference Manual (SLUUBK0). Using the BQSTUDIO tool, these

default values can be changed to cater to specific application requirements during development once the system

parameters, such as fault trigger thresholds for protection, enable/disable of certain features for operation,

configuration of cells, chemistry that best matches the cell used, and more are known. This data is referred to as

the "golden image."

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9.2 Typical Applications

9

PAD

4

2

4,7

5,6,8

1,2,

t°

10.0k ohm

t°

10.0k ohm

t°

10.0k ohm

t°

4

10.0k ohm

1

4

3

2

1

2

1

图9-1. Application Schematic

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9.2.1 Design Requirements

表 9-1 shows the default settings for the main parameters. Use the BQSTUDIO tool to update the settings to

meet the specific application or battery pack configuration requirements.

The device should be calibrated before any gauging test. Follow the procedures on the BQSTUDIO Calibration

page to calibrate the device, and use the information on the BQSTUDIO Chemistry page to update the match

chemistry profile to the device.

表9-1. Design Parameters

DESIGN PARAMETER

Cell Configuration

EXAMPLE

3s1p (3-series with 1 parallel)⁽¹⁾

Design Capacity

4400 mAh

Device Chemistry

1210 (LiCoO₂/graphitized carbon)

Cell Overvoltage at Standard Temperature

Cell Undervoltage

4300 mV

2500 mV

Shutdown Voltage

2300 mV

Overcurrent in CHARGE Mode

Overcurrent in DISCHARGE Mode

Short Circuit in CHARGE Mode

Short Circuit in DISCHARGE Mode

Safety Overvoltage

6000 mA

–6000 mA

0.1 V/Rsense across SRP, SRN

4500 mV

Cell Balancing

Disabled

Internal and External Temperature Sensor

Undertemperature Charging

Undertemperature Discharging

BROADCAST Mode

External temperature sensor is used.

0°C

Disabled

Battery Trip Point (BTP) with active high interrupt

(1) When using the device the first time and if a 1-s or 2-s battery pack is used, then a charger or power supply should be connected to

the PACK+ terminal to prevent device shutdown. Then update the cell configuration (see the BQ40Z50-R2 Technical Reference

Manual [SLUUBK0] for details) before removing the charger connection.

9.2.2 Detailed Design Procedure

9.2.2.1 High-Current Path

The high-current path begins at the PACK+ terminal of the battery pack. As charge current travels through the

pack, it finds its way through protection FETs, a chemical fuse, the Li-ion cells and cell connections, and the

sense resistor, and then returns to the PACK– terminal (see 图 9-2). In addition, some components are placed

across the PACK+ and PACK–terminals to reduce effects from electrostatic discharge.

9.2.2.1.1 Protection FETs

Select the N-channel charge and discharge FETs for a given application. Most portable battery applications are a

good match for the CSD17308Q3. The TI CSD17308Q3 is a 47A, 30-V device with Rds(on) of 8.2 mΩwhen the

gate drive voltage is 8 V.

If a precharge FET is used, R1 is calculated to limit the precharge current to the desired rate. Be sure to account

for the power dissipation of the series resistor. The precharge current is limited to (V_CHARGER– V_BAT)/R1 and

maximum power dissipation is (V_charger–V_bat)²/R1.

The gates of all protection FETs are pulled to the source with a high-value resistor between the gate and source

to ensure they are turned off if the gate drive is open.

Capacitors C1 and C2 help protect the FETs during an ESD event. Using two devices ensures normal operation

if one becomes shorted. To have good ESD protection, the copper trace inductance of the capacitor leads must

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be designed to be as short and wide as possible. Ensure that the voltage ratings of both C1 and C2 are

adequate to hold off the applied voltage if one of the capacitors becomes shorted.

图9-2. BQ40Z50-R2 Protection FETs

9.2.2.1.2 Chemical Fuse

The chemical fuse (Dexerials, Uchihashi, and so on) is ignited under command from either the bq294700

secondary voltage protection IC or from the FUSE pin of the gas gauge. Either of these events applies a positive

voltage to the gate of Q5, shown in 图 9-3, which then sinks current from the third terminal of the fuse, causing it

to ignite and open permanently.

It is important to carefully review the fuse specifications and match the required ignition current to that available

from the N-channel FET. Ensure that the proper voltage, current, and Rds(on) ratings are used for this device.

The fuse control circuit is discussed in detail in 节9.2.2.2.5.

4P

to 2^ndLevel Protector

to FUSE Pin

图9-3. FUSE Circuit

9.2.2.1.3 Li-Ion Cell Connections

For cell connections, it is important to remember that high current flows through the top and bottom connections;

therefore, the voltage sense leads at these points must be made with a Kelvin connection to avoid any errors

due to a drop in the high-current copper trace. The location marked 4P in 图 9-4 indicates the Kelvin connection

of the most positive battery node. The connection marked 1N is equally important. The VC5 pin (a ground

reference for cell voltage measurement), which is in the older generation devices, is not in the BQ40Z50-R2

device. Therefore, the single-point connection at 1N to the low-current ground is needed to avoid an unwanted

voltage drop through long traces while the gas gauge is measuring the bottom cell voltage.

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图9-4. Li-Ion Cell Connections

9.2.2.1.4 Sense Resistor

As with the cell connections, the quality of the Kelvin connections at the sense resistor is critical. The sense

resistor must have a temperature coefficient no greater than 50 ppm in order to minimize current measurement

drift with temperature. Choose the value of the sense resistor to correspond to the available overcurrent and

short-circuit ranges of the BQ40Z50-R2 device. Select the smallest value possible to minimize the negative

voltage generated on the BQ40Z50-R2 V_SSnode(s) during a short circuit. This pin has an absolute minimum of

–0.3 V. Parallel resistors can be used as long as good Kelvin sensing is ensured. The device is designed to

support a 1-mΩto 3-mΩsense resistor.

The BQ40Z50-R2 ground scheme is different from that of the older generation devices. In previous devices, the

device ground (or low current ground) is connected to the SRN side of the R_SENSEresistor pad. In the BQ40Z50-

R2 device, however, it connects the low-current ground on the SRP side of the R_SENSEresistor pad close to the

battery 1N terminal (see 节 9.2.2.1.3). This is because the BQ40Z50-R2 device has one less VC pin (a ground

reference pin VC5) compared to the previous devices. The pin was removed and was internally combined to

SRP.

图9-5. Sense Resistor

9.2.2.1.5 ESD Mitigation

A pair of series 0.1-μF ceramic capacitors is placed across the PACK+ and PACK– terminals to help in the

mitigation of external electrostatic discharges. The two devices in series ensure continued operation of the pack

if one of the capacitors becomes shorted.

Optionally, a tranzorb such as the SMBJ2A can be placed across the terminals to further improve ESD immunity.

9.2.2.2 Gas Gauge Circuit

The gas gauge circuit includes the BQ40Z50-R2 and its peripheral components. These components are divided

into the following groups: differential low-pass filter, PBI, system present, SMBus communication, fuse circuit,

and LED.

9.2.2.2.1 Coulomb-Counting Interface

The BQ40Z50-R2 uses an integrating delta-sigma ADC for current measurements. Add a 100-Ω resistor from

the sense resistor to the SRP and SRN inputs of the device. Place a 0.1-µF (C18) filter capacitor across the SRP

and SRN inputs.

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图9-6. Differential Filter

9.2.2.2.2 Power Supply Decoupling and PBI

The BQ40Z50-R2 device has an internal LDO that is internally compensated and does not require an external

decoupling capacitor.

The PBI pin is used as a power supply backup input pin, providing power during brief transient power outages. A

standard 2.2-µF ceramic capacitor is connected from the PBI pin to ground, as shown in 图9-7.

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

PBI

PTCEN

PTC

VC4

VC3

VC2

VC1

C13

LEDCNTLC

2.2 μF

LEDCNTLB

LEDCNTLA

SMBC

SRN

NC

SMBD

DISP

SRP

图9-7. Power Supply Decoupling

9.2.2.2.3 System Present

The system present signal informs the gas gauge whether the pack is installed into or removed from the system.

In the host system, this pin is grounded. The PRES pin of the BQ40Z50-R2 device is occasionally sampled to

test for system present. In ACTIVE mode, the PRES pin is pulsed every 250 ms for a duration of 5 ms (RHOEN

is on), and just before it is turned off, the state of the PRES pin is checked to see if it is low or high. The average

of the four measurements is used to determine if the PRES is asserted or not. In SLEEP mode, the PRES pin is

pulsed every "Sleep Voltage Time," and the state of the PRES pin is determined. A resistor can be used to pull

the signal low and the resistance must be 20 kΩor lower to ensure that the test pulse is lower than the V_ILlimit.

The pullup current source is typically 10 µA to 20 µA. When the PRES pin is not pulsed, the PRES pin is tied

internally to VSS (RHOUT is on), and any pullup on the PRES pin will cause a battery drain when not charging.

Refer to the PRES pin diagram in

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VIL

<20 K

图9-8. System Present Pull-Down Resistor

Because the System Present signal is part of the pack connector interface to the outside world, it must be

protected from external electrostatic discharge events. The PRES pin has integrated ESD protection to 2 kV.

External protection can be added to support higher ESD protection requirements. The TPD1E10B06 single-

channel ESD protection diode (U2) can protect the input up to 30 kV, and the R8 reduces the holding current to

release the internal SCR in the event that it triggers.

to Discharge FET

图9-9. System Present ESD and Short Protection

9.2.2.2.4 SMBus Communication

The SMBus clock and data pins have integrated high-voltage ESD protection circuits; however, adding

TPD1E10B06 ESD protection diodes (U4 and U5) and series resistors (R24 and R25) provides more robust ESD

performance.

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The SMBus clock and data lines have internal pulldown. When the gas gauge senses that both lines are low

(such as during removal of the pack), the device performs auto-offset calibration and then goes into SLEEP

mode to conserve power.

图9-10. ESD Protection for SMBus Communication

9.2.2.2.5 FUSE Circuitry

The FUSE pin of the BQ40Z50-R2 device is designed to ignite the chemical fuse if one of the various safety

criteria is violated. The FUSE pin also monitors the state of the secondary-voltage protection IC. Q5 ignites the

chemical fuse when its gate is high. The 7-V output of the bq294700 is divided by R18 and R19, which provides

adequate gate drive for Q5 while guarding against excessive back current into the bq294700 if the FUSE signal

is high.

Using C7 is generally a good practice, especially for RFI immunity. C7 may be removed, if desired, because the

chemical fuse is a comparatively slow device and is not affected by any sub-microsecond glitches that come

from the FUSE output during the cell connection process.

If the AFEFUSE output is not used, it should be connected to VSS.

4P

to 2^ndLevel Protector

to FUSE Pin

图9-11. FUSE Circuit

When the BQ40Z50-R2 device is commanded to ignite the chemical fuse, the FUSE pin activates to give a

typical 8-V output. The new design makes it possible to use a higher Vgs FET for Q5. This improves the

robustness of the system, as well as widens the choices for Q5.

9.2.2.3 Secondary-Current Protection

The BQ40Z50-R2 device provides secondary overcurrent and short-circuit protection, cell balancing, cell voltage

multiplexing, and voltage translation. The following section examines cell and battery inputs, pack and FET

control, temperature output, and cell balancing.

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9.2.2.3.1 Cell and Battery Inputs

Each cell input is conditioned with a simple RC filter, which provides ESD protection during cell connect and acts

to filter unwanted voltage transients. The resistor value allows some trade-off for cell balancing versus safety

protection.

The integrated cell balancing FETs enable the AFE to bypass cell current around a given cell or numerous cells,

effectively balancing the entire battery stack. External series resistors placed between the cell connections and

the VCx I/O pins set the balancing current magnitude. The internal FETs provide a 200-Ωresistance (2 V < VDS

< 4 V). Series input resistors between 100 Ωand 300 Ωare recommended for effective cell balancing.

The BAT input uses a diode (D1) to isolate and decouple it from the cells in the event of a transient dip in voltage

caused by a short-circuit event.

Also, as described in 节 9.2.2.1, the top and bottom nodes of the cells must be sensed at the battery

connections with a Kelvin connection to prevent voltage sensing errors caused by a drop in the high-current PCB

copper.

图9-12. Cell and BAT Inputs

9.2.2.3.2 External Cell Balancing

Internal cell balancing can only support up to 10 mA. External cell balancing is provided as another option for

faster cell balancing. For details, refer to the application note, Fast Cell Balancing Using External MOSFET

(SLUA420).

9.2.2.3.3 PACK and FET Control

The PACK and V_CCinputs provide power to the BQ40Z50-R2 device from the charger. The PACK input also

provides a method to measure and detect the presence of a charger. The PACK input uses a 10-kΩ resistor;

whereas, the V_CCinput uses an internal diode to guard against input transients and prevent a misoperation of

the gate driver during short-circuit events.

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图9-13. BQ40Z50-R2 PACK and FET Control

The N-channel charge and discharge FETs are controlled with 5.1-kΩ series gate resistors, which provide a

switching time constant of a few microseconds. The 10-MΩresistors ensure that the FETs are off in the event of

an open connection to the FET drivers. Q4 is provided to protect the discharge FET (Q3) in the event of a

reverse-connected charger. Without Q4, Q3 can be driven into its linear region and suffer severe damage if the

PACK+ input becomes slightly negative.

Q4 turns on in that case to protect Q3 by shorting its gate to source. To use the simple ground gate circuit, the

FET must have a low gate turn-on threshold. If it is desired to use a more standard device, such as the 2N7002

as the reference schematic, the gate should be biased up to 3.3 V with a high-value resistor. The BQ40Z50-R2

device has the capability to provide a current-limited charging path typically used for low battery voltage or low

temperature charging. The BQ40Z50-R2 device uses an external P-channel, precharge FET controlled by

PCHG.

9.2.2.3.4 Temperature Output

For the BQ40Z50-R2 device, TS1, TS2, TS3, and TS4 provide thermistor drive-under program control. Each pin

can be enabled with an integrated 18-kΩ (typical) linearization pullup resistor to support the use of a 10-kΩ at

25°C (103) NTC external thermistor, such as a Mitsubishi BN35-3H103. The reference design includes four 10-

kΩ thermistors: RT2, RT3, RT4, and RT5. The BQ40Z50-R2 device supports up to four external thermistors.

Connect unused thermistor pins to V_SS

.

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图9-14. Thermistor Drive

9.2.2.3.5 LEDs

Three LED control outputs provide constant current sinks for the driving external LEDs. These outputs are

configured to provide voltage and control for up to five LEDs. No external bias voltage is required. Unused

LEDCNTL pins can remain open or they can be connected to V_SS. The DISP pin should be connected to V_SSif

the LED feature is not used.

图9-15. LEDs

9.2.2.3.6 Safety PTC Thermistor

The BQ40Z50-R2 device provides support for a safety PTC thermistor. The PTC thermistor is connected

between the PTC and BAT pins. It can be placed close to the CHG/DSG FETs to monitor the temperature. The

PTC pin monitors the voltage at the pin and will trip if the thermistor resistance exceeds the defined threshold. A

PTC fault is one of the permanent failure modes. It can only be cleared by a POR.

To disable, connect PTC and PTCEN to VSS.

图9-16. PTC Thermistor

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9.2.3 Application Curves

–24.6

–24.8

–25.0

–25.2

–25.4

–25.6

–25.8

87.4

87.2

87.0

86.8

86.6

86.4

86.2

0

20

40

60

80

100

120

0

20

40

60

80

100

120

–40

–20

œ40

œ20

Temperature (°C)

C009

C010

Threshold setting is 88.85 mV.

Threshold setting is –25 mV.

图9-18. Short Circuit Charge Protection Threshold

图9-17. Overcurrent Discharge Protection

vs. Temperature

Threshold vs. Temperature

œ86.0

œ86.2

œ86.4

œ86.6

œ86.8

œ87.0

œ87.2

œ172.9

œ173.0

œ173.1

œ173.2

œ173.3

œ173.4

œ173.5

œ173.6

0

20

40

60

80

100

120

œ40

œ20

0

20

40

60

80

100

120

œ40

œ20

Temperature (°C)

C011

C012

Threshold setting is –88.85 mV.

Threshold setting is –177.7 mV.

图9-19. Short Circuit Discharge 1 Protection

图9-20. Short Circuit Discharge 2 Protection

Threshold vs. Temperature

11.00

10.95

10.90

10.85

10.80

10.75

10.70

452

450

448

446

444

442

440

438

436

434

432

0

20

40

60

80

100

120

0

20

40

60

80

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C013

C014

Threshold setting is 11 ms.

Threshold setting is 465 µs.

图9-21. Overcurrent Delay Time vs. Temperature

图9-22. Short Circuit Charge Current Delay Time

vs. Temperature

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10 Power Supply Recommendations

The device manages its supply voltage dynamically according to the operation conditions. Normally, the BAT

input is the primary power source to the device. The BAT pin should be connected to the positive termination of

the battery stack. The input voltage for the BAT pin ranges from 2.2 V to 26 V.

The VCC pin is the secondary power input, which activates when the BAT voltage falls below minimum V_CC. This

enables the device to source power from a charger (if present) connected to the PACK pin. The VCC pin should

be connected to the common drain of the CHG and DSG FETs. The charger input should be connected to the

PACK pin.

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11 Layout

11.1 Layout Guidelines

A battery fuel gauge circuit board is a challenging environment due to the fundamental incompatibility of high-

current traces and ultra-low current semiconductor devices. The best way to protect against unwanted trace-to-

trace coupling is with a component placement, such as that shown in 图 11-1, where the high-current section is

on the opposite side of the board from the electronic devices. Clearly, this is not possible in many situations due

to mechanical constraints. Still, every attempt should be made to route high-current traces away from signal

traces, which enter the BQ40Z50-R2 directly. IC references and registers can be disturbed and in rare cases

damaged due to magnetic and capacitive coupling from the high-current path.

Note

During surge current and ESD events, the high-current traces appear inductive and can couple

unwanted noise into sensitive nodes of the gas gauge electronics, as illustrated in 图11-2.

BAT +

C2

C3

Q1

Q2

Low Level Circuits

F1

C1

BAT –

J1

R1

图11-1. Separating High- and Low-Current Sections Provides an Advantage in Noise Immunity

PACK+

COMM

BMU

PACK–

图11-2. Avoid Close Spacing Between High-Current and Low-Level Signal Lines

Kelvin voltage sensing is extremely important in order to accurately measure current and top and bottom cell

voltages. Place all filter components as close as possible to the device. Route the traces from the sense resistor

in parallel to the filter circuit. Adding a ground plane around the filter network can add additional noise immunity.

图11-3 and 图11-4 demonstrate correct Kelvin current sensing.

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Current Direction

R

SNS

Current Sensing Direction

To SRP – SRN pin or HSRP – HSRN pin

图11-3. Sensing Resistor PCB Layout

Sense Resistor

Ground Shield

Filter Circuit

图11-4. Sense Resistor, Ground Shield, and Filter Circuit Layout

11.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors

Use wide copper traces to lower the inductance of the bypass capacitor circuit. 图 11-5 shows an example

layout, demonstrating this technique.

BAT+

C2

C3

C2

C3

Q1

Q2

Pack+

F1

Low Level Circuits

F1

BATœ

C1

Packœ

C1

J1

R1

图11-5. Use Wide Copper Traces to Lower the Inductance of Bypass Capacitors C1, C2, and C3

11.1.2 ESD Spark Gap

Protect SMBus clock, data, and other communication lines from ESD with a spark gap at the connector. The

pattern in 图11-6 is recommended, with 0.2-mm spacing between the points.

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图11-6. Recommended Spark-Gap Pattern Helps Protect Communication Lines from ESD

11.2 Layout Example

THERMISTORS

CHARGE

AND

DISCHARGE

PATH

2^NDLEVEL

PROTECTOR

LEDS

CURRENT

FILTER

SENSE

RESISTOR

图11-7. Top Layer

图11-8. Internal Layer 1

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图11-9. Internal Layer 2

CHARGE

AND

DISCHARGE

PATH

FILTER

COMPONENTS

图11-10. Bottom Layer

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12 Device and Documentation Support

12.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation, see the following from the BQ40Z50-R2 product page on TI.com:

• BQ40Z50-R2 Technical Reference Manual (SLUUBK0)

• BQ40Z50EVM Li-Ion Battery Pack Manager Evaluation Module User's Guide (SLUUAV7)

12.2.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

Impedance Track^™and TI E2E^™are trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

GENERIC PACKAGE VIEW

RSM 32

4 x 4, 0.4 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224982/A

www.ti.com

PACKAGE OUTLINE

RSM0032A

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

B

4.1

3.9

A

0.5

0.3

PIN 1 INDEX AREA

4.1

3.9

0.25

0.15

DETAIL

OPTIONAL TERMINAL

TYPICAL

1 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

2X 2.8

1.4 0.05

(0.2) TYP

4X (0.45)

28X 0.4

9

16

8

17

EXPOSED

THERMAL PAD

2X

SYMM

33

2.8

24

0.25

32X

1

SEE TERMINAL

DETAIL

0.15

0.1

C A B

25

32

PIN 1 ID

(OPTIONAL)

0.05

SYMM

0.5

0.3

32X

4219107/A 11/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RSM0032A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.4)

SYMM

32

25

32X (0.6)

1

32X (0.2)

24

SYMM

33

(3.8)

28X (0.4)

(

0.2) VIA

17

8

(R0.05)

TYP

9

16

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219107/A 11/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RSM0032A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.3)

(R0.05) TYP

25

32

32X (0.6)

32X (0.2)

1

24

SYMM

33

(3.8)

28X (0.4)

METAL

TYP

17

8

16

9

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 33:

86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219107/A 11/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	BQ40Z50RSMR-R2
厂家：	TEXAS INSTRUMENTS
描述：	支持涡轮模式 2.0 的 1 至 4 节串联锂离子电池组管理器 \| RSM \| 32 \| -40 to 85 电池
文件：	总56页 (文件大小：3271K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ40Z50RSMR-R2 [TI]

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