BQ40Z80RSMR_技术文档

BQ40Z80

ZHCSIH4B –JUNE 2018 –REVISED SEPTEMBER 2020

BQ40Z80 2-6 节锂离子电池组管理器

BQ40Z80 器件为主机系统提供可用的最大功率和最大

电流，从而支持涡轮模式 2.0/Intel 动态电池功率技术

(DBPTv2)。该器件有八个多功能引脚，可配置为热输

入、ADC 输入、通用输入/输出 (GPIO) 引脚、

Presence 引脚、LED 功能、显示按钮输入或其他功

能。状态和标志寄存器可映射到 GPIO，并用作主机处

理器的中断。

1 特性

• 完全集成的2-6 节锂离子或锂聚合物电池组管理器

和保护功能

• 获得专利的新一代Impedance Track^®技术可准确

测量锂离子和锂聚合物电池中的可用电量

• 具有可配置的多功能引脚，支持多种应用

• 支持椭圆曲线加密(ECC) 或SHA-1 认证

• 高侧N 沟道保护FET 驱动器

• 充电或者静止状态时具有集成的电池平衡功能

• 原生支持29Ah 的电池，扩展后还可支持更大的电

池容量

器件信息

封装

封装尺寸（标称值）

器件型号

BQ40Z80

VQFN (32)

4.00mm × 4.00mm

1k

• 全面的可编程保护功能

– 电压

– 电流

PACK+

10k

100

– 温度

– 充电终止时间

– CHG/DSG FET

LEDCNTLA/

PDSG/GPIO

BAT

VC6

VC5

LEDCNTLB/GPIO

LEDCNTLC/GPIO

DISP*/TS4/

ADCIN2/GPIO

– 模拟前端(AFE)

• 精密的充电算法

/DISP*/GPIO

VC4

VC3

SMBC

SMBD

SMBC

SMBD

– JEITA

– 增强型充电

– 自适应充电

– 电池均衡

VC2

VC1

PDSG/GPIO

TS3/ADCIN1/

GPIO

PRES*/SHUTDN*/

DISP*/PDSG/GPIO

PRES*

• 支持TURBO 模式2.0/Intel^®动态电池功率技术

(DBPTv2)

PACK-

• 诊断使用寿命数据监控器和黑盒记录器

• LED 显示屏

简化版原理图

• 支持双线制SMBus v1.1 接口

• IATA 支持

• 紧凑型封装：32 引线QFN (RSM)

2 应用

• 工业器械和机器人

• 手持式园艺和电动工具

• 电池供电型吸尘器

• 能源存储系统和UPS

3 说明

BQ40Z80 器件采用已获专利的 Impedance Track^™技

术，是一个全集成、单芯片、基于电池组的解决方案，

可为 2-6 节串联锂离子和锂聚合物电池组提供电量监

测、保护和认证等各种特性。

BQ40Z80 器件利用其集成的高性能模拟外设，测量锂

离子或锂聚合物电池的可用容量、电压、电流、温度和

其他关键参数，保留准确的数据记录，并通过 SMBus

v1.1 兼容接口将这些信息报告给系统主机控制器。

椭圆曲线加密 (ECC) 或 SHA-1 认证具有用于认证密钥

的安全存储器，可确保识别真正的电池组。

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSBV4

BQ40Z80

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ZHCSIH4B –JUNE 2018 –REVISED SEPTEMBER 2020

Table of Contents

8.4 Device Functional Modes..........................................25

9 Applications and Implementation................................26

9.1 Application Information............................................. 26

9.2 Typical Applications.................................................. 26

10 Power Supply Recommendations..............................31

11 Layout...........................................................................32

11.1 Layout Guidelines................................................... 32

11.2 Layout Examples.....................................................34

12 Device and Documentation Support..........................38

12.1 Documentation Support.......................................... 38

12.2 Receiving Notification of Documentation Updates..38

12.3 支持资源..................................................................38

12.4 Trademarks.............................................................38

12.5 静电放电警告.......................................................... 38

12.6 术语表..................................................................... 38

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 说明（续）.........................................................................3

6 Pin Configuration and Functions...................................3

Pin Functions.................................................................... 3

7 Specifications.................................................................. 8

7.1 Absolute Maximum Ratings........................................ 8

7.2 ESD Ratings............................................................... 8

7.3 Recommended Operating Conditions.........................8

7.4 Thermal Information....................................................9

7.5 Electrical Characteristics.............................................9

7.6 Typical Characteristics..............................................18

8 Detailed Description......................................................20

8.1 Overview...................................................................20

8.2 Functional Block Diagram.........................................20

8.3 Feature Description...................................................21

Information.................................................................... 38

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (June 2018) to Revision B (September 2020)

Page

• 删除了数据表中的7 节串联器件选项..................................................................................................................1

• Deleted VC7 I/O details...................................................................................................................................... 3

• Changed high-voltage GPIO default from 7-series cell option to GPIO..............................................................9

• Deleted 7-series cell option and BQ40Z80 multifunction pin combinations......................................................22

• Changed the 7-series EVM schematic for the 6-series EVM schematic.......................................................... 26

• Updated the layout examples........................................................................................................................... 34

2

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5 说明（续）

BQ40Z80 器件可针对过压、欠压、过流、短路电流、过载和过热条件以及其他与电池组和电池相关的故障，提供

基于软件的第 1 级和第 2 级安全保护功能。这个紧凑的 32 导线QFN 封装在尽可能地提供电池电量测量应用的功

能性和安全性的同时，更大限度地降低解决方案成本和智能电池的尺寸。

6 Pin Configuration and Functions

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

VC5

VC4

VC3

VC2

VC1

SRN

NC

VCC

FUSE

LEDCNTLC/GPIO

LEDCNTLB/GPIO

LEDCNTLA/PDSG/GPIO

SMBC

SMBD

SRP

/PRES//SHUTDOWN//DISP/PDSG/GPIO

Not to Scale

图6-1. RSM Package 32-Pin VQFN with Exposed Thermal Pad Top View

Pin Functions

TYPE

DESCRIPTION

NAME

NUMBER

Sense voltage input pin for the fifth cell from the bottom of the stack, balance current

input for the fifth cell from the bottom of the stack, and return balance current for the

sixth cell from the bottom of the stack. Should be connected to the positive terminal of

the fifth cell from the bottom of stack with a 100-Ωseries resistor and a 0.1-µF

capacitor to VC4. If not used, connect to VC4.

VC5

VC4

VC3

VC2

VC1

1

AI⁽¹⁾

Sense voltage input pin for the fourth cell from the bottom of the stack, balance

current input for the fourth cell from the bottom of the stack, and return balance

current for the fifth cell from the bottom of the stack. Should be connected to the

positive terminal of the fourth cell from the bottom of stack with a 100-Ωseries

resistor and a 0.1-µF capacitor to VC3. If not used, connect to VC3.

2

3

4

5

AI

Sense voltage input pin for the third cell from the bottom of the stack, balance current

input for the third cell from the bottom of the stack, and return balance current for the

fourth cell from the bottom of the stack. Should be connected to the positive terminal

of the third cell from the bottom of stack with a 100-Ωseries resistor and a 0.1-µF

capacitor to VC2. If not used, connect to VC2.

Sense voltage input pin for the second cell from the bottom of the stack, balance

current input for the second cell from the bottom of the stack, and return balance

current for the third cell from the bottom of the stack. Should be connected to the

positive terminal of the second cell from the bottom of stack with a 100-Ωseries

resistor and a 0.1-µF capacitor to VC1. If not used, connect to VC1.

Sense voltage input pin for the first cell from the bottom of the stack, balance current

input for the first cell from the bottom of the stack, and return balance current for the

second cell from the bottom of the stack. Should be connected to the positive terminal

of the first cell from the bottom of stack with a 100-Ωseries resistor and a 0.1-µF

capacitor to VSS.

Analog input pin connected to the internal coulomb counter peripheral for integrating

a small voltage between SRP and SRN, where SRP is the top of the sense resistor

and charging current flows from SRP to SRN. Should be connected through an RC

filter to the sense resistor terminal connected to PACK–(not CELL–).

SRN

NC

6

7

I

Not internally connected

—

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TYPE

DESCRIPTION

NAME

NUMBER

Analog input pin connected to the internal coulomb counter peripheral for integrating

a small voltage between SRP and SRN, where SRP is the top of the sense resistor

and charging current flows from SRP to SRN. Should be connected through an RC

filter to the sense resistor positive terminal, which is connected to the least-positive

cells negative terminal.

SRP

8

I

VSS

TS1

9

P

Device ground

Temperature sensor 1 thermistor input pin. Connect to thermistor-1. If not used,

connect directly to VSS and configure data flash accordingly.

10

AI

Temperature sensor 2 thermistor input pin. Connect to thermistor-2. If not used,

connect directly to VSS and configure data flash accordingly.

TS2

11

12

AI

Multifunction pin for TS3, ADCIN1, and GPIO. Can be configured in the control

registers. If not used, connect directly to VSS and configure data flash accordingly.

TS3: Temperature sensor 3 thermistor input pin. Connect to thermistor-3.

ADCIN1: General-purpose ADCIN pin. Connect properly scaled input to this pin.

GPIO: Customizable GPIO

TS3/ADCIN1/

GPIO

IO

Multifunction pin for the display button, temperature sensor input, ADC input, or

GPIO. Can be configured in the control registers. If not used, connect directly to VSS

and configure data flash accordingly.

DISP/TS4/ADCIN2/GPIO

13

IO

DISP: Connect to the display button or LED.

TS4: Temperature sensor 4 thermistor input pin. Connect to thermistor-4.

ADCIN2: General-purpose ADCIN pin. Connect properly scaled input to this pin.

GPIO: Customizable GPIO

NC

14

15

Not internally connected

—

Multifunction pin for the display button, or GPIO. Can be configured in the control

registers. If not used, connect directly to VSS and configure data flash accordingly.

DISP: Connect to the display button or LED.

DISP/GPIO

I/OD

GPIO: Customizable GPIO

Multifunction pin for pre-discharge FET control, or GPIO. Can be configured in the

control registers. If not used, connect directly to VSS and configure data flash

accordingly.

PDSG: Connect to the N-CH FET to control PRE-DISCHARGE mode.

GPIO: Customizable GPIO

PDSG/GPIO

16

17

I/OD

Multifunction pin for host system present input, emergency system shutdown, LED

button control, pre-discharge control, or GPIO. Can be configured in the control

registers. If not used, connect directly to VSS and configure data flash accordingly.

PRES: Connect to host to detect system present input for a removable battery pack.

Do not pullup this pin.

PRES/ SHUTDN/ DISP/

PDSG/GPIO

SHUTDN: Emergency shutdown input for an embedded battery pack

DISP: Connect to the display button or LED.

PDSG: Connect to the N-CH FET to control PRE-DISCHARGE mode.

GPIO: Customizable GPIO

SMBD

SMBC

18

19

I/OD

SMBus data pin

SMBus clock pin

Multifunction pin for LED display, pre-discharge, or GPIO. If not used, connect to VSS

with a 20-kΩresistor.

LEDCNTLA: LED display segment that drives the external LEDs, depending on the

firmware configuration.

LEDCNTLA/PDSG/GPIO

20

O

PDSG: Connect to the N-CH FET to control PRE-DISCHARGE mode.

GPIO: Customizable GPIO

Multifunction pin for LED display or GPIO. If not used, connect to VSS with a 20-kΩ

resistor.

LEDCNTLB/GPIO

LEDCNTLC/GPIO

21

22

O

LEDCNTLB: LED display segment that drives the external LEDs, depending on the

firmware configuration.

GPIO: Customizable GPIO

Multifunction pin for LED display or GPIO. If not used, connect to VSS with a 20-kΩ

resistor.

LEDCNTLC: LED display segment that drives the external LEDs, depending on the

firmware configuration

GPIO: Customizable GPIO

4

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TYPE

DESCRIPTION

NAME

NUMBER

Fuse drive output pin. Can be OR'ed together into the fuse N-CH FET gate drive with

secondary protector. If not used, connect directly to VSS.

FUSE

VCC

23

O

Secondary power supply input. Connect to the middle of protection FETs through the

series resistor.

24

P

PACK

DSG

NC

25

26

27

AI

O

Pack sense input pin. Connect through the series resistor to PACK+.

NMOS discharge FET drive output pin. Connect to the DSG FET gate.

Not internally connected.

—

PMOS precharge FET drive output pin. Connect to the PCHG FET gate if the

precharge function is used. Leave floating if not used.

PCHG

CHG

BAT

28

29

30

31

O

P

NMOS charge FET drive output pin. Connect to the CHG FET gate.

Primary power supply input pin. Connect through the diode and series resistor to the

top of the cell stack.

PBI

Power supply backup input pin. Connect to the 2.2-µF capacitor to VSS.

Sense voltage input pin for the sixth cell from the bottom of the stack, balance current

input for the sixth cell from the bottom of the stack. Should be connected to the

positive terminal of the sixth cell from the bottom of stack with 100-Ωseries resistor

and a 0.1-µF capacitor to VC5. If not used, connect to VC5.

VC6

32

AI

(1) P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output

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VC4

CDEN4

CDEN3

BAT

PACK

VCC

VC3

+

BATDET

ENVCC

3.1 V

œ

PACK

Detector

VC2

ADC Mux

ADC

PACKDET

PBI

SHUTDOWN

Shutdown

Latch

CDEN2

Reference

System

1.8 V

Domain

SHOUT

VC1

ENBAT

BAT

Control

CDEN1

Power Supply Control

Cell Balancing

VCC

CHGEN

BAT

2

kꢀ

CHG

Pump

8 kꢀ

PCHG

2 kꢀ

CHGOFF

PCHGEN

Precharge

Drive

PACK

DSGEN

BAT

2 kꢀ

DSG

Pump

DSGOFF

CHG, DSG Drive

图6-2. Pin Equivalent Diagram 1

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1.8 V

ADTHx

BAT

FUSEWKPUP

18 kΩ

2 kΩ

ADC Mux

ADC

150 nA

TS1,2,3,4

FUSEEN

2 kΩ

FUSE

1.8 V

100 kΩ

FUSEDIG

RCWKPUP

RCPUP

FUSE Drive

1 kΩ

RCIN

RCOUT

100 kΩ

SMBCIN

SMBC

Thermistor Inputs

SMBCOUT

SMBCEN

1 MΩ

PBI

100 kΩ

SMBDIN

SMBD

RHOEN

SMBDOUT

10 kΩ

SMBDEN

1 MΩ

PRES

SMBus Interface

RHOUT

100 kΩ

RHIN

High-Voltage GPIO

BAT

RLOEN

LED1, 2, 3

22.5 mA

RLOUT

100 kΩ

RLIN

LED Drive

图6-3. Pin Equivalent Diagram 2

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7 Specifications

7.1 Absolute Maximum Ratings

Over-operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Supply voltage range,

BAT⁽²⁾, VCC⁽²⁾, PBI⁽²⁾, PACK⁽²⁾

V_CC

35

V

–0.3

SMBC, SMBD, DISP/GPIO, PDSG/GPIO, PRES/ SHUTDN/ DISP/

PDSG/GPIO⁽²⁾

V

–0.3

TS1, TS2, TS3/ADCIN1/GPIO, DISP/TS4/ADCIN2/GPIO

LEDCNTLA/PDSG/GPIO, LEDCNTLB/GPIO, LEDCNTLC/GPIO⁽²⁾

SRP, SRN

V_REG+ 0.3

V_BAT+ 0.3

V_REG+ 0.3

VSS + 35

43

V

–0.3

VC6

VC5 –0.3

VC4 –0.3

VC3 –0.3

VC2 –0.3

VC1 –0.3

VSS –0.3

–0.3

Input voltage range, V_IN

VC5

VC4

VC3

VC2

VC1

CHG, DSG⁽²⁾

Output voltage range,

V_O

PCHG, FUSE

35

V

–0.3

Maximum VSS current, I_SS

50

mA

Functional temperature T_FUNC

Storage temperature, T_STG

110

–40

–65

150

°C

Lead temperature (soldering, 10 s), T_SOLDER

300

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) A series 50-Ωor larger resistor is needed when voltage is applied beyond 28 V.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Electrostatic

discharge

V_(ESD)

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Typical values stated where T_A= 25°C and VCC = 25.2 V, Min/Max values stated where T_A= –40°C to 85°C and VCC = 2.2

V to 32 V (unless otherwise noted)

MIN

2.2

NOM

MAX

32

UNIT

V_CC

Supply voltage

BAT⁽¹⁾, VCC⁽¹⁾, PBI⁽¹⁾, PACK⁽¹⁾

V_PACK< V_{SHUTDOWN –}

V

V_SHUTDOWN–Shutdown voltage

1.8

2.0

2.2

V_SHUTDOWN+

V_HYS

Start-up voltage

V_PACK> V_SHUTDOWN–+ V_HYS

2.05

2.25

250

2.45

Shutdown voltage

hysteresis

mV

V

_SHUTDOWN+–V_SHUTDOWN–

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Typical values stated where T_A= 25°C and VCC = 25.2 V, Min/Max values stated where T_A= –40°C to 85°C and VCC = 2.2

V to 32 V (unless otherwise noted)

MIN

NOM

MAX

32

V_REG

V_BAT

UNIT

SMBC, SMBD, DISP/GPIO, PDSG/GPIO, PRES/

SHUTDN/, DISP/PDSG/GPIO⁽¹⁾

TS1, TS2, TS3/ADCIN1/GPIO, DISP/TS4/ADCIN2/GPIO

LEDCNTLA/PDSG/GPIO, LEDCNTLB/GPIO, LEDCNTLC/

GPIO⁽¹⁾

SRP, SRN

VC6

0.2

–0.2

V_IN

Input voltage range

V

V_VC5

V_VC4

V_VC3

V_VC2

V_VC1

V_VSS

VC5 + 5

VC4 + 5

VC3 + 5

VC2 + 5

VC1 + 5

VSS + 5

VC5

VC4

VC3

VC2

VC1

Output voltage

range

V_O

PCHG, FUSE⁽¹⁾

32

V

External PBI

capacitor

C_PBI

T_OPR

2.2

µF

°C

Operating

temperature

85

–40

(1) A series 50-Ωor larger resistor is needed when voltage is applied beyond 28 V.

7.4 Thermal Information

BQ40Z80

THERMAL METRIC⁽¹⁾

RSM (QFN)

32 PINS

47.4

UNIT

R_{θJA, High K}

R_θJC(top)

R_θJB

Junction-to-ambient thermal resistance

Junction-to-case(top) thermal resistance

Junction-to-board thermal resistance

°C/W

40.3

14.7

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

0.8

ψ_JT

14.4

ψ_JB

R_θJC(bottom)

3.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.5 Electrical Characteristics

Typical values stated where T_A= 25°C and VCC = 21.6 V, Min/Max values stated where T_A= –40°C to 85°C and VCC = 2.2

V to 32 V unless otherwise noted

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Supply Currents

CPU not active, CHG on. DSG on, High Frequency

Oscillator on, Low Frequency Oscillator on, REG18

on, ADC on, ADC_Filter on, CC_Filter on, CC on,

LED/Buttons/GPIOs off, SMBus not active, no Flash

write

I_NORMAL

NORMAL mode

663

µA

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Typical values stated where T_A= 25°C and VCC = 21.6 V, Min/Max values stated where T_A= –40°C to 85°C and VCC = 2.2

V to 32 V unless otherwise noted

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

CPU not active, CHG on, DSG on, High Frequency

Oscillator off, Low Frequency Oscillator on, REG18

on, ADC off, ADC_Filter off, CC_Filter off, LED/

Buttons/GPIOs off, SMBus not active, no Flash

write

96

µA

I_SLEEP

SLEEP mode

CPU not active, CHG off. DSG on, High Frequency

Oscillator off, Low Frequency Oscillator on, REG18

on, ADC off, ADC_Filter off, CC_Filter off, LED/

Buttons/GPIOs off, SMBus not active, no Flash

write, BAT = 14.4 V

90

µA

CPU not active, CHG off. DSG off, High Frequency

Oscillator off, Low Frequency Oscillator off, REG18

off, ADC off, ADC_Filter off, CC_Filter off, LED/

Buttons/GPIOs off, SMBus not active, no Flash

write, BAT = 14.4 V

I_SHUTDOWN

SHUTDOWN mode

1.4

Power Supply Control

BAT to VCC switchover

voltage

V_{SWITCHOVER–}

V_SWITCHOVER+

V_HYS

V_BAT< V_{SWITCHOVER–}

1.95

2.9

2.1

3.1

2.2

V

VCC to BAT switchover

voltage

V_BAT> V_{SWITCHOVER–}+ V_HYS

3.25

Switchover voltage

hysteresis

1000

mV

V

_SWITCHOVER+–V_{SWITCHOVER–}

BAT pin, BAT = 0 V, VCC = 32 V, PACK = 32 V

PACK pin, BAT = 32 V, VCC = 0 V, PACK = 0 V

1

I_LKG

Input Leakage Current

µA

kΩ

V

BAT and PACK terminals, BAT = 0 V, VCC = 0 V,

PACK = 0 V, PBI = 32 V

1

Internal pulldown

resistance

R_PD

PACK

30

40

50

AFE Power-On Reset

Negative-going voltage

input

V_REGIT–

V_REG

1.51

1.55

1.59

V_HYS

t_RST

Power-on reset hysteresis

Power-on reset time

70

100

300

130

400

mV

µs

V

_REGIT+–V_REGIT–

200

AFE Watchdog Reset and Wake Timer

t_WDT= 500

372

744

500

1000

2000

4000

250

628

1256

2512

5024

314

ms

t_WDT= 1000

t_WDT= 2000

t_WDT= 4000

t_WAKE= 250

t_WAKE= 500

t_WAKE= 1000

t_WAKE= 2000

t_FETOFF= 512

t_WDT

AFE watchdog timeout

1488

2976

186

372

500

628

t_WAKE

AFE wake timer

744

1000

2000

512

1256

2512

614

1488

409

t_FETOFF

FET off delay after reset

Internal 1.8-V LDO

V_REG

Regulator voltage

1.6

1.8

2

V

Regulator output over

temperature

±0.25%

ΔV_O(TEMP)

ΔV_REG/ ΔT_A, I_REG= 10 mA

Line regulation

Load regulation

0.5%

1.5%

ΔV_O(LINE)

ΔV_O(LOAD)

ΔV_REG/ ΔV_BAT, I_BAT= 10 mA

–0.6%

–1.5%

ΔV_REG/ ΔI_REG, I_REG= 0 mA to 10 mA

Regulator output current

limit

I_REG

V_REG= 0.9 × V_REG(NOM), V_IN> 2.2 V

20

mA

10

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ZHCSIH4B –JUNE 2018 –REVISED SEPTEMBER 2020

Typical values stated where T_A= 25°C and VCC = 21.6 V, Min/Max values stated where T_A= –40°C to 85°C and VCC = 2.2

V to 32 V unless otherwise noted

PARAMETER

CONDITIONS

V_REG= 0 × V_REG(NOM)

MIN

TYP

MAX

UNIT

Regulator short-circuit

current limit

I_SC

25

40

55

mA

Power supply rejection

ratio

ΔV_BAT/ ΔV_REG, I_REG= 10 mA, V_IN> 2.5 V, f = 10

Hz

PSRR_REG

V_SLEW

40

dB

V

Slew rate enhancement

voltage threshold

V_REG

1.58

1.65

Voltage Reference 1

V_REF1

Internal reference voltage T_A= 25°C, after trim

1.215

1.22 1.225

V

T_A= 0°C to 60°C, after trim

±50

±80

PPM/°C

Internal reference voltage

drift

V_REF1(DRIFT)

T_A= –40°C to 85°C, after trim

Voltage Reference 2

V_REF2

Internal reference voltage T_A= 25°C, after trim

1.22 1.225

1.23

V

T_A= 0°C to 60°C, after trim

±50

±80

PPM/°C

Internal reference voltage

drift

V_REF2(DRIFT)

T_A= –40°C to 85°C, after trim

VC1, VC2, VC3, VC4, VC5, VC6, BAT, PACK

VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3,

VC5–VC4, VC6–VC5

0.198

0.2 0.202

0.032 0.0333 0.034

0.0275 0.0286 0.0295

VC6–VSS

K

Scaling factor

–

BAT–VSS, PACK–VSS

V_REF2

0.49

0.5

0.51

5

VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3,

VC5–VC4, VC6–VC5

–0.2

V_IN

Input voltage range

Input leakage current

V

30

32

VC6–VSS

–0.2

PACK–VSS

VC1, VC2, VC3, VC4, VC5, VC6, cell balancing off,

cell detach detection off, ADC multiplexer off

I_LKG

1

µA

Cell Balancing and Cell Detach Detection

Internal cell balance

resistance

R_CB

R_DS(ON)for internal FET switch at 2 V < VDS < 4 V

VCx > VSS + 0.8 V

200

70

Ω

Internal cell detach check

current

I_CD

30

50

µA

ADC

Internal reference (V_REF1

)

1

–0.2

–V_FS

V_IN

Input voltage range

Full scale range

V

0.8 ×

V_REG

External reference (V_REG

V_FS= V_REF1or V_REG

)

V_FS

Integral nonlinearity (1 LSB

= V_REF1/(10 × 2^N) =

1.225/(10 × 2¹⁵) = 37.41

µV)

±8.5

16-bit, best fit, –0.1 V to 0.8 × V_REF1

INL

LSB

±13.1

16-bit, best fit, –0.2 V to –0.1 V

OE

Offset error

16-bit, post calibration, V_FS= V_REF1

16-bit, –0.1 V to 0.8 × V_FS

±67

0.6

±157

3

µV

OED

Offset error drift

Gain error

µV/°C

/FSR

GE

±0.2% ±0.8%

GED

Gain error drift

Effective input resistance

150 PPM/°C

16-bit, –0.1 V to 0.8 × V_FS

EIR

8

MΩ

ADC Digital Filter

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ZHCSIH4B –JUNE 2018 –REVISED SEPTEMBER 2020

Typical values stated where T_A= 25°C and VCC = 21.6 V, Min/Max values stated where T_A= –40°C to 85°C and VCC = 2.2

V to 32 V unless otherwise noted

PARAMETER

CONDITIONS

ADCTL[SPEED1, SPEED0] = 0, 0

ADCTL[SPEED1, SPEED0] = 0, 1

ADCTL[SPEED1, SPEED0] = 1, 0

ADCTL[SPEED1, SPEED0] = 1, 1

MIN

TYP

31.25

15.63

7.81

MAX

UNIT

t_CONV

Conversion time

ms

1.95

No missing codes, ADCTL[SPEED1, SPEED0] = 0,

0

Res

Resolution

16

Bits

With sign, ADCTL[SPEED1, SPEED0] = 0, 0

With sign, ADCTL[SPEED1, SPEED0] = 0, 1

With sign, ADCTL[SPEED1, SPEED0] = 1, 0

With sign, ADCTL[SPEED1, SPEED0] = 1, 1

14

13

11

9

15

14

12

10

Eff_Res

Effective Resolution

Current Wake Comparator

±0.3 ±0.625

±0.9

±1.8

±3.6

±7.2

V_WAKE= V_SRP–V_SRN= ± 0.625 mV

V_WAKE= V_SRP–V_SRN= ± 1.25 mV

V_WAKE= V_SRP–V_SRN= ± 2.5 mV

V_WAKE= V_SRP–V_SRN= ± 5 mV

±0.6

±1.2

±2.4

±1.25

±2.5

±5.0

V_WAKE

Wake voltage threshold

mV

Temperature drift of V_WAKE

accuracy

V_WAKE(DRIFT)

t_WAKE

0.5%

250

/°C

µs

Time from application of

current to wake interrupt

700

Wake comparator startup

time

t_WAKE(SU)

500

1000

µs

Coulomb Counter

V_INPUT

Input voltage range

0.1

V

–0.1

–

V_REF1/

V_REF1

/

V_RANGE

Full scale range

10

Integral nonlinearity (1 LSB

= V_REF1/(10 × 2^N) =

INL

16-bit, best fit over input voltage range

±5.2 ±22.3

LSB

1.215/(10 × 2¹⁵) = 3.71 µV)

OE

Offset error

16-bit, post calibration

±5.0

0.2

±10

0.3

µV

OED

GE

Offset error drift

Gain error

15-bit + sign, post calibration

µV/°C

/FSR

15-bit + sign, Over input voltage range

±0.2% ±0.8%

GED

EIR

Gain error drift

150 PPM/°C

Effective input resistance

Conversion Time

Effective Resolution

2.5

15

MΩ

ms

t_CONV

Eff_Res

Single conversion

250

Bits

Current Protection Thresholds

V_OCD= V_SRP–V_SRN

PROTECTION_CONTROL[RSNS] = 1

,

mV

–16.6

–8.3

–100

–50

OCD detection threshold

voltage range

V_OCD

V_OCD= V_SRP–V_SRN

PROTECTION_CONTROL[RSNS] = 0

,

V_OCD= V_SRP–V_SRN

PROTECTION_CONTROL[RSNS] = 1

,

–5.56

–2.78

OCD detection threshold

voltage program step

ΔV_OCD

V_OCD= V_SRP–V_SRN

PROTECTION_CONTROL[RSNS] = 0

,

12

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ZHCSIH4B –JUNE 2018 –REVISED SEPTEMBER 2020

Typical values stated where T_A= 25°C and VCC = 21.6 V, Min/Max values stated where T_A= –40°C to 85°C and VCC = 2.2

V to 32 V unless otherwise noted

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

V_SCC= V_SRP–V_SRN

PROTECTION_CONTROL[RSNS] = 1

,

44.4

200

mV

SCC detection threshold

voltage range

V_SCC

V_SCC= V_SRP–V_SRN

PROTECTION_CONTROL[RSNS] = 0

,

22.2

100

mV

V_SCC= V_SRP–V_SRN

,

22.2

11.1

PROTECTION_CONTROL[RSNS] = 1

SCC detection threshold

voltage program step

ΔV_SCC

V_SCC= V_SRP–V_SRN

,

PROTECTION_CONTROL[RSNS] = 0

V_SCD1= V_SRP–V_SRN

PROTECTION_CONTROL[RSNS] = 1

,

–44.4

–22.2

–200

–100

SCD1 detection threshold

voltage range

V_SCD1

V_SCD1= V_SRP–V_SRN

PROTECTION_CONTROL[RSNS] = 0

,

V_SCD1= V_SRP–V_SRN

PROTECTION_CONTROL[RSNS] = 1

,

–22.2

–11.1

SCD1 detection threshold

voltage program step

ΔV_SCD1

V_SCD1= V_SRP–V_SRN

PROTECTION_CONTROL[RSNS] = 0

,

V_SCD2= V_SRP–V_SRN

PROTECTION_CONTROL[RSNS] = 1

,

–44.4

–22.2

–200

–100

SCD2 detection threshold

voltage range

V_SCD2

V_SCD2= V_SRP–V_SRN

PROTECTION_CONTROL[RSNS] = 0

,

V_SCD2= V_SRP–V_SRN

PROTECTION_CONTROL[RSNS] = 1

,

–22.2

–11.1

SCD2 detection threshold

voltage program step

ΔV_SCD2

V_SCD2= V_SRP–V_SRN

PROTECTION_CONTROL[RSNS] = 0

,

OCD, SCC, and SCDx

offset error

V_OFFSET

Post-trim

2.5

–2.5

No trim

10%

5%

–10%

–5%

OCD, SCC, and SCDx

scale error

V_SCALE

Post-trim

Current Protection Timing

t_OCD

OCD detection delay time

1

0

31

ms

µs

OCD detection delay time

program step

2

Δt_OCD

t_SCC

SCC detection delay time

915

SCC detection delay time

program step

61

µs

Δt_SCC

PROTECTION_CONTROL[SCDDx2] = 0

PROTECTION_CONTROL[SCDDx2] = 1

PROTECTION_CONTROL[SCDDx2] = 0

PROTECTION_CONTROL[SCDDx2] = 1

PROTECTION_CONTROL[SCDDx2] = 0

PROTECTION_CONTROL[SCDDx2] = 1

PROTECTION_CONTROL[SCDDx2] = 0

PROTECTION_CONTROL[SCDDx2] = 1

0

915

µs

t_SCD1

SCD1 detection delay time

1850

61

SCD1 detection delay time

program step

Δt_SCD1

121

0

458

915

t_SCD2

SCD2 detection delay time

30.5

61

SCD2 detection delay time

program step

Δt_SCD2

V

_SRP–V_SRN= V_T–3 mV for OCD, SCD1 and

t_DETECT

t_ACC

Current fault detect time

160

µs

SCD2, V_SRP–V_SRN= VT –3 mV for SCC

Current fault delay time

accuracy

Max delay setting

10%

–10%

Internal Temperature Sensor

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ZHCSIH4B –JUNE 2018 –REVISED SEPTEMBER 2020

Typical values stated where T_A= 25°C and VCC = 21.6 V, Min/Max values stated where T_A= –40°C to 85°C and VCC = 2.2

V to 32 V unless otherwise noted

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

mV/°C

V_TEMPP

_TEMPP–V_TEMPN, assured by design

–1.9

–2.1

Internal temperature

sensor voltage drift

V_TEMPT

0.177 0.178 0.179

V

NTC Thermistor Measurement Support (TS1, TS2, Pins 12 and 13 configured as TS3 and TS4)

TS1

TS2

14.4

18

21.6

kΩ

R_NTC(PU)

Internal pullup resistance

TS3

TS4

kΩ

R_NTC(DRIFT)

PPM/°C

–360 –280 –200

Low-Voltage General Purpose I/O (Multifunction Pins 12 and 13 configured as GPIO)

0.65 ×

V_REG

V_IH

V_IL

High-level input

Low-level input

V

0.35 ×

V_REG

Output high, pullup enabled, I_OH= –1.0 mA

Output high, pullup enabled, I_OH= –10 µA

0.75 ×

V_REG

V_OH

Output voltage high

Output voltage low

V

0.2 ×

V_REG

V_OL

Output Low, I_OL= 1mA

C_IN

Input capacitance

5

pF

µA

I_LKG

Input leakage current

1

High-Voltage General Purpose I/O (multifunction pins 15, 16, 17 configured as GPIO, PRES, DISP, or SHUTDN Pin 15 configured

as GPIO; Pin 16 configured as PDSG)

V_IH

V_IL

High-level input

Low-level input

1.3

V

0.55

3.5

1.8

Output enabled, V_BAT> 5.5 V, I_OH= –0 µA

Output enabled, V_BAT> 5.5 V, I_OH= –10 µA

Output disabled, I_OL= 1.5 mA

V_OH

Output voltage high

V

V_OL

C_IN

Output voltage low

Input capacitance

Input leakage current

0.4

3

V

5

pF

µA

I_LKG

Between GPIO, PRES, DISP, SHUTDN, PDSG,

and PBI

R_O

Output reverse resistance

8

kΩ

General Purpose I/O with Constant Current Sink (Multifunction Pins 20, 21, 22 configured as LEDCNTLx)

V_IH

V_IL

High-level input

Low-level input

LEDCNTLx

1.45

V

0.55

LEDCNTLx, Output Enabled, V_BAT> 3.0 V, I_OH= – V_BAT

–

V_OH

V_OL

Output voltage high

Output voltage low

V

22.5 mA

1.6

LEDCNTLx, Output Disabled, V_BAT> 3.0 V, I_OH= 3

mA

0.4

High level output current

protection

I_SC

LEDCNTLx

mA

–30

–45

–60

I_OL

Low level output current

LEDCNTLx, V_BAT> 3.0 V, V_OL> 0.4 V

LEDCNTLx, V_BAT= V_LED+ 2.5 V

15.75

22.5 29.25

+/–1%

Current matching between

outputs

I_LEDCNTLx

C_IN

Input capacitance

LEDCNTLx

20

pF

µA

Hz

°C

I_LKG

Input leakage current

1

f_LED

Frequency of LED pattern LEDCNTLx

Thermal shutdown LEDCNTLx, assured by design

124

135

t_SHUTDOWN

120

150

General Purpose I/O (Multifunction Pins 20, 21, 22 configured as GPIO) (Pin 20 configured as PDSG)

14

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ZHCSIH4B –JUNE 2018 –REVISED SEPTEMBER 2020

Typical values stated where T_A= 25°C and VCC = 21.6 V, Min/Max values stated where T_A= –40°C to 85°C and VCC = 2.2

V to 32 V unless otherwise noted

PARAMETER

High-level input

Low-level input

CONDITIONS

MIN

TYP

MAX

UNIT

V

V_IH

V_IL

1.45

0.55

V

V_BAT

–

V

Output enabled, V_BAT> 3.0 V, I_OH= –22.5 mA

1.6

V_OH

Output voltage high

Output disabled, I_OL= 3 mA

0.4

High level output current

protection

I_SC

mA

–30

–45

–60

I_OL

Low level output current

Input capacitance

V_BAT> 3.0 V, V_OL> 0.4 V

15.75

22.5 29.25

mA

pF

C_IN

I_LKG

20

Input leakage current

1

uA

SMBD, SMBC High Voltage I/O

V_IH

Input voltage high

Input voltage low

SMBC, SMBD, V_REG= 1.8 V

1.3

V

V_IL

SMBC, SMBD, V_REG= 1.8 V

0.8

V_OL

C_IN

Output low voltage

Input capacitance

Input leakage current

Pulldown resistance

SMBC, SMBD, V_REG= 1.8 V, I_OL= 1.5 mA

0.4

V

5

pF

µA

MΩ

I_LKG

R_PD

SMBus

1

0.7

10

1

1.3

SMBus operating

frequency

f_SMB

SLAVE mode, SMBC 50% duty cycle

100

kHz

µs

SMBus master clock

frequency

f_MAS

MASTER mode, no clock low slave extend

51.2

Bus free time between

start and stop

t_BUF

4.7

4

Hold time after (repeated)

start

t_HD(START)

µs

t_SU(START)

t_SU(STOP)

t_HD(DATA)

t_SU(DATA)

t_TIMEOUT

t_LOW

Repeated start setup time

Stop setup time

4.7

4

µs

ns

ms

µs

ns

Data hold time

300

250

25

Data setup time

Error signal detect time

Clock low period

Clock high period

Clock rise time

35

4.7

4

t_HIGH

50

1000

300

t_R

10% to 90%

90% to 10%

t_F

Clock fall time

Cumulative clock low slave

extend time

t_LOW(SEXT)

25

10

ms

Cumulative clock low

master extend time

t_LOW(MEXT)

SMBus XL

f_SMBXL

SMBus XL operating

frequency

SLAVE mode, SMBC 50% duty cycle

40

4.7

4

400

kHz

µs

Bus free time between

start and stop

t_BUF

Hold time after (repeated)

start

t_HD(START)

µs

t_SU(START)

t_SU(STOP)

Repeated start setup time

Stop setup time

4.7

4

µs

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ZHCSIH4B –JUNE 2018 –REVISED SEPTEMBER 2020

Typical values stated where T_A= 25°C and VCC = 21.6 V, Min/Max values stated where T_A= –40°C to 85°C and VCC = 2.2

V to 32 V unless otherwise noted

PARAMETER

CONDITIONS

MIN

TYP

MAX

20

UNIT

ms

µs

t_TIMEOUT

t_LOW

Error signal detect time

Clock low period

Clock high period

5

20

t_HIGH

20

µs

FUSE Drive (AFEFUSE)

6

7

8.65

V_BAT

V

_BAT≥8 V, C_L= 1 nF, I_AFEFUSE= 0 µA

V_OH

Output voltage high

V_BAT

–

0.1

V_BAT< 8 V, C_L= 1 nF, I_AFEFUSE= 0 µA

V_IH

High-level input

1.5

2

150

2.6

5

2.5

330

3.2

V

nA

kΩ

pF

µs

I_AFEFUSE(PU)

R_AFEFUSE

C_IN

Internal pullup current

Output impedance

Input capacitance

V_BAT< 8 V, V_AFEFUSE= VSS

t_DELAY

t_RISE

Fuse trim detection delay

Fuse output rise time

128

256

20

5

µs

N-CH FET Drive (CHG, DSG)

Ratio_DSG= (V_DSG–V_BAT) / V_BAT, 2.2 V < V_BAT

4.92 V, 10 MΩbetween PACK and DSG

<

2.133 2.333

2.45

––

V

Output voltage ratio

Ratio_CHG= (V_CHG–V_BAT) / V_BAT, 2.2 V < V_BAT

4.92 V, 10 MΩbetween BAT and CHG

2.133 2.333 2.433

V_DSG(ON)= (V_DSG–V_BAT), V_BAT≥4.92 V (up to 32

V), 10 MΩbetween PACK and DSG

10.5

11.5

12.5

0.4

Output voltage, CHG and

DSG on

V_FETON

V_CHG(ON)= (V_CHG–V_BAT), V_BAT≥4.92 V (up to 32

V), 10 MΩbetween BAT and CHG

V

V_DSG(OFF)= (V_DSG–V_PACK), 10 MΩbetween

PACK and DSG

V

–0.4

Output voltage, CHG and

DSG off

V_FETOFF

V_CHG(OFF)= (V_CHG–V_BAT), 10 MΩbetween BAT

and CHG

0.4

V

V_DSGfrom 0% to 35% V_DSG(ON)(TYP), V_BAT≥2.2 V,

C_L= 4.7 nF between DSG and PACK, 5.1 kΩ

between DSG and C_L, 10 MΩbetween PACK and

DSG

200

500

µs

t_R

Rise time

V_CHGfrom 0% to 35% V_CHG(ON)(TYP), V_BAT≥2.2 V,

C_L= 4.7 nF between CHG and BAT, 5.1 kΩ

between CHG and C_L, 10 MΩbetween BAT and

CHG

V_DSGfrom V_DSG(ON)(TYP)to 1 V, V_BAT≥2.2 V, C_L=

4.7 nF between DSG and PACK, 5.1 kΩbetween

DSG and C_L, 10 MΩbetween PACK and DSG

40

300

200

µs

t_F

Fall time

V_CHGfrom V_CHG(ON)(TYP)to 1 V, V_BAT≥2.2 V, C_L=

4.7 nF between CHG and BAT, 5.1 kΩbetween

CHG and C_L, 10 MΩbetween BAT and CHG

P-CH FET Drive (PCHG)

V_PCHG(ON)= V_CC–V_PCHG, 10 MΩbetween VCC

and CHG, V_BAT≥8 V

V_FETON

Output voltage, PCHG on

6

7

8

V

V_PCHG(OFF)= V_CC–V_PCHG, 10 MΩbetween VCC

and CHG

V_FETOFF

Output voltage, PCHG off

Rise time

0.4

–0.4

V_PCHGfrom 10% to 90% V_{PCHG(ON)(TYP)}, V_SS≥8 V,

C_L= 4.7 nF between PCHG and VCC, 5.1 kΩ

between PCHG and C_L, 10 MΩbetween VCC and

CHG

t_R

40

200

µs

16

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ZHCSIH4B –JUNE 2018 –REVISED SEPTEMBER 2020

Typical values stated where T_A= 25°C and VCC = 21.6 V, Min/Max values stated where T_A= –40°C to 85°C and VCC = 2.2

V to 32 V unless otherwise noted

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

V_PCHGfrom 90% to 10% V_{PCHG(ON)(TYP)}, V_SS≥8 V,

C_L= 4.7 nF between PCHG and VCC, 5.1 kΩ

between PCHG and C_L, 10 MΩbetween VCC and

CHG

t_F

Fall time

40

200

µs

High-Frequency Oscillator

f_HFO

Operating frequency

16.78

±0.25%

MHz

2.5%

3.5%

T_A= –20°C to 70°C, includes frequency drift

T_A= –40°C to 85°C, includes frequency drift

–2.5%

–3.5%

f_HFO(ERR)

Frequency error

Start-up time

T_A= –20°C to 85°C, CLKCTL[HFRAMP] = 1,

oscillator frequency within ±3% of nominal

4

ms

µs

t_HFO(SU)

T_A= –20°C to 85°C, CLKCTL[HFRAMP] = 0,

oscillator frequency within ±3% of nominal

100

Low-Frequency Oscillator

262.14

4

f_LFO

Operating frequency

kHz

±0.25%

80

1.5%

2.5%

100

T_A= –20°C to 70°C, includes frequency drift

T_A= –40°C to 85°C, includes frequency drift

–1.5%

–2.5%

30

f_LFO(ERR)

Frequency error

t_LFO(FAIL)

Failure detection frequency

Instruction Flash

Data retention

10

Years

Flash programming write

cycles

1000

Cycles

t_PROGWORD

t_MASSERASE

t_PAGEERASE

t_FLASHREAD

t_FLASHWRITE

I_FLASHERASE

Data Flash

Word programming time

Mass-erase time

40

2

µs

ms

mA

Page-erase time

Flash-read current

Flash-write current

Flash-erase current

5

15

Data retention

10

Years

Flash programming write

cycles

20000

Cycles

t_PROGWORD

t_MASSERASE

t_PAGEERASE

t_FLASHREAD

t_FLASHWRITE

I_FLASHERASE

Word programming time

Mass-erase time

40

1

µs

ms

mA

Page-erase time

Flash-read current

Flash-write current

Flash-erase current

5

15

ECC Authentication

CPU active, CHG on. DSG on, High Frequency

Oscillator on, Low Frequency Oscillator on, REG18

on, ADC on, ADC_Filter on, CC_Filter on, CC on,

SMBus not active, Authentication Start

NORMAL mode +

Authentication

I_NORMAL+AUTH

1350

375

µA

EC-KCDSA signature

signing time

t_SIGN

3.8 V < VCC or BAT < 32 V

ms

Number of Authentication

operations

20000

Operations

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7.6 Typical Characteristics

1.9

1.88

1.86

1.84

1.82

1.8

1.225

1.224

1.223

1.222

1.221

1.22

1.78

1.76

1.74

1.72

1.7

1.219

1.218

1.217

1.216

1.215

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100 110

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100 110

Temperature (èC)

VREF

图7-1. VREG 1.8-V Voltage vs. Temperature

图7-2. VREF 1 Voltage vs. Temperature

1.23

1.229

1.228

1.227

1.226

1.225

1.224

1.223

1.222

1.221

1.22

271

269

267

265

263

261

259

257

255

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100 110

-40

-20

0

20

40

60

80

100

Temperature (èC)

VREF

Temperature (èC)

LFOv

图7-3. VREF 2 Voltage vs. Temperature

图7-4. Low-Frequency Oscillator vs. Temperature

17.55

17.4

-22

-22.2

-22.4

-22.6

-22.8

-23

17.25

17.1

16.95

16.8

-23.2

-23.4

-23.6

-23.8

-24

16.65

16.5

-24.2

-24.4

-24.6

16.35

16.2

-24.8

Setting is -25 mV

16.05

-25

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100 110

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100 110

Temperature (èC)

HFOv

OCD(

图7-5. High-Frequency Oscillator vs. Temperature

图7-6. Overcurrent Discharge Protection

Threshold vs. Temperature

90

89.75

89.5

89.25

89

-86.5

-87

-87.5

-88

88.75

88.5

88.25

88

-88.5

-89

87.75

87.5

87.25

87

-89.5

86.75

Setting is 88.85 mV

Setting is -88.85 mV

60 80 100

86.5

-40 -30 -20 -10

-90

-40

0

10 20 30 40 50 60 70 80 90 100 110

-20

0

20

40

Temperature (èC)

SCC(

Temperature (èC)

SCD1

图7-7. Short Circuit Charge Protection Threshold

图7-8. Short Circuit Discharge 1 Protection

vs. Temperature

Threshold vs. Temperature

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182

181

180

179

178

177

176

175

174

173

172

12.25

12

11.75

11.5

11.25

11

10.75

10.5

10.25

10

Setting is 11 ms

9.75

-40

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100 110

-20

0

20

40

60

80

100

Temperature (èC)

SCD2

Temperature (èC)

OCDe

Threshold setting is –177.7 mV.

图7-10. Overcurrent Delay Time vs. Temperature

图7-9. Short Circuit Discharge 2 Protection

Threshold vs. Temperature

510

505

500

495

490

485

480

475

470

510

505

500

495

490

485

480

475

470

465

488 ms Setting

460

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100 110

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100 110

Temperature (èC)

SCCD

SCD1

图7-11. Short Circuit Charge Current Delay Time

图7-12. Short Circuit Discharge 1 Delay Time vs.

vs. Temperature

Temperature

276

270

264

258

252

246

240

234

228

222

2510

2509

2508

2507

2506

2505

2504

2503

2502

2501

2500

216

244 ms Setting

210

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100 110

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100 110

Temperature (èC)

SCD2

VCEL

图7-13. Short Circuit Discharge 2 Delay Time vs.

图7-14. V_CELLMeasurement at 2.5-V vs.

Temperature

3510

3509

3508

3507

3506

3505

3504

3503

3502

3501

3500

4308

4307

4306

4305

4304

4303

4302

4301

4300

4299

4298

4297

4296

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100 110

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100 110

Temperature (èC)

VCEL

This is the V_CELLaverage for single cell.

图7-15. V_CELLMeasurement at 3.5 V vs.

图7-16. V_CELLMeasurement at 4.3 V vs.

Temperature

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8 Detailed Description

8.1 Overview

The BQ40Z80 device, incorporating patented Impedance Track^™technology, provides cell balancing while

charging or at rest. This fully integrated, single-chip, PACK-based solution provides a rich array of features for

gas gauging, protection, and authentication for 2-series to 7-series cell Li-Ion and Li-Polymer battery packs,

including a diagnostic lifetime data monitor and black box recorder.

8.2 Functional Block Diagram

Cell, Stack,

Pack

Voltage

High Side

N-CH FET

Drive

Cell

Balancing

Cell Detach

Detection

P-CH

FET Drive

Power Mode

Control

Wake

Comparator

Power On

Reset

Watchdog

Timer

ADCIN1

ADCIN2

Short Circuit

Comparator

SRP

SRN

FUSE

Control

Over

Current

Comparator

FUSE

Voltage

Reference 2

Random

Number

Generator

NTC Bias

High

Voltage

I/O

PRES or SHUTDN

TS1

TS2

DISP

Internal

Temp

Sensor

PDSG

GPIO or TS3

GPIO or TS4

GPIO

LEDCNTLC or GPIO

LEDCNTLB or GPIO

LEDCNTLA or PDSG or GPIO

LED Display

Drive I O

/

Voltage

Reference1

AFE Control

ADC MUX

Low

Frequency

Oscillator

SBS High

Voltage

Translation

SMBD

SMBC

ADC/ CC

FRONTEND

1.8 V LDO

Regulator

AFE COM

Engine

High

Frequency

Oscillator

Low Voltage

I/O

I/ O &

Interrupt

Controller

ADC/ CC

Digital Filter

Timers&

PWM

AFE COM

Engine

SBS COM

Engine

Data (8bit)

DMAddr (16bit)

bqBMP

CPU

PMInstr

PMAddr

Program

Flash

EEPROM

Data Flash

EEPROM

Data

SRAM

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8.3 Feature Description

8.3.1 Primary (1st Level) Safety Features

The BQ40Z80 supports a wide range of battery and system protection features that can easily be configured.

See the BQ40Z80 Technical Reference Manual (SLUUBT5) for detailed descriptions of each protection function.

The primary safety features include:

• Cell Overvoltage Protection

• Cell Undervoltage Protection

• Cell Undervoltage Protection Compensated

• Overcurrent in Charge Protection

• Overcurrent in Discharge Protection

• Overload in Discharge Protection

• Short Circuit in Charge Protection

• Short Circuit in Discharge Protection

• Overtemperature in Charge Protection

• Overtemperature in Discharge Protection

• Undertemperature in Charge Protection

• Undertemperature in Discharge Protection

• Overtemperature FET protection

• Precharge Timeout Protection

• Host Watchdog Timeout Protection

• Fast Charge Timeout Protection

• Overcharge Protection

• Overcharging Voltage Protection

• Overcharging Current Protection

• Over Precharge Current Protection

8.3.2 Secondary (2nd Level) Safety Features

The secondary safety features of the BQ40Z80 can be used to indicate more serious faults via the FUSE pin.

This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or

discharging. See the BQ40Z80 Technical Reference Manual (SLUUBT5) for detailed descriptions of each

protection function.

The secondary safety features provide protection against:

• Safety Overvoltage Permanent Failure

• Safety Undervoltage Permanent Failure

• Safety Overtemperature Permanent Failure

• Safety FET Overtemperature Permanent Failure

• Qmax Imbalance Permanent Failure

• Impedance Imbalance Permanent Failure

• Capacity Degradation Permanent Failure

• Cell Balancing Permanent Failure

• Fuse Failure Permanent Failure

• Voltage Imbalance at Rest Permanent Failure

• Voltage Imbalance Active Permanent Failure

• Charge FET Permanent Failure

• Discharge FET Permanent Failure

• AFE Register Permanent Failure

• AFE Communication Permanent Failure

• Second Level Protector Permanent Failure

• Instruction Flash Checksum Permanent Failure

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• Open Cell Connection Permanent Failure

• Data Flash Permanent Failure

• Open Thermistor Permanent Failure

8.3.3 Charge Control Features

The BQ40Z80 charge control features include:

• Supports JEITA temperature ranges. Reports charging voltage and charging current according to the active

temperature range

• Handles more complex charging profiles. Allows for splitting the standard temperature range into two sub-

ranges and allows for varying the charging current according to the cell voltage

• Reports the appropriate charging current needed for constant current charging and the appropriate charging

voltage needed for constant voltage charging to a smart charger using SMBus broadcasts

• Reduces the charge difference of the battery cells in fully charged state of the battery pack gradually using a

voltage-based cell balancing algorithm during charging. A voltage threshold can be set up for cell balancing

to be active. This prevents fully charged cells from overcharging and causing excessive degradation and also

increases the usable pack energy by preventing premature charge termination.

• Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range

• Reports charging fault and also indicates charge status via charge and discharge alarms

8.3.4 Gas Gauging

The BQ40Z80 uses the Impedance Track algorithm to measure and calculate the available capacity in battery

cells. The BQ40Z80 accumulates a measure of charge and discharge currents and compensates the charge

current measurement for the temperature and state-of-charge of the battery. The BQ40Z80 estimates self-

discharge of the battery and also adjusts the self-discharge estimation based on temperature. The device also

has TURBO Mode 2.0/DBPTv2 support, which enables the BQ40Z80 to provide the necessary data for the MCU

to determine what level of peak power consumption can be applied without causing a system reset or transient

battery voltage level spike to trigger termination flags. See the BQ40Z80 Technical Reference Manual

(SLUUBT5) for further details.

8.3.5 Multifunction Pins

The BQ40Z80 includes several multifunction pins that firmware uses to implement different functions. 图 8-1 is a

simplified schematic of an example system implementation that uses a 6-series pack with PRECHARGE mode,

six LEDs, two thermistors, and system-present functionality.

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1k

PACK+

10k

100

LEDCNTLA/

PDSG/GPIO

BAT

VC6

VC5

LEDCNTLB/GPIO

LEDCNTLC/GPIO

DISP*/TS4/

ADCIN2/GPIO

/DISP*/GPIO

VC4

VC3

SMBC

SMBD

SMBC

SMBD

VC2

VC1

PDSG/GPIO

TS3/ADCIN1/

GPIO

PRES*/SHUTDN*/

DISP*/PDSG/GPIO

PRES*

PACK-

图8-1. Simplified Schematic of a BQ40Z80 Configuration

表8-1 shows a summary of other common configurations.

表8-1. BQ40Z80 Multifunction Pin Combinations

Number of

Cells (with

Balancing)

Number of Thermistors

LEDs

LED Button

Pre-Discharge

SYSPRES

4

Yes

Yes (use DISP)

Yes (uses PDSG)

Yes

2S–6S

8.3.6 Configuration

8.3.6.1 Oscillator Function

The BQ40Z80 fully integrates the system oscillators and does not require any external components to support

this feature.

8.3.6.2 System Present Operation

The BQ40Z80 checks the PRES pin periodically (1 s). If PRES input is pulled to ground by the external system,

the BQ40Z80 detects this as system present.

8.3.6.3 Emergency Shutdown

For battery maintenance, the emergency shutdown feature enables a push button action connecting the

SHUTDN pin to shut down an embedded battery pack system before removing the battery. A high-to-low

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transition of the SHUTDN pin signals the BQ40Z80 to turn off both CHG and DSG FETs, disconnecting the

power from the system to safely remove the battery pack. The CHG and DSG FETs can be turned on again by

another high-to-low transition detected by the SHUTDN pin or when a data flash configurable timeout is reached.

8.3.6.4 2-Series, 3-Series, 4-Series, 5-Series, or 6-Series Cell Configuration

In a 2-series cell configuration, VC6 is shorted to VC5, VC4, VC3, and VC2. In a 3-series cell configuration, VC6

is shorted to VC5, VC4, and VC3. In a 4-series cell configuration, VC6 is shorted to VC5 and VC4. In a 5-series

cell configuration, VC6 is shorted to VC5.

8.3.6.5 Cell Balancing

For up to a 6-series cell configuration, the device supports cell balancing by bypassing the current of each cell

during charging or at rest. If the device's internal bypass is used, up to 10 mA can be bypassed and multiple

cells can be bypassed at the same time. A higher cell balance current can be achieved by using an external cell

balancing circuit. In EXTERNAL CELL BALANCING mode, only one cell at a time can be balanced.

The cell balancing algorithm determines the amount of charge needed to be bypassed to balance the capacity of

all cells.

8.3.7 Battery Parameter Measurements

8.3.7.1 Charge and Discharge Counting

The BQ40Z80 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a

second delta-sigma ADC for individual cell and battery voltage and temperature measurement.

The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage

drop across a small-value sense resistor between the SRP and SRN terminals. The integrating ADC measures

bipolar signals from –0.1 V to 0.1 V. The BQ40Z80 detects charge activity when V_SR= V_(SRP)– V_(SRN)is

positive, and discharge activity when V_SR= V_(SRP)– V_(SRN)is negative. The BQ40Z80 continuously integrates

the signal over time, using an internal counter. The fundamental rate of the counter is 0.26 nVh.

8.3.8 Lifetime Data Logging Features

The BQ40Z80 offers lifetime data logging for several critical battery parameters. The following parameters are

updated every 10 hours if a difference is detected between values in RAM and data flash:

• Maximum and Minimum Cell Voltages

• Maximum Delta Cell Voltage

• Maximum Charge Current

• Maximum Discharge Current

• Maximum Average Discharge Current

• Maximum Average Discharge Power

• Maximum and Minimum Cell Temperature

• Maximum Delta Cell Temperature

• Maximum and Minimum Internal Sensor Temperature

• Maximum FET Temperature

• Number of Safety Events Occurrences and the Last Cycle of the Occurrence

• Number of Valid Charge Termination and the Last Cycle of the Valid Charge Termination

• Number of Qmax and Ra Updates and the Last Cycle of the Qmax and Ra Updates

• Number of Shutdown Events

• Cell Balancing Time for Each Cell

(This data is updated every two hours if a difference is detected.)

• Total FW Runtime and Time Spent in Each Temperature Range

(This data is updated every two hours if a difference is detected.)

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8.3.9 Authentication

To support host authentication, the BQ40Z80 uses Elliptic Curve Cryptography (ECC), which requires a strong

163-bit key system for the authentication process. Additionally, the private key is required to be stored only in the

BQ40Z80 Battery Pack Manager, which makes key management more simple and secure. See the BQ40Z80

Technical Reference Manual (SLUUBT5) for further details.

8.3.10 LED Display

The BQ40Z80 can drive a 3-, 4-, or 5- segment LED display for remaining capacity indication and/or a

permanent fail (PF) error code indication.

8.3.11 IATA Support

The BQ40Z80 supports IATA with several new commands and procedures. See the BQ40Z80 Technical

Reference Manual (SLUUBT5) for further details.

8.3.12 Voltage

The BQ40Z80 updates the individual series cell voltages at a 1-second interval. The internal ADC of the

BQ40Z80 measures the voltage, and scales and calibrates it appropriately. This data is also used to calculate

the impedance of the cell for the Impedance Track gas gauging.

8.3.13 Current

The BQ40Z80 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current

using a 1-mΩto 3-mΩtyp. sense resistor.

8.3.14 Temperature

The BQ40Z80 has an internal temperature sensor and inputs for up to four external temperature sensors. All five

temperature sensor options can be individually enabled and configured for cell or FET temperature usage. Two

configurable thermistor models are provided to allow the monitoring of cell temperature in addition to FET

temperature, which use a different thermistor profile.

8.3.15 Communications

The BQ40Z80 uses SMBus v1.1 with MASTER mode and packet error checking (PEC) options per the SBS

specification.

8.3.15.1 SMBus On and Off State

The BQ40Z80 detects an SMBus off state when SMBC and SMBD are low for two or more seconds. Clearing

this state requires that either SMBC or SMBD transition high. The communication bus will resume activity within

1 ms.

8.3.15.2 SBS Commands

See the BQ40Z80 Technical Reference Manual (SLUUBT5) for further details.

8.4 Device Functional Modes

The BQ40Z80 supports three power modes to reduce power consumption:

• In NORMAL mode, the BQ40Z80 performs measurements, calculations, protection decisions, and data

updates in 250-ms intervals. Between these intervals, the BQ40Z80 is in a reduced power stage.

• In SLEEP mode, the BQ40Z80 performs measurements, calculations, protection decisions, and data updates

in adjustable time intervals. Between these intervals, the BQ40Z80 is in a reduced power stage. The

BQ40Z80 has a wake function that enables exit from SLEEP mode when current flow or failure is detected.

• In SHUTDOWN mode, the BQ40Z80 is completely disabled.

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9 Applications and Implementation

Note

以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适

用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The BQ40Z80 is a gas gauge with primary protection support, and can be used with a 2-series to 6-series li-

ion/li-polymer battery pack. To implement and design a comprehensive set of parameters for a specific battery

pack, the Battery Management Studio (BQSTUDIO) graphical user-interface tool must be installed on a PC

during development.

9.2 Typical Applications

图9-1. BQ40Z80EVM Gauge and Protector Schematic

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9.2.1 Design Requirements

表 9-1 shows the default settings for the main parameters. Use the BQSTUDIO tool to update the settings to

meet the specific application or battery pack configuration requirements.

The device should be calibrated before any gauging test. Follow the BQSTUDIO Calibration page to calibrate

the device, and use the BQSTUDIO Chemistry page to update the match chemistry profile to the device. Design

Parameters shows all of the settings that are configurable in BQSTUDIO and in the BQ40Z80 firmware.

表9-1. Design Parameters

DESIGN PARAMETER

Cell Configuration

EXAMPLE

6s (6-series)⁽¹⁾

Design Capacity

6000 mAh

Device Chemistry

1210 (LiCoO₂/graphitized carbon)

Cell Overvoltage at Standard Temperature

Cell Undervoltage

4300 mV

2500 mV

Shutdown Voltage

2300 mV

Overcurrent in CHARGE Mode

Overcurrent in DISCHARGE Mode

Short Circuit in CHARGE Mode

Short Circuit in DISCHARGE Mode

Safety Overvoltage

6000 mA

–6000 mA

0.1 V/Rsense across SRP, SRN

4500 mV

Cell Balancing

Disabled

Internal and External Temperature Sensor

Undertemperature Charging

Undertemperature Discharging

BROADCAST Mode

External Temperature Sensor is used.

0°C

Disabled

(1) When using the device the first time, if the a 1-s or 2-s battery pack is used, then a charger or power supply should be connected to

the PACK+ terminal to prevent device shutdown. Then update the cell configuration (see the BQ40Z80 Technical Reference Manual

[SLUUBT5] for details) before removing the charger connection.

9.2.2 Detailed Design Procedure

This application section uses the BQ40Z80 evaluation module (EVM) and jumper configurations to allow the user

to evaluate many of the BQ40Z80 features.

9.2.2.1 Using the BQ40Z80EVM with BQSTUDIO

The firmware installed on the BQSTUDIO tool has BQ40Z80 default values, which are summarized in the

BQ40Z80 Technical Reference Manual (SLUUBT5). Using the BQSTUDIO tool, these default values can be

changed to cater to specific application requirements during development once the system parameters, such as

fault trigger thresholds for protection, enable/disable of certain features for operation, configuration of cells,

chemistry that best matches the cell used, and more, are known.

9.2.2.2 High-Current Path

The high-current path begins at the PACK+ terminal of the battery pack. As charge current travels through the

pack, it finds its way through protection FETs, a chemical fuse, the lithium-ion cells and cell connections, and the

sense resistor, and then returns to the PACK– terminal. In addition, some components are placed across the

PACK+ and PACK–terminals to reduce effects from electrostatic discharge.

9.2.2.2.1 Protection FETs

Select the N-CH charge and discharge FETs for a given application. For a 7-series cell application, the charge

FET must be rated above the max voltage, and for this reason the TI CSD18504Q5A is used. The TI

CSD18504Q5A is a 50-A, 40-V device with Rds(on) of 5.3 mΩ when the gate drive voltage is 10 V. For the

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discharge FET, it may see a higher voltage, and so the TI CSD18540Q5B is used. The TI CSD18540Q5B is a

100-A, 60-V device with Rds(on) of 1.8 mΩwhen the gate drive voltage is 10 V.

If a precharge FET is used, R2 is calculated to limit the precharge current to the desired rate. Be sure to account

for the power dissipation of the series resistor. The precharge current is limited to (V_CHARGER– V_BAT)/R2 and

maximum power dissipation is (V_CHARGER–V_BAT)²/R2.

The gates of all protection FETs are pulled to the source with a high-value resistor between the gate and source

to ensure they are turned off if the gate drive is open.

Capacitors C1 and C2 help protect the FETs during an ESD event. Using two devices ensures normal operation

if one becomes shorted. To have good ESD protection, the copper trace inductance of the capacitor leads must

be designed to be as short and wide as possible. Ensure that the voltage rating of both C1 and C2 are adequate

to hold off the applied voltage if one of the capacitors becomes shorted.

9.2.2.2.2 Chemical Fuse

The chemical fuse (Dexerials, Uchihashi, and so on) is ignited under command from either the bq771800

secondary voltage protection IC or from the FUSE pin of the gas gauge. Either of these events applies a positive

voltage to the gate of Q9, which then sinks current from the third terminal of the fuse, causing it to ignite and

open permanently.

It is important to carefully review the fuse specifications and match the required ignition current to that available

from the N-CH FET. Ensure that the proper voltage, current, and Rds(on) ratings are used for this device. The

fuse control circuit is discussed in detail in 节9.2.2.3.5.

9.2.2.2.3 Lithium-Ion Cell Connections

The important part about the cell connections is that high current flows through the top and bottom connections;

therefore, the voltage sense leads at these points must be made with a Kelvin connection to avoid any errors

due to a drop in the high-current copper trace. The location marked 6P indicates the Kelvin connection of the

most positive directly measured battery node. The single-point connection at 1N to the low-current ground is

needed to avoid an undesired voltage drop through long traces while the gas gauge is measuring the bottom cell

voltage.

9.2.2.2.4 Sense Resistor

As with the cell connections, the quality of the Kelvin connections at the sense resistor is critical. The sense

resistor must have a temperature coefficient no greater than 50 ppm to minimize current measurement drift with

temperature. Choose the value of the sense resistor to correspond to the available overcurrent and short-circuit

ranges of the BQ40Z80. Select the smallest value possible to minimize the negative voltage generated on the

BQ40Z80 V_SSnode(s) during a short circuit. This pin has an absolute minimum of –0.3 V. Parallel resistors can

be used as long as good Kelvin sensing is ensured. The device is designed to support a 1-mΩ to 3-mΩ sense

resistor, and a 1-mΩ sense resistor is used, shown as R52. When using 1-mΩ, large currents during a short

circuit event can cause the voltage across the sense resistor to exceed the abs max of the pin. Therefore, it is

required to place 100-Ωseries resistors R47 and R48 as shown in the schematic.

9.2.2.2.5 ESD Mitigation

A pair of series 0.1-µF ceramic capacitors is placed across the PACK+ and PACK– terminals to help mitigate

external electrostatic discharges. The two devices in series ensure continued operation of the pack if one of the

capacitors becomes shorted.

Optionally, a transorb such as the SMBJ2A can be placed across the terminals to further improve ESD immunity.

9.2.2.3 Gas Gauge Circuit

The gas gauge circuit includes the BQ40Z80 and its peripheral components. These components are divided into

the following groups: differential low-pass filter, PBI, system present, SMBus communication, FUSE circuit, and

LED.

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9.2.2.3.1 Coulomb-Counting Interface

The BQ40Z80 uses an integrating delta-sigma ADC for current measurements. Add a 100-Ω resistor from the

sense resistor to the SRP and SRN inputs of the device. Place a 100-pF (C29) filter capacitor across the SRP

and SRN inputs. Optional 0.1-µF filter capacitors (C26 and C27) can be added for additional noise filtering, if

required for your circuit.

9.2.2.3.2 Power Supply Decoupling and PBI

The BQ40Z80 has an internal LDO that is internally compensated and does not require an external decoupling

capacitor.

The PBI pin is used as a power supply backup input pin providing power during brief transient power outages. A

standard 2.2-µF ceramic capacitor is connected from the PBI pin to ground.

9.2.2.3.3 System Present

The System Present signal is used to inform the gas gauge whether the pack is installed into or removed from

the system. In the host system, this pin is grounded. The PRES pin of the BQ40Z80 is used if J5[1, 2] jumper is

installed, and is occasionally sampled to test for system present. To save power, an internal pullup is provided by

the gas gauge during a brief 4-μs sampling pulse once per second. A resistor can be used to pull the signal low

and the resistance must be 20 kΩ or lower to ensure that the test pulse is lower than the VIL limit. The pullup

current source is typically 10 µA to 20 µA.

Because the System Present signal is part of the pack connector interface to the outside world, it must be

protected from external electrostatic discharge events. An integrated ESD protection on the PRES device pin

reduces the external protection requirement to just R12 for an 8-kV ESD contact rating. However, if it is possible

that the System Present signal may short to PACK+, then an E2 spark gap must be included for high-voltage

protection.

9.2.2.3.4 SMBus Communication

The SMBus clock and data pins have integrated high-voltage ESD protection circuits; however, adding a ESD

protection device, TPD1E10B06D (U5 and U6) and series resistor (R50 and R51), provides more robust ESD

performance.

The SMBus clock and data lines have an internal pulldown. When the gas gauge senses that both lines are low

(such as during removal of the pack), the device performs auto-offset calibration and then goes into SLEEP

mode to conserve power.

9.2.2.3.5 FUSE Circuitry

The FUSE pin of the BQ40Z80 is designed to ignite the chemical fuse if one of the various safety criteria is

violated. The FUSE pin also monitors the state of the secondary-voltage protection IC. Q9 ignites the chemical

fuse when its gate is high. The output of the bq7718xx is divided by R22 and R30, which provides adequate gate

drive for Q9 while guarding against excessive back current into the bq7718xx if the FUSE signal is high.

Using C8 is generally a good practice, especially for RFI immunity. C8 may be removed, if desired, because the

chemical fuse is a comparatively slow device and is not affected by any sub-microsecond glitches that come

from the FUSE output during the cell connection process.

If the AFEFUSE output is not used, it should be connected to VSS.

When the BQ40Z80 is commanded to ignite the chemical fuse, the FUSE pin activates to give a typical 8-V

output.

9.2.2.4 Secondary-Current Protection

The BQ40Z80 provides secondary overcurrent and short-circuit protection, cell balancing, cell voltage

multiplexing, and voltage translation. The following discussion examines cell and battery inputs, pack and FET

control, temperature output, and cell balancing.

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9.2.2.4.1 Cell and Battery Inputs

Each cell input is conditioned with a simple RC filter, which provides ESD protection during cell connect and acts

to filter unwanted voltage transients. The resistor value allows some trade-off for cell balancing versus safety

protection.

The BQ40Z80 has integrated cell balancing FETs The internal cell balancing FETs allow the AFE to bypass cell

current around a given cell or numerous cells. External series resistors placed between the cell connections and

the VCx I/O pins set the balancing current magnitude. The internal FETs provide a 200-Ωresistance (2 V < VDS

< 4 V). Series input resistors between 100 Ωand 1 kΩare recommended for effective cell balancing.

The BAT input uses a diode (D6) to isolate and decouple it from the cells in the event of a transient dip in voltage

caused by a short-circuit event.

9.2.2.4.2 External Cell Balancing

Internal cell balancing can only support up to 10 mA. External cell balancing provides another option for faster

cell balancing. For details, refer to the application note, Fast Cell Balancing Using External MOSFET (SLUA420).

9.2.2.4.3 PACK and FET Control

The PACK and V_CCinputs provide power to the BQ40Z80 from the charger. The PACK input also provides a

method to measure and detect the presence of a charger. The PACK input uses a 100-Ω resistor; whereas, the

V_CCinput uses a diode to guard against input transients and prevents misoperation of the date driver during

short-circuit events.

The N-CH charge and discharge FETs are controlled with 10-kΩseries gate resistors, which provide a switching

time constant of a few microseconds. The 10-MΩ resistors ensure that the FETs are off in the event of an open

connection to the FET drivers. Q4 is provided to protect the discharge FET (Q3) in the event of a reverse-

connected charger. Without Q4, Q3 can be driven into its linear region and suffer severe damage if the PACK+

input becomes slightly negative. Q4 turns on in that case to protect Q3 by shorting its gate to source. To use the

simple ground gate circuit, the FET must have a low gate turn-on threshold. If it is desired to use a more

standard device, such as the 2N7002, as the reference schematic, the gate should be biased up to 3.3 V with a

high-value resistor. The BQ40Z80 device has the capability to provide a current-limited charging path typically

used for low battery voltage or low temperature charging. The BQ40Z80 device uses an external P-CH,

precharge FET controlled by PCHG.

9.2.2.4.4 Pre-Discharge Control

Some applications have a large capacitive load that requires a pre-discharge feature that can slowly charge the

cap and avoid a large current that may trip the OC protection. The BQ40Z80 device can be configured to use the

PDSG output of Pins 16, 17, or 20 to drive the N-CH FET Q7 to turn on the pre-discharge P-CH FET Q5. The

precharge rate can be set by adjusting the resistor R9.

9.2.2.4.5 Temperature Output

For the BQ40Z80 device, up to four thermistor inputs can be configured. TS1, TS2, TS3, and TS4 provide

thermistor drive-under program control. Each pin can be enabled with an integrated 18-kΩ (typical) linearization

pullup resistor to support the use of a 10-kΩ at 25°C (103) NTC external thermistor, such as a Mitsubishi

BN35-3H103. The reference design includes four 10-kΩ thermistors: RT1, RT2, RT3, and RT4.

9.2.2.4.6 LEDs

Multifunction Pins 20, 21, and 22 can be configured as three LED control outputs that provide constant current

sinks for driving external LEDs. These outputs are configured to provide voltage and control for up to six LEDs.

No external bias voltage is required. Unused LEDCNTL pins can remain open or they can be connected to V_SS

The DISP pin should be connected to V_SSif the LED feature is not used.

.

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9.2.3 Application Curve

452

450

448

446

444

442

440

438

436

434

432

0

20

40

60

80

100

120

œ40

œ20

Temperature (°C)

C014

图9-2. Short Circuit Charge Current Delay Time vs. Temperature

10 Power Supply Recommendations

The device manages its supply voltage dynamically according to the operation conditions. Normally, the BAT

input is the primary power source to the device. The BAT pin should be connected to the positive termination of

the battery stack. The input voltage for the BAT pin ranges from 2.2 V to 32 V.

The VCC pin is the secondary power input, which activates when the BAT voltage falls below minimum V_CC. This

enables the device to source power from a charger (if present) connected to the PACK pin. The VCC pin should

be connected to the common drain of the CHG and DSG FETs. The charger input should be connected to the

PACK pin.

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11 Layout

11.1 Layout Guidelines

A battery fuel gauge circuit board is a challenging environment due to the fundamental incompatibility of high-

current traces and ultra-low current semiconductor devices. The best way to protect against unwanted trace-to-

trace coupling is with a component placement, such as that shown in 图 11-1, where the high-current section is

on the opposite side of the board from the electronic devices. This may not possible in many situations due to

mechanical constraints. Still, every attempt should be made to route high-current traces away from signal traces,

which enter the BQ40Z80 directly. IC references and registers can be disturbed and in rare cases damaged due

to magnetic and capacitive coupling from the high-current path.

Note

During surge current and ESD events, the high-current traces appear inductive and can couple

unwanted noise into sensitive nodes of the gas gauge electronics, as illustrated in 图11-2.

BAT +

C2

C3

Q1

Q2

Low Level Circuits

F1

C1

BAT –

J1

R1

图11-1. Separating High- and Low-Current Sections Provides an Advantage in Noise Immunity

PACK+

COMM

BMU

PACK–

图11-2. Avoid Close Spacing Between High-Current and Low-Level Signal Lines

Kelvin voltage sensing is extremely important in order to accurately measure current and top and bottom cell

voltages. Place all filter components as close as possible to the device. Route the traces from the sense resistor

in parallel to the filter circuit. Adding a ground plane around the filter network can add additional noise immunity.

图11-3 and 图11-4 demonstrate correct kelvin current sensing.

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Current Direction

R

SNS

Current Sensing Direction

To SRP – SRN pin or HSRP – HSRN pin

图11-3. Sensing Resistor PCB Layout

Sense Resistor

Ground Shield

Filter Circuit

图11-4. Sense Resistor, Ground Shield, and Filter Circuit Layout

11.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors

Use wide copper traces to lower the inductance of the bypass capacitor circuit. In 图 11-5, an example layout

demonstrates this technique. Note that in the BQ40Z80EVM-Rev A Schematic, these capacitors are C1, C2, C3,

and C4.

BAT+

C2

C3

C2

C3

Q1

Q2

Pack+

F1

Low Level Circuits

F1

BATœ

C1

Packœ

C1

J1

R1

图11-5. Wide Copper Traces Lower the Inductance of Bypass Capacitors C1, C2, and C3

11.1.2 ESD Spark Gap

Protect the SMBus clock, data, and other communication lines from ESD with a spark gap at the connector. The

pattern in 图11-6 is recommended, with 0.2-mm spacing between the points.

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图11-6. Recommended Spark-Gap Pattern Helps Protect Communication Lines from ESD

11.2 Layout Examples

图11-7. BQ40Z80EVM Top Composite

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图11-8. BQ40Z80EVM Top Layer

图11-9. BQ40Z80EVM GND Layer

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图11-10. BQ40Z80EVM Signal Layer

图11-11. BQ40Z80EVM Bottom Layer

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图11-12. BQ40Z80EVM Bottom Layer Composite

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

• BQ40Z80 Technical Reference Manual (SLUUBT5)

• BQ40Z80 Manufacture, Production, and Calibration Application Note (SLUA868)

• BQ40Z80EVM Li-Ion Battery Pack Manager Evaluation Module User's Guide (SLUUBZ5)

• How to Complete a Successful Learning Cycle for the BQ40Z80 Application Note (SLUA848)

• TI Fuel Gauge Authentication Key Packager and Programmer Tools User's Guide (SLUUBU3)

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

Impedance Track^™and TI E2E^™are trademarks of Texas Instruments.

Impedance Track^®is a registered trademark of Texas Instruments.

Intel^®is a registered trademark of Intel.

所有商标均为其各自所有者的财产。

12.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, package, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

38

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PACKAGE MATERIALS INFORMATION

www.ti.com

17-Aug-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ40Z80RSMR

BQ40Z80RSMT

VQFN

RSM

32

3000

250

330.0

180.0

12.4

4.25

1.15

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Aug-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ40Z80RSMR

BQ40Z80RSMT

VQFN

RSM

32

3000

250

367.0

210.0

367.0

185.0

35.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RSM 32

4 x 4, 0.4 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224982/A

www.ti.com

PACKAGE OUTLINE

RSM0032A

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

B

4.1

3.9

A

0.5

0.3

PIN 1 INDEX AREA

4.1

3.9

0.25

0.15

DETAIL

OPTIONAL TERMINAL

TYPICAL

1 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

2X 2.8

1.4 0.05

(0.2) TYP

4X (0.45)

28X 0.4

9

16

8

17

EXPOSED

THERMAL PAD

2X

SYMM

33

2.8

24

0.25

32X

1

SEE TERMINAL

DETAIL

0.15

0.1

C A B

25

32

PIN 1 ID

(OPTIONAL)

0.05

SYMM

0.5

0.3

32X

4219107/A 11/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RSM0032A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.4)

SYMM

32

25

32X (0.6)

1

32X (0.2)

24

SYMM

33

(3.8)

28X (0.4)

(

0.2) VIA

17

8

(R0.05)

TYP

9

16

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219107/A 11/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RSM0032A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.3)

(R0.05) TYP

25

32

32X (0.6)

32X (0.2)

1

24

SYMM

33

(3.8)

28X (0.4)

METAL

TYP

17

8

16

9

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 33:

86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219107/A 11/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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型号：	BQ40Z80RSMR
厂家：	TEXAS INSTRUMENTS
描述：	采用 Impedance Track™ 电量监测技术的 2 节至 7 节电池组管理器 \| RSM \| 32 \| -40 to 85 电池
文件：	总47页 (文件大小：3453K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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