BQ2202SN-NTR [TI]
暂无描述;
| 型号： | BQ2202SN-NTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 暂无描述 静态存储器 控制器 |
| 文件： | 总10页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq2202
SRAM NV Controller With Reset
Power for the external SRAMs is
Features
General Description
switched from the V
supply to the
CC
battery-backup supply as V
de-
The CMOS bq2202 SRAM Nonvolatile
Controller With Reset provides all the
necessary functions for converting one
or t wo ba n ks of st a n da r d CMOS
SRAM into nonvolatile read/write
memory.
CC
Power monitoring and switching
for nonvolatile control of SRAMs
cays. On a subsequent power--up, the
s u p p ly is a u t om a t ica lly
V
OU T
switched from the backup supply to
the V supply. The external SRAMs
Write-protect control
CC
Input decoder allows control of
up to 2 banks of SRAM
are write-protected until a power-
valid condition exists. The reset out-
put provides power-fail and power-on
resets for the system.
A precision comparator monitors the
3-volt primary cell input
5V V
input for an out-of-tolerance
CC
condition. When out-of-tolerance is
d e t e ct e d , t h e t w o con d it ion e d
chip-enable outputs are forced inac-
tive to write-protect both banks of
SRAM.
3-volt rechargeable battery in-
put/output
During power-valid operation, the
in pu t decoder select s on e of t wo
banks of SRAM.
Reset output for system power-on
reset
L e s s t h a n 1 0 n s ch ip e n a b le
propagation delay
5% or 10% supply operation
Pin Connections
Pin Names
VOUT
Supply output
RST
Reset output
THS
Threshold select input
V
1
2
3
4
5
6
16
15
14
13
12
11
V
CC
OUT
BC
P
BC
CE
CE
CE
NC
CE
Chip enable active low input
Conditioned chip enable outputs
S
NC
A
CECON1
,
CON2
CE
CON1
CON2
A
Bank select input
NC
NC
THS
BCP
BCS
NC
VCC
VSS
3V backup supply input
3V rechargeable backup supply input/output
No connect
7
8
10
9
RST
NC
V
SS
+5 volt supply input
Ground
16-Pin Narrow DIP or SOIC
PN220201.eps
Functional Description
If THS is tied to V , power-fail detection occurs at
CC
Two banks of CMOS static RAM can be battery-backed
4.37V typical for 10% supply operation. The THS pin
must be tied to V or V for proper operation.
using the V
from the bq2202. As the voltage input V
and conditioned chip-enable output pins
OUT
slews down
SS
CC
CC
during a power failure, the two conditioned chip enable
ou t pu t s, CE a n d CE , a r e for ced in a ct ive
independent of the chip enable input CE.
If a memory access is in process to any of the two exter-
nal banks of SRAM during power-fail detection, that
memory cycle continues to completion before the memory
is write-protected. If the memory cycle is not terminated
CON1
CON2
This activity unconditionally write-protects external
within time t
(150µsec maximum), the two chip en-
SRAM as V
falls to an out-of-tolerance threshold
WPT
CC
able outputs are unconditionally driven high, write-
protecting the controlled SRAMs.
V
. V
is selected by the threshold select input pin,
PFD PFD
THS. If THS is tied to V , the power-fail detection oc-
SS
curs at 4.62V typical for 5% supply operation.
Sept. 1997 D
1
bq2202
As the supply continues to fall past V
, an internal
The reset output (RST) goes active within t
(150µsec
PFD
PFD
switching device forces V
to the internal backup en-
maximum) after V
and remains active for a minimum
OUT
PFD,
ergy source. CE
and CE
are held high by the
of 40ms (120ms maximum) after power returns valid. The
RST output can be used as the power-on reset for a micro-
processor. Access to the external RAM may begin when
RST returns inactive.
CON1
CON2
V
energy source.
OUT
During power-up, V
is switched back to the 5V sup-
OUT
ply as V
rises above the backup cell input voltage
CC
sourcing V
inactive for time t
. Outputs CE
and CE
are held
OUT
CON1
CON2
Energy Cell Inputs—BC , BC
P
S
(120ms maximum) after the
CE R
power supply has reached V
input, to allow for processor stabilization.
, independent of the CE
PFD
Two backup energy source inputs are provided on the
bq2202—a primary cell BC and a secondary cell BC .
P
S
The primary cell input is designed to accept any 3V pri-
mary battery (non-rechargeable), typically some type of
lithium chemistry. If a primary cell is not to be used, the
During power-valid operation, the CE input is passed
through to one of the two CE
outputs with a propa-
CON
gation delay of less than 10ns. The CE input is output on
one of the two CE output pins; depending on the
BC pin should be grounded. The secondary cell input
P
CON
BC is designed to accept constant-voltage current-
S
level of bank select input A, as shown in the Truth Ta-
ble.
limited rechargeable cells.
During normal 5V power valid operation, 3.3V is output
Bank select input A is usually tied to a high-order ad-
dress pin so that a large nonvolatile memory can be de-
signed using lower-density memory devices. Nonvolatility
and decoding are achieved by hardware hookup as shown
in Figure 1.
on the BC pin and is current-limited internally.
S
5V
V
OUT
V
CC
V
CC
V
CC
CMOS
SRAM
CMOS
SRAM
bq2202
A
CE
CE
CON1
From Address
Decoder
CE
CE
CE
CON2
BC
BC
S
P
THS
To Microprocessor
RST
V
SS
FG220201.eps
Figure 1. Hardware Hookup (5% Supply Operation)
Sept. 1997 D
2
bq2202
If a secondary cell is not to be used, the BC pin must be
S
tied directly to V . If both inputs are used, during
SS
power failure the V
and CE
outputs are forced
OUT
CON
high by the secondary cell so long as it is greater than
2.5V. Only the secondary cell is loaded by the data reten-
V
PFD
tion current of the SRAM until the voltage at the BC
pin falls below 2.5V. When and if the voltage at BC
S
S
falls below 2.5V, an internal isolation switch automati-
cally transfers the load from the secondary cell to the
primary cell.
V
CC
V
SO
To prevent battery drain when there is no valid data to
retain, V
, CE
OUT
, and CE
are internally iso-
CON1
CON2
lated from BC and BC by either:
P
S
0.5 V
CC
CE
■
■
Initial connection of a battery to BCP or BCS or
Presentation of an isolation signal on CE.
700ns
TD220201.eps
A valid isolation signal requires CE low as V
crosses
CC
both V
and V
during a power-down. See Figure
PFD
SO
2. Bet ween t h ese two points in time, CE must be
brought to V (0.48 to 0.52) and held for at least
700ns. The isolation signal is invalid if CE exceeds V
CC
Figure 2. Battery Isolation Signal
CC
*
0.54 at any point between V crossing V
and V
, a n d
CON 1
.
CC
PFD
SO
Th e ba t t er y is con n ect ed t o V
, CE
OU T
CE
immediately on subsequent application and
CON2
removal of V
.
CC
Truth Table
Input
Output
CE
H
A
X
L
CE
CE
CON2
CON1
H
L
H
H
L
L
L
H
H
Sept. 1997 D
3
bq2202
Absolute Maximum Ratings
Symbol
Parameter
DC voltage applied on V relative to V
SS
Value
Unit
Conditions
V
V
-0.3 to +7.0
V
CC
CC
DC voltage applied on any pin excluding V
CC
-0.3 to +7.0
V
V
≤ V + 0.3
T CC
T
relative to V
SS
0 to +70
-40 to +85
-55 to +125
-40 to +85
260
°C
°C
Commercial
T
Operating temperature
OPR
Industrial “N”
T
T
T
Storage temperature
Temperature under bias
Soldering temperature
°C
STG
°C
BIAS
°C
For 10 seconds
SOLDER
OUT
I
V
OUT
current
200
mA
Note:
Permanent device damage may occur if Absolu te Ma xim u m Ra tin gs are exceeded. Functional opera-
tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-
sure to conditions beyond the operational limits for extended periods of time may affect device reliability.
Recommended DC Operating Conditions (T = T
)
OPR
A
Symbol
Parameter
Supply voltage
Minimum Typical Maximum
Unit
V
Notes
4.75
4.50
2.0
2.5
0
5.0
5.5
THS = V
THS = V
SS
V
CC
5.0
5.5
4.0
4.0
0
V
CC
V
V
V
V
V
-
-
BCP
BCS
SS
Backup cell input voltage
V
V < V
CC BC
Supply voltage
0
-
V
V
V
V
Input low voltage
Input high voltage
Threshold select
-0.3
2.2
-0.3
0.8
IL
-
V
CC
V
CC
+ 0.3
IH
THS
-
+ 0.3
Note:
Typical values indicate operation at T = 25°C, V
A
= 5V or V
.
CC
BC
Sept. 1997 D
4
bq2202
DC Electrical Characteristics (T = T
, V
OPR CC
= 5V ± 10%)
A
Symbol
Parameter
Input leakage current
Output high voltage
Minimum
Typical
Maximum
Unit
µA
V
Conditions/Notes
I
-
-
-
-
-
± 1
-
V
= V to V
SS CC
LI
IN
V
V
V
2.4
I
= -2.0mA
OH
OH
V
OH
, backup supply
V
BC
- 0.3
-
V
V
BC
> V , I
= -10µA
OHB
OL
CC OH
Output low voltage
-
0.4
V
I
= 4.0mA
OL
No load on V
, CE
OUT
,
CON1
I
Operating supply current
-
3
6
mA
CC
and CE
CON2
4.55
4.30
-
4.62
4.37
4.75
4.50
-
V
V
V
THS = V
SS
V
V
Power-fail detect voltage
Supply switch-over voltage
PFD
THS = V
CC
V
BC
SO
Data-retention mode
current
No load on V
, CE
OUT
,
CON1
I
-
-
100
nA
CCDR
and CE
CON2
V
CC
V
CC
V
BC
- 0.2
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
V
V
> V , I
BC OUT
= 100mA
= 160mA
= 100µA
CC
V
V
V
V
voltage
voltage
OUT1
OUT
- 0.3
- 0.2
> V , I
BC OUT
CC
< V , I
OUT2
OUT
CC
BC OUT
-
V
V
> 2.5V
BCS
BCP
BCS
BCS
V
Active backup cell voltage
BC
-
< 2.5V
BC charge output internal
S
resistance
R
V
500
3.0
1000
3.3
1750
3.6
Ω
V
≥ 3.0V
BCSO
BCS
V
CC
> V
, RST inactive,
PFD
BC charge output voltage
V
BCSO
S
full charge or no load
I
I
V
V
current
current
-
-
-
160
-
mA
V
≥ V
≥ V
- 0.3V
- 0.2V
OUT1
OUT2
OUT
OUT
OUT
CC
BC
100
µA
V
OUT
Note:
Typical values indicate operation at T = 25°C, V
= 5V or V
.
A
CC
BC
Capacitance (T = 25°C, F = 1MHz, V
= 5.0V)
CC
A
Symbol
IN
Parameter
Input capacitance
Output capacitance
Minimum
Typical
Maximum
Unit
Conditions
C
C
-
-
-
-
8
pF
pF
Input voltage = 0V
Output voltage = 0V
10
OUT
Note:
This parameter is sampled and not 100% tested.
Sept. 1997 D
5
bq2202
AC Test Conditions
Parameter
Test Conditions
0V to 3.0V
Input pulse levels
Input rise and fall times
5ns
Input and output timing reference levels
1.5V (unless otherwise specified)
5V
960
CE
CON
510
100pF
FG220102.eps
Figure 3. Output Load
Power-Fail Control (T = T
)
OPR
A
Symbol
Parameter
Min.
300
10
0
Typ. Max. Unit
Conditions
t
V
V
V
slew 4.75 to 4.25V
-
-
-
-
µs
µs
µs
ns
PF
CC
CC
t
t
t
slew 4.25 V to V
SO
FS
slew 4.25 to 4.75V
-
-
PU
CED
CC
Chip-enable propagation delay
-
7
10
Time during which SRAM is write-
t
Chip-enable recovery time
t
-
t
ms protected after V
power-up
passes V
on
CER
RR
RR
CC
PFD
Time, after V
RST is cleared
becomes valid, before
CC
t
t
VPFD to RST inactive
Input A set up to CE
40
0
80
-
120
-
ms
ns
RR
AS
Delay after V
before SRAM is write-protected
slews down past V
CC
PFD
t
t
Write-protect time
t
-
t
µs
µs
WPT
R
R
R
Delay after V slews down past V
before RST is active
CC
PFD
V
PFD
to RST active
40
100
150
Note:
Typical values indicate operation at T = 25°C, V
= 5V.
CC
A
Sept. 1997 D
6
bq2202
Power-Down Timing
t
PF
4.75
V
PFD
t
FS
4.25
V
CC
V
SO
CE
t
WPT
V
OHB
CE
CON
t
R
RST
TD220202.eps
Power-Up Timing
t
PU
4.75
V
PFD
V
CC
4.25
SO
V
t
CER
CE
t
t
CED
CED
V
OHB
CE
CON
t
RR
RST
TD220203.eps
Address-Decode Timing
A
t
AS
CE
t
t
CED
CED
CE
CE
CON1
CON2
TD220204.eps
Sept. 1997 D
7
bq2202
16-Pin SOIC Narrow
16-Pin SOIC Narrow (SN)
Dimension
Minimum
0.060
0.004
0.013
0.007
0.385
0.150
0.045
0.225
0.015
Maximum
0.070
0.010
0.020
0.010
0.400
0.160
0.055
0.245
0.035
A
A1
B
D
B
e
C
D
E
E
e
H
L
H
All dimensions are in inches.
A
C
A1
.004
L
16-Pin DIP Narrow
16-Pin DIP Narrow (PN)
Dimension
Minimum
0.160
0.015
0.015
0.055
0.008
0.740
0.300
0.230
0.300
0.090
0.115
0.020
Maximum
0.180
0.040
0.022
0.065
0.013
0.770
0.325
0.280
0.370
0.110
0.150
0.040
A
A1
B
B1
C
D
E
E1
e
G
L
S
All dimensions are in inches.
Sept. 1997 D
8
bq2202
Data Sheet Revision History
Change No.
Page No.
Description
Deleted last sentence
Nature of Change
Clarification
1
2
Was: 3.15 min, 3.3 typ, 3.45 max
Is: 3.0 min, 3.3 typ, 3.6 max
1
2
3
5
5
V
—BC charge output voltage
BCSO S
Changed maximum charge output internal resis-
tance (R
Was: 1500Ω
Is: 1750Ω
)
BCS
Was: THS tied to V
OUT
CC
1, 4, 5
10% supply operation
Is: THS tied to V
Note:
Change 1 = Dec. 1992 B changes from Sept. 1991 A.
Change 2 = Nov. 1994 C changes from Dec. 1992 B.
Change 3 = Sept. 1997 D changes from Nov. 1994 C.
Ordering Information
bq2202
Tem p er a tu r e Ra n ge:
blank = Commercial (0 to +70°C)
N = Industrial (-40 to +85°C)
Pa ck a ge Op tion :
PN = 16-pin narrow plastic DIP
SN = 16-pin narrow SOIC
Device:
bq2202 SRAM Nonvolatile Controller With Reset
Sept. 1997 D
9
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明