BQ2203A [TI]
NV Controller With Battery Monitor; NV控制器，电池监视器
| 型号： | BQ2203A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | NV Controller With Battery Monitor |
| 文件： | 总12页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq2203A
NV Controller With Battery Monitor
Power for the external SRAMs is
Features
General Description
switched from the V
supply to the
CC
battery-backup supply as V
de-
The CMOS bq2203A SRAM Nonvolatile
Controller With Battery Monitor pro-
vides all the necessary functions for con-
verting one or two banks of standard
CMOS SRAM in t o n on vola t ile
read/write memory. The bq2203A is
compatible with the Personal Computer
Memory Card International Association
(P CMCIA) r ecom m en da t ion s for
battery-backed static RAM memory
cards.
CC
Power monitoring and switching
for nonvolatile control of SRAMs
cays. On a subsequent power-up, the
s u p p ly is a u t om a t ica lly
V
OU T
switched from the backup supply to
the V supply. The external SRAMs
Write-protect control
CC
Battery-low and battery-fail indi-
cators
are write-protected until a power-
valid condition exists. The reset out-
put provides power-fail and power-on
resets for the system. The battery
monitor indicates battery-low and
battery-fail conditions.
Reset output for system power-on
reset
Input decoder for control of up to
2 banks of SRAM
During power-valid operation, the
in pu t decoder select s on e of t wo
banks of SRAM.
A precision comparator monitors the 5V
V
CC
input for an out-of-tolerance condi-
3-volt primary cell input
tion. When out of tolerance is detected,
the two conditioned chip-enable outputs
are forced inactive to write-protect
banks of SRAM.
3-volt rechargeable battery in-
put/output
Pin Connections
Pin Names
VOUT
RST
THS
CE
CECON1
CECON2
Supply output
Reset output
Threshold select input
chip-enable active low input
Conditioned chip-enable outputs
V
1
2
3
4
5
6
16
15
14
13
12
11
V
CC
OUT
BC
P
BC
CE
CE
CE
S
,
NC
A
A
Bank select input
CON1
CON2
BCF
BCL
BCP
BCS
NC
Battery fail push-pull output
Battery low push-pull output
3V backup supply input
3V rechargeable backup supply input/output
No connect
BCF
NC
BCL
THS
7
8
10
9
RST
NC
V
SS
VCC
VSS
5-volt supply input
Ground
16-Pin Narrow DIP or SOIC
PN220301.eps
Functional Description
Two banks of CMOS static RAM can be battery-backed us-
If THS is tied to V , power-fail detection occurs at
CC
4.37V typical for 10% supply operation. The THS pin
must be tied to V or V for proper operation.
ing the V
and the conditioned chip-enable output pins
OUT
from the bq2203A. As the voltage input V
slews down
SS
CC
CC
during a power failure, the two conditioned chip-enable
ou t pu t s, CE a n d CE , a r e for ced in a ct ive
independent of the chip-enable input CE.
If a memory access is in process to any of the two exter-
nal banks of SRAM during power-fail detection, that
memory cycle continues to completion before the memory
is write-protected. If the memory cycle is not terminated
CON1
CON2
This activity unconditionally write-protects external SRAM
as V
falls to an out-of-tolerance threshold V . V
PFD PFD
is
within time t
(150µs maximum), the two chip-enable
CC
WPT
selected by the threshold select input pin, THS. If THS is
outputs are unconditionally driven high, write-protecting
the controlled SRAMs.
tied to V , the power-fail detection occurs at 4.62V typical
SS
for 5% supply operation.
Nov. 1994 B
1
bq2203A
As the supply continues to fall past V
, an internal
The reset output (RST) goes active within t
(150µs
PFD
PFD
switching device forces V
to the external backup en-
maximum) after V
and remains active for a mini-
OUT
PFD,
ergy source. CE
and CE
are held high by the
mum of 40ms (120ms maximum) after power returns
valid. The RST output can be used as the power-on re-
set for a microprocessor. Access to the external RAM
may begin when RST returns inactive.
CON1
CON2
V
energy source.
OUT
During power-up, V
is switched back to the 5V sup-
OUT
ply as V
rises above the backup cell input voltage
CC
sourcing V
inactive for time t
. Outputs CE
and CE
are held
OUT
CON1
CON2
Energy Cell Inputs—BC , BC
P
S
(120ms maximum) after the
CE R
power supply has reached V
input, to allow for processor stabilization.
, independent of the CE
Two backup energy source inputs are provided on the
bq2203A—a primary cell BC and a secondary cell BC .
PFD
P
S
The primary cell input is designed to accept any 3V pri-
mary battery (non-rechargeable), typically some type of
lithium chemistry. If a primary cell is not to be used, the
During power-valid operation, the CE input is passed
through to one of the two CE
outputs with a propaga-
CON
tion delay of less than 10ns. The CE input is output on
one of the two CE output pins depending on the level
BC pin should be tied to V . The secondary cell input
P
SS
CON
BC is designed to accept constant-voltage current-
S
of bank select input A, as shown in the Truth Table.
limited rechargeable cells.
Bank select input A is usually tied to a high-order ad-
dress pin so that a large nonvolatile memory can be de-
signed using lower-density memory devices. Nonvolatil-
ity and decoding are achieved by hardware hookup as
shown in Figure 1.
During normal 5V power valid operation, 3.3V typical is out-
put on the BC pin and is current-limited internally. Al-
S
though this charging method can be used with various 3V
secondary cells, it is specifically designed for a Panasonic VL
(vanadium-lithium) series of rechargeable cells.
5V
bq2203A
V
V
OUT
CC
V
CC
V
CC
CMOS
SRAM
CMOS
SRAM
BCF
BCL
A
CE
CE
From Address
Decoder
CON1
CE
CE
CE
CON2
To Microprocessor
BC
RST
P
THS
BC
S
3V Primary
Cell
3V Secondary
Cell
V
SS
FG220301.eps
Figure 1. Hardware Hookup (5% Supply Operation)
Nov. 1994 B
2
bq2203A
If a secondary cell is not to be used, the BC pin must be
S
tied directly to V
.
SS
V
falling below V
starts the comparison of BC
CC
PFD
S
and BC . The BC input comparison continues until V
P
CC
V
PFD
rises above V
.
Power to V begins with BC and
OUT S
SO
switches to BC only when BC is less than BC minus
P
S
P
V
. The controller alternates to the higher BC voltage
BSO
V
CC
when the difference between the BC input voltages is
greater than V . Alternating the backup batteries al-
BSO
V
SO
lows one-at-a-time battery replacement and efficient use
of both backup batteries.
To prevent battery drain when there is no valid data to
retain, V
, CE
P
, and CE
S
are internally iso-
OUT
CON1
CON2
0.5 V
CC
CE
lated from BC and BC by either of two methods:
700ns
■
Initial connection of a battery to BCP or BCS (VCC
grounded) or
TD220101.eps
■
Presentation of an isolation signal on CE.
A valid isolation signal requires CE low as V
crosses
CC
both V
and V
during a power-down. See Figure
PFD
SO
2. Bet ween t h ese two points in time, CE must be
brought to V (0.48 to 0.52) and held for at least 700ns.
CC
*
Figure 2. Battery Isolation Signal
The isolation signal is invalid if CE exceeds V
0.54 at
CC
*
any point between V crossing V
and V
.
CC
PFD
SO
The isolation function is terminated and the appropriate
battery is connected to V , CE , and CE by
OUT
CON1
CON2
powering V up through V
.
CC
PFD
Battery Monitor—BCL, BCF
As V
rises past V , the battery voltage on BC is
PFD P
CC
compared with a dual-voltage reference. The result of
this comparison is latched internally, and output after
t
when V
rises past V
. If the battery voltage on
BC
CC
PFD
BC is below V , then BCL is asserted low. If the bat-
P
BL
tery is below V , then BCL and BCF are asserted low.
BF
The results of this comparison remain latched until V
CC
falls below V
.
PFD
Truth Table
Input
Output
CE
A
X
L
CE
CE
CON2
CON1
H
L
L
H
L
H
H
L
H
H
Nov. 1994 B
3
bq2203A
Absolute Maximum Ratings
Symbol
Parameter
DC voltage applied on V relative to V
SS
Value
Unit
Conditions
V
V
-0.3 to +7.0
V
CC
CC
DC voltage applied on any pin excluding V
CC
-0.3 to +7.0
V
V
≤ V + 0.3
T CC
T
relative to V
SS
0 to 70
-40 to +85
-55 to +125
-40 to +85
260
°C
°C
Commercial
T
Operating temperature
OPR
“N” Industrial
T
T
T
Storage temperature
Temperature under bias
Soldering temperature
°C
STG
°C
BIAS
°C
For 10 seconds
SOLDER
OUT
I
V
OUT
current
200
mA
Note:
Permanent device damage may occur if Absolu te Ma xim u m Ra tin gs are exceeded. Functional opera-
tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-
sure to conditions beyond the operational limits for extended periods of time may affect device reliability.
Recommended DC Operating Conditions (T = T
)
OPR
A
Symbol
Parameter
Supply voltage
Minimum Typical Maximum
Unit
V
Notes
4.75
4.50
2.0
2.0
0
5.0
5.5
THS = V
THS = V
SS
CC
BC
BC
V
CC
5.0
5.5
4.0
4.0
0
V
V
V
V
V
V
-
-
V
V
CC
V
CC
< V
< V
BCP
BCS
SS
Backup cell input voltage
V
Supply voltage
0
-
V
Input low voltage
Input high voltage
Threshold select
-0.3
2.2
-0.3
0.8
V
IL
-
V
CC
V
CC
+ 0.3
V
IH
THS
-
+ 0.3
V
Note:
Typical values indicate operation at T = 25°C, V
= 5V.
CC
A
Nov. 1994 B
4
bq2203A
bq2203A
DC Electrical Characteristics (T = T
, V
OPR CC
= 5V ± 10%)
A
Symbol
Parameter
Input leakage current
Output high voltage
Minimum
Typical
Maximum
Unit
µA
V
Conditions/Notes
I
-
-
± 1
V
= V to V
SS CC
LI
IN
V
V
V
2.4
-
-
-
I
= -2.0mA
> V , I
OH
OH
V
OH
, backup supply
V - 0.3
BC
-
-
V
V
BC
= -10µA
CC OH
OHB
OL
Output low voltage
-
0.4
6
V
I
= 4.0mA
OL
I
Operating supply current
-
3
mA
V
No load on outputs
CC
4.55
4.30
-
4.62
4.37
4.75
4.50
-
THS = V
SS
V
V
Power-fail detect voltage
PFD
V
THS = V
CC
Supply switch-over voltage
V
BC
V
SO
Data-retention mode
current
-
-
100
nA
No load on outputs
I
CCDR
-
-
V
V
-
-
V
V
V
V
V
> V
> V
+ V
+ V
BCS
BCS
BCP
BSO
Active backup cell voltage
Battery switch-over voltage
V
BC
BCP
BCP
BCS
BSO
V
R
0.25
0.4
0.6
BSO
BC charge output internal
S
resistance
500
1000
1750
3.5
Ω
V
≥ 3.0V
BCSO
BCS
V
> V
, RST inactive,
CC
PFD
V
BCSO
BC charge output voltage
3.15
3.3
V
S
full charge or no load
I
I
V
V
current
current
-
-
100
-
160
-
mA
µA
V
V
V
≥ V
≥ V
- 0.3V
- 0.2V
OUT1
OUT2
OUT
OUT
OUT
CC
BC
-
OUT
V
V
Voltage battery low
Voltage battery fail
2.3
2.0
2.5
2.2
BC input only
P
BL
BF
-
V
BC input only
P
Note:
Typical values indicate operation at T = 25°C, V
= 5V or V
.
A
CC
BC
Capacitance (T = 25°C, F = 1MHz, V
= 5.0V)
CC
A
Symbol
IN
Parameter
Input capacitance
Output capacitance
Minimum
Typical
Maximum
Unit
Conditions
C
C
-
-
-
-
8
pF
pF
Input voltage = 0V
Output voltage = 0V
10
OUT
Note:
This parameter is sampled and not 100% tested.
Nov. 1994 B
5
bq2203A
AC Test Conditions
Parameter
Test Conditions
0V to 3.0V
Input pulse levels
Input rise and fall times
5ns
Input and output timing reference levels
Output load (including scope and jig)
1.5V (unless otherwise specified)
See Figure 3
5V
960
CE
CON
510
100pF
FG220102.eps
Figure 3. Output Load
Power-Fail Control (T = T
)
A
OPR
Parameter
slew 4.75 to 4.25 V
Symbol
Min.
300
10
Typ. Max. Unit
Conditions
t
t
t
t
V
V
V
-
-
-
-
µs
µs
µs
ns
PF
CC
CC
slew 4.25 V to V
FS
SO
slew 4.25 to 4.75 V
0
-
-
PU
CC
Chip-enable propagation delay
7
10
CED
Time during which SRAM is write-
t
Chip-enable recovery time
40
80
120
ms protected after V
passes V
on
CER
CC
PFD
power-up
Time, after V
RST is cleared
becomes valid, before
CC
t
t
V
to RST inactive
tCER
0
-
-
tCER
-
ms
ns
RR
AS
PFD
Input A set up to CE
Write-protect time
Delay after V
slews down past
CC
t
t
t
40
100
150
µs
µs
ms
WPT
R
V
PFD
before SRAM is write-protected
Delay after V
slews down past
CC
V
V
to RST active
tWPT
tCER
-
-
tWPT
PFD
V
PFD
before RST is active
Delay after V
before BCL or BCF is active
slews up past V
PFD
CC
to BCL/BCF active
tCER
BC
PFD
Note:
Typical values indicate operation at T = 25°C, V
= 5V.
A
CC
Ca u tion : Nega tive u n d er sh oots below th e a bsolu te m a xim u m r a tin g of -0.3V in ba tter y-ba ck u p m od e
m a y a ffect d a ta in tegr ity.
Nov. 1994 B
6
bq2203A
Power-Down Timing
t
PF
4.75
V
PFD
t
FS
4.25
V
CC
V
SO
CE
t
WPT
V
OHB
CE
CON
t
R
RST
TD220202.eps
Power-Up Timing
t
PU
4.75
V
PFD
V
CC
4.25
V
SO
t
CER
CE
t
t
CED
CED
V
OHB
CE
CON
t
RR
RST
t
BC
BCL
BCF
TD220302.eps
Address-Decode Timing
A
t
AS
CE
t
t
CED
CED
CE
CE
CON1
CON2
TD220204.eps
Nov. 1994 B
7
bq2203A
16-Pin SOIC Narrow
(
)
16-Pin SN SOIC Narrow
Dimension
Minimum
0.060
0.004
0.013
0.007
0.385
0.150
0.045
0.225
0.015
Maximum
0.070
0.010
0.020
0.010
0.400
0.160
0.055
0.245
0.035
A
A1
B
D
B
e
C
D
E
E
e
H
L
H
All dimensions are in inches.
A
C
A1
.004
L
Nov. 1994 B
8
bq2203A
16-Pin DIPNarrow
(
)
16-Pin PN DIP Narrow
Dimension
Minimum
0.160
0.015
0.015
0.055
0.008
0.740
0.300
0.230
0.300
0.090
0.115
0.020
Maximum
0.180
0.040
0.022
0.065
0.013
0.770
0.325
0.280
0.370
0.110
0.150
0.040
A
A1
B
B1
C
D
E
E1
e
G
L
S
All dimensions are in inches.
Nov. 1994 B
9
bq2203A
Data Sheet Revision History
Change No.
Page No.
Description
Nature of Change
1
-
Changed data sheet from “Preliminary” to “Final”
Changed maximum charge output internal resis-
Was: 1500Ω
Is: 1750Ω
1
5
tance (R
)
BCS
Note:
Change 1 = Nov. 1994 B changes from Dec. 1992 A.
Nov. 1994 B
10
bq2203A
Ordering Information
bq2203A
Tem p er a tu r e Ra n ge:
blank = Commercial (0 to +70°C)
N = Industrial (-40 to +85°C)*
Pa ck a ge Op tion :
PN = 16-pin plastic DIP Narrow
SN = 16-pin SOIC Narrow
Device:
bq2203A SRAM Nonvolatile Controller
With Battery Monitor and Reset
*Contact factory for availability.
Nov. 1994 B
11
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