BQ2057TSTRG4_技术文档

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ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢉ

SLUS025F − MAY 2001 − REVISED JULY 2002

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ꢑꢓ ꢎ ꢔ ꢊꢍꢊꢓ ꢎꢔ ꢎꢍꢈ ꢐꢇ

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FEATURES

DESCRIPTION

D

Ideal for Single (4.1 V or 4.2 V) and Dual-Cell

(8.2 V or 8.4 V) Li-Ion or Li-Pol Packs

The BENCHMARQ bq2057 series advanced

Lithium-Ion (Li-Ion) and Lithium-Polymer (Li-Pol) linear

charge-management ICs are designed for cost-

sensitive and compact portable electronics. They

combine high-accuracy current and voltage regulation,

battery conditioning, temperature monitoring, charge

termination, charge-status indication, and AutoComp

charge-rate compensation in a single 8-pin IC. MSOP,

TSSOP, and SOIC package options are offered to fit a

wide range of end applications.

Requires Small Number of External

Components

0.3 V Dropout Voltage for Minimizing Heat

Dissipation

Better Than 1% Voltage Regulation Accuracy

With Preset Voltages

AutoCompt Dynamic Compensation of

Battery Pack’s Internal Impedance to Reduce

Charge Time

The bq2057 continuously measures battery

temperature using an external thermistor. For safety,

the bq2057 inhibits charge until the battery temperature

is within user-defined thresholds. The bq2057 then

charges the battery in three phases: conditioning,

constant current, and constant voltage. If the battery

D

Optional Cell-Temperature Monitoring Before

and During Charge

Integrated Voltage and Current Regulation

With Programmable Charge-Current and High-

or Low-Side Current Sensing

voltage is below the low-voltage threshold, V

, the

(min)

D

Integrated Cell Conditioning for Reviving

Deeply Discharged Cells and Minimizing Heat

Dissipation During Initial Stage Of Charge

bq2057 precharges using a low current to condition the

battery. The conditioning charge rate is approximately

10% of the regulation current. The conditioning current

also minimizes heat dissipation in the external pass-

element during the initial stage of the charge. After

conditioning, the bq2057 applies a constant current to

the battery. An external sense-resistor sets the current.

The sense-resistor can be on either the high or low side

of the battery without additional components. The

constant-current phase continues until the battery

reaches the charge-regulation voltage.

Charge Status Output for Single or Dual Led

or Host Processor Interface

D

Automatic Battery-Recharge Feature

Charge Termination by Minimum Current

Automatic Low-Power Sleep Mode When V

CC

Is Removed

D

EVMs Available for Quick Evaluation

D

Packaging: 8-Pin SOIC, 8-Pin TSSOP, 8-Pin

MSOP

bq2057xSN or bq2057xTS

SOIC (SN) or TSSOP (TS) PACKAGE

(TOP VIEW)

bq2057xDGK

MSOP (DGK) PACKAGE

(TOP VIEW)

COMP

CC

BAT

SNS

BAT

VCC

TS

8

7

6

5

VCC

TS

8

7

6

5

1

2

3

4

1

2

3

4

SNS

COMP

CC

VSS

STAT

VSS

STAT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

AutoComp is a trademark of Texas Instruments.

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Copyright  2002, Texas Instruments Incorporated

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1

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SLUS025F − MAY 2001 − REVISED JULY 2002

DESCRIPTION (continued)

The bq2057 then begins the constant-voltage phase. The accuracy of the voltage regulation is better than 1%

over the operating-temperature and supply-voltage ranges. For single and dual cells, the bq2057 is offered in

four fixed-voltage versions: 4.1 V, 4.2 V, 8.2 V, and 8.4 V. Charge stops when the current tapers to the charge

termination threshold, I

. The bq2057 automatically restarts the charge if the battery voltage falls below

(TERM)

the V

threshold.

(RCH)

The designer also may use the AutoComp feature to reduce charging time. This proprietary technique allows

safe and dynamic compensation for the internal impedance of the battery pack during charge.

AVAILABLE OPTIONS

PACKAGE

†

MSOP

T

CHARGE REGULATION

VOLTAGE

SOIC

(SN)

TSSOP

(TS)

A

(DGK)

bq2057DGK

bq2057CDGK

4.1 V

4.2 V

8.2 V

8.4 V

Not available

bq2057CSN

Not available

bq2057WSN

bq2057TS

bq2057CTS

bq2057TTS

bq2057WTS

−20°C to 70°C

Not available

†

Note the difference in pinout for this package.

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SLUS025F − MAY 2001 − REVISED JULY 2002

function block diagram

VCC

V

Internal Reference

CC

_

+

DONE

Sleep Mode

_

+

V-Control

I-Control

BAT

CC

Voltage Regulation

COMP

G

(comp)

+

_

Battery

Recharge

V

CC

+

_

V

CC

Battery

Conditioning

Control

Block

STAT

_

+

TS

TS2 Trip

_

+

TS1 Trip

I-Control

_

0.5 V

High/Low SNS Set

CC

+

SNS

+

_

V

−V

CC (SNS)

Current Regulation

Charge Termination

V

−V

SS (SNS)

+

_

VSS

3

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SLUS025F − MAY 2001 − REVISED JULY 2002

Terminal Functions

TERMINAL

NO.

I/O

DESCRIPTION

NAME

SOIC (SN) and

TSSOP (TS)

MSOP

(DGK)

BAT

2

7

8

1

5

4

3

6

8

5

6

7

3

2

1

4

I

O

I

Voltage sense input

Charge control output

CC

COMP

SNS

STAT

TS

Charge-rate compensation input (AutoComp)

Current sense input

I

O

I

Charge status output

Temperature sense input

Supply voltage

VCC

VSS

I

Ground

detailed description

current-sense input

Battery current is sensed via the voltage developed on this pin by an external sense resistor. The external

resistor can be placed on either the high or low side of the battery. (See schematics for details.)

battery-voltage input

Voltage sense-input tied directly to the positive side of the battery.

temperature sense input

Input for an external battery-temperature monitoring circuit. Connecting this input to VCC/2 disables this feature.

charge-status output

3-state indication of charge in progress, charge complete, and temperature fault or sleep mode.

charge-control output

Source-follower output that drives an external pass-transistor (PNP or P-channel MOSFET) for current and

voltage regulation.

charge-rate compensation input

Sets the charge-rate compensation level. The voltage-regulation output may be programmed to vary as a

function of the charge current delivered to the battery.

supply voltage input

Power supply input and current reference for high-side sensing configuration.

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SLUS025F − MAY 2001 − REVISED JULY 2002

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage (V

with respect to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 to +18 V

CC

Input voltage, SNS, BAT, TS, COMP (all with respect to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V +0.3 V

Sink current (STAT pin) not to exceed P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Source current (STAT pin) not to exceed P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA

Output current (CC pin) not to exceed P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA

CC

D

Total power dissipation, P (at 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mW

D

Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20°C to 70°C

A

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C

stg

Lead temperature (soldering, 10 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATING TABLE

DERATING FACTOR

T

≤ 25°C

T = 70°C

A

POWER RATING

A

PACKAGE

ABOVE T = 25°C

POWER RATING

A

DGK

3.4 mW/°C

424 mW

271 mW

recommended operating conditions

MIN

MAX

15

UNIT

V

Supply voltage, V

CC

4.5

Operating free-air temperature range, T

−20

70

°C

A

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I

V

Current

V > V

CC CC(min)

, Excluding external loads

2

4

mA

(VCC)

CC

For bq2057 and bq2957C,

≥ V

3

6

V

(BAT)

,

V

(BAT)

– V

≥ 0.8 V

(min)

CC

I

Sleep current

µA

(VCCS)

CC

For bq2057T and bq2957W,

10

V

(BAT)

≥ V

,

V

(BAT)

– V

(min)

CC

I

Input bias current on BAT pin

Input bias current on SNS pin

Input bias current on TS pin

Input bias current on COMP pin

V

= V

1

5

µA

IB(BAT)

IB(SNS)

IB(TS)

(BAT)

(REG)

V(

= 5 V

SNS)

V

(TS)

= 5 V

IB(COMP)

(COMP)

BATTERY VOLTAGE REGULATION

bq2057, See Notes 1, 2, 3

4.059

4.158

8.119

8.317

4.10 4.141

4.20 4.242

8.20 8.282

8.40 8.484

bq2057C, See Notes 1, 2, 3

bq2057T, See Notes 1, 2, 3

bq2057W, See Notes 1, 2, 3

V

Output voltage

V

O(REG)

NOTES: 1. For high-side current sensing configuration

2. For low-side current sensing configuration, the tolerance is 1% for T = 25°C and 1.2% for −20°C ≥ T ≥ 70°C

A

3.

V +0.3 V ≤ V

(BAT) CC

≤ V

CC(max)

5

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SLUS025F − MAY 2001 − REVISED JULY 2002

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CURRENT REGULATION

bq2057 and bq2057C,

High-side current sensing configuration

95.4

113.6

100

105

125

110

130

115.5

137.5

121

bq2057T and bq2057W,

High-side current sensing configuration

Current regulation

threshold

V

mV

(SNS)

bq2057 and bq2057C,

Low-side current sensing configuration

bq2057T and bq2057W,

Low-side current sensing configuration

118.1

143

CHARGE TERMINATION DETECTION

Charge termination Voltage at pin SNS, relative to V

for high-side

CC

sensing, and to Vss for low-side sensing,

I

current detect

threshold

−24

−14

−4

mV

(TERM)

0°C ≤ T ≤ 50°C

A

TEMPERATURE COMPARATOR

Lower temperature

threshold

V

29.1

58.3

30

60

30.9

61.8

(TS1)

(TS2)

TS pin voltage

%V

CC

Upper temperature

threshold

V

PRECHARGE COMPARATOR

bq2057

2.94

3.04

5.98

6.18

3

3.1

6.1

6.3

3.06

3.16

6.22

6.43

bq2057C

bq2057T

bq2057W

Precharge

threshold

V

(min)

V

PRECHARGE CURRENT REGULATION

Voltage at pin SNS, relative to V

for high-side

CC

for low-side sensing,

sensing, and to V

SS

13

mV

Precharge current

regulation

0°C ≤ T ≤ 50°C

A

I

(PRECHG)

Voltage at pin SNS, relative to V

for high-side

= 5 V

CC

3

22

sensing, 0°C ≤ T ≤ 50°C, V

CC

A

V

RCH

COMPARATOR (Battery Recharge Threshold)

V

−

V

−

V

−

O(REG)

98 mV

O(REG)

100 mV

O(REG)

102 mV

bq2057 and bq2057C

Recharge

V

V/V

V

(RCH)

threshold

−

O(REG)

204 mV

O(REG)

bq2057T and bq2057W

196 mV

200 mV

CHARGE-RATE COMPENSATION (AutoComp)

V

+0.3 V≤ V ≤ V

, bq2057, bq2057C,

(BAT) CC CC(max)

1.87

2.09

2.2

2.4

2.53

2.76

bq2057T, bq2057W

G

AutoComp gain

(COMP)

V

+0.3 V ≤ V

≤ V

, bq2057T and

CC(max)

(BAT) CC

bq2057W in low-side sensing configuration

STAT PIN

Output (low)

voltage

V

I

= 10 mA

= 5 mA

0.7

OL(STAT)

OH(STAT)

OL

Output (high)

voltage

V

CC

-0.5

5

OH

CC PIN

V

Output low voltage

Sink current

I

= 5 mA (sink)

1.5

40

V

OL(CC)

O(CC)

I

Not to exceed power rating specification (P )

D

mA

O(CC)

6

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SLUS025F − MAY 2001 − REVISED JULY 2002

APPLICATION INFORMATION

Q1

FZT788B

R

0.2 Ω

SNS

PACK+

DC+

C1

0.1 µF

V

CC

R1

PACK−

1 kΩ

NTC

V

CC

bq2057

CC

COMP

R

T1

SNS

VCC

VSS

BAT

TS

TEMP

C2

STAT

0.1 µF

Battery

Pack

D1

GND

R

T2

R2

2 kΩ

Figure 1. Low Dropout Single- or Two-Cell Li-Ion/Li-Pol Charger

functional description

The bq2057 is an advanced linear charge controller for single or two-cell Li-Ion or Li-Pol applications. Figure 1

shows the schematic of charger using a PNP pass transistor. Figure 2 is an operational state diagram, and

Figure 3 is a typical charge profile. Figure 4 shows the schematic of a charger using P-channel MOSFET.

7

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SLUS025F − MAY 2001 − REVISED JULY 2002

APPLICATION INFORMATION

POR

Sleep Mode

V

> V

)

CC

(BAT

Indicate SLEEP

MODE

(STAT = Hi-Z)

No

Checked at All

Times

Yes

Suspend Charge

TS Pin

in TS1 to TS2

Range

Indicate CHARGE

SUSPEND

(STAT = Hi-Z)

No

Yes

Regulate

(PRECHG)

I

V

<V

(BAT) (min)

Yes

Indicate

Charge In-Progress

(STAT = High)

Suspend Charge

No

Indicate CHARGE

SUSPEND

(STAT = Hi-Z)

TS Pin

in TS1 to TS2

Range

No

Regulate

Current or Voltage

Indicate

Charge In-Progress

(STAT = High)

Yes

TS Pin

in TS1 to TS2

Range

V

< V

(min)

No

Suspend Charge

(BAT)

No

TS Pin

in TS1 to TS2

Range

Indicate CHARGE

SUSPEND

No

(STAT = Hi-Z)

Yes

TS Pin

in TS1 to TS2

Range

Yes

No

V

< V

(min)

Yes

(BAT)

No

Terminate Charge

I

Indicate CHARGE

Done

(TERM)

Detected

Yes

No

Yes

V

< V

(RCH)

(BAT)

(STAT = Low)

Yes

Figure 2. Operation Flowchart

8

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SLUS025F − MAY 2001 − REVISED JULY 2002

APPLICATION INFORMATION

Preconditioning

Phase

Current Regulation

Phase

Voltage Regulation and Charge

Termination Phase

Regulation Voltage

Regulation Current

Minimum Charge

Voltage

Preconditioning

and Taper Detect

Figure 3. Typical Charge Profile

qualification and precharge

When power is applied, the bq2057 starts a charge-cycle if a battery is already present or when a battery is

inserted. Charge qualification is based on battery temperature and voltage. The bq2057 suspends charge if the

battery temperature is outside the V

to V

range and suspends charge until the battery temperature is

(TS1)

(TS2)

within the allowed range. The bq2057 also checks the battery voltage. If the battery voltage is below the

precharge threshold V , the bq2057 uses precharge to condition the battery. The conditioning charge rate

(min)

I

is set at approximately 10% of the regulation current. The conditioning current also minimizes heat

(PRECHG)

dissipation in the external pass-element during the initial stage of charge. See Figure 3 for a typical

charge-profile.

9

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SLUS025F − MAY 2001 − REVISED JULY 2002

APPLICATION INFORMATION

Q1

SI6475DQ

R

0.2 Ω

SNS

D1

PACK+

PACK−

Battery

Pack

DC+

C2

0.1 µF

R2

1 kΩ

NTC

U1

bq2057

R

T1

CC

COMP

SNS

VCC

VSS

BAT

TS

TEMP

STAT

R4

R

T2

511 Ω

U2

C1

0.1 µF

R5

1 kΩ

CMD67−

22SRUC

R3

1 kΩ

GND

Figure 4. 0.5-A Charger Using P-Channel MOSFET

current regulation phase

The bq2057 regulates current while the battery-pack voltage is less than the regulation voltage, V

. The

, in series

O(REG)

bq2057 monitors charge current at the SNS input by the voltage drop across a sense-resistor, R

SNS

with the battery pack. In high-side current sensing configuration (Figure 5), R

is between the VCC and SNS

SNS

pins, and in low-side sensing (Figure 6) the R

is between VSS (battery negative) and SNS (charger ground)

SNS

pins. Charge-current feedback, applied through pin SNS, maintains a voltage of V

resistor. The following formula calculates the value of the sense resistor:

across the current sense

(SNS)

(1)

V

(SNS)

R

+

SNS

I

O(REG)

is the desired charging current.

Where I

O(REG)

10

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ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢇ

ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢉ

SLUS025F − MAY 2001 − REVISED JULY 2002

APPLICATION INFORMATION

DC+

R

SNS

BAT+

bq2057

SNS

COMP

SNS

COMP

BAT

VCC

TS

CC

VSS

BAT

VCC

TS

CC

VSS

STAT

DC−

BAT−

DC−

R

SNS

BAT−

Figure 5. High-Side Current Sensing

Figure 6. Low-Side Current Sensing

voltage regulation phase

The voltage regulation feedback is through the BAT pin. This input is tied directly to the positive side of the

battery pack. The bq2057 monitors the battery-pack voltage between the BAT and VSS pins. The bq2057 is

offered in four fixed-voltage versions: 4.1 V, 4.2 V, 8.2 V and 8.4 V.

Other regulation voltages can be achieved by adding a voltage divider between the positive and negative

terminals of the battery pack and using bq2057T or bq2057W. The voltage divider presents scaled battery-pack

voltage to BAT input. (See Figure 7 and Figure 8.) The resistor values RB1 and RB2 for the voltage divider are

calculated by the following equation:

(2)

V

R

(CELL)

B1

B2

+

N

–1

ǒ Ǔ

V

O(REG)

Where:

N = Number of cells in series

V

= Desired regulation voltage per cell

(CELL)

11

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ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢇ

ꢀ ꢁ ꢂꢃ ꢄꢅ ꢈꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢉ

SLUS025F − MAY 2001 − REVISED JULY 2002

APPLICATION INFORMATION

DC+

BAT+

BAT−

R

SNS

BAT+

R

B1

B2

bq2057

R

B1

SNS

bq2057

COMP

SNS

COMP

BAT

VCC

TS

CC

VSS

B2

BAT

VCC

TS

CC

VSS

BAT−

STAT

R

SNS

STAT

DC−

Figure 7. Optional Voltage Divider for

Nonstandard Regulation Voltage,

(High-Side Current Sensing)

Figure 8. Optional Voltage Divider for

Nonstandard Regulation Voltage,

(Low-Side Current Sensing)

charge termination and recharge

The bq2057 monitors the charging current during the voltage-regulation phase. The bq2057 declares a done

condition and terminates charge when the current tapers off to the charge termination threshold, I . A new

(TERM)

charge cycle begins when the battery voltage falls below the V

threshold.

(RCH)

battery temperature monitoring

The bq2057 continuously monitors temperature by measuring the voltage between the TS and VSS pins. A

negative- or a positive-temperature coefficient thermistor (NTC, PTC) and an external voltage divider typically

develop this voltage. (See Figure 9.) The bq2057 compares this voltage against its internal V

thresholds to determine if charging is allowed. (See Figure 10.) The temperature sensing circuit is immune to

and V

(TS1)

(TS2)

any fluctuation in V , since both the external voltage divider and the internal thresholds (V

are referenced to VCC.

and V

)

CC

(TS1)

(TS2)

The resistor values of R

and R

are calculated by the following equations:

(T1)

(T2)

For NTC Thermistors

(3)

(4)

5 R

R

* R

TH

TC

TH

R

+

T1

T2

ǒ

Ǔ

3 R

5 R

R

TH

TC

ǒ

Ǔ_–ǒ_{7 R}

Ǔ

ƫ

ƪ _{2 R}

TC

TH

12

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ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢇ

ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢉ

SLUS025F − MAY 2001 − REVISED JULY 2002

APPLICATION INFORMATION

battery temperature monitoring (continued)

For PTC Thermistors

(5)

(6)

5 R

R

* R

TH

TC

R

+

T1

T2

ǒ

Ǔ

3 R

5 R

R

TH

TC

ǒ

Ǔ_–ǒ_{7 R}

Ǔ

ƫ

ƪ _{2 R}

TH

TC

Where R

is the cold temperature resistance and R

is the hot temperature resistance of thermistor, as

(TC)

(TH)

specified by the thermistor manufacturer.

R

the V

or R can be omitted If only one temperature (hot or cold) setting is required. Applying a voltage between

T1

T2

and V

thresholds to pin TS disables the temperature-sensing feature.

(TS1)

(TS2)

DC+

R

SNS

BAT+

bq2057

R

T1

SNS

COMP

BAT

VCC

TS

BAT

VCC

TS

CC

VSS

CC

VSS

DC−

STAT

R

T1

T2

DC−

R

Thermistor

BAT−

T2

BAT−

Thermistor

R

SNS

High-Side Current Sensing

Low-Side Current Sensing

Figure 9. Temperature Sensing Circuits

V

CC

Temperature Fault

V

(TS2)

Normal Temperature Range

(TS1)

Temperature Fault

V

SS

Figure 10. bq2057 TS Input Thresholds

13

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SLUS025F − MAY 2001 − REVISED JULY 2002

APPLICATION INFORMATION

charge inhibit function

The TS pin can be used as charge-inhibit input. The user can inhibit charge by connecting the TS pin to VCC

or VSS (or any level outside the V to V thresholds). Applying a voltage between the V and V

(TS2)

(TS1)

(TS2)

(TS1)

thresholds to pin TS returns the charger to normal operation.

charge status indication

The bq2057 reports the status of the charger on the 3-state STAT pin. The following table summarized the

operation of the STAT pin.

CONDITION

STAT PIN

High

Battery conditioning and charging

Charge complete (Done)

Low

Temperature fault or sleep mode

Hi-Z

The STAT pin can be used to drive a single LED (Figure 1), dual-chip LEDs (Figure 4) or for interface to a host

or system processor (Figure 11). When interfacing the bq2057 to a processor, the user can use an output port,

as shown in Figure 11, to recognize the high-Z state of the STAT pin. In this configuration, the user needs to

read the input pin, toggle the output port and read the STAT pin again. In a high-Z condition, the input port always

matches the signal level on the output port.

Host

Processor

bq2057CTS

SNS

COMP

BAT

VCC

TS

OUT

CC

VSS

IN

STAT

Figure 11. Interfacing the bq2057 to a Host Processor

low-power sleep mode

The bq2057 enters the sleep mode if the VCC falls below the voltage at the BAT input. This feature prevents

draining the battery pack during the absence of VCC.

14

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SLUS025F − MAY 2001 − REVISED JULY 2002

APPLICATION INFORMATION

selecting an external pass-transistor

The bq2057 is designed to work with both PNP transistor and P-channel MOSFET. The device should be chosen

to handle the required power dissipation, given the circuit parameters, PCB layout and heat sink configuration.

The following examples illustrate the design process for either device:

PNP transistor:

Selection steps for a PNP bipolar transistor: Example: V = 4.5 V, I

= 1 A, 4.2-V single-cell Li-Ion (bq2057C).

I

(REG)

V is the input voltage to the charger and I

is the desired charge current (see Figure 1).

I

(REG)

1. Determine the maximum power dissipation, P , in the transistor.

D

The worst case power dissipation happens when the cell voltage, V

, is at its lowest (typically 3 V at the

(BAT)

beginning of current regulation phase) and V is at its maximum.

I

Where V

is the voltage drop across the current sense resistor.

CS

P = (V − V

– V ) × IREG

(BAT)

(7)

D

I

CS

P = (4.5 – 0.1 − 3) × 1 A

D

P = 1.4 W

D

2. Determine the package size needed in order to keep the junction temperature below the manufacturer’s

recommended value, T

. Calculate the total theta, θ(°C/W), needed.

(J)max

(8)

ǒ_T(J)max

150–40

1.4

Ǔ

* T

A(max)

θ

+

JC

P

D

(

)

θ

JC

+ 78°CńW

Now choose a device package with a theta at least 10% below this value to account for additional thetas

other than the device. A SOT223 package, for instance, has typically a theta of 60°C/W.

3. Select a collector-emitter voltage, V

be adequate in this example.

, rating greater than the maximum input voltage. A 15-V device will

(CE)

4. Select a device that has at least 50% higher drain current I rating than the desired charge current I

.

C

(REG)

5. Using the following equation, calculate the minimum beta (β or h ) needed:

FE

(9)

I

CMAX

b

+

min

I

B

1

b

min

0.035

b

+ 28

where I

is the maximum collector current (in this case same as I

), and I is the base current

max(C))

(REG) B

(chosen to be 35 mA in this example).

NOTE:

The beta of a transistor drops off by a factor of 3 over temperature and also drops off with load.

Therefore, note the beta of device at I and the minimum ambient temperature when choosing

(REG)

the device. This beta should be larger than the minimum required beta.

Now choose a PNP transistor that is rated for V

SOT223 package.

≥15 V, θ ≤ 78°C/W, I ≥ 1.5 A, β ≥ 28 and that is in a

min

(CE)

JC

C

15

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ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢇ

ꢀ ꢁ ꢂꢃ ꢄꢅ ꢈꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢉ

SLUS025F − MAY 2001 − REVISED JULY 2002

APPLICATION INFORMATION

selecting an external pass-transistor (continued)

P-channel MOSFET:

Selection steps for a P-channel MOSFET: Example: V = 5.5 V, I

= 500 mA, 4.2-V single-cell Li−Ion

I

(REG)

(bq2057C). V is the input voltage to the charger and I

is the desired charge current. (See Figure 4.)

I

(REG)

1. Determine the maximum power dissipation, P , in the transistor.

D

The worst case power dissipation happens when the cell voltage, V

, is at its lowest (typically 3 V at

(BAT)

the beginning of current regulation phase) and V is at its maximum.

I

Where V is the forward voltage drop across the reverse-blocking diode (if one is used), and V

D

voltage drop across the current sense resistor.

is the

(10)

CS

P = (V – V − V

– V

) × I

D

I

D

(CS)

(BAT) (REG)

P = (5.5 – 0.4 – 0.1 −3) × 0.5 A

D

P = 1 W

D

2. Determine the package size needed in order to keep the junction temperature below the manufacturer’s

recommended value, T . Calculate the total theta, θ(°C/W), needed.

JMAX

(11)

ǒ_{Tmax(J) A(max)}

150–40

1

Ǔ

–T

θ

+

JC

P

D

(

)

θ

JC

+ 110°CńW

Now choose a device package with a theta at least 10% below this value to account for additional thetas

other than the device. A TSSOP-8 package, for instance, has typically a theta of 70°C/W.

3. Select a drain-source voltage, V

adequate in this example.

, rating greater than the maximum input voltage. A 12 V device will be

(DS)

4. Select a device that has at least 50% higher drain current (I ) rating than the desired charge current I

D

.

(REG)

5. Verify that the available drive is large enough to supply the desired charge current.

V

= (V +V

+ V

) − V

I

(12)

(GS)

D

(CS)

OL(CC)

= (0.4 + 0.1 + 1.5) – 5.5

= −3.5

Where V

(if one is used), and V

output low voltage specification for the bq2057.

is the gate-to-source voltage, V is the forward voltage drop across the reverse-blocking diode

D

(GS)

is the voltage drop across the current sense resistor, and V

is the CC pin

CS

OL(CC)

Select a MOSFET with gate threshold voltage, V

, rating less than the calculated V

.

(GSth)

(GS)

Now choose a P-channel MOSFET transistor that is rated for VDS ≤ −15 V, θ

(GSth)

≤ 110°C/W, I ≥ 1 A,

D

JC

V

≥ −3.5 V and in a TSSOP package.

16

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ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢇ

ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢉ

SLUS025F − MAY 2001 − REVISED JULY 2002

APPLICATION INFORMATION

selecting input capacitor

In most applications, all that is needed is a high-frequency decoupling capacitor. A 0.1 µF ceramic, placed in

proximity to VCC and VSS pins, works well. The bq2057 works with both regulated and unregulated external

dc supplies. If a non-regulated supply is chosen, the supply unit should have enough capacitance to hold up

the supply voltage to the minimum required input voltage at maximum load. If not, more capacitance must be

added to the input of the charger.

selecting output capacitor

The bq2057 does not require any output capacitor for loop stability. The user can add output capacitance in order

to control the output voltage when a battery is not present. The charger quickly charges the output capacitor

to the regulation voltage, but the output voltage decays slowly, because of the low leakage current on the BAT

pin, down to the recharge threshold. Addition of a 0.1µF ceramic capacitor, for instance, results in a 100 mV(pp)

ripple waveform, with an approximate frequency of 25Hz. Higher capacitor values can be used if a lower

frequency is desired.

automatic charge-rate compensation

To reduce charging time, the bq2057 uses the proprietary AutoComp technique to compensate safely for

internal impedance of the battery pack. The AutoComp feature is disabled by connecting the COMP pin to VCC

in high-side current-sensing configuration, and to VSS in low-side current-sensing configuration. The COMP

pin must not be left floating.

Figure 12 outlines the major components of a single-cell Li-Ion battery pack. The Li-Ion battery pack consists

of a cell, protection circuit, fuse, connector, current sense-resistors, and some wiring. Each of these components

contains some resistance. Total impedance of the battery pack is the sum of the minimum resistances of all

battery-pack components. Using the minimum resistance values reduces the odds for overcompensating.

Overcompensating may activate the safety circuit of the battery pack.

BAT+

Wire

Fuse

Terminal

Cell

Protection

Controller

BAT−

Wire

Terminal

Discharge

Charge

Figure 12. Typical Components of a Single-Cell Li-Ion Pack

Compensation is achieved through input pin COMP (Figure 13). A portion of the current-sense voltage,

presented through this pin, is scaled by a factor of G

and summed with the regulation threshold, V

.

(COMP)

O(REG)

This process increases the output voltage to compensate for the battery pack’s internal impedance and for

undesired voltage drops in the circuit.

17

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ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢇ

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SLUS025F − MAY 2001 − REVISED JULY 2002

APPLICATION INFORMATION

automatic charge-rate compensation (continued)

AutoComp setup requires the following information:

D

Total impedance of battery pack (Z

)

(PACK)

Maximum charging current (I

(REG)

)

The voltage drop across the internal impedance of battery pack, V , can then be calculated using the following

(Z)

equation:

V

= Z

× I

(PACK) (REG)

(13)

(14)

(Z)

The required compensation is then calculated using the following equations:

V

(Z)

V

+

(COMP)

G

(COMP)

O(REG)

₎ǒ_G(COMP)

Ǔ

V

+ V

V

(PACK)

(COMP

Where V

is the voltage on COMP pin. This voltage is referenced to VCC in high-side current sensing

(COMP)

configuration and to VSS for low-side sensing. V

is the voltage across the battery pack.

(PACK)

The values of R

and R can be calculated using the following equation:

(COMP2)

(COMP1)

(15)

V

R

(COMP)

COMP2

+

V

R

) R

(SNS)

COMP1

COMP2

DC+

BAT+

DC+

R

COMP2

BAT+

R

COMP1

bq2057

SNS

COMP

R

SNS

COMP

BAT

VCC

TS

CC

VSS

BAT

VCC

TS

CC

VSS

DC−

STAT

DC−

R

COMP2

R

SNS

COMP1

BAT−

High-Side Current Sensing

Low-Side Current Sensing

Figure 13. AutoComp Circuits

18

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ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢇ

ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢉ

SLUS025F − MAY 2001 − REVISED JULY 2002

APPLICATION INFORMATION

automatic charge-rate compensation (continued)

The following example illustrates these calculations:

Assume Z

V

= 100 mΩ, I

= 500 mA, high-side current sensing bq2057C

(REG)

(PACK)

(16)

(17)

+ Z

I

(Z)

(PACK)

(REG)

V

+ 0.1 0.5

= 50 mV

(Z)

V

(Z)

V

(Z)

V

+

(COMP)

G

(COMP)

0.05

2.2

V

+

V

= 22.7 mV

(COMP)

Let R

= 10 kΩ

COMP2

(18)

ǒ_V(SNS)

Ǔ

R

* V

COMP2

(COMP)

)

R

+

COMP1

V

(COMP)

(

105 mV * 22.7 mV

R

+ 10k

COMP1

22.7 mV

R

+ 36.25 kW

COMP1

Use the closest standard value (36.0 kΩ) for R

COMP1

19

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ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢇ

ꢀ ꢁ ꢂꢃ ꢄꢅ ꢈꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢉ

SLUS025F − MAY 2001 − REVISED JULY 2002

MECHANICAL DATA

DGK (R-PDSO-G8)

PLASTIC SMALL-OUTLINE PACKAGE

0,38

0,25

M

0,65

8

0,25

5

0,15 NOM

3,05

2,95

4,98

4,78

Gage Plane

0,25

0°−ā6°

1

4

0,69

3,05

2,95

0,41

Seating Plane

0,10

0,15

0,05

1,07 MAX

4073329/B 04/98

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. Falls within JEDEC MO-187

20

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ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢉ

SLUS025F − MAY 2001 − REVISED JULY 2002

MECHANICAL DATA

8−Pin SOIC Narrow (SN)

(

)

8−Pin SN 0.150” SOIC

Inches

Millimeters

Min.

Max.

Min.

Max.

Dimension

A

A1

B

0.060

0.004

0.013

0.007

0.185

0.150

0.045

0.225

0.015

0.070

0.010

0.020

0.010

0.200

0.160

0.055

0.245

0.035

1.52

0.10

0.33

0.18

4.70

3.81

1.14

5.72

0.38

1.78

0.25

0.51

0.25

5.08

4.06

1.40

6.22

0.89

C

D

E

e

H

L

TS: 8−Pin TSSOP

Inches

Millimeters

Dimension

Min.

Max.

Min.

Max.

A

A1

B

-

0.043

0.006

0.012

0.007

0.122

0.176

-

1.10

0.15

0.30

0.18

3.10

4.48

0.002

0.007

0.004

0.114

0.169

0.05

0.18

0.09

2.90

4.30

C

D

E

e

0.0256BSC

0.65BSC

H

0.246

0.256

6.25

6.50

Notes:

1.

Controlling dimension: millimeters. Inches shown for reference only.

2

3

’D’ and ’E’ do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0,15 mm per side

Each lead centerline shall be located within 0,10 mm of its exact true position.

4

5

Leads shall be coplanar within 0,08 mm at the seating plane.

Dimension ’B’ does not include dambar protrusion. The dambar protrusion(s) shall not cause the lead width

to exceed ’B’ maximum by more than 0,08 mm.

6

7

Dimension applies to the flat section of the lead between 0,10 mm and 0,25 mm from the lead tip.

’A1’ is defined as the distance from the seating plane to the lowest point of the package body (base plane).

21

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PACKAGE OPTION ADDENDUM

www.ti.com

24-Feb-2006

PACKAGING INFORMATION

Orderable Device

BQ2057CDGK

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

MSOP

DGK

8

80 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

BQ2057CDGKG4

BQ2057CDGKR

BQ2057CDGKRG4

MSOP

DGK

80 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

BQ2057CSN

BQ2057CSNTR

BQ2057CTS

ACTIVE

SOIC

D

8

75

TBD

CU NIPDAU Level-1-220C-UNLIM

2500

TSSOP

PW

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

BQ2057CTSG4

BQ2057CTSTR

BQ2057CTSTRG4

BQ2057DGK

ACTIVE

TSSOP

MSOP

PW

8

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

PW

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

DGK

80 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

BQ2057DGKR

BQ2057DGKRG4

BQ2057PDGK

BQ2057PDGKR

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

80 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

BQ2057SN

BQ2057SNTR

BQ2057SNTRG4

BQ2057TS

ACTIVE

SOIC

D

8

75

TBD

CU NIPDAU Level-1-220C-UNLIM

2500

Call TI

Level-1-220C-UNLIM

Call TI

SOIC

D

TSSOP

PW

150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

BQ2057TSN

BQ2057TSNTR

BQ2057TSNTRG4

BQ2057TSTR

ACTIVE

SOIC

D

8

75

TBD

CU NIPDAU Level-1-220C-UNLIM

2500

SOIC

D

Call TI

TSSOP

PW

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

BQ2057TSTRG4

BQ2057TTS

ACTIVE

TSSOP

PW

8

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

BQ2057TTSG4

BQ2057TTSTR

BQ2057TTSTRG4

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

24-Feb-2006

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

BQ2057WSN

BQ2057WSNTR

BQ2057WSNTRG4

BQ2057WTS

ACTIVE

SOIC

D

8

75

TBD

CU NIPDAU Level-1-220C-UNLIM

SOIC

2500

SOIC

D

Call TI

TSSOP

PW

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

BQ2057WTSG4

BQ2057WTSTR

ACTIVE

TSSOP

PW

8

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for

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Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

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www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	BQ2057TSTRG4
厂家：	TEXAS INSTRUMENTS
描述：	IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, PLASTIC, TSSOP-8, Power Management Circuit 光电二极管
文件：	总27页 (文件大小：492K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ2057TSTRG4 [TI]

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