AWR1843ABGABLQ1_技术文档

AWR1843

ZHCSJ79C –DECEMBER 2018 –REVISED JANUARY 2022

AWR1843 单芯片77GHz 至79GHz FMCW 雷达传感器

• 器件安全（在部分器件型号上）

1 特性

– 支持经过身份验证和加密的安全引导

– 具有密钥撤销功能的客户可编程根密钥、对称密

钥（256 位）、非对称密钥（最高RSA-2K）

– 加密软件加速器–PKA、AES（最高256

位）、SHA（最高256 位）、TRNG/DRGB

• 符合功能安全标准

• FMCW 收发器

– 集成PLL、发送器、接收器、基带和ADC

– 76GHz 至81GHz 的覆盖范围，具有4GHz 的可

用带宽

– 四个接收通道

– 三个发送通道

– 基于分数N PLL 的超精确线性调频脉冲引擎

– TX 功率：12dBm

– 专为功能安全应用开发

– 文档有助于使ISO 26262 功能安全系统设计满

足ASIL-D 级要求

– RX 噪声系数：

– 硬件完整性高达ASIL-B 级

– 安全相关认证

• 14dB（76 至77GHz）

• 15dB（77 至81GHz）

– 1MHz 时的相位噪声：

• 经TUV SUD 进行ISO 26262 认证达到ASIL

B 级

• 符合AEC-Q100 标准

• 器件高级特性

• –95dBc/Hz（76 至77GHz）

• –93dBc/Hz（77 至81GHz）

• 内置校准和自检（监控）

– ^®基于Arm^®Cortex^®-R4F 的无线电控制系统

– 内置固件(ROM)

– 针对工艺和温度进行自校准的系统

• 用于FMCW 信号处理的C674x DSP

• 片上存储器：2MB

– 嵌入式自监控，无需使用主机处理器

– 复基带架构

– 嵌入式干扰检测功能

– 发送路径中的可编程相位旋转器，用于实现波束

形成

• 电源管理

– 内置LDO 网络，可增强PSRR

– I/O 支持双电压3.3V/1.8V

• 时钟源

• 用于物体跟踪和分类、AUTOSAR 和接口控制的

Cortex-R4F 微控制器

– 支持自主模式（从QSPI 闪存加载用户应用）

• 集成外设

– 支持频率为40MHz 的外部振荡器

– 支持外部驱动、频率为40MHz 的时钟（方波/正

弦波）

– 具有ECC 的内部存储器

• 主机接口

– 支持40MHz 晶体与负载电容器相连接

– CAN 和CAN-FD

• 轻松的硬件设计

• 为用户应用提供的其他接口

– 多达6 个ADC 通道

– 多达2 个SPI 通道

– 多达2 个UART

– 0.65mm 间距、161 引脚10.4mm × 10.4mm 覆

晶BGA 封装，可实现轻松组装和低成本PCB

设计

– 小尺寸解决方案

– I²C

– GPIO

• 运行条件

– 结温范围：–40°C 至125°C

– 用于原始ADC 数据和调试仪表的双通道LVDS

接口

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SWRS222

AWR1843

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ZHCSJ79C –DECEMBER 2018 –REVISED JANUARY 2022

• 泊车辅助

• 占位检测

• 手势识别

2 应用

• 盲点检测

• 变道辅助

• 侧向来车警示

40-MHz

Crystal

Serial

Flash

Power Management

QSPI

Integrated MCU

ARM Cortex-R4F

DCAN

PHY

Automotive

Network

CAN

Antenna

Structure

RX1

RX2

RX3

RX4

MCAN

PHY

Automotive

Network

CAN FD

Radar

Front End

TX1

TX2

TX3

Integrated DSP

TI C674x

AWR1843

图2-1. 适用于汽车应用的自主雷达传感器

3 说明

AWR1843 器件是一款能够在 76 至 81GHz 频带中运行的集成式单芯片 FMCW 雷达传感器。该器件采用 TI 的低

功耗 45nm RFCMOS 工艺进行构建，并且在超小封装中实现了出色的集成度。AWR1843 是适用于汽车领域中的

低功耗、自监控、超精确雷达系统的理想解决方案。

AWR1843 器件是一种自包含FMCW 雷达传感器单芯片解决方案，能够简化76 至81GHz 频带中的汽车雷达传感

器实施。它基于 TI 的低功耗 45nm RFCMOS 工艺构建，从而实现了一个具有内置 PLL 和 ADC 转换器的单片实

施 3TX、4RX 系统。它集成了 DSP 子系统，该子系统包含 TI 用于雷达信号处理的高性能 C674x DSP。该器件

包含一个BIST 处理器子系统，该子系统负责无线电配置、控制和校准。此外，该器件还包含用于汽车连接的用户

可编程 ARM R4F。硬件加速器区块(HWA) 可执行雷达处理，并且有助于以更高级的算法在DSP 上节省 MIPS。

简单编程模型更改可支持各种传感器实施（近距离、中距离和远距离），并且能够进行动态重新配置，从而实现

多模式传感器。此外，该器件作为完整的平台解决方案进行提供，其中包括 TI 参考设计、软件驱动程序、示例配

置、API 指南以及用户文档。

器件信息

器件型号⁽²⁾

AWR1843ABGABLQ1

AWR1843ABGABLRQ1

AWR1843ABSABLQ1

AWR1843ABSABLRQ1

封装⁽¹⁾

托盘/卷带包装

封装尺寸

托盘

卷带包装

托盘

FCBGA (161)

10.4mm × 10.4mm

卷带包装

(1) 如需更多信息，请参阅节13 机械、封装和可订购信息。

(2) 如需更多信息，请参阅节12.1，器件命名规则。

2

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4 功能方框图

图4-1 展示了器件的功能方框图

Serial Flash interface

QSPI

Cortex R4F

@ 200MHz

LNA

IF

ADC

Optional External

MCU interface

SPI

(User programmable)

Digital

Front-end

PMIC control

SPI / I2C

Prog RAM

(512kB*)

Data RAM

(192kB*)

Boot

ROM

DCAN

CAN-FD

UARTs

(Decimation

filter chain)

Primary communication

interfaces (automotive)

Radar Hardware Accelerator

(FFT, Log mag, and others)

DMA

Main sub-system

(Customer programmed)

Test/

Debug

JTAG for debug/

development

ADC

Buffer

PA

û-

Mailbox

High-speed ADC output

interface (for recording)

LVDS

HIL

Synth

(20 GHz)

Ramp

Generator

PA

x4

High-speed input for

hardware-in-loop verification

C674x DSP

@ 400/600 MHz

Radio (BIST)

processor

PA

GPADC

Osc.

6

(For RF Calibration

& Self-test œ TI

programmed)

L1P

(32kB)

L1D

(32kB)

L2 (256kB)

Prog RAM

& ROM

Data

RAM

VMON

Temp

DMA

CRC

Radar Data Memory

1024 kB*

Radio processor

sub-system

(TI programmed)

DSP sub-system

(Customer programmed)

RF/Analog sub-system

* Up to 512kB of Radar Data Memory can be switched to the Main R4F program and data RAMs

图4-1. 功能方框图

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Table of Contents

9 Detailed Description......................................................54

9.1 Overview...................................................................54

9.2 Functional Block Diagram.........................................54

9.3 Subsystems.............................................................. 55

9.4 Other Subsystems.................................................... 62

10 Monitoring and Diagnostics....................................... 65

10.1 Monitoring and Diagnostic Mechanisms................. 65

11 Applications, Implementation, and Layout............... 70

11.1 Application Information............................................70

11.2 Short- and Medium-Range Radar ..........................70

11.3 Reference Schematic..............................................71

12 Device and Documentation Support..........................72

12.1 Device Nomenclature..............................................72

12.2 Tools and Software................................................. 73

12.3 Documentation Support.......................................... 73

12.4 支持资源..................................................................73

12.5 Trademarks.............................................................73

12.6 Electrostatic Discharge Caution..............................74

12.7 术语表..................................................................... 74

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 2

3 说明................................................................................... 2

4 功能方框图.........................................................................3

5 Revision History.............................................................. 5

6 Device Comparison.........................................................6

6.1 Related Products........................................................ 7

7 Terminal Configuration and Functions..........................8

7.1 Pin Diagram................................................................ 8

7.2 Signal Descriptions................................................... 12

7.3 Pin Attributes.............................................................17

8 Specifications................................................................ 25

8.1 Absolute Maximum Ratings...................................... 25

8.2 ESD Ratings............................................................. 25

8.3 Power-On Hours (POH)............................................26

8.4 Recommended Operating Conditions.......................26

8.5 Power Supply Specifications.....................................27

8.6 Power Consumption Summary................................. 28

8.7 RF Specification........................................................29

8.8 CPU Specifications................................................... 30

8.9 Thermal Resistance Characteristics for FCBGA

Information.................................................................... 75

13.1 Packaging Information............................................ 75

13.2 Tray Information for ................................................75

Package [ABL0161].....................................................30

8.10 Timing and Switching Characteristics..................... 31

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5 Revision History

Changes from May 1, 2020 to December 31, 2021 (from Revision B (May 2020) to Revision C

(December 2021))

Page

• 通篇：已更新以反映功能安全合规性.................................................................................................................. 1

• 通篇：将“A2D”替换为“ADC”；将“主子系统”和“主R4F”更改为“主要子系统”和“主要R4F”；在

主/从术语方面改用了更具包容性的措辞..............................................................................................................1

•

（特性）：更新了功能安全合规性认证资料；提及了毫米波传感器的额定工作温度范围；更新了关于器件安全

的其他信息.........................................................................................................................................................1

（器件信息）：添加了毫米波传感器的其他安全量产器件..................................................................................2

•

• 更新/更改了“功能方框图”以改用包容性术语...................................................................................................3

• (Device Comparison): Removed a row on Functional-Safety compliance and instead added a table-note for

this and LVDS Interface; Additional information on Device security added........................................................ 6

• (Signal Descriptions) :Updated/Changed CLKP and CLKM descriptions.........................................................15

• (Absolute Maximum Ratings): Added entries for externally supplied power on the RF inputs (TX and RX) and

a table-note for the signal level applied on TX..................................................................................................25

• (Average Power Consumption at Power Terminals): Updated/Changed the typical average power numbers....

28

• (RF Specifications) : Added lead-in paragraph and "Noise Figure, In-band P1dB vs Receiver Gain" image...29

• (Clock Specifications): Updated/Changed 表8-5 to reflect correct device operating temperature range........ 32

• (Table. External Clock Mode Specifications): Revised frequency tolerance specs from +/-50 to +/-100 ppm..32

• Added a footnote for L3-Shared memory in DSP C674x Memory Map ...........................................................61

• (Monitoring and Diagnostic Mechanisms): Updated/Changed table header and description to reflect

Functional Safety-Compliance; added a note for reference to safety related collateral................................... 65

• (Reference Schematics) : Added weblinks to device EVM documentation collateral ......................................71

• (Device Nomenclature):Updated/changed Device Nomenclature ................................................................... 72

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6 Device Comparison

FUNCTION

AWR1243

AWR1443

AWR1642

AWR1843⁽¹⁾

Number of receivers

Number of transmitters

On-chip memory

4

3

4

3

4

2

4

3

576KB

5

1.5MB

5

2MB

10

—

15

Max I/F (Intermediate Frequency) (MHz)

Max real/complex 2x sampling rate (Msps)

Max complex 1x sampling rate (Msps)

Device Security⁽²⁾

37.5

18.75

12.5

6.25

—

12.5

6.25

Yes

25

12.5

Yes

—

Processor

MCU (R4F)

Yes

—

DSP (C674x)

—

Peripherals

Serial Peripheral Interface (SPI) ports

Quad Serial Peripheral Interface (QSPI)

Inter-Integrated Circuit (I²C) interface

Controller Area Network (DCAN) interface

CAN-FD

1

2

Yes

1

Yes

1

Yes

1

—

Yes

—

Trace

—

PWM

—

Hardware In Loop (HIL/DMM)

—

GPADC

Yes

—

LVDS/Debug⁽³⁾

Yes

CSI2

—

Hardware accelerator

1-V bypass mode

Yes

—

Yes

Cascade (20-GHz sync)

JTAG

—

2

—

Yes

2

—

Yes

2

—

Yes

3⁽⁴⁾

Yes

Number of Tx that can be simultaneously used

Per chirp configurable Tx phase shifter

—

PRODUCT PREVIEW (PP),

Product

ADVANCE INFORMATION (AI),

status⁽⁵⁾

PD

or PRODUCTION DATA (PD)

(1) Developed for Functional Safety applications, the device supports hardware integrity upto ASIL-B. Refer to the related documentation

for more details.

(2) Device security features including Secure Boot and Customer Programmable Keys are available in select devices for only select part

variants as indicated by the Device Type identifier in Section 3, Device Information table.

(3) The LVDS interface is not a production interface and is only used for debug.

(4) 3 Tx Simultaneous operation is supported only in AWR1843 with 1V LDO bypass and PA LDO disable mode. In this mode 1V supply

needs to be fed on the VOUT PA pin. Rest of the other devices only support simultaneous operation of 2 Transmitters.

(5) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

6

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6.1 Related Products

For information about other devices in this family of products or related products see the links that follow.

mmWave sensors

TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with less

power using the smallest footprint mmWave sensor portfolio for automotive applications.

Automotive

mmWave sensors

TI’s automotive mmWave sensor portfolio offers high-performance radar front end to

ultra-high resolution, small and low-power single-chip radar solutions. TI’s scalable

sensor portfolio enables design and development of ADAS system solution for every

performance, application and sensor configuration ranging from comfort functions to

safety functions in all vehicles.

Companion

products for

AWR1843

Review products that are frequently purchased or used in conjunction with this product.

Reference designs TI Designs Reference Design Library is a robust reference design library spanning

for AWR1843

analog, embedded processor and connectivity. Created by TI experts to help you jump-

start your system design, all TI Designs include schematic or block diagrams, BOMs,

and design files to speed your time to market. Search and download designs at ti.com/

tidesigns.

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7 Terminal Configuration and Functions

7.1 Pin Diagram

图 7-1 shows the pin locations for the 161-pin FCBGA package. 图 7-2, 图 7-3, 图 7-4, and 图 7-5 show the

same pins, but split into four quadrants.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

VOUT_

14APLL

OSC

_CLKOUT

A

B

C

D

E

F

VSSA

VOUT_PA

VSSA

VOUT

_14SYNTH

VIN

_18CLK

VIN

_18VCO

VSSA

VOUT_PA

VSSA

TX1

VSSA

TX2

VSSA

TX3

VSSA

VBGAP

VSSA

CLKP

CLKM

VIN

_13RF2

VSSA

GPACD_5

SPIA_mosi

SPIA_clk

SPIB_mosi

SYNC_OUT

GPIO_0

VSSA

VIOIN

_18DIFF

VIN

_13RF2

GPADC_6

SPIA_miso

SPIB_clk

SPIB_miso

SPIB_cs_n

VSSA

RX4

VSSA

VSS

SPIA_cs_n

VIN_18BB

VSS

VIOIN

VIN

_13RF1

G

H

J

VSSA

RX3

VSSA

VSS

VIN_SRAM

VIN

_13RF1

VSSA

VSS

VDDIN

VIN

_13RF1

VSSA

RX2

VSSA

VSS

GPIO_1

LVDS_TXP0 LVDS_TXM0

LVDS_TXP1 LVDS_TXM1

LVDS_CLKP LVDS_CLKM

K

L

VSSA

VIN_18BB

VSS

GPIO_2

VSSA

RX1

VSSA

VSS

VPP

LVDS

_FRCLKP

LVDS

_FRCLKM

M

N

P

R

VSSA

MCU

_CLKOUT

Warm

_Reset

VSSA

GPADC1

VSSA

GPADC2

GPADC4

VSSA

rs232_rx

SYNC_in

GPIO_31

rs232_tx

GPIO_32

GPIO_33

nERROR_OUT nERROR_IN

TMS

TCK

VDDIN

QSPI_cs_n

TDI

QSPI[1]

QSPI[3]

QSPI_clk

TDO

DMM_SYNC

GPIO_47

VDDIN

SPI_HOST

_INTR

PMIC

_CLKOUT

GPADC3

NRESET

GPIO_34

VDDIN

GPIO_36

GPIO_35

GPIO_38

GPIO_37

VNWA

VIOIN_18

VIOIN

QSPI[0]

QSPI[2]

VSS

Not to scale

图7-1. Pin Diagram

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1

2

3

4

5

6

7

8

A

B

C

D

E

F

VSSA

VOUT_PA

VSSA

VOUT_PA

VSSA

TX1

VSSA

TX2

VSSA

TX3

VIN

_13RF2

VSSA

VIN

_13RF2

VSSA

VSS

RX4

VIN_18BB

VIN

_13RF1

G

VSSA

VSS

Not to scale

1

3

2

4

图7-2. Top Left Quadrant

9

10

11

12

13

14

15

VOUT_

14APLL

OSC

_CLKOUT

A

B

C

D

E

F

VSSA

VOUT

_14SYNTH

VIN

_18CLK

VIN

_18VCO

VSSA

VBGAP

VSSA

CLKP

CLKM

GPACD_5

SPIA_mosi

SPIA_clk

VSSA

VIOIN

_18DIFF

GPADC_6

SPIA_miso

SPIB_clk

VSS

SPIA_cs_n

VSS

SPIB_mosi

SYNC_OUT

VIOIN

G

VSS

SPIB_miso

VIN_SRAM

Not to scale

1

3

2

4

图7-3. Top Right Quadrant

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1

2

3

4

5

6

7

8

VIN

_13RF1

H

RX3

VSSA

VSS

VIN

_13RF1

J

VSSA

VSS

K

L

RX2

VIN_18BB

VSSA

VSS

M

N

P

R

RX1

VSSA

MCU

_CLKOUT

VSSA

GPADC1

VSSA

rs232_rx

SYNC_in

GPIO_31

rs232_tx

GPIO_32

GPIO_33

nERROR_OUT nERROR_IN

GPADC2

GPADC4

GPADC3

NRESET

GPIO_34

GPIO_36

GPIO_35

GPIO_38

GPIO_37

VDDIN

Not to scale

1

3

2

4

图7-4. Bottom Left Quadrant

10

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9

10

11

12

13

14

15

H

J

VSS

GPIO_0

SPIB_cs_n

VDDIN

VSS

GPIO_1

GPIO_2

VPP

LVDS_TXP0 LVDS_TXM0

LVDS_TXP1 LVDS_TXM1

LVDS_CLKP LVDS_CLKM

K

L

VSS

LVDS

_FRCLKP

LVDS

_FRCLKM

M

N

P

R

Warm

_Reset

TMS

TCK

VDDIN

QSPI_cs_n

TDI

QSPI[1]

QSPI[3]

QSPI_clk

TDO

DMM_SYNC

GPIO_47

VDDIN

SPI_HOST

_INTR

PMIC

_CLKOUT

VNWA

VIOIN_18

VIOIN

QSPI[0]

QSPI[2]

VSS

Not to scale

1

3

2

4

图7-5. Bottom Right Quadrant

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7.2 Signal Descriptions

备注

All digital IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET) are non-

failsafe; hence, care needs to be taken that they are not driven externally without the VIO supply being

present to the device.

备注

The GPIO state during the power supply ramp is not ensured. In case the GPIO is used in the

application where the state of the GPIO is critical, even when NRESET is low, a tri-state buffer should

be used to isolate the GPIO output from the radar device and a pull resister used to define the

required state in the application. The NRESET signal to the radar device could be used to control the

output enable (OE) of the tri-state buffer.

7.2.1 Signal Descriptions - Digital

SIGNAL NAME

ADC_VALID

PIN TYPE

DESCRIPTION

BALL NO.

O

When high, indicating valid ADC samples

H13, J13, P13

F14, H14, K13, N10, N13,

N4, N5, R8

BSS_UART_TX

O

Debug UART Transmit [Radar Block]

CAN_FD_RX

CAN_FD_TX

CAN_RX

CAN_TX

CHIRP_END

CHIRP_START

DMM0

I

O

I

CAN FD (MCAN) Receive Signal

D13, F14, N10, N4, P12

CAN FD (MCAN) Transmit Signal

E14, H14, N5, P10, R14

CAN (DCAN) Receive Signal

E13

IO

O

I

CAN (DCAN) Transmit Signal

E15

Pulse signal indicating the end of each chirp

Pulse signal indicating the start of each chirp

Debug Interface (Hardware In Loop) - Data Line

Debug Interface (Hardware In Loop) - Clock

K13, N8, P9

R4

P5

DMM1

I

DMM2

I

R5

P6

DMM3

I

DMM4

I

R7

P7

DMM5

I

DMM6

I

R8

P8

DMM7

I

DMM_CLK

I

N15

Debug Interface (Hardware In Loop) Mux Select between DMM1 and

DMM2 (Two Instances)

DMM_MUX_IN

I

G13, J13, P4

DMM_SYNC

DSS_UART_TX

EPWM1A

I

Debug Interface (Hardware In Loop) - Sync

Debug UART Transmit [DSP]

PWM Module 1 - Output A

N14

O

I

D13, E13, G14, P8, R12

N5, N8

EPWM1B

PWM Module 1 - Output B

H13, N5, P9

EPWM1SYNCI

EPWM2A

PWM Module 1 - Sync Input

PWM Module 2- Output A

J13

O

IO

H13, N4, N5, P9

EPWM2B

PWM Module 2 - Output B

N4

R7

EPWM2SYNCO

EPWM3A

PWM Module 2 - Sync Output

PWM Module 3 - Output A

N4

EPWM3SYNCO

FRAME_START

GPIO_0

PWM Module 3 - Sync Output

Pulse signal indicating the start of each frame

General-purpose I/O

P6

K13, N8, P9

H13

12

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SIGNAL NAME

ZHCSJ79C –DECEMBER 2018 –REVISED JANUARY 2022

PIN TYPE

IO

O

DESCRIPTION

BALL NO.

J13

K13

E13

H14

F14

P11

R12

R13

N12

R14

P12

P13

H13

N5

GPIO_1

General-purpose I/O

I2C Clock

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

GPIO_8

GPIO_9

GPIO_10

GPIO_11

GPIO_12

GPIO_13

GPIO_14

GPIO_15

GPIO_16

GPIO_17

GPIO_18

GPIO_19

GPIO_20

GPIO_21

GPIO_22

GPIO_23

GPIO_24

GPIO_25

GPIO_26

GPIO_27

GPIO_28

GPIO_29

GPIO_30

GPIO_31

GPIO_32

GPIO_33

GPIO_34

GPIO_35

GPIO_36

GPIO_37

GPIO_38

GPIO_47

I2C_SCL

I2C_SDA

LVDS_TXP[0]

LVDS_TXM[0]

LVDS_TXP[1]

LVDS_TXM[1]

N4

J13

P10

N10

D13

E14

F13

G14

R11

N13

N8

K13

P9

P4

G13

E15

R4

P5

R5

P6

R7

P7

R8

P8

N15

G14, N4

F13, N5

J14

J15

K14

K15

I2C Data

Differential data Out –Lane 0

Differential data Out –Lane 1

O

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BALL NO.

ZHCSJ79C –DECEMBER 2018 –REVISED JANUARY 2022

SIGNAL NAME

LVDS_CLKP

PIN TYPE

DESCRIPTION

O

I

L14

L15

Differential clock Out

LVDS_CLKM

LVDS_FRCLKP

LVDS_FRCLKM

MCU_CLKOUT

MSS_UARTA_RX

MSS_UARTA_TX

MSS_UARTB_RX

M14

Differential Frame Clock

M15

Programmable clock given out to external MCU or the processor

Main Subsystem - UART A Receive

N8

F14, N4, R11

H14, N13, N5, R4

N4, P4

O

IO

Main Subsystem - UART A Transmit

Main Subsystem - UART B Receive

F14, H14, K13, N13, N5,

P10, P7

MSS_UARTB_TX

NDMM_EN

O

I

Main Subsystem - UART B Transmit

Debug Interface (Hardware In Loop) Enable - Active Low Signal

N13, N5

Failsafe input to the device. Nerror output from any other device can

be concentrated in the error signaling monitor module inside the

device and appropriate action can be taken by Firmware

NERROR_IN

I

N7

Open drain fail safe output signal. Connected to PMIC/

Processor/MCU to indicate that some severe criticality fault has

happened. Recovery would be through reset.

NERROR_OUT

O

N6

PMIC_CLKOUT

QSPI[0]

O

IO

I

Output Clock from AWR1843 device for PMIC

QSPI Data Line #0 (Used with Serial Data Flash)

QSPI Data Line #1 (Used with Serial Data Flash)

QSPI Data Line #2 (Used with Serial Data Flash)

QSPI Data Line #3 (Used with Serial Data Flash)

QSPI Clock (Used with Serial Data Flash)

QSPI Chip Select (Used with Serial Data Flash)

Debug UART (Operates as Bus Main) - Receive Signal

Debug UART (Operates as Bus Main) - Transmit Signal

Sense On Power - Line#0

H13, K13, P9

R13

QSPI[1]

N12

QSPI[2]

R14

QSPI[3]

IO

I

P12

QSPI_CLK

QSPI_CLK_EXT

QSPI_CS_N

RS232_RX

RS232_TX

SOP[0]

R12

H14

IO

I

P11

N4

O

I

N5

N13

SOP[1]

I

Sense On Power - Line#1

G13

SOP[2]

I

Sense On Power - Line#2

P9

SPIA_CLK

SPIA_CS_N

SPIA_MISO

SPIA_MOSI

SPIB_CLK

SPIB_CS_N

SPIB_CS_N_1

SPIB_CS_N_2

SPIB_MISO

SPIB_MOSI

SPI_HOST_INTR

SYNC_IN

SYNC_OUT

TCK

IO

O

I

SPI Channel A - Clock

E13

SPI Channel A - Chip Select

E15

SPI Channel A - Main In Slave Out

SPI Channel A - Main Out Slave In

SPI Channel B - Clock

E14

D13

F14, R12

H14, P11

G13, J13, P13

G13, J13, N12

G14, R13

F13, N12

P13

SPI Channel B Chip Select (Instance ID 0)

SPI Channel B Chip Select (Instance ID 1)

SPI Channel B Chip Select (Instance ID 2)

SPI Channel B - Main In Slave Out

SPI Channel B - Main Out Slave In

Out of Band Interrupt to an external host communicating over SPI

Low frequency Synchronization signal input

Low Frequency Synchronization Signal output

JTAG Test Clock

P4

O

I

G13, J13, K13, P4

P10

TDI

I

JTAG Test Data Input

R11

TDO

O

I

JTAG Test Data Output

N13

TMS

JTAG Test Mode Signal

N10

TRACE_CLK

O

Debug Trace Output - Clock

N15

14

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SIGNAL NAME

ZHCSJ79C –DECEMBER 2018 –REVISED JANUARY 2022

PIN TYPE

DESCRIPTION

Debug Trace Output - Control

BALL NO.

N14

R4

TRACE_CTL

O

TRACE_DATA_0

TRACE_DATA_1

TRACE_DATA_2

TRACE_DATA_3

TRACE_DATA_4

TRACE_DATA_5

TRACE_DATA_6

TRACE_DATA_7

Debug Trace Output - Data Line

P5

R5

P6

R7

P7

R8

P8

Open drain fail safe warm reset signal. Can be driven from PMIC for

diagnostic or can be used as status signal that the device is going

through reset.

WARM_RESET

IO

N9

7.2.2 Signal Descriptions - Analog

TYPE

INTERFACE

SIGNAL NAME

DESCRIPTION

Single ended transmitter1 o/p

BALL NO.

TX1

TX2

TX3

RX1

RX2

RX3

RX4

O

I

B4

B6

B8

M2

K2

H2

F2

R3

Transmitters

Single ended transmitter2 o/p

Single ended transmitter3 o/p

Single ended receiver1 i/p

Single ended receiver2 i/p

Single ended receiver3 i/p

Single ended receiver4 i/p

Power on reset for chip. Active low

I

Receivers

Reset

I

NRESET

I

In XTAL mode: Input for the reference crystal

In External clock mode: Single ended input

reference clock port

CLKP

I

B15

Reference

Oscillator

In XTAL mode: : Feedback drive for the reference

crystal

In External clock mode: Connect this port to ground

CLKM

C15

A14

Reference clock output from clocking subsystem

after cleanup PLL (1.4V output voltage swing).

Reference clock

Bandgap voltage

OSC_CLKOUT

O

VBGAP

VDDIN

Device's Band Gap Reference Output

B10

H15, N11, P15, R6

G15

Power 1.2V digital power supply

VIN_SRAM

VNWA

Power 1.2V power rail for internal SRAM

Power 1.2V power rail for SRAM array back bias

P14

I/O Supply (3.3V or 1.8V): All CMOS I/Os would

operate on this supply

VIOIN

Power

R10, F15

Power supply

VIOIN_18

VIN_18CLK

VIOIN_18DIFF

VPP

Power 1.8V supply for CMOS IO

Power 1.8V supply for clock module

Power 1.8V supply for LVDS port

Power Voltage supply for fuse chain

R9

B11

D15

L13

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BALL NO.

ZHCSJ79C –DECEMBER 2018 –REVISED JANUARY 2022

TYPE

INTERFACE

SIGNAL NAME

VIN_13RF1

DESCRIPTION

1.3V Analog and RF supply,VIN_13RF1 and

VIN_13RF2 could be shorted on the board

Power

G5, H5, J5

VIN_13RF2

VIN_18BB

VIN_18VCO

Power 1.3V Analog and RF supply

Power 1.8V Analog base band power supply

Power 1.8V RF VCO supply

C2,D2

K5, F5

B12

L5, L6, L8, L10, K7,

K8, K9, K10, K11,

J6, J7, J8, J10, H7,

H9, H11, G6, G7,

G8, G10, F9, F11,

E5, E6, E8, E10,

E11, R15

VSS

Ground Digital ground

Power supply

A1, A3, A5, A7,

A15, B1, B3, B5,

B7, C1, C3, C4, C5,

C6, C7, E1, E2, E3,

F3, G1, G2, G3, H3,

J1, J2, J3, K3, L1,

L2, L3, M3, N1, N2,

N3, R1, A13,

VSSA

Ground Analog ground

C8,A9, B9, C9, B14,

C14

VOUT_14APLL

O

Internal LDO output

A10

B13

VOUT_14SYNTH

O

When internal PA LDO is used this pin provides the

output voltage of the LDO. When the internal PA

Internal LDO output/

inputs

VOUT_PA

IO

LDO is bypassed and disabled 1V supply should be A2, B2

fed on this pin. This is mandatory in 3TX

simultaneous use case.

Analog Test1 / ADC1

Analog Test2 / ADC2

Analog Test3 / ADC3

Analog Test4 / ADC4

ANAMUX / ADC5

IO

ADC Channel 1⁽¹⁾

ADC Channel 2⁽¹⁾

ADC Channel 3⁽¹⁾

ADC Channel 4⁽¹⁾

ADC Channel 5⁽¹⁾

ADC Channel 6⁽¹⁾

P1

Test and Debug

output for pre-

production phase.

Can be pinned out

on production

hardware for field

debug

P2

P3

R2

C13

D14

VSENSE / ADC6

(1) For details, see 节9.4.1.

16

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8 Specifications

8.1 Absolute Maximum Ratings

PARAMETERS^{(1) (2)}

1.2 V digital power supply

MIN

–0.5

MAX

1.4

UNIT

VDDIN

V

VIN_SRAM

VNWA

1.2 V power rail for internal SRAM

1.4

1.2 V power rail for SRAM array back bias

1.4

I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this

supply.

VIOIN

3.8

V

–0.5

VIOIN_18

1.8 V supply for CMOS IO

1.8 V supply for clock module

1.8 V supply for LVDS port

2

V

–0.5

VIN_18CLK

VIOIN_18DIFF

VIN_13RF1

VIN_13RF2

VIN_13RF1

1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could

be shorted on the board.

1.45

V

–0.5

1-V Internal LDO bypass mode. Device supports mode where

external Power Management block can supply 1 V on

VIN_13RF1 and VIN_13RF2 rails. In this configuration, the

internal LDO of the device would be kept bypassed.

1.4

V

–0.5

VIN_13RF2

VIN_18BB

VIN_18VCO supply

RX1-4

1.8-V Analog baseband power supply

1.8-V RF VCO supply

2

V

–0.5

2

V

Externally applied power on RF inputs

Externally applied power on RF outputs⁽³⁾

Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)

10

dBm

TX1-3

VIOIN + 0.3

VIOIN + 20% up to

–0.3V

Input and output

voltage range

V

Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V

(Transient Overshoot/Undershoot) or external oscillator input

20% of signal period

CLKP, CLKM

Clamp current

Input ports for reference crystal

2

V

–0.5

Input or Output Voltages 0.3 V above or below their respective

power rails. Limit clamp current that flows through the internal

diode protection cells of the I/O.

20

mA

–20

T_J

Operating junction temperature range

125

150

°C

–40

–55

T_STG

Storage temperature range after soldered onto PC board

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

(3) This value is for an externally applied signal level on the TX. Additionally, a reflection coefficient up to Gamma = 1 can be applied on

the TX output.

8.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) Corner pins are rated as ±750 V

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8.3 Power-On Hours (POH)

JUNCTION

OPERATING

TEMPERATURE (T_j)

NOMINAL CVDD VOLTAGE (V)

POWER-ON HOURS [POH] (HOURS)

CONDITION

(1) (2)

600 (6%)

2000 (20%)

6500 (65%)

900 (9%)

–40°C

75°C

100% duty cycle

95°C

1.2

125°C

(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard

terms and conditions for TI semiconductor products.

(2) The specified POH are applicable with max Tx output power settings using the default firmware gain tables. The specified POH would

not be applicable, if the Tx gain table is overwritten using an API.

8.4 Recommended Operating Conditions

MIN

1.14

3.135

1.71

NOM

1.2

3.3

1.8

MAX

1.32

3.465

1.89

1.9

UNIT

VDDIN

1.2 V digital power supply

V

VIN_SRAM

VNWA

1.2 V power rail for internal SRAM

1.2 V power rail for SRAM array back bias

I/O supply (3.3 V or 1.8 V):

All CMOS I/Os would operate on this supply.

VIOIN

V

VIOIN_18

1.8 V supply for CMOS IO

1.8 V supply for clock module

1.8 V supply for LVDS port

V

VIN_18CLK

VIOIN_18DIFF

VIN_13RF1

VIN_13RF2

1.9

1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2

could be shorted on the board

1.23

1.3

1.36

V

VIN_13RF1

(1-V Internal LDO

bypass mode)

0.95

1

1.05

V

VIN_13RF2

(1-V Internal LDO

bypass mode)

VIN18BB

1.8-V Analog baseband power supply

1.8V RF VCO supply

1.71

1.17

2.25

1.8

1.9

V

VIN_18VCO

Voltage Input High (1.8 V mode)

Voltage Input High (3.3 V mode)

Voltage Input Low (1.8 V mode)

Voltage Input Low (3.3 V mode)

High-level output threshold (I_OH= 6 mA)

Low-level output threshold (I_OL= 6 mA)

V_IL(1.8V Mode)

V_IH

V_IL

V

0.3*VIOIN

0.62

V_OH

V_OL

mV

VIOIN –450

450

0.2

V_IH(1.8V Mode)

0.96

1.57

NRESET

SOP[2:0]

V

V_IL(3.3V Mode)

0.3

V_IH(3.3V Mode)

26

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8.5 Power Supply Specifications

表8-1 describes the four rails from an external power supply block of the AWR1843 device.

表8-1. Power Supply Rails Characteristics

SUPPLY

DEVICE BLOCKS POWERED FROM THE SUPPLY

RELEVANT IOS IN THE DEVICE

Input: VIN_18VCO, VIN18CLK, VIN_18BB,

VIOIN_18DIFF, VIOIN_18

LDO Output: VOUT_14SYNTH, VOUT_14APLL

Synthesizer and APLL VCOs, crystal oscillator, IF

Amplifier stages, ADC, LVDS

1.8 V

1.3 V (or 1 V in internal

LDO bypass mode)⁽¹⁾

Power Amplifier, Low Noise Amplifier, Mixers and LO

Distribution

Input: VIN_13RF2, VIN_13RF1

LDO Output: VOUT_PA

3.3 V (or 1.8 V for 1.8 V

I/O mode)

Digital I/Os

Input VIOIN

1.2 V

Core Digital and SRAMs

Input: VDDIN, VIN_SRAM

(1) Three simultaneous transmitter operation is supported only in 1-V LDO bypass and PA LDO disable mode. In this mode 1V supply

needs to be fed on the VOUT PA pin.

The 1.3-V (1.0 V) and 1.8-V power supply ripple specifications mentioned in 表 8-2 are defined to meet a target

spur level of –105 dBc (RF Pin = –15 dBm) at the RX. The spur and ripple levels have a dB-to-dB relationship,

for example, a 1-dB increase in supply ripple leads to a ~1 dB increase in spur level. Values quoted are rms

levels for a sinusoidal input applied at the specified frequency.

表8-2. Ripple Specifications

RF RAIL

VCO/IF RAIL

FREQUENCY (kHz)

1.0 V (INTERNAL LDO BYPASS)

1.3 V (µV_RMS

)

1.8 V (µV_RMS)

(µV_RMS

)

137.5

275

7

5

648

76

22

4

83

21

11

6

550

3

1100

2200

4400

6600

2

11

13

22

82

93

117

13

19

29

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8.6 Power Consumption Summary

表8-3 and 表8-4 summarize the power consumption at the power terminals.

表8-3. Maximum Current Ratings at Power Terminals

PARAMETER

SUPPLY NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

Total current drawn by all

nodes driven by 1.2V rail

VDDIN, VIN_SRAM, VNWA

1000

Total current drawn by all

nodes driven by 1.3V or

1.0V rail (2TX, 4 RX

simultaneously)⁽²⁾

VIN_13RF1, VIN_13RF2

2000

Current consumption⁽¹⁾

mA

VIOIN_18, VIN_18CLK,

VIOIN_18DIFF, VIN_18BB,

VIN_18VCO

Total current drawn by all

nodes driven by 1.8V rail

850

Total current drawn by all

nodes driven by 3.3V

rail⁽³⁾

VIOIN

50

(1) The specified current values are at typical supply voltage level.

(2) Simultaneous 3 Transmitter operation is supported only with 1-V LDO bypass and PA LDO disable mode. In this mode, the 1-V supply

needs to be fed on the VOUT_PA pin. In this case, the peak 1-V supply current goes up to 2500 mA. To enable the LDO bypass mode,

see the Interface Control document in the mmWave Device Firmware Package.

(3) The exact VIOIN current depends on the peripherals used and their frequency of operation.

表8-4. Average Power Consumption at Power Terminals

PARAMETER

CONDITION

DESCRIPTION

MIN

TYP MAX UNIT

1TX, 4RX

2TX, 4RX

Use Case: Regular mode, 6.4

MSps complex transceiver, 25-

ms frame time, 128 chirps, 128

samples/chirp, 5-µs idle time

(25% duty cycle), 3us ADC

start time and excess ramp

time, DSP and HWA active

1.29

1.36

25% Duty

Cycle

3TX, 4RX

1.43

1.0-V internal

LDO bypass

mode

Average power

consumption

W

1TX, 4RX

2TX, 4RX

Use Case: Regular mode, 6.4

MSps complex transceiver, 25-

ms frame time, 256 chirps, 128

samples/chirp, 5-µs idle time

(50% duty cycle), 3us ADC

start time and excess ramp

time, DSP and HWA active

1.82

1.96

50% Duty

Cycle

3TX, 4RX

2.08

28

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8.7 RF Specification

over recommended operating conditions and with run time calibrations enabled (unless otherwise noted)

PARAMETER

MIN

TYP

14

15

–8

48

24

2

MAX UNIT

76 to 77 GHz

77 to 81 GHz

Noise figure⁽²⁾

dB

1-dB compression point (Out Of Band / Specified at 10 kHz)⁽¹⁾

Maximum gain

dBm

dB

Gain range

dB

Gain step size

dB

Image Rejection Ratio (IMRR)

IF bandwidth⁽³⁾

30

dB

10 MHz

25 Msps

12.5 Msps

Bits

ADC sampling rate (real/complex 2x)

ADC sampling rate (complex 1x)

ADC resolution

Receiver

12

<–10

±0.5

±3

Return loss (S11)

dB

Gain mismatch variation (over temperature)

Phase mismatch variation (over temperature)

RX gain = 30dB

dB

°

IF = 1.5, 2 MHz at

–12 dBFS

In-band IIP2

16

24

dBm

RX gain = 24dB

IF = 10 kHz at -10dBm,

1.9 MHz at -30 dBm

Out-of-band IIP2

Idle Channel Spurs

Output power

dBFS

dBm

–90

12

Transmitter

Amplitude noise

Frequency range

Ramp rate

dBc/Hz

–145

76

81 GHz

100 MHz/µs

Clock

subsystem

76 to 77 GHz

77 to 81 GHz

–95

–93

Phase noise at 1-MHz offset

dBc/Hz

(1) 1-dB Compression Point (Out Of Band) is measured by feed a Continuous wave Tone (10 kHz) well below the lowest HPF cut-off

frequency.

(2) Specification is quoted for complex 1x mode.

(3) The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set

of available HPF corners is summarized as follows:

Available HPF Corner Frequencies (kHz)

HPF1

HPF2

175, 235, 350, 700

350, 700, 1400, 2800

The filtering performed by the digital baseband chain is targeted to provide:

•

Less than ±0.5 dB pass-band ripple/droop, and

Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.

图8-1 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain programmed.

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18

16

14

12

10

8

-18

-24

-30

-36

-42

-48

NF (dB)

In-band P1DB (dBm)

30

32

34

36

38 40

RX Gain (dB)

42

44

46

48

图8-1. Noise Figure, In-band P1dB vs Receiver Gain

8.8 CPU Specifications

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

600

32

MAX UNIT

Clock Speed

DSP

MHz

KB

L1 Code Memory

Subsystem

(C674

Family)

L1 Data Memory

32

KB

L2 Memory

256

200

512

192

KB

Clock Speed

MHz

KB

Main

Subsystem

(R4F Family)

Tightly Coupled Memory - A (Program)

Tightly Coupled Memory - B (Data)

KB

Shared

Memory

Shared L3 Memory

1024

KB

8.9 Thermal Resistance Characteristics for FCBGA Package [ABL0161]

THERMAL METRICS⁽¹⁾

°C/W^{(2) (3)}

4.2

Junction-to-case

RΘ_JC

RΘ_JB

RΘ_JA

RΘ_JMA

Psi_JT

5.7

Junction-to-board

20.9

Junction-to-free air

Junction-to-moving air

Junction-to-package top

Junction-to-board

14.5 ⁽⁴⁾

0.38

Psi_JB

5.6

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) °C/W = degrees Celsius per watt.

(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/

JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(4) Air flow = 1 m/s

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8.10 Timing and Switching Characteristics

8.10.1 Power Supply Sequencing and Reset Timing

The AWR1843 device expects all external voltage rails and SOP lines to be stable before reset is deasserted. 图

8-2 describes the device wake-up sequence.

SOP

Setup

Time

SOP

Hold time to

nRESET

DC power

Stable before

nRESET

MSS

BOOT

START

nRESET

ASSERT

tPGDEL

DC

Power

notOK

DC

Power

OK

QSPI

READ

release

VDDIN,

VIN_SRAM

VNWA

VIOIN_18

VIN18_CLK

VIOIN_18DIFF

VIN18_BB

VIN_13RF1

VIN_13RF2

VIOIN

SOP IO

Reuse

SOP IO‘s can be used as functional IO‘s

SOP[2.1.0]

nRESET

WARMRESET

OUTPUT

VBGAP

OUTPUT

CLKP, CLKM

Using Crystal

MCUCLK

OUTPUT (1)

QSPI_CS

OUTPUT

8 ms (XTAL Mode)

850 µs (REFCLK Mode)

A. MCU_CLK_OUT in autonomous mode, where AWR1843 application is booted from the serial flash, MCU_CLK_OUT is not enabled by

default by the device bootloader.

图8-2. Device Wake-up Sequence

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8.10.2 Input Clocks and Oscillators

8.10.2.1 Clock Specifications

The AWR1843 requires external clock source (that is, a 40-MHz crystal) for initial boot and as a reference for an

internal APLL hosted in the device. An external crystal is connected to the device pins. 图 8-3 shows the crystal

implementation.

C_f1

CLKP

C_p

40 MHz

CLKM

C_f2

图8-3. Crystal Implementation

备注

The load capacitors, C_f1and C_f2in 图 8-3, should be chosen such that 方程式 1 is satisfied. C_Lin the

equation is the load specified by the crystal manufacturer. All discrete components used to implement

the oscillator circuit should be placed as close as possible to the associated oscillator CLKP and

CLKM pins.

C _f2

C_L= C _f1

´

+C_P

C

_f1+C _f2

(1)

表8-5 lists the electrical characteristics of the clock crystal.

表8-5. Crystal Electrical Characteristics (Oscillator Mode)

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

MHz

pF

f_P

Parallel resonance crystal frequency

40

C_L

Crystal load capacitance

Crystal ESR

5

8

12

ESR

50

Ω

Temperature range Expected temperature range of operation

125

°C

–40

Frequency

Crystal frequency tolerance^{(1) (2)}

tolerance

200

ppm

µW

–200

Drive level

50

(1) The crystal manufacturer's specification must satisfy this requirement.

(2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.

In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only; CLKM

is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally. 表 8-6 lists

the electrical characteristics of the external clock signal.

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表8-6. External Clock Mode Specifications

SPECIFICATION

PARAMETER

UNIT

MIN

TYP

MAX

Frequency

40

MHz

mV (pp)

dBc/Hz

%

AC-Amplitude

700

1200

–132

–143

–152

–153

65

Phase Noise at 1 kHz

Phase Noise at 10 kHz

Phase Noise at 100 kHz

Phase Noise at 1 MHz

Duty Cycle

Input Clock:

External AC-coupled sine wave or DC-

coupled square wave

Phase Noise referred to 40 MHz

35

Freq Tolerance

100

ppm

–100

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8.10.3 Multibuffered / Standard Serial Peripheral Interface (MibSPI)

8.10.3.1 Peripheral Description

The SPI uses a MibSPI Protocol by TI.

The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of

programmed length (2 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The

MibSPI/SPI is normally used for communication between the microcontroller and external peripherals or another

microcontroller.

Standard and MibSPI modules have the following features:

• 16-bit shift register

• Receive buffer register

• 8-bit baud clock generator

• SPICLK can be internally-generated (controller mode) or received from an external clock source

(peripheral mode)

• Each word transferred can have a unique format.

• SPI I/Os not used in the communication can be used as digital input/output signals

8.10.3.2 MibSPI Transmit and Receive RAM Organization

The Multibuffer RAM is comprised of 256 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a 16-bit

transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer RAM can be

partitioned into multiple transfer group with variable number of buffers each.

节8.10.3.2.2 and 节8.10.3.2.3 assume the operating conditions stated in 节8.10.3.2.1.

8.10.3.2.1 SPI Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOADOutput load capacitance

2

15

pF

8.10.3.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output,

SPISIMO = output, and SPISOMI = input)^{(1) (2) (3)}

NO.

PARAMETER

Cycle time, SPICLK⁽⁴⁾

MIN

25

TYP

MAX UNIT

1

t_c(SPC)M

256_tc(VCLK)

0.5t_c(SPC)M+ 4

ns

t_w(SPCH)M

t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

0.5t_c(SPC)M–4

0.5t_c(SPC)M–3

2⁽⁴⁾

ns

3⁽⁴⁾

ns

t_d(SPCH-

Delay time, SPISIMO valid before SPICLK low, (clock

polarity = 0)

SIMO)M

4⁽⁴⁾

t_d(SPCL-

Delay time, SPISIMO valid before SPICLK high, (clock

polarity = 1)

0.5t_c(SPC)M–3

SIMO)M

t_v(SPCL-

Valid time, SPISIMO data valid after SPICLK low, (clock

polarity = 0)

0.5t_c(SPC)M

–

10.5

SIMO)M

5⁽⁴⁾

ns

t_v(SPCH-

Valid time, SPISIMO data valid after SPICLK high, (clock

polarity = 1)

0.5t_c(SPC)M

–

10.5

SIMO)M

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PARAMETER

MIN

TYP

MAX UNIT

(C2TDELAY+2)

CSHOLD = 0

CSHOLD = 1

CSHOLD = 0

CSHOLD = 1

(C2TDELAY+2)*

Setup time CS active until SPICLK

high

(clock polarity = 0)

* t_c(VCLK)+ 7

t

_c(VCLK)–7.5

(C2TDELAY +3)

* t_c(VCLK)–7.5

(C2TDELAY+3)

* t_c(VCLK)+ 7

6⁽⁵⁾

t_C2TDELAY

ns

(C2TDELAY+2)*

(C2TDELAY+2)

* t_c(VCLK)+ 7

t

_c(VCLK)–7.5

Setup time CS active until SPICLK low

(clock polarity = 1)

(C2TDELAY +3)

* t_c(VCLK)–7.5

(C2TDELAY+3)

* t_c(VCLK)+ 7

Hold time, SPICLK low until CS inactive (clock polarity = 0)

0.5*t_c(SPC)M

(T2CDELAY +

1) *t_c(VCLK)–7

+

0.5*t_c(SPC)M

(T2CDELAY +

1) * t_c(VCLK)

7.5

+

7⁽⁵⁾

t_T2CDELAY

ns

Hold time, SPICLK high until CS inactive (clock polarity = 1)

0.5*t_c(SPC)M

+

0.5*t_c(SPC)M

+

(T2CDELAY +

1) * t_c(VCLK)

+

1) *t_c(VCLK)–7

7.5

t_su(SOMI-

Setup time, SPISOMI before SPICLK low

(clock polarity = 0)

5

3

SPCL)M

8⁽⁴⁾

ns

t_su(SOMI-

Setup time, SPISOMI before SPICLK high

(clock polarity = 1)

SPCH)M

t_h(SPCL-

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 0)

SOMI)M

9⁽⁴⁾

t_h(SPCH-

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 1)

SOMI)M

(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared (where x= 0 or 1).

(2) t_{c(MSS_VCLK)}= main subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, see the Technical Reference Manual.

(3) When the SPI is in Controller mode, the following must be true: For PS values from 1 to 255: t_c(SPC)M≥(PS +1)t_{c(MSS_VCLK)}≥25ns,

where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: t_c(SPC)M= 2t_{c(MSS_VCLK)}≥25ns.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

11

SPICLK

(clock polarity = 0)

2

1

3

SPICLK

(clock polarity = 1

4

5

Master Out Data Is Valid

SPISIMO

1

8

9

Master In Data

Must Be Valid

SPISOMI

图8-4. SPI Controller Mode External Timing (CLOCK PHASE = 0)

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Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

Master Out Data Is Valid

6

7

SPICSn

图8-5. SPI Controller Mode Chip Select Timing (CLOCK PHASE = 0)

8.10.3.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output,

SPISIMO = output, and SPISOMI = input)^{(1) (2) (3)}

NO.

PARAMETER

Cycle time, SPICLK⁽⁴⁾

MIN

TYP

MAX UNIT

1

t_c(SPC)M

25

256t_c(VCLK)

ns

t_w(SPCH)M

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

0.5t_c(SPC)M+ 4

0.5t_c(SPC)M

–

4

2⁽⁴⁾

3⁽⁴⁾

4⁽⁴⁾

5⁽⁴⁾

ns

t_w(SPCL)M

t_w(SPCH)M

0.5t_c(SPC)M

–

4

–

4

ns

–

4

t_d(SPCH-

Delay time, SPISIMO valid before SPICLK low, (clock polarity

= 0)

–

3

SIMO)M

t_d(SPCL-

Delay time, SPISIMO valid before SPICLK high, (clock

polarity = 1)

–

3

SIMO)M

t_v(SPCL-

Valid time, SPISIMO data valid after SPICLK low, (clock

polarity = 0)

–

10.5

SIMO)M

t_v(SPCH-

Valid time, SPISIMO data valid after SPICLK high, (clock

polarity = 1)

0.5t_c(SPC)M

–

10.5

SIMO)M

t_C2TDELAY

Setup time CS active until SPICLK

high

(clock polarity = 0)

CSHOLD = 0

CSHOLD = 1

CSHOLD = 0

CSHOLD = 1

0.5*t_c(SPC)M

+

(C2TDELAY +

2)*t_c(VCLK)–7

0.5*t_c(SPC)M

(C2TDELAY+2

) * t_c(VCLK)

7.5

+

0.5*t_c(SPC)M

(C2TDELAY +

2)*t_c(VCLK)–7

+

0.5*t_c(SPC)M

+

(C2TDELAY+2

) * t_c(VCLK)

+

7.5

6⁽⁵⁾

ns

0.5*t_c(SPC)M

(C2TDELAY+2

)*t_c(VCLK)–7

+

0.5*t_c(SPC)M

+

(C2TDELAY+2

) * t_c(VCLK)

+

Setup time CS active until SPICLK

low

(clock polarity = 1)

7.5

0.5*t_c(SPC)M

(C2TDELAY+3

+

0.5*t_c(SPC)M

+

(C2TDELAY+3

) * t_c(VCLK)

+

)*t_c(VCLK)–7

7.5

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PARAMETER

MIN

TYP

MAX UNIT

(T2CDELAY +

Hold time, SPICLK low until CS inactive (clock polarity = 0)

(T2CDELAY +

1) *t_c(VCLK)+ 7

1) *t_c(VCLK)

–

7.5

7⁽⁵⁾

t_T2CDELAY

ns

Hold time, SPICLK high until CS inactive (clock polarity = 1)

(T2CDELAY +

1) *t_c(VCLK)+ 7

1) *t_c(VCLK)

–

7.5

t_su(SOMI-

Setup time, SPISOMI before SPICLK low

(clock polarity = 0)

5

SPCL)M

8⁽⁴⁾

ns

t_su(SOMI-

Setup time, SPISOMI before SPICLK high

(clock polarity = 1)

5

3

SPCH)M

t_h(SPCL-

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 0)

SOMI)M

9⁽⁴⁾

t_h(SPCH-

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 1)

SOMI)M

(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set ( where x = 0 or 1 ).

(2) t_{c(MSS_VCLK)}= main subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, see the Technical Reference Manual.

(3) When the SPI is in Controller mode, the following must be true: For PS values from 1 to 255: t_c(SPC)M≥(PS +1)t_{c(MSS_VCLK)}≥25 ns,

where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: t_c(SPC)M= 2t_{c(MSS_VCLK)}≥25 ns.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

Master Out Data Is Valid

Data Valid

SPISIMO

8

9

Master In Data

Must Be Valid

SPISOMI

图8-6. SPI Controller Mode External Timing (CLOCK PHASE = 1)

Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

SPICSn

Master Out Data Is Valid

6

7

图8-7. SPI Controller Mode Chip Select Timing (CLOCK PHASE = 1)

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8.10.3.3 SPI Peripheral Mode I/O Timings

8.10.3.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input,

and SPISOMI = output)^{(1) (2) (3)}

NO.

PARAMETER

MIN

25

TYP

MAX

UNIT

1

t_c(SPC)S

Cycle time, SPICLK⁽⁴⁾

ns

t_w(SPCH)S

t_w(SPCL)S

t_w(SPCH)S

t_{d(SPCH-SOMI)S}

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

10

2⁽⁵⁾

ns

10

3⁽⁵⁾

10

Delay time, SPISOMI valid after SPICLK high

(clock polarity = 0)

10

4⁽⁵⁾

ns

t_{d(SPCL-SOMI)S}

t_{h(SPCH-SOMI)S}

t_{h(SPCL-SOMI)S}

t_{d(SPCH-SOMI)S}

Delay time, SPISOMI valid after SPICLK low (clock

polarity = 1)

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 0)

2

5⁽⁵⁾

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 1)

Delay time, SPISOMI valid after SPICLK high

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)

10

4⁽⁵⁾

5⁽⁵⁾

6⁽⁵⁾

7⁽⁵⁾

ns

t_{d(SPCL-SOMI)S}

t_{h(SPCH-SOMI)S}

t_{h(SPCL-SOMI)S}

Delay time, SPISOMI valid after SPICLK low (clock

polarity = 1; clock phase = 0) OR (clock polarity =

0; clock phase = 1)

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)

2

3

1

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 1; clock phase = 0) OR (clock

polarity = 0; clock phase = 1)

Setup time, SPISIMO before SPICLK low (clock

polarity = 0; clock phase = 0) OR (clock polarity =

1; clock phase = 1)

t_{su(SIMO-SPCL)S}

Setup time, SPISIMO before SPICLK high (clock

t_{su(SIMO-SPCH)S}polarity = 1; clock phase = 0) OR (clock polarity =

0; clock phase = 1)

Hold time, SPISIMO data valid after SPICLK low

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)

t_{h(SPCL-SIMO)S}

Hold time, SPISIMO data valid after SPICLK high

(clock polarity = 1; clock phase = 0) OR (clock

polarity = 0; clock phase = 1)

t_{h(SPCL-SIMO)S}

(1) The MASTER bit (SPIGCRx.0) is cleared ( where x = 0 or 1 ).

(2) The CLOCK PHASE bit (SPIFMTx.16) is either cleared or set for CLOCK PHASE = 0 or CLOCK PHASE = 1 respectively.

(3) t_{c(MSS_VCLK)}= main subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, see the Technical Reference Manual.

(4) When the SPI is in peripheral mode, the following must be true: For PS values from 1 to 255: t_c(SPC)S≥(PS +1)t_{c(MSS_VCLK)}≥25 ns,

where PS is the prescale value set in the SPIFMTx.[15:8] register bits.For PS values of 0: t_c(SPC)S= 2t_{c(MSS_VCLK)}≥25 ns.

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

5

4

SPISOMI

SPISOMI Data Is Valid

6

7

SPISIMO Data

Must Be Valid

SPISIMO

图8-8. SPI peripheral Mode External Timing (CLOCK PHASE = 0)

1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

SPISOMI

SPISOMI Data Is Valid

6

7

SPISIMO Data

Must Be Valid

SPISIMO

图8-9. SPI peripheral Mode External Timing (CLOCK PHASE = 1)

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8.10.3.4 Typical Interface Protocol Diagram (Peripheral Mode)

1. Host should ensure that there is a delay of two SPI clocks between CS going low and start of SPI clock.

2. Host should ensure that CS is toggled for every 16 bits of transfer through SPI.

图8-10 shows the SPI communication timing of the typical interface protocol.

2 SPI clocks

CS

CLK

0x4321

0x1234

CRC

0x5678

0x8765

MOSI

MISO

IRQ

0xDCBA

0xABCD

CRC

16 bytes

图8-10. SPI Communication

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8.10.4 LVDS Interface Configuration

The supported AWR1843 LVDS lane configuration is two Data lanes (LVDS_TXP/M), one Bit Clock lane

(LVDS_CLKP/M) and one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface is used for debugging. The

LVDS interface supports the following data rates:

• 900 Mbps (450 MHz DDR Clock)

• 600 Mbps (300 MHz DDR Clock)

• 450 Mbps (225 MHz DDR Clock)

• 400 Mbps (200 MHz DDR Clock)

• 300 Mbps (150 MHz DDR Clock)

• 225 Mbps (112.5 MHz DDR Clock)

• 150 Mbps (75 MHz DDR Clock)

Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data.

LVDS_TXP/M

LVDS_FRCLKP/M

Data bitwidth

LVDS_CLKP/M

图8-11. LVDS Interface Lane Configuration And Relative Timings

8.10.4.1 LVDS Interface Timings

表8-7. LVDS Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Duty Cycle Requirements

max 1 pF lumped capacitive load on

LVDS lanes

48%

52%

Output Differential Voltage

peak-to-peak single-ended with 100 Ω

resistive load between differential pairs

250

450

mV

Output Offset Voltage

Trise and Tfall

1125

1275

mV

ps

20%-80%, 900 Mbps

900 Mbps

330

80

Jitter (pk-pk)

ps

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Trise

LVDS_CLK

Clock Jitter = 6sigma

LVDS_TXP/M

LVDS_FRCLKP/M

1100 ps

图8-12. Timing Parameters

8.10.5 General-Purpose Input/Output

节8.10.5.1 lists the switching characteristics of output timing relative to load capacitance.

8.10.5.1 Switching Characteristics for Output Timing versus Load Capacitance (C_L)

PARAMETER^{(1) (2)}

TEST CONDITIONS

C_L= 20 pF

VIOIN = 1.8V

VIOIN = 3.3V

UNIT

2.8

6.4

9.4

2.8

6.4

9.4

3.3

6.7

9.6

3.1

6.6

9.6

3.0

6.9

10.2

2.8

6.6

9.8

3.3

7.2

10.5

3.1

6.6

9.6

t_r

t_f

t_r

t_f

Max rise time

C_L= 50 pF

ns

C_L= 75 pF

Slew control = 0

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

Max fall time

Max rise time

Max fall time

ns

Slew control = 1

(1) Slew control, which is configured by PADxx_CFG_REG, changes behavior of the output driver (faster or slower output slew rate).

(2) The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.

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8.10.6 Controller Area Network Interface (DCAN)

The DCAN supports the CAN 2.0B protocol standard and uses a serial, multi-commander communication

protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps.

The DCAN is ideal for applications operating in noisy and harsh environments that require reliable serial

communication or multiplexed wiring.

The DCAN has the following features:

• Supports CAN protocol version 2.0 part A, B

• Bit rates up to 1 Mbps

• Configurable Message objects

• Individual identifier masks for each message object

• Programmable FIFO mode for message objects

• Suspend mode for debug support

• Programmable loop-back modes for self-test operation

• Direct access to Message RAM in test mode

• Supports two interrupt lines - Level 0 and Level 1

• Automatic Message RAM initialization

8.10.6.1 Dynamic Characteristics for the DCANx TX and RX Pins

PARAMETER

MIN

TYP

MAX

15

UNIT

ns

t_{d(CAN_tx)}

t_{d(CAN_rx)}

Delay time, transmit shift register to CAN_tx pin⁽¹⁾

Delay time, CAN_rx pin to receive shift register⁽¹⁾

10

ns

(1) These values do not include rise/fall times of the output buffer.

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8.10.7 Controller Area Network - Flexible Data-rate (CAN-FD)

The CAN-FD module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications.

CAN FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD

devices can coexist on the same network without any conflict.

The CAN-FD has the following features:

• Conforms with CAN Protocol 2.0 A, B and ISO 11898-1

• Full CAN FD support (up to 64 data bytes per frame)

• AUTOSAR and SAE J1939 support

• Up to 32 dedicated Transmit Buffers

• Configurable Transmit FIFO, up to 32 elements

• Configurable Transmit Queue, up to 32 elements

• Configurable Transmit Event FIFO, up to 32 elements

• Up to 64 dedicated Receive Buffers

• Two configurable Receive FIFOs, up to 64 elements each

• Up to 128 11-bit filter elements

• Internal Loopback mode for self-test

• Mask-able interrupts, two interrupt lines

• Two clock domains (CAN clock / Host clock)

• Parity / ECC support - Message RAM single error correction and double error detection (SECDED)

mechanism

• Full Message Memory capacity (4352 words).

8.10.7.1 Dynamic Characteristics for the CANx TX and RX Pins

PARAMETER

MIN

TYP

MAX

UNIT

t_{d(CAN_FD_tx)}

t_{d(CAN_FD_rx)}

Delay time, transmit shift register to CAN_FD_tx

pin⁽¹⁾

15

ns

Delay time, CAN_FD_rx pin to receive shift

register⁽¹⁾

10

ns

(1) These values do not include rise/fall times of the output buffer.

8.10.8 Serial Communication Interface (SCI)

The SCI has the following features:

• Standard universal asynchronous receiver-transmitter (UART) communication

• Standard non-return to zero (NRZ) format

• Double-buffered receive and transmit functions

• Asynchronous or iso-synchronous communication modes with no CLK pin

• Capability to use Direct Memory Access (DMA) for transmit and receive data

• Two external pins: RS232_RX and RS232_TX

8.10.8.1 SCI Timing Requirements

MIN

TYP

921.6

MAX

UNIT

f(baud)

Supported baud rate at 20 pF

kHz

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8.10.9 Inter-Integrated Circuit Interface (I2C)

The inter-integrated circuit (I2C) module is a multicontroller communication module providing an interface

between devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an

I²C-bus™. This module will support any target or controller I2C compatible device.

The I2C has the following features:

• Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number 9398

393 40011)

– Bit/Byte format transfer

– 7-bit and 10-bit device addressing modes

– General call

– START byte

– Multi-controller transmitter/ target receiver mode

– Multi-controller receiver/ target transmitter mode

– Combined controller transmit/receive and receive/transmit mode

– Transfer rates of 100 kbps up to 400 kbps (Phillips fast-mode rate)

• Free data format

• Two DMA events (transmit and receive)

• DMA event enable/disable capability

• Module enable/disable capability

• The SDA and SCL are optionally configurable as general purpose I/O

• Slew rate control of the outputs

• Open drain control of the outputs

• Programmable pullup/pulldown capability on the inputs

• Supports Ignore NACK mode

备注

This I2C module does not support:

• High-speed (HS) mode

• C-bus compatibility mode

• The combined format in 10-bit address mode (the I2C sends the target address second byte every

time it sends the target address first byte)

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8.10.9.1 I2C Timing Requirements⁽¹⁾

STANDARD MODE

FAST MODE

UNIT

MIN

10

MAX

MIN

2.5

MAX

t_c(SCL)

Cycle time, SCL

μs

t_{su(SCLH-SDAL)}

Setup time, SCL high before SDA low

(for a repeated START condition)

4.7

0.6

t_h(SCLL-SDAL)

Hold time, SCL low after SDA low

4

0.6

μs

(for a START and a repeated START condition)

t_w(SCLL)

Pulse duration, SCL low

4.7

4

1.3

0.6

100

0

μs

t_w(SCLH)

Pulse duration, SCL high

t_su(SDA-SCLH)

t_h(SCLL-SDA)

t_w(SDAH)

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low

250

0

3.45⁽¹⁾

0.9

Pulse duration, SDA high between STOP and START

conditions

4.7

1.3

t_{su(SCLH-SDAH)}

t_w(SP)

Setup time, SCL high before SDA high

(for STOP condition)

4

0.6

0

μs

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

50

ns

(2) (3)

C_b

400

pF

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the

SCL signal.

(3) C_b= total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.

SDA

t_w(SDAH)

t_su(SDA-SCLH)

t_w(SP)

t_w(SCLL)

t_r(SCL)

t_{su(SCLH-SDAH)}

t_w(SCLH)

SCL

t_c(SCL)

t_h(SCLL-SDAL)

t_f(SCL)

t_h(SCLL-SDAL)

t_{su(SCLH-SDAL)}

t_h(SDA-SCLL)

Stop

Start

Repeated Start

Stop

图8-13. I2C Timing Diagram

备注

• A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the

VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.

• The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW period

(tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a Standard-mode

I2C-bus system, but the requirement t_su(SDA-SCLH)≥250 ns must then be met. This will

automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a

device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA

line tr max + t_su(SDA-SCLH)

.

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8.10.10 Quad Serial Peripheral Interface (QSPI)

The quad serial peripheral interface (QSPI) module is a kind of SPI module that allows single, dual, or quad read

access to external SPI devices. This module has a memory mapped register interface, which provides a direct

interface for accessing data from external SPI devices and thus simplifying software requirements. The QSPI

works as a controller only. The QSPI in the device is primarily intended for fast booting from quad-SPI flash

memories.

The QSPI supports the following features:

• Programmable clock divider

• Six-pin interface

• Programmable length (from 1 to 128 bits) of the words transferred

• Programmable number (from 1 to 4096) of the words transferred

• Support for 3-, 4-, or 6-pin SPI interface

• Optional interrupt generation on word or frame (number of words) completion

• Programmable delay between chip select activation and output data from 0 to 3 QSPI clock cycles

节8.10.10.2 and 节8.10.10.3 assume the operating conditions stated in 节8.10.10.1.

8.10.10.1 QSPI Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOAD

Output load capacitance

2

15

pF

8.10.10.2 Timing Requirements for QSPI Input (Read) Timings^{(1) (2)}

MIN

7.3

TYP

MAX

UNIT

ns

t_su(D-SCLK)

t_h(SCLK-D)

t_su(D-SCLK)

t_h(SCLK-D)

Setup time, d[3:0] valid before falling sclk edge (Q12)

Hold time, d[3:0] valid after falling sclk edge (Q13)

Setup time, final d[3:0] bit valid before final falling sclk edge

Hold time, final d[3:0] bit valid after final falling sclk edge

1.5

ns

7.3 –P⁽³⁾

1.5 + P⁽³⁾

ns

(1) Clock Mode 0 (clk polarity = 0 ; clk phase = 0 ) is the mode of operation.

(2) The Device captures data on the falling clock edge in Clock Mode 0, as opposed to the traditional rising clock edge. Although non-

standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that

launch data on the falling edge in Clock Mode 0.

(3) P = SCLK period in ns.

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8.10.10.3 QSPI Switching Characteristics

NO.

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

PARAMETER

Cycle time, sclk

MIN

25

TYP

MAX

UNIT

ns

t_c(SCLK)

0.5*P –3⁽¹⁾

0.5*P –3

–M*P –1⁽²⁾

N*P –1⁽²⁾

–3.5

t_w(SCLKL)

Pulse duration, sclk low

ns

t_w(SCLKH)

Pulse duration, sclk high

ns

–M*P + 2.5⁽²⁾

N*P + 2.5⁽²⁾

7

t_d(CS-SCLK)

t_d(SCLK-CS)

t_d(SCLK-D1)

t_ena(CS-D1LZ)

t_dis(CS-D1Z)

t_d(SCLK-D1)

Delay time, sclk falling edge to cs active edge

Delay time, sclk falling edge to cs inactive edge

Delay time, sclk falling edge to d[0] transition

Enable time, cs active edge to d[0] driven (lo-z)

Disable time, cs active edge to d[0] tri-stated (hi-z)

ns

–P –4⁽²⁾

–P +1⁽²⁾

ns

Delay time, sclk first falling edge to first d[1] transition

(for PHA = 0 only)

ns

–3.5 –P⁽²⁾

7 –P⁽²⁾

Q9

(1) P = SCLK period in ns.

(2) M = QSPI_SPI_DC_REG.DDx + 1, N = 2

图8-14. QSPI Read (Clock Mode 0)

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PHA=0

cs

Q5

Q4

Q1

Q2

Q3

POL=0

sclk

Q8

Q6

Q7

Q9

Q6

Command

Bit n-1

Command

Bit n-2

Write Data

Bit 1

Write Data

Bit 0

d[0]

d[3:1]

SPRS85v_TIMING_OSPI1_04

图8-15. QSPI Write (Clock Mode 0)

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8.10.11 ETM Trace Interface

节8.10.11.2 and List item.referenceTitle assume the recommended operating conditions stated in 节8.10.11.1.

8.10.11.1 ETMTRACE Timing Conditions

MIN

TYP

MAX

UNIT

Output Conditions

C_LOAD

Output load capacitance

2

20

pF

8.10.11.2 ETM TRACE Switching Characteristics

NO.

1

PARAMETER

Cycle time, TRACECLK period

Pulse Duration, TRACECLK High

Pulse Duration, TRACECLK Low

Clock and data rise time

MIN

TYP

MAX

UNIT

ns

t_cyc(ETM)

t_h(ETM)

t_l(ETM)

20

9

2

ns

3

9

ns

4

t_r(ETM)

t_f(ETM)

3.3

7

ns

5

Clock and data fall time

ns

t_d(ETMTRACEDelay time, ETM trace clock high to ETM data valid

1

ns

6

7

CLKH-

ETMDATAV)

t_d(ETMTRACEDelay time, ETM trace clock low to ETM data valid

7

ns

CLKl-

ETMDATAV)

t_l(ETM)

t_h(ETM)

t_r(ETM)

t_f(ETM)

t_cyc(ETM)

图8-16. ETMTRACECLKOUT Timing

图8-17. ETMDATA Timing

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8.10.12 Data Modification Module (DMM)

A Data Modification Module (DMM) gives the ability to write external data into the device memory.

The DMM has the following features:

• Acts as a bus controller, thus enabling direct writes to the 4GB address space without CPU intervention

• Writes to memory locations specified in the received packet (leverages packets defined by trace mode of the

RAM trace port [RTP] module)

• Writes received data to consecutive addresses, which are specified by the DMM (leverages packets defined

by direct data mode of RTP module)

• Configurable port width (1, 2, 4, 8, 16 pins)

• Up to 65 Mbit/s pin data rate

8.10.12.1 DMM Timing Requirements

MIN

TYP

MAX

UNIT

ns

t_cyc(DMM)

t_R

Clock period

15.4

1

Clock rise time

3

ns

t_F

Clock fall time

1

ns

t_h(DMM)

t_l(DMM)

t_ssu(DMM)

t_sh(DMM)

t_dsu(DMM)

t_dh(DMM)

High pulse width

6

ns

Low pulse width

6

ns

SYNC active to clk falling edge setup time

DMM clk falling edge to SYNC deactive hold time

DATA to DMM clk falling edge setup time

DMM clk falling edge to DATA hold time

2

ns

3

ns

2

ns

3

ns

t_l(DMM)

t_h(DMM)

t_f

t_r

t_cyc(DMM)

图8-18. DMMCLK Timing

t_ssu(DMM)

t_sh(DMM)

DMMSYNC

DMMCLK

DMMDATA

t_dsu(DMM)

t_dh(DMM)

图8-19. DMMDATA Timing

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8.10.13 JTAG Interface

节8.10.13.2 and 节8.10.13.3 assume the operating conditions stated in 节8.10.13.1.

8.10.13.1 JTAG Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOAD

Output load capacitance

2

15

pF

8.10.13.2 Timing Requirements for IEEE 1149.1 JTAG

NO.

MIN

TYP

MAX

UNIT

ns

1

t_c(TCK)

Cycle time TCK

66.66

26.67

2.5

1a

1b

t_w(TCKH)

Pulse duration TCK high (40% of tc)

Pulse duration TCK low(40% of tc)

Input setup time TDI valid to TCK high

Input setup time TMS valid to TCK high

Input hold time TDI valid from TCK high

Input hold time TMS valid from TCK high

ns

t_w(TCKL)

ns

t_su(TDI-TCK)

t_su(TMS-TCK)

t_h(TCK-TDI)

t_h(TCK-TMS)

ns

3

4

2.5

ns

18

ns

18

ns

8.10.13.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG

NO.

PARAMETER

MIN

TYP

MAX

UNIT

2

t_d(TCKL-TDOV)

Delay time, TCK low to TDO valid

0

25

ns

1

1a

1b

TCK

TDO

2

3

4

TDI/TMS

SPRS91v_JTAG_01

图8-20. JTAG Timing

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9 Detailed Description

9.1 Overview

The AWR1843 device includes the entire Millimeter Wave blocks and analog baseband signal chain for two

transmitters and four receivers, as well as a customer-programmable MCU. This device is applicable as a radar-

on-a-chip in use-cases with modest requirements for memory, processing capacity, and application code size.

These could be cost-sensitive automotive applications that are evolving from 24 GHz narrowband

implementation and some emerging simple ultra-short-range radar applications. Typical application examples for

this device include basic Blind Spot Detect, Parking Assist, and so forth.

In terms of scalability, the AWR1843 device could be paired with a low-end external MCU, to address more

complex applications that might require additional memory for larger application software footprint and faster

interfaces. Because the AWR1843 device also provides high speed data interfaces like Serial-LVDS, it is suitable

for interfacing with more capable external processing blocks. Here system designers can choose the AWR1843

to provide raw ADC data.

9.2 Functional Block Diagram

Serial Flash interface

QSPI

Cortex R4F

@ 200MHz

LNA

IF

ADC

Optional External

MCU interface

SPI

(User programmable)

Digital

Front-end

PMIC control

SPI / I2C

DCAN

Prog RAM

(512kB*)

Data RAM

(192kB*)

Boot

ROM

(Decimation

filter chain)

Primary communication

interfaces (automotive)

CAN-FD

UARTs

Radar Hardware Accelerator

(FFT, Log mag, and others)

DMA

Main sub-system

(Customer programmed)

Test/

Debug

JTAG for debug/

development

ADC

Buffer

PA

û-

Mailbox

High-speed ADC output

interface (for recording)

LVDS

HIL

Synth

(20 GHz)

Ramp

Generator

PA

x4

High-speed input for

hardware-in-loop verification

C674x DSP

@ 400/600 MHz

Radio (BIST)

processor

PA

GPADC

Osc.

6

(For RF Calibration

& Self-test œ TI

programmed)

L1P

(32kB)

L1D

(32kB)

L2 (256kB)

Prog RAM

& ROM

Data

RAM

VMON

Temp

DMA

CRC

Radar Data Memory

1024 kB*

Radio processor

sub-system

(TI programmed)

DSP sub-system

(Customer programmed)

RF/Analog sub-system

* Up to 512kB of Radar Data Memory can be switched to the Main R4F program and data RAMs

图9-1. Functional Block Diagram

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9.3 Subsystems

9.3.1 RF and Analog Subsystem

The RF and analog subsystem includes the RF and analog circuitry – namely, the synthesizer, PA, LNA, mixer,

IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The three transmit

channels can be operated up to a maximum of two at a time (simultaneously) for transmit beamforming purpose

as required; whereas the four receive channels can all be operated simultaneously.

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9.3.1.1 Clock Subsystem

The AWR1843 clock subsystem generates 76 to 81 GHz from an input reference of 40-MHz crystal. It has a

built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF

synthesizer is then processed by an X4 multiplier to create the required frequency in the 76 to 81 GHz spectrum.

The RF synthesizer output is modulated by the timing engine block to create the required waveforms for effective

sensor operation.

The clean-up PLL also provides a reference clock for the host processor after system wakeup.

The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring the

quality of the generated clock.

图9-2 describes the clock subsystem.

Self Test

RF SYNTH

Timing

SYNC_OUT

Engine

Lock Detect

SoC Clock

Clean-

Up PLL

x4

MULT

XO/

Slicer

CLK Detect

40 MHz

图9-2. Clock Subsystem

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9.3.1.2 Transmit Subsystem

The AWR1843 transmit subsystem consists of three parallel transmit chains, each with independent phase and

amplitude control. All three transmitters can be used simultaneously. For AWR1843, additional phase shifters are

associated with Tx channels, and these can programmed on a per chirp basis.

Each transmit chain can deliver a maximum of 12 dBm at the antenna port on the PCB. The transmit chains also

support programmable backoff for system optimization.

图9-3 describes the transmit subsystem.

Loopback Path

Fine Phase Shifter Control

PCB

6 bits

12dBm

@ 50 Ω

û-

LO

0/180°

(from Timing Engine)

Self Test

图9-3. Transmit Subsystem (Per Channel)

9.3.1.3 Receive Subsystem

The AWR1843 receive subsystem consists of four parallel channels. A single receive channel consists of an

LNA, mixer, IF filtering, ADC conversion, and decimation. All four receive channels can be operational at the

same time an individual power-down option is also available for system optimization.

Unlike conventional real-only receivers, the AWR1843 device supports a complex baseband architecture, which

uses quadrature mixer and dual IF and ADC chains to provide complex I and Q outputs for each receiver

channel. The AWR1843 is targeted for fast chirp systems. The band-pass IF chain has configurable lower cutoff

frequencies above 175 kHz and can support bandwidths up to 10 MHz.

图9-4 describes the receive subsystem.

Self Test

DAC

Loopback

Path

DSM

PCB

I

RSSI

50 W

GSG

LO

Q

DSM

DAC

图9-4. Receive Subsystem (Per Channel)

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9.3.2 Processor Subsystem

Unified

128KB x 2

ROM

L2

Cache/

RAM

TCM A 512KB

TCM B 192KB

L1P

32KB

EDMA

Main

R4F

DSP

HIL

JTAG

CRC

HIL

L1d

DSP Interconnect œ 128 bit @ 200 MHz

Main Interconnect

BSS Interconnect

Data

Handshake

Memory

CRC

ADC Buffer

Mail

Box

MSS

DMA

L3

HWA

32KB

32KB Ping-Pong

1024 KB

(static sharing

with R4F Space)

Interconnect

LVDS

PWM,

PMIC

CLK

CAN

FD

I²C

QSPI

UART

CAN

SPI

图9-5. Processor Subsystem

图9-5 shows the block diagram for customer programmable processor subsystems in the AWR1843 device. At a

high level there are two customer programmable subsystems, as shown separated by a dotted line in the

diagram. Left hand side shows the DSP Subsystem which contains TI's high-performance C674x DSP, a high-

bandwidth interconnect for high performance (128-bit, 200MHz), and associated peripherals – four DMAs for

data transfer. LVDS interface for Measurement data output, L3 Radar data cube memory, ADC buffers, CRC

engine, and data handshake memory (additional memory provided on interconnect).

The right side of the diagram shows the Main subsystem. Main subsystem as name suggests is the brain of the

device and controls all the device peripherals and house-keeping activities of the device. Main subsystem

contains Cortex-R4F (Main R4F) processor and associated peripherals and house-keeping components such as

DMAs, CRC and Peripherals (I²C, UART, SPIs, CAN, PMIC clocking module, PWM, and others) connected to

Main Interconnect through Peripheral Central Resource (PCR interconnect).

Details of the DSP CPU core can be found at https://www.ti.com/product/TMS320C6748.

HIL module is shown in both the subsystems and can be used to perform the radar operations feeding the

captured data from outside into the device without involving the RF subsystem. HIL on Main SS is for controlling

the configuration and HIL on DSPSS for high speed ADC data input to the device. Both HIL modules uses the

same IOs on the device, one additional IO (DMM_MUX_IN) allows selecting either of the two.

9.3.3 Automotive Interface

The AWR1843 communicates with the automotive network over the following main interfaces:

• CAN and CAN-FD

9.3.4 Main Subsystem Cortex-R4F Memory Map

表9-1 shows the main subsystem, Cortex-R4F memory map.

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备注

There are separate Cortex-R4F addresses and DMA MSS addresses for the main subsystem. See the

Technical Reference Manual for a complete list.

表9-1. Main Subsystem, Cortex-R4F Memory Map

FRAME ADDRESS (HEX)

NAME

SIZE

DESCRIPTION

START

END

CPU Tightly-Coupled Memories

TCMA ROM

TCM RAM-A

0x0000_0000

0x0020_0000

0x0001_FFFF

128 KiB

Program ROM

0x0023_FFFF (or

0x0027_FFFF)

512 KiB

256/512KB based on variant

TCM RAM-B

0x0800_0000

0x0802_FFFF

192 KB

Data RAM

S/W Scratch Pad Memory

SW_ Buffer

0x0C20_0000

0x0C20_1FFF

8 KB

2 KB

188 B

2 KB

188 B

2 KB

188 B

S/W Scratchpad memory

System Peripherals

Mail Box

MSS<->RADARSS

0xF060_1000

0xF060_2000

0xF060_8000

0xF060_8060

0xF060_4000

0xF060_5000

0xF060_8400

0xF060_8300

0xF060_6000

0xF060_7000

0xF060_8200

0xF060_17FF

0xF060_27FF

0xF060_80FF

0xF060_86FF

0xF060_47FF

0xF060_57FF

0xF060_84FF

0xF060_83FF

0xF060_67FF

0xF060_7FFF

0xF060_82FF

RADARSS to MSS mailbox memory space

MSS to RADARSS mailbox memory space

MSS to RADARSS mailbox Configuration registers

RADARSS to MSS mailbox Configuration registers

DSPSS to MSS mailbox memory space

Mail Box

MSS<->DSPSS

MSS to DSPSS mailbox memory space

MSS to DSPSS mailbox Configuration registers

DSPSS to MSS mailbox Configuration registers

RADARSS to DSPSS mailbox memory space

DSPSS to RADARSS mailbox memory space

Mail Box

RADARSS<-

>DSPSS

RADARSS to DSPSS mailbox Configuration

registers

0xF060_8100

0xF060_81FF

DSPSS to RADARSS mailbox Configuration

registers

PRCM and Control

Module

0xFFFF_E100

0xFFFF_FF00

0xFFFF_EA00

0xFFFF_F800

0xFFF7_BC00

0xFFFF_F000

0xFCFF_F800

0xFCFF_F700

0xFCFF_F600

0xFFFF_FD00

0xFFFF_FC00

0xFFFF_EE00

0xFFFF_E2FF

0xFFFF_FFFF

0xFFFF_EBFF

0xFFFF_FBFF

0xFFF7_BDFF

0xFFFF_F3FF

0xFCFF_FBFF

0xFCFF_F7FF

0xFCFF_F6FF

0xFFFF_FEFF

0xFFFF_FCFF

0xFFFF_EEFF

756 B

256 B

512 KB

352 B

180 B

1 KB

TOP Level Reset, Clock management registers

MSS Reset, Clock management registers

IO Mux module registers

General-purpose control registers

GIO module configuration registers

DMA-1 module configuration registers

DMA-2 module configuration registers

DMM-1 module configuration registers

DMM-2 module configuration registers

VIM module configuration registers

RTI-A module configuration registers

RTI-B module configuration registers

GIO

DMA-1

DMA-2

DMM-1

DMM-2

VIM

1 KB

472 B

512 B

192 B

RTI-A/WD

RTI-B

Serial Interfaces and Connectivity

QSPI

0xC000_0000

0xC080_0000

0xFFF7_F400

0xFFF7_F600

0xFFF7_E500

0xFFF7_E700

0xC07F_FFFF

0xC0FF_FFFF

0xFFF7_F5FF

0xFFF7_F7FF

0xFFF7_E5FF

0xFFF7_E7FF

8 MB

116 B

512 B

148 B

QSPI –flash memory space

QSPI module configuration registers

MIBSPI-A module configuration registers

MIBSPI-B module configuration registers

SCI-A module configuration registers

SCI-B module configuration registers

MIBSPI-A

MIBSPI-B

SCI-A

SCI-B

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表9-1. Main Subsystem, Cortex-R4F Memory Map (continued)

FRAME ADDRESS (HEX)

NAME

SIZE

DESCRIPTION

START END

CAN

0xFFF7_DC00

0xFFF7_C800

0xFFF7_A000

0xFFF7_D400

0xFFF7_DDFF

0xFFF7_CFFF

0xFFF7_A1FF

0xFFF7_D4FF

512 B

CAN module configuration registers

CAN_FD(MCAN)

768 B

452 B

112 B

CAN-FD module configuration registers

MCAN ECC module registers

I2C

I2C module configuration registers

Interconnects

PCR-1

0xFFF7_8000

0xFCFF_1000

0xFFF7_87FF

0xFCFF_17FF

1 KiB

PCR-1 interconnect configuration port

PCR-2 interconnect configuration port

PCR-2

Safety Modules

CRC

0xFE00_0000

0xFFFF_E400

0xFFFF_E600

0xFFFF_EC00

0xFFFF_F400

0xFFFF_F500

0xFFFF_F600

0xFEFF_FFFF

0xFFFF_E5FF

0xFFFF_E7FF

0xFFFF_ECFF

0xFFFF_F4FF

0xFFFF_F5FF

0xFFFF_F6FF

16 KiB

464 B

284 B

44 B

CRC module configuration registers

PBIST module configuration registers

STC module configuration registers

DCC-A module configuration registers

DCC-B module configuration registers

ESM module configuration registers

CCMR4 module configuration registers

PBIST

STC

DCC-A

DCC-B

44 B

ESM

156 B

136 B

CCMR4

Security Modules

Crypto

0xFD00_0000

0XFDFF_FFFF

3 KiB

Crypto module configuration registers

Other Subsystems

DSS_TPTC0

DSS_REG

DSS_TPTC1

DSS_REG2

DSS_TPCC0

DSS_RTIA/WDT

DSS_SCI

0x5000 0000

0x5000 0400

0x5000 0800

0x5000 0C00

0x5001 0000

0x5002 0000

0x5003 0000

0x5004 0000

0x5007 0000

0x5009 0000

0x5009 0400

0x500A 0000

0x500D 0000

0x500F 0000

0x5000 0317

0x5000 075F

0x5000 0B17

0x5000 0EA3

0x5001 3FFF

0x5002 00BF

0x5003 0093

0x5004 011B

0x5007 0233

0x5009 0317

0x5009 0717

0x500A 3FFF

0x500D 005B

0x500F 00BF

0x511F FFFF

792 B

864 B

792 B

676 B

16 KB

192 B

148 B

284 B

564 B

792 B

16 KB

92 B

TPTC0 module configuration space

DSPSS control module registers

TPTC1 module configuration space

DSPSS control module registers

TPCC0 module configuration space

DSS_RTIA/WDT configuration space

SCI memory space

DSS_STC

DSS_CBUFF

DSS_TPTC2

DSS_TPTC3

DSS_TPCC1

DSS_ESM

DSS_RTIB

STC module configuration space

Common Buffer module configuration registers

TPTC2 module configuration space

TPTC3 module configuration space

TPCC1 module configuration space

ESM module configuration registers

RTI-B module configuration registers

L3 shared memory space

192 B

2 MB⁽¹⁾

DSS_L3RAM Shared 0x5100 0000

memory

DSS_ADCBUF Buffer 0x5200 0000

DSS_CBUFF_FIFO 0x5202 0000

0x5200 7FFF

0x5202 3FFF

0x5208 7FFF

0x577F FFFF

32 KB

16 KB

32 KB

128 KB

ADC buffer memory space

Common buffer FIFO space

Handshake memory space

L2 RAM space

DSS_HSRAM1

0x5208 0000

DSS_DSP_L2_UMA 0x577E 0000

P1

DSS_DSP_L2_UMA 0x5780 0000

P0

0x5781 FFFF

128 KB

L2 RAM space

DSS_DSP_L1P

DSS_DSP_L1D

0x57E0 0000

0x57F0 0000

0x57E0 7FFF

0x57F0 7FFF

32 KB

L1 program memory space

L1 data memory space

Peripheral Memories (System and Nonsystem)

CAN RAM 0xFF1E_0000 0xFF1F_FFFF

128 KB

CAN RAM memory space

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表9-1. Main Subsystem, Cortex-R4F Memory Map (continued)

FRAME ADDRESS (HEX)

SIZE

DESCRIPTION

START END

CAN-FD RAM

0xFF50_0000

0xFFF8_0000

0xFCF8 1000

0xFFF8_2000

0xFF0C_0000

0xFF0C_0200

0xFF0E_0000

0xFF0E_0200

0xFF51_FFFF

0xFFF8_0FFF

0xFCF8_0FFF

0xFFF8_2FFF

0xFF0C_01FF

0xFF0C_03FF

0xFF0E_01FF

0xFF0E_03FF

68 KB

CAN-FD RAM memory space

DMA1 RAM memory space

DMA1 RAM

4 KB

DMA2 RAM

4 KB

DMA2 RAM memory space

VIM RAM

2 KB

VIM RAM memory space

MIBSPIB-TX RAM

MIBSPIB-RX RAM

MIBSPIA-TX RAM

MIBSPIA- RX RAM

Debug Modules

Debug subsystem

0.5 KB

MIBSPIB-TX RAM memory space

MIBSPIB-RX RAM memory space

MIBSPIA-TX RAM memory space

MIBSPIA- RX RAM memory space

0xFFA0_0000

0xFFAF_FFFF

244 KB

Debug subsystem memory space and registers

(1) 768 KB memory within 2 MB memory space

9.3.5 DSP Subsystem Memory Map

表9-2 shows the DSP C674x memory map.

表9-2. DSP C674x Memory Map

Name

Frame Address (Hex)

Size

Description

Start

End

DSP Memories

DSP_L1D

0x00F0_0000

0x00E0_0000

0x00F0_7FFF

0x00E0_7FFF

32 KiB

L1 data memory space

DSP_L1P

L1 program memory

space

DSP_L2_UMAP0

DSP_L2_UMAP1

EDMA

0x0080_0000

0x007E_0000

0x0081_FFFF

0x007F_FFFF

128 KiB

L2 RAM space

TPCC0

0x0201_0000

0x020A_0000

0x0200 0000

0x0200 0800

0x0209_0000

0x0209_0400

0x0201_3FFF

0x020A_3FFF

0x0200 03FF

0x0200 0BFF

0x0209_03FF

0x0209_07FF

16 KiB

1 KiB

TPCC0 module

configuration space

TPCC1

TPTC0

TPTC1

TPTC2

TPTC3

TPCC1 module

configuration space

TPTC0 module

configuration space

TPTC1 module

configuration space

TPTC2 module

configuration space

TPTC3 module

configuration space

Control Registers

DSS_REG

0x0200_0400

0x0200_0C00

0x0200_07FF

0x0200_0FFF

864 B

624 B

DSPSS control module

registers

DSS_REG2

DSPSS control module

registers

System Memories

ADC Buffer

0x2100_0000

0x2102_0000

0x2100_7FFC

0x2102_3FFC

32 KiB

16 KiB

ADC buffer memory space

CBUFF-FIFO

Common buffer FIFO

space

L3-Shared memory⁽¹⁾

HS-RAM

0x2000_0000

0x2108_0000

0x201F_FFFF

0x2108_7FFC

2 MB

L3 shared memory space

Handshake memory space

32 KiB

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表9-2. DSP C674x Memory Map (continued)

Name

Frame Address (Hex)

Size

Description

Start

End

System Peripherals

RTI-A/WD

0x0202_0000

0x020F_0000

0x0207_0000

0x5060_1000

0x5060_2000

0x0460_8000

0x0202_00FF

0x020F_00FF

0x0207_03FF

0x5060_17FF

0x5060_27FF

0x0460_80FF

192 B

564 B

2 KiB

RTI-A module

configuration registers

RTI-B

RTI-B module

configuration registers

CBUFF

Common Buffer module

Configuration registers

Mail Box

MSS<->RADARSS

RADARSS to MSS

mailbox memory space

MSS to RADARSS

mailbox memory space

188 B

MSS to RADARSS

mailbox Configuration

registers

0x0460_8060

0x0460_86FF

RADARSS to MSS

mailbox Configuration

registers

Mail Box

MSS<->DSPSS

0x5060_4000

0x5060_5000

0x0460_8400

0x0460_8300

0x5060_6000

0x5060_7000

0x0460_8200

0x5060_47FF

0x5060_57FF

0x0460_84FF

0x0460_83FF

0x5060_67FF

0x5060_7FFF

0x0460_82FF

2 KiB

188 B

2 KiB

188 B

DSPSS to MSS mailbox

memory space

MSS to DSPSS mailbox

memory space

MSS to DSPSS mailbox

Configuration registers

DSPSS to MSS mailbox

Configuration registers

Mail Box

RADARSS<->DSPSS

RADARSS to DSPSS

mailbox memory space

DSPSS to RADARSS

mailbox memory space

RADARSS to DSPSS

mailbox Configuration

registers

0x0460_8100

0x0460_81FF

DSPSS to RADARSS

mailbox Configuration

registers

Safety Modules

ESM

0x020D_0000

0x2200_0000

0x0204_0000

92 B

ESM module

Configuration registers

CRC

STC

0x2200_03FF

0x0204_01FF

1 KiB

284 B

CRC module

Configuration registers

STC module Configuration

registers

Nonsystem Peripherals

SCI

0x0203_0000

0x0203_00FF

148 B

SCI module Configuration

registers

(1) 768 KB memory within 2 MB memory space

9.4 Other Subsystems

9.4.1 ADC Channels (Service) for User Application

The AWR1843 device includes provision for an ADC service for user application, where the

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GPADC engine present inside the device can be used to measure up to six external voltages. The ADC1, ADC2,

ADC3, ADC4, ADC5, and ADC6 pins are used for this purpose.

• ADC itself is controlled by TI firmware running inside the BIST subsystem and access to it for customer’s

external voltage monitoring purpose is via ‘monitoring API’calls routed to the BIST subsystem. This API

could be linked with the user application running on MSS R4F.

• BIST subsystem firmware will internally schedule these measurements along with other RF and Analog

monitoring operations. The API allows configuring the settling time (number of ADC samples to skip) and

number of consecutive samples to take. At the end of a frame, the minimum, maximum and average of the

readings will be reported for each of the monitored voltages.

GPADC Specifications:

• 625 Ksps SAR ADC

• 0 to 1.8V input range

• 10-bit resolution

• For 5 out of the 6 inputs, an optional internal buffer is available. Without the buffer, the ADC has a switched

capacitor input load modeled with 5pF of sampling capacitance and 12pF parasitic capacitance (GPADC

channel 6, the internal buffer is not available).

5

ANALOG TEST 1-4,

GPADC

ANAMUX

5

VSENSE

A. GPADC structures are used for measuring the output of internal temperature sensors. The accuracy of these measurements is ±7°C.

图9-6. ADC Path

9.4.1.1 GP-ADC Parameter

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TYP

1.8

UNIT

V

ADC supply

ADC unbuffered input voltage range

ADC buffered input voltage range⁽¹⁾

ADC resolution

V

0 –1.8

0.4 –1.3

10

V

bits

LSB

Ksps

ns

ADC offset error

±5

ADC gain error

±5

ADC DNL

–1/+2.5

±2.5

625

ADC INL

ADC sample rate⁽²⁾

ADC sampling time⁽²⁾

ADC internal cap

400

10

pF

ADC buffer input capacitance

2

pF

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over operating free-air temperature range (unless otherwise noted)

PARAMETER

TYP

UNIT

ADC input leakage current

3

uA

(1) Outside of given range, the buffer output will become nonlinear.

(2) ADC itself is controlled by TI firmware running inside the BIST subsystem. For more details please refer to the API calls.

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10 Monitoring and Diagnostics

10.1 Monitoring and Diagnostic Mechanisms

表 10-1 is a list of the main monitoring and diagnostic mechanisms available in the Functional Safety-Compliant

devices

表10-1. Monitoring and Diagnostic Mechanisms for Functional Safety-Compliant Devices

NO

FEATURE

DESCRIPTION

Device architecture supports hardware logic BIST (LBIST) engine self-test Controller (STC).

This logic is used to provide a very high diagnostic coverage (>90%) on the MSS R4F CPU

core and Vectored Interrupt Module (VIM) at a transistor level.

LBIST for the CPU and VIM need to be triggered by application code before starting the

functional safety application. CPU stays there in while loop and does not proceed further if a

fault is identified.

Boot time LBIST For MSS

R4F Core and associated

VIM

1

MSS R4F has three Tightly coupled Memories (TCM) memories TCMA, TCMB0 and

TCMB1. Device architecture supports a hardware programmable memory BIST (PBIST)

engine. This logic is used to provide a very high diagnostic coverage (March-13n) on the

implemented MSS R4F TCMs at a transistor level.

PBIST for TCM memories is triggered by Bootloader at the boot time before starting

download of application from Flash or peripheral interface. CPU stays there in while loop

and does not proceed further if a fault is identified.

Boot time PBIST for MSS

R4F TCM Memories

2

3

TCMs diagnostic is supported by Single error correction double error detection (SECDED)

ECC diagnostic. An 8-bit code word is used to store the ECC data as calculated over the 64-

bit data bus. ECC evaluation is done by the ECC control logic inside the CPU. This scheme

provides end-to-end diagnostics on the transmissions between CPU and TCM. CPU can be

configured to have predetermined response (Ignore or Abort generation) to single and

double bit error conditions.

End to End ECC for MSS

R4F TCM Memories

Logical TCM word and its associated ECC code is split and stored in two physical SRAM

banks. This scheme provides an inherent diagnostic mechanism for address decode failures

in the physical SRAM banks. Faults in the bank addressing are detected by the CPU as an

ECC fault.

Further, bit multiplexing scheme implemented such that the bits accessed to generate a

logical (CPU) word are not physically adjacent. This scheme helps to reduce the probability

of physical multi-bit faults resulting in logical multi-bit faults; rather they manifest as multiple

single bit faults. As the SECDED TCM ECC can correct a single bit fault in a logical word,

this scheme improves the usefulness of the TCM ECC diagnostic.

MSS R4F TCM bit

multiplexing

4

Both these features are hardware features and cannot be enabled or disabled by application

software.

Device architecture supports Three Digital Clock Comparators (DCCs) and an internal

RCOSC. Dual functionality is provided by these modules –Clock detection and Clock

Monitoring.

DCCint is used to check the availability/range of Reference clock at boot otherwise the

device is moved into limp mode (Device still boots but on 10MHz RCOSC clock source. This

provides debug capability). DCCint is only used by boot loader during boot time. It is

disabled once the APLL is enabled and locked.

DCC1 is dedicated for APLL lock detection monitoring, comparing the APLL output divided

version with the Reference input clock of the device. Initially (before configuring APLL),

DCC1 is used by bootloader to identify the precise frequency of reference input clock

against the internal RCOSC clock source. Failure detection for DCC1 would cause the

device to go into limp mode.

5

Clock Monitor

DCC2 module is one which is available for user software . From the list of clock options

given in detailed spec, any two clocks can be compared. One example usage is to compare

the CPU clock with the Reference or internal RCOSC clock source. Failure detection is

indicated to the MSS R4F CPU via Error Signaling Module (ESM).

Device architecture supports the use of an internal watchdog that is implemented in the real-

time interrupt (RTI) module. The internal watchdog has two modes of operation: digital

watchdog (DWD) and digital windowed watchdog (DWWD). The modes of operation are

mutually exclusive; the designer can elect to use one mode or the other but not both at the

same time.

7

RTI/WD for MSS R4F

Watchdog can issue either an internal (warm) system reset or a CPU non-mask able

interrupt upon detection of a failure.

The Watchdog is enabled by the bootloader in DWD mode at boot time to track the boot

process. Once the application code takes up the control, Watchdog can be configured again

for mode and timings based on specific customer requirements.

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表10-1. Monitoring and Diagnostic Mechanisms for Functional Safety-Compliant Devices (continued)

NO

FEATURE

DESCRIPTION

Cortex-R4F CPU includes an MPU. The MPU logic can be used to provide spatial

separation of software tasks in the device memory. Cortex-R4F MPU supports 12 regions. It

is expected that the operating system controls the MPU and changes the MPU settings

based on the needs of each task. A violation of a configured memory protection policy

results in a CPU abort.

8

MPU for MSS R4F

Device architecture supports a hardware programmable memory BIST (PBIST) engine for

Peripheral SRAMs as well.

PBIST for peripheral SRAM memories can be triggered by the application. User can elect to

PBIST for Peripheral interface run the PBIST on one SRAM or on groups of SRAMs based on the execution time, which

9

SRAMs - SPIs, CANs

can be allocated to the PBIST diagnostic. The PBIST tests are destructive to memory

contents, and as such are typically run only at boot time. However, the user has the freedom

to initiate the tests at any time if peripheral communication can be hindered.

Any fault detected by the PBIST results in an error indicated in PBIST status registers.

Peripheral interface SRAMs diagnostic is supported by Single error correction double error

detection (SECDED) ECC diagnostic. When a single or double bit error is detected the MSS

R4F is notified via ESM (Error Signaling Module). This feature is disabled after reset.

Software must configure and enable this feature in the peripheral and ESM module. ECC

failure (both single bit corrected and double bit uncorrectable error conditions) is reported to

the MSS R4F as an interrupt via ESM module.

ECC for Peripheral interface

SRAMs –SPIs, CANs

10

All the Main SS peripherals (SPIs, CANs, I2C, DMAs, RTI/WD, DCCs, IOMUX etc.) are

connected to interconnect via Peripheral Central resource (PCR). This provides two

diagnostic mechanisms that can limit access to peripherals. Peripherals can be clock gated

per peripheral chip select in the PCR. This can be utilized to disable unused features such

that they cannot interfere. In addition, each peripheral chip select can be programmed to

limit access based on privilege level of transaction. This feature can be used to limit access

to entire peripherals to privileged operating system code only.

Configuration registers

protection for Main SS

peripherals

11

These diagnostic mechanisms are disabled after reset. Software must configure and enable

these mechanisms. Protection violation also generates an ‘error’that result in abort to

MSS R4F or error response to other peripherals such as DMAs.

Device architecture supports hardware CRC engine on Main SS implementing the below

polynomials.

•

CRC16 CCITT –0x10

CRC32 Ethernet –0x04C11DB7

CRC64

CRC 32C –CASTAGNOLI –0x1EDC6F4

CRC32P4 –E2E Profile4 –0xF4ACFB1

CRC-8 –H2F Autosar –0x2F

CRC-8 –VDA CAN –0x1D

Cyclic Redundancy Check –

Main SS

12

The read operation of the SRAM contents to the CRC can be done by CPU or by DMA. The

comparison of results, indication of fault, and fault response are the responsibility of the

software managing the test.

Device architecture supports MPUs on Main SS DMAs. Failure detection by MPU is reported

to the MSS R4F CPU core as an interrupt via ESM.

13

14

15

MPU for DMAs

DSPSS’s high performance EDMAs also includes MPUs on both read and write ports.

EDMA MPUs supports 8 regions. Failure detection by MPU is reported to the DSP core as

an interrupt via local ESM.

Device architecture supports hardware logic BIST (LBIST) even for BIST R4F core and

associated VIM module. This logic provides very high diagnostic coverage (>90%) on the

BIST R4F CPU core and VIM.

This is triggered by MSS R4F boot loader at boot time and it does not proceed further if the

fault is detected.

Boot time LBIST For BIST

R4F Core and associated

VIM

Device architecture supports a hardware programmable memory BIST (PBIST) engine for

BIST R4F TCMs which provide a very high diagnostic coverage (March-13n) on the BIST

R4F TCMs.

PBIST is triggered by MSS R4F Bootloader at the boot time and it does not proceed further

if the fault is detected.

Boot time PBIST for BIST

R4F TCM Memories

66

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表10-1. Monitoring and Diagnostic Mechanisms for Functional Safety-Compliant Devices (continued)

NO

FEATURE

DESCRIPTION

BIST R4F TCMs diagnostic is supported by Single error correction double error detection

(SECDED) ECC diagnostic. Single bit error is communicated to the BIST R4FCPU while

double bit error is communicated to MSS R4F as an interrupt so that application code

becomes aware of this and takes appropriate action.

End to End ECC for BIST

R4F TCM Memories

16

Logical TCM word and its associated ECC code is split and stored in two physical SRAM

banks. This scheme provides an inherent diagnostic mechanism for address decode failures

in the physical SRAM banks and helps to reduce the probability of physical multi-bit faults

resulting in logical multi-bit faults.

BIST R4F TCM bit

multiplexing

17

18

Device architecture supports an internal watchdog for BIST R4F. Timeout condition is

reported via an interrupt to MSS R4F and rest is left to application code to either go for SW

reset for BIST SS or warm reset for the device to come out of faulty condition.

RTI/WD for BIST R4F

Device architecture supports a hardware programmable memory BIST (PBIST) engine for

DSPSS’s L1P, L1D, L2 and L3 memories which provide a very high diagnostic coverage

(March-13n).

PBIST is triggered by MSS R4F Bootloader at the boot time and it does not proceed further

if the fault is detected.

Boot time PBIST for L1P,

L1D, L2 and L3 Memories

19

20

Device architecture supports Parity diagnostic on DSP’s L1P memory. Parity error is

reported to the CPU as an interrupt.

Note:- L1D memory is not covered by parity or ECC and need to be covered by application

level diagnostics.

Parity on L1P

Device architecture supports both Parity Single error correction double error detection

(SECDED) ECC diagnostic on DSP’s L2 memory. L2 Memory is a unified 256KB of

memory used to store program and Data sections for the DSP. A 12-bit code word is used to

store the ECC data as calculated over the 256-bit data bus (logical instruction fetch size).

The ECC logic for the L2 access is located in the DSP and evaluation is done by the ECC

control logic inside the DSP. This scheme provides end-to-end diagnostics on the

transmissions between DSP and L2. Byte aligned Parity mechanism is also available on L2

to take care of data section.

21

ECC on DSP’s L2 Memory

L3 memory is used as Radar data section in Device. Device architecture supports Single

error correction double error detection (SECDED) ECC diagnostic on L3 memory. An 8-bit

code word is used to store the ECC data as calculated over the 64-bit data bus.

Failure detection by ECC logic is reported to the MSS R4F CPU core as an interrupt via

ESM.

ECC on Radar Data Cube

(L3) Memory

22

23

Device architecture supports the use of an internal watchdog for BIST R4F that is

implemented in the real-time interrupt (RTI) module –replication of same module as used in

Main SS. This module supports same features as that of RTI/WD for MSS/BIST R4F.

This watchdog is enabled by customer application code and Timeout condition is reported

via an interrupt to MSS R4F and rest is left to application code in MSS R4F to either go for

SW reset for DSP SS or warm reset for the device to come out of faulty condition.

RTI/WD for DSP Core

Device architecture supports dedicated hardware CRC on DSPSS implementing the below

polynomials.

•

CRC16 CCITT - 0x10

CRC32 Ethernet - 0x04C11DB7

CRC64

24

25

CRC for DSP Sub-System

The read of SRAM contents to the CRC can be done by DSP CPU or by DMA. The

comparison of results, indication of fault, and fault response are the responsibility of the

software managing the test.

Device architecture supports MPUs for DSP memory accesses (L1D, L1P, and L2). L2

memory supports 64 regions and 16 regions for L1P and L1D each. Failure detection by

MPU is reported to the DSP core as an abort.

MPU for DSP

Device architecture supports various temperature sensors all across the device (next to

power hungry modules such as PAs, DSP etc) which is monitored during the inter-frame

period.⁽¹⁾

26

27

Temperature Sensors

Tx Power Monitors

Device architecture supports power detectors at the Tx output.⁽²⁾

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表10-1. Monitoring and Diagnostic Mechanisms for Functional Safety-Compliant Devices (continued)

NO

FEATURE

DESCRIPTION

When a diagnostic detects a fault, the error must be indicated. The device architecture

provides aggregation of fault indication from internal monitoring/diagnostic mechanisms

using a peripheral logic known as the Error Signaling Module (ESM). The ESM provides

mechanisms to classify errors by severity and to provide programmable error response.

ESM module is configured by customer application code and specific error signals can be

enabled or masked to generate an interrupt (Low/High priority) for the MSS R4F CPU.

device supports Nerror output signal (IO) which can be monitored externally to identify any

kind of high severity faults in the design which could not be handled by the R4F.

Error Signaling

Error Output

28

Monitors Synthesizer’s frequency ramp by counting (divided-down) clock cycles and

comparing to ideal frequency ramp. Excess frequency errors above a certain threshold, if

any, are detected and reported.

Synthesizer (Chirp) frequency

monitor

29

30

Device architecture supports a ball break detection mechanism based on Impedance

measurement at the TX output(s) to detect and report any large deviations that can indicate

a ball break.

Monitoring is done by TIs code running on BIST R4F and failure is reported to the MSS R4F

via Mailbox.

Ball break detection for TX

ports (TX Ball break monitor)

It is completely up to customer SW to decide on the appropriate action based on the

message from BIST R4F.

Built-in TX to RX loopback to enable detection of failures in the RX path(s), including Gain,

inter-RX balance, etc.

31

32

33

34

RX loopback test

Built-in IF (square wave) test tone input to monitor IF filter’s frequency response and detect

failure.

IF loopback test

Provision to detect ADC saturation due to excessive incoming signal level and/or

interference.

RX saturation detect

Boot time LBIST for DSP core

Device supports boot time LBIST for the DSP Core. LBIST can be triggered by the MSS R4F

application code during boot time.

(1) Monitoring is done by TI's code running on BIST R4F.

There are two modes in which it could be configured to report the temperature sensed via API by customer application.

a. Report the temperature sensed after every N frames

b. Report the condition once the temperature crosses programmed threshold.

It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4Fvia Mailbox.

(2) Monitoring is done by the TI's code running on BIST R4F.

There are two modes in which it could be configured to report the detected output power via API by customer application.

a. Report the power detected after every N frames

b. Report the condition once the output power degrades by more than configured threshold from the configured.

It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4F.

备注

Refer to the Device Safety Manual or other relevant collaterals for more details on applicability of all

diagnostics mechanisms. For Certification details, refer to the Device product folder.

68

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10.1.1 Error Signaling Module

When a diagnostic detects a fault, the error must be indicated. AWR1843 architecture provides aggregation of

fault indication from internal diagnostic mechanisms using a peripheral logic known as the error signaling module

(ESM). The ESM provides mechanisms to classify faults by severity and allows programmable error response.

Below is the high level block diagram for ESM module.

Low Priority

Interrupt

Interrupy

Handing

Error Group 1

Interrupt Enable

High Priority

Interrupt

Handing

High Priority

Interrupy

Interrupt Priority

Error Group 2

Error Group 3

Nerror Enable

Error Signal

Handling

Device Output

图10-1. ESM Module Diagram

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11 Applications, Implementation, and Layout

备注

Information in the following Applications section is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI's customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

11.1 Application Information

Key device features driving the following applications are:

• Integration of Radar Front End and Programmable MCU

• Flexible boot modes: Autonomous Application boot using a serial flash or external boot over SPI.

11.2 Short- and Medium-Range Radar

40-MHz

Crystal

Serial

Flash

Power Management

QSPI

Integrated MCU

ARM Cortex-R4F

DCAN

PHY

Automotive

Network

CAN

Antenna

Structure

RX1

RX2

RX3

RX4

MCAN

PHY

Automotive

Network

CAN FD

Radar

Front End

TX1

TX2

TX3

Integrated DSP

TI C674x

AWR1843

图11-1. Short- and Meduim-Range Radar

70

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11.3 Reference Schematic

The reference schematic and power supply information can be found in the AWR1843 EVM Documentation.

Listed for convenience are: Design Files, Schematics, Layouts, and Stack up for PCB.

• Altium AWR1843 EVM Design Files

• AWR1843 EVM Schematic Drawing, Assembly Drawing, and Bill of Materials

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12 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions follow.

12.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for

example, AWR1843). Texas Instruments recommends two of three possible prefix designators for its support

tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering

prototypes (TMDX) through fully qualified production devices and tools (TMDS).

Device development evolutionary flow:

X

P

Experimental device that is not necessarily representative of the final device's electrical specifications and

may not use production assembly flow.

Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical

specifications.

null Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.

TMDS Fully-qualified development-support product.

X and P devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

Production devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (X or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(for example, ABL0161 ALB0161), the temperature range (for example, blank is the default commercial

temperature range). 图12-1 provides a legend for reading the complete device name for any AWR1843 device.

For orderable part numbers of AWR1843 devices in the ABL0161 package types, see the Package Option

Addendum of this document , the TI website (www.ti.com), or contact your TI sales representative.

For additional description of the device nomenclature markings on the die, see the AWR1843 Device Errata.

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1

8

43

B

AWR

G

ABL

Q1

Qualification

Q1 = AEC-Q100

Blank = no special Qual

Prefix

AWR = Production

Tray or Tape & Reel

Generation

1 = 76 œ 81 GHz

R = Big Reel

Blank = Tray

Variant

Package

ABL = BGA

2 = FE

4 = FE + FFT + MCU

6 = FE + MCU + DSP

8 = FE + FFT + MCU + DSP

Security

Num RX/TX Channels

RX = 1,2,3,4

TX = 1,2,3

G = General

S = Secure

D = Development Secure

Silicon PG Revision

Blank = Rev 1.0

A = Rev 2.0

Features

Blank = Baseline

Safety

B= Functional Safety-Compliant, ASIL-B

图12-1. Device Nomenclature

12.2 Tools and Software

Models

AWR1843 BSDL model Boundary scan database of testable input and output pins for IEEE 1149.1 of the

specific device.

AWR1843 IBIS model IO buffer information model for the IO buffers of the device. For simulation on a circuit

board, see IBIS Open Forum.

12.3 Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

The current documentation that describes the DSP, related peripherals, and other technical collateral follows.

Errata

AWR1843 device errata Describes known advisories, limitations, and cautions on silicon and provides

workarounds.

12.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

^®, Arm^®, and Cortex^®are registered trademarks of ARM Limited.

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所有商标均为其各自所有者的财产。

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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13 Mechanical, Packaging, and Orderable Information

13.1 Packaging Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

13.2 Tray Information for

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PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2022

TRAY

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

W

K0

P1

CL

CW

Name

Type

(mm) (µm) (mm) (mm) (mm)

AWR1843ABGABLQ1

ABL

FCCSP

161

176

8 x 22

150

315 135.9 7620 13.4

16.8

17.2

Pack Materials-Page 1

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	AWR1843ABGABLQ1
厂家：	TEXAS INSTRUMENTS
描述：	集成 DSP、MCU 和雷达加速器的单芯片 76GHz 至 81GHz 汽车雷达传感器 \| ABL \| 161 \| -40 to 125 雷达传感器
文件：	总79页 (文件大小：2470K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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