AWR1843ARBGALPQ1 [TI]
AWR1843AOP Single-chip 77- and 79-GHz FMCW radar sensor;
| 型号： | AWR1843ARBGALPQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AWR1843AOP Single-chip 77- and 79-GHz FMCW radar sensor |
| 文件： | 总88页 (文件大小：3537K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AWR1843AOP
SWRS236A – MARCH 2021 – REVISED SEPTEMBER 2021
AWR1843AOP Single-chip 77- and 79-GHz FMCW radar sensor
•
Functional Safety-Compliant targeted
– Developed for functional safety applications
– Documentation will be available to aid
ISO26262 functional safety system design
– Hardware integrity up to ASIL-B targeted
– Safety-related certification
1 Features
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FMCW transceiver
– Integrated 4 receivers and 3 transmitters
Antennas-On-Package (AOP)
– Integrated PLL, transmitter, receiver, Baseband,
and ADC
•
ISO 26262 certification by TUV Sud planned
– 76- to 81-GHz coverage with 4 GHz available
bandwidth
– Ultra-accurate chirp engine based on fractional-
N PLL
– TX Effective isotropic radiated power (EIRP):
16 dBm
– RX Effective isotropic noise figure: 10 dB (76 to
81 GHz)
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•
AEC-Q100 qualified
AWR1843AOP advanced features
– Embedded self-monitoring with no host
processor involvement
– Complex baseband architecture
– Embedded interference detection capability
– Programmable phase rotators in transmit path
to enable beam forming
– Phase noise at 1 MHz:
•
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Power management
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–95 dBc/Hz (76 to 77 GHz)
–93 dBc/Hz (77 to 81 GHz)
– Built-in LDO network for enhanced PSRR
– I/Os support dual voltage 3.3 V/1.8 V
Clock source
– Supports external oscillator at 40 MHz
– Supports externally driven clock (square/sine)
at 40 MHz
– Supports 40 MHz crystal connection with load
capacitors
Easy hardware design
– 0.8-mm pitch, 180-pin 15 mm × 15 mm flip chip
BGA package (ALP) for easy assembly and
low-cost PCB design
– Small solution size
Supports automotive temperature operating range
•
Built-in calibration and self-test (monitoring)
– Arm® Cortex®-R4F-based radio control system
– Built-in firmware (ROM)
– Self-calibrating system across frequency and
temperature
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•
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C674x DSP for FMCW signal processing
On-chip Memory: 2MB RAM
•
•
Arm Cortex-R4F microcontroller for object tracking
and classification, AUTOSAR, and interface control
– Supports autonomous mode (loading user
application from QSPI flash memory)
Host interface
•
•
– CAN (two instances, one being CAN-FD)
Other interfaces available to user application
– Up to 6 general purpose ADC channels
– Up to 2 SPI ports
– Up to 2 UARTs
– I2C
– GPIOs
– 2-lane LVDS interface for raw ADC data and
debug instrumentation
2 Applications
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Car door opener applications
Blind spot detection
Lane change assistance
Cross traffic alert
Parking assistance
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AWR1843AOP
SWRS236A – MARCH 2021 – REVISED SEPTEMBER 2021
www.ti.com
40-MHz
Crystal
Serial
Flash
Power Management
QSPI
Package
Integrated MCU
ARM Cortex-R4F
DCAN
PHY
Automotive
Network
CAN
Antenna
RX1
on Package
RX2
RX3
MCAN
PHY
Automotive
Network
CAN FD
RX4
Radar
Front End
TX1
TX2
TX3
Integrated DSP
TI C674x
AWR1843AOP
Figure 2-1. Autonomous Radar Sensor for Automotive Applications
3 Description
The AWR1843AOP is an Antenna-On-Package device capable of operation in the 76- to 81GHz band. The
device is built with TI’s low-power 45-nm RFCMOS process and enables unprecedented levels of integration
in an extremely small form factor. The AWR1843AOP is an ideal solution for low-power, self-monitored, ultra-
accurate radar systems in the automotive space.
It integrates a DSP subsystem, which contains TI's high-performance C674x DSP for the Radar Signal
processing. The device includes a BIST processor subsystem, which is responsible for radio configuration,
control, and calibration. Additionally the device includes a user programmable Arm Cortex-R4F based for
automotive interfacing. The Hardware Accelerator block (HWA) can perform radar processing and can offload
the DSP in order to execute higher level algorithms. Simple programming model changes can enable a wide
variety of sensor applications with the possibility of dynamic reconfiguration for implementing a multimode
sensor. Additionally, the device is provided as a complete platform solution including reference hardware design,
software drivers, sample configurations, API guide, and user documentation.
Device Information
BODY SIZE
PART NUMBER
AWR1843ARBGALPQ1
AWR1843ARBGALPRQ1
AWR1843ARBSALPQ1
AWR1843ARBSALPRQ1
PACKAGE(1)
FCBGA (180)
FCBGA (180)
FCBGA (180)
FCBGA (180)
TRAY / TAPE AND REEL
15 mm × 15 mm Tray
15 mm × 15 mm Tape and Reel
15 mm × 15 mm Tray
15 mm × 15 mm Tape and Reel
(1) For more information, see Section 12, Mechanical Packaging and Orderable Information.
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3.1 Functional Block Diagram
Figure 3-1 is functional block diagram for the device.
Antennas are on Package
QSPI
SPI
Serial Flash interface
LNA
LNA
LNA
LNA
IF
IF
IF
IF
ADC
ADC
ADC
ADC
Cortex R4F
@ 200MHz
External MCU interface
(User programmable)
Digital
Front-End
PMIC control
SPI / I2C
DCAN
Data
RAM
Boot
ROM
Prog RAM
(Decimation
Filter Chain)
Primary Communication
Interfaces (Automotive)
CAN-FD
Radar Hardware
Accelerator
DMA
Debug
UARTs
For debug
Main Sub-System
(Customer Programmed)
Test/Debug
JTAG for debug/development
Phase
Shift
ADC
Buffer
PA
Mailbox
High-speed ADC output
interface (for recording)
LVDS
HIL
Ramp
Generator
Phase
Shift
Synth
(20 GHz)
PA
x3
High-speed input for hardware-in-
loop verification
C674x DSP
@600 MHz
Phase
Shift
PA
Radio (BIST)
Processor
6
L1P
(32kB)
L1D
(32kB)
L2
(256kB)
GPADC
(For RF Calibration
& Self-Test œ TI
Programmed)
DMA
CRC
Prog RAM
& ROM
Data
RAM
Temp
Osc.
Radar Data Memory
(L3)
DSP Sub-System
(Customer Programmed)
Radio Processor
Sub-System
(TI Programmed)
RF/Analog Sub-System
Figure 3-1. Functional Block Diagram
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................2
3.1 Functional Block Diagram...........................................3
4 Revision History.............................................................. 5
5 Device Comparison.........................................................6
5.1 Related Products........................................................ 7
6 Terminal Configuration and Functions..........................8
6.1 Pin Diagram................................................................ 8
6.2 Pin Attributes...............................................................9
6.3 Signal Descriptions................................................... 22
7 Specifications................................................................ 27
7.1 Absolute Maximum Ratings...................................... 27
7.2 ESD Ratings............................................................. 27
7.3 Power-On Hours (POH)............................................27
7.4 Recommended Operating Conditions.......................28
7.5 Power Supply Specifications.....................................29
7.6 Power Consumption Summary................................. 30
7.7 RF Specification........................................................31
7.8 CPU Specifications................................................... 31
7.9 Thermal Resistance Characteristics for FCBGA
8 Detailed Description......................................................62
8.1 Overview...................................................................62
8.2 Functional Block Diagram.........................................62
8.3 Subsystems.............................................................. 63
8.4 Other Subsystems.................................................... 71
9 Monitoring and Diagnostics......................................... 73
9.1 Monitoring and Diagnostic Mechanisms................... 73
10 Applications, Implementation, and Layout............... 78
10.1 Application Information........................................... 78
10.2 Reference Schematic..............................................78
11 Device and Documentation Support..........................79
11.1 Device Nomenclature..............................................79
11.2 Tools and Software..................................................80
11.3 Documentation Support.......................................... 80
11.4 Support Resources................................................. 80
11.5 Trademarks............................................................. 80
11.6 Electrostatic Discharge Caution..............................81
11.7 Glossary..................................................................81
12 Mechanical, Packaging, and Orderable
Information.................................................................... 82
12.1 Packaging Information............................................ 82
12.2 Tray Information for ALP, 15 × 15 mm.................... 82
Package [ALP0180A].................................................. 32
7.10 Timing and Switching Characteristics..................... 32
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4 Revision History
Changes from March 29, 2021 to September 15, 2021 (from Revision * (March 2021) to
Revision A (September 2021))
Page
•
Global: Updated/Changed AWR1843AOP device information and document Product Status from "Advanced
Information" to "Production Data (PD)" ..............................................................................................................1
Global: Updated/Changed Master Subsystem to Main Subsystem and Masters R4F to MSS R4F...................1
(Features): Added Auto Temp Range bullet....................................................................................................... 1
(Features): Updated/changed the TX power and RX noise................................................................................1
(Applications): Deleted Occupancy and Gesture Applications .......................................................................... 1
(Applications): Add a system block diagram.......................................................................................................1
(Device Information): Added RTM orderable part numbers ...............................................................................2
(Device Information): Updated table...................................................................................................................2
(Pin Attributes): Updated/Changed ball number C2 to show correct signal name as "CAN_TX"....................... 9
(Pin Attributes): Updated/Changed ball number D2 to show correct signal name as "CAN_RX".......................9
(Pin Functions): Added a row for signal name "CAN_RX" to the list and reassociated ball no. D2. Deleted D2
from CAN_FD_RX row......................................................................................................................................22
(Pin Functions): Added a row for signal name "CAN_TX" to the list and reassociated ball no. C2. Deleted C2
from CAN_FD_TX row......................................................................................................................................22
(Power Supply Specifications) : Additional details on ripple specifications are added..................................... 29
(Power Consumption Summary) : Updated Average Power Consumption at Power Terminals.......................30
(RF Specification): Updated Antenna row for Tx and Rx..................................................................................31
Updated/changed Receiver Antenna Radiation Pattern image........................................................................ 33
Added new image RX Effective Isotropic Noise Figure ................................................................................... 33
Updated/changed Transmitter Antenna Radiation Pattern image.................................................................... 36
Updated/changed temperature range max for Crystal Electrical Characteristics (Oscillator Mode).................39
(Processor Subsystem): Updated image for inclusive terminology.................................................................. 66
(GP-ADC Parameter): Added a table for GPADC specifications...................................................................... 71
Updated/Changed Device Nomenclature image to reflect Safety Level B....................................................... 79
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5 Device Comparison
Table 5-1 shows a comparison between devices, highlighting the differences.
Table 5-1. Device Features Comparison
FUNCTION
Antenna on Package (AOP)
Number of receivers
AWR6843AOP
AWR1843AOP
AWR1843
AWR1642
AWR1443
Yes
Yes
—
—
—
4
3(1)
4
4
4
4
Number of transmitters
RF frequency range
3(1)
76 to 81 GHz
2MB
3(1)
76 to 81 GHz
2MB
2
76 to 81 GHz
1.5MB
5
3
76 to 81 GHz
576KB
5
60 to 64 GHz
1.75MB
10
On-chip memory
Max I/F (Intermediate Frequency) (MHz)
Max real sampling rate (Msps)
Max complex sampling rate (Msps)
Processors
10
10
25
25
25
12.5
12.5
12.5
12.5
12.5
6.25
6.25
MCU (Arm Cortex-R4F)
DSP (C674x)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Peripherals
Serial Peripheral Interface (SPI) ports
Quad Serial Peripheral Interface (QSPI)
Inter-Integrated Circuit (I2C) interface
Controller Area Network (DCAN) interface
Controller Area Network (CAN-FD) interface
Trace
2
2
2
2
1
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
—
1
1
1
1
2
1
1
1
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
PWM
—
Hardware In Loop (HIL/DMM)
GPADC
—
Yes
Yes
Yes
Yes
Yes
LVDS/Debug
Hardware accelerator
1-V bypass mode
Yes
Yes
JTAG
Product Preview (PP),
Product
Advance Information (AI),
status
PD(2)
PD(2)
PD(2)
PD(2)
PD(2)
or Production Data (PD)
(1) 3 Tx Simultaneous operation is supported only with 1-V LDO bypass and PA LDO disable mode. In this mode, the 1-V supply needs to
be fed on the VOUT PA pin.
(2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty.
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5.1 Related Products
For information about other devices in this family of products or related products see the links that follow.
mmWave Sensors
TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with
less power using the smallest footprint mmWave sensor portfolio for automotive
applications.
Automotive mmWave TI’s automotive mmWave sensor portfolio offers high-performance radar front end to
Sensors
ultra-high resolution, small and low-power single-chip radar solutions. TI’s scalable
sensor portfolio enables design and development of ADAS system solution for every
performance, application and sensor configuration ranging from comfort functions to
safety functions in all vehicles.
Companion Products Review products that are frequently purchased or used in conjunction with this
for AWR1843AOP product.
Reference Designs for TI Designs Reference Design Library is a robust reference design library spanning
AWR1843AOP
analog, embedded processor and connectivity. Created by TI experts to help you
jump-start your system design, all TI Designs include schematic or block diagrams,
BOMs and design files to speed your time to market. Search and download designs at
ti.com/tidesigns.
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6 Terminal Configuration and Functions
6.1 Pin Diagram
Figure 6-1 shows the pin locations for the 180-pin 15 × 15 mm FCBGA package.
Figure 6-1. Pin Diagram
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6.2 Pin Attributes
Table 6-1. Pin Attributes (ALP180A Package)
PINCNTL
BALL RESET
STATE [7]
PULL UP/DOWN
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
MODE [5] [9]
TYPE [6]
ADDRESS [4]
TYPE [8]
M2
GPIO_0
GPIO_13
0xFFFFEA04
0
IO
IO
O
O
O
O
IO
IO
O
O
I
Output Disabled
Pull Down
GPIO_0
1
PMIC_CLKOUT
ADC_VALID
EPWM1B
2
7
10
11
0
ePWM2A
L3
GPIO_1
GPIO_16
0xFFFFEA08
Output Disabled
Pull Down
GPIO_1
1
SYNC_OUT
ADC_VALID
DMM_MUX_IN
SPIB_CS_N_1
SPIB_CS_N_2
EPWM1SYNCI
GPIO_26
2
7
12
13
14
15
0
IO
IO
I
K3
GPIO_2
0xFFFFEA64
IO
IO
O
O
O
O
O
O
O
O
O
IO
I
Output Disabled
Pull Down
GPIO_2
1
OSC_CLKOUT
MSS_UARTB_TX
BSS_UART_TX
SYNC_OUT
PMIC_CLKOUT
CHIRP_START
CHIRP_END
FRAME_START
TRACE_DATA_0
GPIO_31
2
7
8
9
10
11
12
13
0
U7
GPIO_31 (DP0)
0xFFFFEA7C
Output Disabled
Pull Down
1
DMM0
2
MSS_UARTA_TX
TRACE_DATA_1
GPIO_32
4
IO
O
IO
I
U6
V5
GPIO_32 (DP1)
GPIO_33 (DP2)
0xFFFFEA80
0xFFFFEA84
0
Output Disabled
Output Disabled
Pull Down
Pull Down
1
DMM1
2
TRACE_DATA_2
GPIO_33
0
O
IO
I
1
DMM2
2
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Table 6-1. Pin Attributes (ALP180A Package) (continued)
PINCNTL
BALL RESET
STATE [7]
PULL UP/DOWN
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
MODE [5] [9]
TYPE [6]
ADDRESS [4]
TYPE [8]
U5
V3
M1
L2
GPIO_34 (DP3)
GPIO_35 (DP4)
GPIO_36 (DP5)
GPIO_37 (DP6)
GPIO_38 (DP7)
GPIO_39 (DP8)
TRACE_DATA_3
GPIO_34
0xFFFFEA88
0
1
2
4
0
1
2
4
0
1
2
5
0
1
2
5
0
1
2
5
0
1
2
4
5
0
1
2
4
5
0
1
2
4
O
IO
I
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Pull Down
Pull Down
Pull Down
Pull Down
Pull Down
Pull Down
DMM3
EPWM3SYNCO
TRACE_DATA_4
GPIO_35
O
O
IO
I
0xFFFFEA8C
0xFFFFEA90
0xFFFFEA94
0xFFFFEA98
0xFFFFEA9C
DMM4
EPWM2SYNCO
TRACE_DATA_5
GPIO_36
O
O
IO
I
DMM5
MSS_UARTB_TX
TRACE_DATA_6
GPIO_37
O
O
IO
I
DMM6
BSS_UART_TX
TRACE_DATA_7
GPIO_38
O
O
IO
I
L1
DMM7
DSS_UART_TX
TRACE_DATA_8
GPIO_39
O
O
IO
I
C3
DMM8
CAN_FD_TX
EPWM1SYNCI
TRACE_DATA_9
GPIO_40
O
I
B3
C4
GPIO_40 (DP9)
0xFFFFEAA0
0xFFFFEAA4
O
IO
I
Output Disabled
Pull Down
DMM9
CAN_FD_RX
EPWM1SYNCO
TRACE_DATA_10
GPIO_41
I
O
O
IO
I
GPIO_41 (DP10)
Output Disabled
Pull Down
DMM10
EPWM3A
O
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Table 6-1. Pin Attributes (ALP180A Package) (continued)
PINCNTL
BALL RESET
STATE [7]
PULL UP/DOWN
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
MODE [5] [9]
TYPE [6]
ADDRESS [4]
TYPE [8]
A3
B4
GPIO_42 (DP11)
GPIO_43 (DP12)
TRACE_DATA_11
GPIO_42
0xFFFFEAA8
0
1
2
4
0
1
2
4
5
0
1
2
4
5
0
1
2
4
0
1
2
4
0
1
2
0
2
0
1
2
6
7
12
0
0
O
IO
I
Output Disabled
Pull Down
Pull Down
DMM11
EPWM3B
O
O
IO
I
TRACE_DATA_12
GPIO_43
0xFFFFEAAC
0xFFFFEAB0
Output Disabled
DMM12
EPWM1A
O
O
O
IO
I
CAN_FD_TX
TRACE_DATA_13
GPIO_44
A4
GPIO_44 (DP13)
Output Disabled
Pull Down
DMM13
EPWM1B
O
I
CAN_FD_RX
TRACE_DATA_14
GPIO_45
C5
B5
U3
GPIO_45 (DP14)
GPIO_46 (DP15)
0xFFFFEAB4
0xFFFFEAB8
0xFFFFEABC
O
IO
I
Output Disabled
Output Disabled
Output Disabled
Pull Down
Pull Down
Pull Down
DMM14
EPWM2A
O
O
IO
I
TRACE_DATA_15
GPIO_46
DMM15
EPWM2B
O
O
IO
I
GPIO_47 (DMM_CLK)
TRACE_CLK
GPIO_47
DMM_CLK
TRACE_CTL
DMM_SYNC
GPIO_25
U4
DMM_SYNC
0xFFFFEAC0
0xFFFFEA60
O
I
Output Disabled
Output Disabled
Pull Down
Pull Down
V13
MCU_CLKOUT
IO
O
O
O
O
O
I
MCU_CLKOUT
CHIRP_START
CHIRP_END
FRAME_START
EPWM1A
U14
U15
NERROR_IN
NERROR_IN
NERROR_OUT
0xFFFFEA44
0xFFFFEA4C
Input
NERROR_OUT
O
Hi-Z (Open Drain)
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Table 6-1. Pin Attributes (ALP180A Package) (continued)
PINCNTL
BALL RESET
STATE [7]
PULL UP/DOWN
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
MODE [5] [9]
TYPE [6]
ADDRESS [4]
TYPE [8]
V10
PMIC_CLKOUT
SOP[2]
0xFFFFEA68
During Power Up
I
Output Disabled
Pull Down
GPIO_27
0
IO
O
O
O
O
O
O
IO
IO
IO
IO
I
PMIC_CLKOUT
CHIRP_START
CHIRP_END
FRAME_START
EPWM1B
1
6
7
8
11
12
0
EPWM2A
H3
G2
QSPI[0]
QSPI[1]
GPIO_8
0xFFFFEA2C
0xFFFFEA30
Output Disabled
Output Disabled
Pull Down
Pull Down
QSPI[0]
1
SPIB_MISO
GPIO_9
2
0
QSPI[1]
1
SPIB_MOSI
SPIB_CS_N_2
GPIO_10
2
IO
IO
IO
I
8
J3
QSPI[2]
0xFFFFEA34
0xFFFFEA38
0xFFFFEA3C
0
Output Disabled
Output Disabled
Output Disabled
Pull Down
Pull Down
Pull Down
QSPI[2]
1
CAN_FD_TX
GPIO_11
8
O
IO
I
K2
H2
QSPI[3]
0
QSPI[3]
1
CAN_FD_RX
GPIO_7
8
I
QSPI_CLK
0
IO
O
IO
O
IO
O
IO
IO
I
QSPI_CLK
SPIB_CLK
DSS_UART_TX
GPIO_6
1
2
6
J2
QSPI_CS_N
RS232_RX
0xFFFFEA40
0xFFFFEA74
0
Output Disabled
Input Enabled
Pull Up
Pull Up
QSPI_CS_N
SPIB_CS_N
GPIO_15
1
2
V16
0
RS232_RX
MSS_UARTA_RX
BSS_UART_TX
MSS_UARTB_RX
CAN_FD_RX
I2C_SCL
1
2
I
6
IO
IO
I
7
8
9
IO
O
O
O
EPWM2A
10
11
12
EPWM2B
EPWM3A
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Table 6-1. Pin Attributes (ALP180A Package) (continued)
PINCNTL
BALL RESET
STATE [7]
PULL UP/DOWN
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
MODE [5] [9]
TYPE [6]
ADDRESS [4]
TYPE [8]
U16
RS232_TX
GPIO_14
0xFFFFEA78
0
IO
O
IO
IO
IO
O
IO
O
O
I
Output Enabled
RS232_TX
1
MSS_UARTA_TX
MSS_UARTB_TX
BSS_UART_TX
CAN_FD_TX
I2C_SDA
5
6
7
10
11
12
13
14
15
0
EPWM1A
EPWM1B
NDMM_EN
EPWM2A
O
IO
IO
I
D2
SPIA_CLK
GPIO_3
0xFFFFEA14
Output Disabled
Pull Up
SPIA_CLK
1
CAN_RX
6
DSS_UART_TX
GPIO_30
7
O
IO
IO
O
IO
IO
O
IO
IO
I
C2
D1
F2
SPIA_CS_N
SPIA_MISO
SPIA_MOSI
0xFFFFEA18
0xFFFFEA10
0xFFFFEA0C
0
Output Disabled
Output Disabled
Output Disabled
Pull Up
Pull Up
Pull Up
SPIA_CS_N
CAN_TX
1
6
GPIO_20
0
SPIA_MISO
CAN_FD_TX
GPIO_19
1
2
0
SPIA_MOSI
CAN_FD_RX
DSS_UART_TX
GPIO_5
1
2
8
O
IO
IO
I
E2
SPIB_CLK
0xFFFFEA24
0
Output Disabled
Pull Up
SPIB_CLK
1
MSS_UARTA_RX
MSS_UARTB_TX
BSS_UART_TX
CAN_FD_RX
GPIO_4
2
6
O
O
I
7
8
D3
SPIB_CS_N
0xFFFFEA28
0
IO
IO
O
O
IO
I
Output Disabled
Pull Up
SPIB_CS_N
MSS_UARTA_TX
MSS_UARTB_TX
BSS_UART_TX
QSPI_CLK_EXT
CAN_FD_TX
1
2
6
7
8
9
O
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Table 6-1. Pin Attributes (ALP180A Package) (continued)
PINCNTL
BALL RESET
STATE [7]
PULL UP/DOWN
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
MODE [5] [9]
TYPE [6]
ADDRESS [4]
TYPE [8]
G3
SPIB_MISO
GPIO_22
0xFFFFEA20
0
IO
IO
IO
O
IO
IO
IO
IO
O
O
IO
IO
I
Output Disabled
Pull Up
SPIB_MISO
I2C_SCL
1
2
DSS_UART_TX
GPIO_21
6
G1
B2
SPIB_MOSI
0xFFFFEA1C
0xFFFFEA00
0
Output Disabled
Output Disabled
Pull Up
SPIB_MOSI
I2C_SDA
1
2
SPI_HOST_INTR
GPIO_12
0
Pull Down
SPI_HOST_INTR
ADC_VALID
SPIB_CS_N_1
GPIO_28
1
2
6
U12
SYNC_IN
0xFFFFEA6C
0xFFFFEA70
0
Output Disabled
Pull Down
SYNC_IN
1
MSS_UARTB_RX
DMM_MUX_IN
SYNC_OUT
SOP[1]
6
IO
I
7
9
O
I
M3
SYNC_OUT
During Power Up
Output Disabled
Pull Down
GPIO_29
0
IO
O
I
SYNC_OUT
DMM_MUX_IN
SPIB_CS_N_1
SPIB_CS_N_2
GPIO_17
1
9
10
IO
IO
IO
I
11
T3
TCK
0xFFFFEA50
0
Input Enabled
Pull Down
Pull Up
TCK
1
MSS_UARTB_TX
CAN_FD_TX
GPIO_23
2
O
O
IO
I
8
U9
TDI
0xFFFFEA58
0xFFFFEA5C
0
Input Enabled
TDI
1
MSS_UARTA_RX
SOP[0]
2
I
U10
TDO
During Power Up
I
Output Enabled
GPIO_24
0
1
2
6
7
9
IO
O
O
O
O
I
TDO
MSS_UARTA_TX
MSS_UARTB_TX
BSS_UART_TX
NDMM_EN
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Table 6-1. Pin Attributes (ALP180A Package) (continued)
PINCNTL
BALL RESET
STATE [7]
PULL UP/DOWN
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
MODE [5] [9]
TYPE [6]
ADDRESS [4]
TYPE [8]
U8
TMS
GPIO_18
0xFFFFEA54
0
1
2
6
0
IO
I
Input Enabled
Pull Down
TMS
BSS_UART_TX
CAN_FD_RX
WARM_RESET
O
I
U13
WARM_RESET
0xFFFFEA48
IO
Hi-Z Input (Open
Drain)
R2
R1
N2
N1
P2
LVDS_CLKM
LVDS_CLKP
LVDS_TXP[0]
LVDS_TXM[0]
LVDS_TXP[1]
LVDS_TXM[1]
LVDS_FRCLKP
LVDS_FRCLKM
NRESET
LVDS_CLKM
LVDS_CLKP
LVDS_TXP[0]
LVDS_TXM[0]
LVDS_TXP[1]
LVDS_TXM[1]
LVDS_FRCLKP
LVDS_FRCLKM
NRESET
O
O
O
O
O
P1
O
T1
O
T2
O
U11
A7
I
CLKP
CLKP
I
B7
CLKM
CLKM
I
A14
A16
E1
OSC_CLKOUT
VBGAP
OSC_CLKOUT
VBGAP
O
O
VDDIN
VDDIN
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
J1
VDDIN
VDDIN
V4
VDDIN
VDDIN
V8
VDDIN
VDDIN
V15
A5
VDDIN
VDDIN
VIN_SRAM
VIN_SRAM
VIN_SRAM
VNWA
VIN_SRAM
VIN_SRAM
VIN_SRAM
VNWA
V6
V12
C1
V7
VNWA
VNWA
V14
H1
V9
VNWA
VNWA
VIOIN
VIOIN
VIOIN
VIOIN
B1
VIOIN_18
VIOIN_18
VIOIN_18
VIOIN_18
VIN_18CLK
VIN_18CLK
VIOIN_18DIFF
VIOIN_18
VIOIN_18
VIOIN_18
VIOIN_18
VIN_18CLK
VIN_18CLK
VIOIN_18DIFF
F1
K1
V11
C15
C18
U2
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Table 6-1. Pin Attributes (ALP180A Package) (continued)
PINCNTL
BALL RESET
STATE [7]
PULL UP/DOWN
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
MODE [5] [9]
TYPE [6]
ADDRESS [4]
TYPE [8]
V2
VPP
VPP
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J16
J17
J18
H16
H17
H18
M16
M17
M18
A12
C11
A1
VIN_13RF1
VIN_13RF1
VIN_13RF1
VIN_13RF2
VIN_13RF2
VIN_13RF2
VIN_18BB
VIN_18BB
VIN_18BB
VIN_18VCO
VIN_18VCO
VSS
VIN_13RF1
VIN_13RF1
VIN_13RF1
VIN_13RF2
VIN_13RF2
VIN_13RF2
VIN_18BB
VIN_18BB
VIN_18BB
VIN_18VCO
VIN_18VCO
VSS
A2
VSS
VSS
E3
VSS
VSS
F3
VSS
VSS
N3
VSS
VSS
P3
VSS
VSS
R3
VSS
VSS
T4
VSS
VSS
T5
VSS
VSS
T6
VSS
VSS
T7
VSS
VSS
T8
VSS
VSS
T9
VSS
VSS
T10
T11
T12
T13
T14
T15
T16
U1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V1
VSS
VSS
A6
VSSA
VSSA
A8
VSSA
VSSA
A11
A13
A15
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
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Table 6-1. Pin Attributes (ALP180A Package) (continued)
PINCNTL
BALL RESET
STATE [7]
PULL UP/DOWN
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
MODE [5] [9]
TYPE [6]
ADDRESS [4]
TYPE [8]
A17
A18
B6
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
C6
C7
C8
C12
C13
C14
C16
C17
D16
D17
D18
E16
E17
E18
F16
F17
F18
K16
K17
K18
L16
L17
L18
N16
N17
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Table 6-1. Pin Attributes (ALP180A Package) (continued)
PINCNTL
BALL RESET
STATE [7]
PULL UP/DOWN
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
MODE [5] [9]
TYPE [6]
ADDRESS [4]
TYPE [8]
N18
P16
R16
R17
T17
U17
U18
V17
V18
A10
A9
VSSA
VSSA
GND
GND
GND
GND
GND
GND
GND
GND
GND
O
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VOUT_14APLL
VOUT_14SYNTH
VOUT_PA
VOUT_PA
VOUT_PA
VOUT_14APLL
VOUT_14SYNTH
VOUT_PA
VOUT_PA
VOUT_PA
O
G16
G17
G18
P18
P17
R18
T18
C9
IO
IO
IO
Analog Test1 / GPADC1
Analog Test2 / GPADC2
Analog Test3 / GPADC3
Analog Test4 / GPADC4
ANAMUX / GPADC5
Analog Test1 / GPADC1
Analog Test2 / GPADC2
Analog Test3 / GPADC3
Analog Test4 / GPADC4
ANAMUX / GPADC5
IO
IO
IO
IO
IO
C10
VSENSE / GPADC6
VSENSE / GPADC6
IO
The following list describes the table column headers:
1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
2. BALL NAME: Mechanical name from package device (name is taken from muxmode 1).
3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 1).
4. PINCNTL ADDRESS: MSS Address for PinMux Control
5. MODE: Multiplexing mode number: value written to PinMux Cntl register to select specific Signal name for this Ball number. Mode column has bit
range value.
6. TYPE: Signal type and direction:
•
•
•
I = Input
O = Output
IO = Input or Output
7. BALL RESET STATE: The state of the terminal after supplies are stable after power-on-reset (NRESET) is asserted
8. PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled
via software.
•
•
Pull Up: Internal pullup
Pull Down: Internal pulldown
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•
An empty box means No pull.
9. Pin Mux Control Value maps to lower 4 bits of register.
IO MUX registers are available in the MSS memory map and the respective mapping to device pins is as follows:
Table 6-2. PAD IO Control Registers
Default Pin/Ball Name
SPI_HOST_INTR
GPIO_0
Package Ball /Pin (Address)
Pin Mux Config Register
0xFFFFEA00
0xFFFFEA04
0xFFFFEA08
0xFFFFEA0C
0xFFFFEA10
0xFFFFEA14
0xFFFFEA18
0xFFFFEA1C
0xFFFFEA20
0xFFFFEA24
0xFFFFEA28
0xFFFFEA2C
0xFFFFEA30
0xFFFFEA34
0xFFFFEA38
0xFFFFEA3C
0xFFFFEA40
0xFFFFEA44
0xFFFFEA48
0xFFFFEA4C
0xFFFFEA50
0xFFFFEA54
0xFFFFEA58
0xFFFFEA5C
0xFFFFEA60
0xFFFFEA64
0xFFFFEA68
0xFFFFEA6C
B2
M2
L3
GPIO_1
SPIA_MOSI
SPIA_MISO
SPIA_CLK
SPIA_CS_N
SPIB_MOSI
SPIB_MISO
SPIB_CLK
SPIB_CS_N
QSPI[0]
F2
D1
D2
C2
G1
G3
E2
D3
H3
G2
J3
QSPI[1]
QSPI[2]
QSPI[3]
K2
QSPI_CLK
QSPI_CS_N
NERROR_IN
WARM_RESET
NERROR_OUT
TCK
H2
J2
U14
U13
U15
T3
TMS
U8
U9
U10
V13
K3
TDI
TDO
MCU_CLKOUT
GPIO_2
PMIC_CLKOUT
SYNC_IN
V10
U12
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Table 6-2. PAD IO Control Registers (continued)
Default Pin/Ball Name
SYNC_OUT
RS232_RX
RS232_TX
GPIO_31
Package Ball /Pin (Address)
Pin Mux Config Register
0xFFFFEA70
0xFFFFEA74
0xFFFFEA78
0xFFFFEA7C
0xFFFFEA80
0xFFFFEA84
0xFFFFEA88
0xFFFFEA8C
0xFFFFEA90
0xFFFFEA94
0xFFFFEA98
0xFFFFEA9C
0xFFFFEAA0
0xFFFFEAA4
0xFFFFEAA8
0xFFFFEAAC
0xFFFFEAB0
0xFFFFEAB4
0xFFFFEAB8
0xFFFFEABC
0xFFFFEAC0
M3
V16
U16
U7
U6
V5
U5
V3
M1
L2
GPIO_32
GPIO_33
GPIO_34
GPIO_35
GPIO_36
GPIO_37
GPIO_38
L1
GPIO_39
C3
B3
C4
A3
B4
A4
C5
B5
U3
U4
GPIO_40
GPIO_41
GPIO_42
GPIO_43
GPIO_44
GPIO_45
GPIO_46
GPIO_47
DMM_SYNC
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The register layout is as follows:
Table 6-3. PAD IO Register Bit Descriptions
RESET (POWER
ON DEFAULT)
BIT
FIELD
TYPE
DESCRIPTION
31-11 NU
RW
RW
0
0
Reserved
10
9
SC
IO slew rate control:
0 = Higher slew rate
1 = Lower slew rate
PUPDSEL
PI
RW
RW
0
0
Pullup/PullDown Selection
0 = Pull Down
1 = Pull Up (This field is valid only if Pull Inhibit is set as '0')
8
Pull Inhibit/Pull Disable
0 = Enable
1 = Disable
7
6
OE_OVERRIDE
RW
RW
1
1
Output Override
OE_OVERRIDE_CTRL
Output Override Control:
(A '1' here overrides any o/p manipulation of this IO by any of the peripheral block hardware it is
associated with for example a SPI Chip select)
5
4
IE_OVERRIDE
RW
RW
0
0
Input Override
IE_OVERRIDE_CTRL
Input Override Control:
(A '1' here overrides any i/p value on this IO with a desired value)
3-0
FUNC_SEL
RW
1
Function select for Pin Multiplexing (Refer to the Pin Mux Sheet)
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6.3 Signal Descriptions
Note
All IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET) are non-failsafe;
hence, care needs to be taken that they are not driven externally without the VIO supply being present
to the device.
Note
The GPIO state during the power supply ramp is not ensured. In case the GPIO is used in the
application where the state of the GPIO is critical, even when NRESET is low , a tri-state buffer
should be used to isolate the GPIO output from the radar device and a pull resister used to define the
required state in the application. The NRESET signal to the radar device could be used to control the
output enable (OE) of the tri-state buffer.
6.3.1 Pin Functions - Digital and Analog [ALP Package]
Table 6-4 lists the pins by function and describes that function.
Table 6-4. Pin Functions - Digital and Analog [ALP Package]
NAME
I/O
DESCRIPTION
NO.
DIGITAL
D3, E2, K3, L2, U8, U10,
U16, V16
BSS_UART_TX
CAN_FD_RX
CAN_FD_TX
O
I
Debug UART Transmit [Radar Block]
CAN FD (MCAN) Receive Signal
CAN FD (MCAN) Transmit Signal
A4, B3, E2, F2, K2, U8,
V16
B4, C3, D1, D3, J3, T3,
U16
O
CAN_RX
CAN_TX
DMM0
CAN (DCAN) Receive Signal
D2
C2
U7
U6
V5
U5
V3
M1
L2
CAN (DCAN) Transmit Signal
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Clock
DMM1
DMM2
DMM3
DMM4
DMM5
DMM6
DMM7
L1
DMM8
C3
B3
C4
A3
B4
A4
C5
B5
U3
DMM9
DMM10
DMM11
DMM12
DMM13
DMM14
DMM15
DMM_CLK
Debug Interface (Hardware In Loop) Mux Select between DMM1 and
DMM2 (Two Instances)
DMM_MUX_IN
I
L3, M3, U12
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Table 6-4. Pin Functions - Digital and Analog [ALP Package] (continued)
NAME
I/O
DESCRIPTION
Debug Interface (Hardware In Loop) - Sync
Debug UART Transmit [DSP]
PWM Module 1 - Output A
PWM Module 1 - Output B
PWM Module 1 - Sync Input
PWM Module 1 - Sync Output
PWM Module 2- Output A
PWM Module 2 - Output B
PWM Module 2 - Sync Output
PWM Module 3 - Output A
PWM Module 3 - Output A
PWM Module 3 - Sync Output
General-purpose I/O
NO.
DMM_SYNC
DSS_UART_TX
EPWM1A
EPWM1B
EPWM1SYNCI
EPWM1SYNCO
EPWM2A
EPWM2B
EPWM2SYNCO
EPWM3A
EPWM3B
EPWM3SYNCO
GPIO_0
I
U4
O
D2, F2, G3, H2, L1
O
B4, U16, V13
O
A4, M2, U16, V10
I
C3, L3
I
B3
O
C5, M2, U16, V10, V16
O
B5, V16
V3
O
O
C4, V16
A3
O
O
U5
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
M2
L3
GPIO_1
General-purpose I/O
GPIO_2
General-purpose I/O
K3
GPIO_3
General-purpose I/O
D2
GPIO_4
General-purpose I/O
D3
GPIO_5
General-purpose I/O
E2
GPIO_6
General-purpose I/O
J2
GPIO_7
General-purpose I/O
H2
GPIO_8
General-purpose I/O
H3
GPIO_9
General-purpose I/O
G2
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
General-purpose I/O
J3
General-purpose I/O
K2
General-purpose I/O
B2
General-purpose I/O
M2
U16
V16
L3
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
T3
General-purpose I/O
U8
General-purpose I/O
F2
General-purpose I/O
D1
General-purpose I/O
G1
General-purpose I/O
G3
General-purpose I/O
U9
General-purpose I/O
U10
V13
K3
General-purpose I/O
General-purpose I/O
General-purpose I/O
V10
U12
M3
C2, D2
U7
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
U6
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Table 6-4. Pin Functions - Digital and Analog [ALP Package] (continued)
NAME
I/O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
DESCRIPTION
NO.
V5
U5
V3
M1
L2
GPIO_33
GPIO_34
GPIO_35
GPIO_36
GPIO_37
GPIO_38
GPIO_39
GPIO_40
GPIO_41
GPIO_42
GPIO_43
GPIO_44
GPIO_45
GPIO_46
GPIO_47
I2C_SCL
I2C_SDA
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
I2C Clock
L1
C3
B3
C4
A3
B4
A4
C5
B5
U3
G3, V16
I2C Data
G1, U16
LVDS_TXP[0]
Differential data Out – Lane 0
Differential data Out – Lane 0
Differential data Out – Lane 1
Differential data Out – Lane 1
Differential clock Out
N2
LVDS_TXM[0]
LVDS_TXP[1]
O
N1
O
P2
LVDS_TXM[1]
LVDS_CLKP
O
P1
O
R1
LVDS_CLKM
O
Differential clock Out
R2
T1
LVDS_FRCLKP
LVDS_FRCLKM
MCU_CLKOUT
MSS_UARTA_RX
MSS_UARTA_TX
MSS_UARTB_RX
O
Differential Frame Clock
O
Differential Frame Clock
T2
O
Programmable clock given out to external MCU or the processor
Main Subsystem - UART A Receive
Main Subsystem - UART A Transmit
Main Subsystem - UART B Receive
V13
I
E2, U9, V16
D3, U7, U10, U16
U12, V16
O
IO
D3, E2, K3, M1, T3, U10,
U16
MSS_UARTB_TX
NDMM_EN
O
I
Main Subsystem - UART B Transmit
Debug Interface (Hardware In Loop) Enable - Active Low Signal
U10, U16
Failsafe input to the device. Nerror output from any other device
can be concentrated in the error signaling monitor module inside the
device and appropriate action can be taken by Firmware
NERROR_IN
I
U14
Open drain fail safe output signal. Connected to PMIC/
Processor/MCU to indicate that some severe criticality fault has
happened. Recovery would be through reset.
NERROR_OUT
O
U15
PMIC_CLKOUT
QSPI[0]
O
IO
I
Output Clock from AWR6843AOP device for PMIC
QSPI Data Line #0 (Used with Serial Data Flash)
QSPI Data Line #1 (Used with Serial Data Flash)
QSPI Data Line #2 (Used with Serial Data Flash)
QSPI Data Line #3 (Used with Serial Data Flash)
QSPI Clock (Used with Serial Data Flash)
K3, M2, V10
H3
G2
J3
QSPI[1]
QSPI[2]
I
QSPI[3]
I
K2
H2
D3
J2
QSPI_CLK
QSPI_CLK_EXT
QSPI_CS_N
RS232_RX
O
I
QSPI Clock (Used with Serial Data Flash)
O
I
QSPI Chip Select (Used with Serial Data Flash)
Debug UART (Operates as Bus Master) - Receive Signal
V16
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Table 6-4. Pin Functions - Digital and Analog [ALP Package] (continued)
NAME
I/O
O
I
DESCRIPTION
Debug UART (Operates as Bus Master) - Transmit Signal
Sense On Power - Line#0
NO.
RS232_TX
U16
SOP[0]
U10
SOP[1]
I
Sense On Power - Line#1
M3
SOP[2]
I
Sense On Power - Line#2
V10
SPIA_CLK
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
I
SPI Channel A - Clock
D2
SPIA_CS_N
SPIA_MISO
SPI Channel A - Chip Select
C2
SPI Channel A - Master In Slave Out
SPI Channel A - Master Out Slave In
SPI Channel B - Clock
D1
SPIA_MOSI
F2
SPIB_CLK
E2, H2
SPIB_CS_N
SPIB_CS_N_1
SPIB_CS_N_2
SPIB_MISO
SPI Channel B Chip Select (Instance ID 0)
SPI Channel B Chip Select (Instance ID 1)
SPI Channel B Chip Select (Instance ID 2)
SPI Channel B - Master In Slave Out
SPI Channel B - Master Out Slave In
Out of Band Interrupt to an external host communicating over SPI
Low frequency Synchronization signal input
Low Frequency Synchronization Signal output
JTAG Test Clock
D3, J2
B2, L3, M3
G2, L3, M3
G3, H3
SPIB_MOSI
G1, G2
SPI_HOST_INTR
SYNC_IN
B2
U12
SYNC_OUT
TCK
O
I
K3, L3, M3, U12
T3
TDI
I
JTAG Test Data Input
U9
TDO
O
I
JTAG Test Data Output
U10
TMS
JTAG Test Mode Signal
U8
TRACE_CLK
TRACE_CTL
TRACE_DATA_0
TRACE_DATA_1
TRACE_DATA_2
TRACE_DATA_3
TRACE_DATA_4
TRACE_DATA_5
TRACE_DATA_6
TRACE_DATA_7
TRACE_DATA_8
TRACE_DATA_9
TRACE_DATA_10
TRACE_DATA_11
TRACE_DATA_12
TRACE_DATA_13
TRACE_DATA_14
TRACE_DATA_15
FRAME_START
CHIRP_START
CHIRP_END
ADC_VALID
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Debug Trace Output - Clock
U3
Debug Trace Output - Control
U4
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Pulse signal indicating the start of each frame
Pulse signal indicating the start of each chirp
Pulse signal indicating the end of each chirp
When high, indicating valid ADC samples
U7
U6
V5
U5
V3
M1
L2
L1
C3
B3
C4
A3
B4
A4
C5
B5
K3, V10, V13
K3, V10, V13
K3, V10, V13
B2, L3, M2
Open drain fail safe warm reset signal. Can be driven from PMIC for
diagnostic or can be used as status signal that the device is going
through reset.
WARM_RESET
IO
U13
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Table 6-4. Pin Functions - Digital and Analog [ALP Package] (continued)
NAME
I/O
DESCRIPTION
NO.
ANALOG
NRESET
CLKP
I
I
Power on reset for chip. Active low
U11
A7
In XTAL mode: Differential port for reference crystal In External clock
mode: Single ended input reference clock port
In XTAL mode: Differential port for reference crystal In External clock
mode: Connect this port to ground
CLKM
I
B7
Reference clock output from clocking sub system after cleanup PLL
(1.4-V output voltage swing).
OSC_CLKOUT
O
A14, K3
VBGAP
VDDIN
O
Device's Band Gap Reference Output
1.2V digital power supply
A16
Power
Power
Power
E1, J1, V4, V8, V15
A5, V6, V12
VIN_SRAM
VNWA
1.2V power rail for internal SRAM
1.2V power rail for SRAM array back bias
C1, V7, V14
I/O Supply (3.3V or 1.8V): All CMOS I/Os would operate on this
supply
VIOIN
Power
H1, V9
VIOIN_18
VIN_18CLK
VIOIN_18DIFF
VPP
Power
Power
Power
Power
1.8V supply for CMOS IO
1.8V supply for clock module
1.8V supply for LVDS port
Voltage supply for fuse chain
B1, F1, K1, V11
C15, C18
U2
V2
1.3V Analog and RF supply,VIN_13RF1 and VIN_13RF2 could be
shorted on the board
VIN_13RF1
Power
J16, J17, J18
VIN_13RF2
VIN_18BB
VIN_18VCO
Power
Power
Power
1.3V Analog and RF supply
1.8V Analog base band power supply
1.8V RF VCO supply
H16, H17, H18
M16, M17, M18
A12, C11
A1, A2, E3, F3, N3, P3,
R3, T4, T5, T6, T7, T8, T9,
T10, T11, T12, T13, T14,
T15, T16, U1, V1
VSS
Ground
Ground
Digital ground
A6, A8, A11, A13, A15,
A17, A18, B6, B8, B9,
B10, B11, B12, B13, B14,
B15, B16, B17, B18, C6,
C7, C8, C12, C13, C14,
C16, C17, D16, D17, D18,
E16, E17, E18, F16, F17,
F18, K16, K17, K18, L16,
L17, L18, N16, N17, N18,
P16, R16, R17, T17, U17,
U18, V17, V18
VSSA
Analog ground
VOUT_14APLL
O
Internal LDO output
A10
VOUT_14SYNTH
O
Internal LDO output
A9
VOUT_PA
IO
IO
IO
IO
IO
IO
IO
Internal LDO output
G16, G17, G18
Analog Test1 / GPADC1
Analog Test2 / GPADC2
Analog Test3 / GPADC3
Analog Test4 / GPADC4
ANAMUX / GPADC5
VSENSE / GPADC6
Analog IO dedicated for ADC service
Analog IO dedicated for ADC service
Analog IO dedicated for ADC service
Analog IO dedicated for ADC service
Analog IO dedicated for ADC service
Analog IO dedicated for ADC service
P18
P17
R18
T18
C9
C10
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7 Specifications
7.1 Absolute Maximum Ratings
PARAMETERS(1) (2)
1.2 V digital power supply
MIN
–0.5
–0.5
–0.5
MAX
1.4
UNIT
VDDIN
V
V
V
VIN_SRAM
VNWA
1.2 V power rail for internal SRAM
1.4
1.2 V power rail for SRAM array back bias
1.4
I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this
supply.
VIOIN
–0.5
3.8
V
VIOIN_18
1.8 V supply for CMOS IO
1.8 V supply for clock module
1.8 V supply for LVDS port
–0.5
–0.5
–0.5
2
2
2
V
V
V
VIN_18CLK
VIOIN_18DIFF
VIN_13RF1
VIN_13RF2
VIN_13RF1
1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could
be shorted on the board.
–0.5
1.45
V
1-V Internal LDO bypass mode. Device supports mode
where external Power Management block can supply 1 V on
VIN_13RF1 and VIN_13RF2 rails. In this configuration, the
internal LDO of the device would be kept bypassed.
–0.5
1.4
V
VIN_13RF2
VIN_18BB
1.8-V Analog baseband power supply
1.8-V RF VCO supply
–0.5
–0.5
2
2
V
V
VIN_18VCO supply
Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)
–0.3V
VIOIN + 0.3
Input and output
voltage range
V
Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V
(Transient Overshoot/Undershoot) or external oscillator input
VIOIN + 20% up to
20% of signal period
CLKP, CLKM
Clamp current
Input ports for reference crystal
–0.5
2
V
Input or Output Voltages 0.3 V above or below their respective
power rails. Limit clamp current that flows through the internal
diode protection cells of the I/O.
–20
20
mA
TJ
Operating junction temperature range
–40
–55
125
150
°C
°C
TSTG
Storage temperature range after soldered onto PC board
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011(2)
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) Corner pins are rated as ±750 V
7.3 Power-On Hours (POH)
JUNCTION
OPERATING
CONDITION
TEMPERATURE (Tj)
NOMINAL CVDD VOLTAGE (V)
POWER-ON HOURS [POH] (HOURS)
(1) (2)
–40°C
75°C
600 (6%)
2000 (20%)
6500 (65%)
900 (9%)
100% duty cycle
1.2
95°C
125°C
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard
terms and conditions for TI semiconductor products.
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(2) The specified POH are applicable with max Tx output power settings using the default firmware gain tables. The specified POH would
not be applicable, if the Tx gain table is overwritten using an API.
7.4 Recommended Operating Conditions
MIN
1.14
1.14
1.14
3.15
1.71
1.71
1.71
1.71
NOM
1.2
1.2
1.2
3.3
1.8
1.8
1.8
1.8
MAX
1.32
1.32
1.32
3.45
1.89
1.9
UNIT
VDDIN
1.2 V digital power supply
V
V
V
VIN_SRAM
VNWA
1.2 V power rail for internal SRAM
1.2 V power rail for SRAM array back bias
I/O supply (3.3 V or 1.8 V):
All CMOS I/Os would operate on this supply.
VIOIN
V
VIOIN_18
1.8 V supply for CMOS IO
1.8 V supply for clock module
1.8 V supply for LVDS port
V
V
V
VIN_18CLK
VIOIN_18DIFF
VIN_13RF1
VIN_13RF2
1.9
1.9
1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2
could be shorted on the board
1.23
1.3
1.36
V
VIN_13RF1
(1-V Internal LDO
bypass mode)
Device supports mode where external Power Management
block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails.
In this configuration, the internal LDO of the device would be
kept bypassed.
0.95
1
1.05
V
VIN_13RF2
(1-V Internal LDO
bypass mode)
VIN18BB
1.8-V Analog baseband power supply
1.8V RF VCO supply
1.71
1.71
1.17
2.25
1.8
1.8
1.9
1.9
V
V
VIN_18VCO
Voltage Input High (1.8 V mode)
Voltage Input High (3.3 V mode)
Voltage Input Low (1.8 V mode)
Voltage Input Low (3.3 V mode)
High-level output threshold (IOH = 6 mA)
Low-level output threshold (IOL = 6 mA)
VIL (1.8V Mode)
VIH
VIL
V
V
0.3*VIOIN
0.62
VOH
VOL
VIOIN – 450
mV
mV
450
0.2
VIH (1.8V Mode)
0.96
1.57
NRESET
SOP[2:0]
V
VIL (3.3V Mode)
0.3
VIH (3.3V Mode)
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7.5 Power Supply Specifications
Table 7-1 describes the four rails from an external power supply block of the AWR1843AOP device.
Table 7-1. Power Supply Rails Characteristics
SUPPLY
DEVICE BLOCKS POWERED FROM THE SUPPLY
RELEVANT IOS IN THE DEVICE
Input: VIN_18VCO, VIN18CLK, VIN_18BB,
VIOIN_18DIFF, VIOIN_18IO
LDO Output: VOUT_14SYNTH, VOUT_14APLL
Synthesizer and APLL VCOs, crystal oscillator, IF
Amplifier stages, ADC, LVDS
1.8 V
1.3 V (or 1 V in internal
LDO bypass mode)(1)
Power Amplifier, Low Noise Amplifier, Mixers and LO
Distribution
Input: VIN_13RF2, VIN_13RF1
LDO Output: VOUT_PA
3.3 V (or 1.8 V for 1.8 V
I/O mode)
Digital I/Os
Input VIOIN
1.2 V
Core Digital and SRAMs
Input: VDDIN, VIN_SRAM
(1) Three simultaneous transmitter operation is supported only in 1-V LDO bypass and PA LDO disable mode. In this mode 1V supply
needs to be fed on the VOUT PA pin.
The 1.3-V (1.0 V) and 1.8-V power supply ripple specifications mentioned in Table 7-2 are defined to meet
a target spur level of –105 dBc (RF Pin = –15 dBm) at the RX. The spur and ripple levels have a dB-to-dB
relationship, for example, a 1-dB increase in supply ripple leads to a ~1 dB increase in spur level. Values quoted
are rms levels for a sinusoidal input applied at the specified frequency.
Table 7-2. Ripple Specifications
RF RAIL
VCO/IF RAIL
FREQUENCY (kHz)
1.0 V (INTERNAL LDO BYPASS)
1.3 V (µVRMS
)
1.8 V (µVRMS)
(µVRMS
)
137.5
275
7
5
648
76
22
4
83
21
11
6
550
3
1100
2200
4400
6600
2
11
13
22
82
93
117
13
19
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7.6 Power Consumption Summary
Table 7-3 and summarize the power consumption at the power terminals.
Table 7-3. Maximum Current Ratings at Power Terminals
PARAMETER
SUPPLY NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
Total current drawn by
all nodes driven by
1.2V rail
VDDIN, VIN_SRAM, VNWA
1000
Total current drawn
by all nodes driven
by 1.3V or 1.0V
VIN_13RF1, VIN_13RF2
2000
rail (2TX, 4 RX
simultaneously)(1)
Current consumption
mA
VIOIN_18, VIN_18CLK,
VIOIN_18DIFF, VIN_18BB,
VIN_18VCO
Total current drawn by
all nodes driven by
1.8V rail
850
50
Total current drawn by
all nodes driven by
3.3V rail
VIOIN
(1) 3 Transmitters can simultaneously be deployed only in AWR1843AOP and AWR2243 devices with 1V / LDO bypass and PA LDO
disable mode. In this mode 1V supply needs to be fed on the VOUT PA pin. In this case the peak 1V supply current goes up to 2500
mA.
Table 7-4. Average Power Consumption at Power Terminals
PARAMETER
CONDITION
DESCRIPTION
MIN
TYP MAX UNIT
1TX, 4RX
2TX, 4RX
Use Case: Regular mode, 6.4
MSps complex transceiver, 25-
ms frame time, 128 chirps, 128
samples/chirp, 5-µs idle time
(25% duty cycle), 3us ADC
start time and excess ramp
time, DSP and HWA active
1.29
1.36
25% Duty
Cycle
3TX, 4RX
1.43
1.0-V internal
LDO bypass
mode
Average power
consumption
W
1TX, 4RX
2TX, 4RX
Use Case: Regular mode, 6.4
MSps complex transceiver, 25-
ms frame time, 256 chirps, 128
samples/chirp, 5-µs idle time
(50% duty cycle), 3us ADC
start time and excess ramp
time, DSP and HWA active
1.82
1.96
50% Duty
Cycle
3TX, 4RX
2.08
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7.7 RF Specification
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
dB
Effective isotropic noise figure(1)
IF bandwidth(2)
10
10
25
MHz
Msps
Msps
Bits
ADC sampling rate (real)
Receiver
ADC sampling rate (complex 1x)
12.5
ADC resolution
12
–90
16
Idle Channel Spurs
dBFS
dBm
deg
Transmitter
Antenna
Single transmitter effective isotropic radiated power (EIRP)
Receiver antenna 8dB beamwidth
Transmitter antenna 6dB beamwidth
Frequency range
±60
±60
deg
76
81
GHz
Ramp rate
100 MHz/µs
Clock subsystem
76 to 77 GHz
Phase noise at 1-MHz offset
–95
–93
dBc/Hz
77 to 81 GHz
(1) Specification is quoted for complex 1x mode.
(2) The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set
of available HPF corners is summarized as follows:
Available HPF Corner Frequencies (kHz)
HPF1
HPF2
175, 235, 350, 700
350, 700, 1400, 2800
The filtering performed by the digital baseband chain is targeted to provide:
•
•
Less than ±0.5 dB pass-band ripple/droop, and
Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.
7.8 CPU Specifications
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
600
32
MAX UNIT
Clock Speed
DSP
MHz
KB
L1 Code Memory
Subsystem
(C674
Family)
L1 Data Memory
32
KB
L2 Memory
256
200
512
192
KB
Clock Speed
MHz
KB
Main
Subsystem
(R4F Family)
Tightly Coupled Memory - A (Program)
Tightly Coupled Memory - B (Data)
KB
Shared
Memory
Shared L3 Memory
1024
KB
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7.9 Thermal Resistance Characteristics for FCBGA Package [ALP0180A]
THERMAL METRICS(1) (4)
°C/W(2) (3)
RΘJC
RΘJB
RΘJA
RΘJMA
PsiJT
PsiJB
Junction-to-case
3.3
10.9
21.1
N/A(4)
1.9
Junction-to-board
Junction-to-free air
Junction-to-moving air
Junction-to-package top
Junction-to-board
10.8
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) °C/W = degrees Celsius per watt.
(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
A junction temperature of 125°C is assumed.
(4) N/A = not applicable
7.10 Timing and Switching Characteristics
7.10.1 Antenna Radiation Patterns
This section discusses transmitter and receiver antenna radiation patterns in both Azmiuth and Elevation planes
for a specified frequency.
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7.10.1.1 Antenna Radiation Patterns for Receiver
Figure 7-1 shows the RX effective Isotropic noise figure across the entire frequency band.
Figure 7-1. RX Effective Isotropic Noise Figure
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Figure 7-2 and Figure 7-3 shows typical antenna radiation patterns for the four receivers in both Azimuth and Elevation planes.
Rx Gain Across Azimuth
RX1
RX2
Angle
RX3
Angle
RX4
Angle
Angle
Figure 7-2. Receiver Antenna Radiation Pattern - Azimuth
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Rx Gain Across Elevation
RX1
RX2
Angle
RX3
Angle
RX4
Angle
Angle
Figure 7-3. Receiver Antenna Radiation Pattern - Elevation
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7.10.1.2 Antenna Radiation Patterns for Transmitter
Figure 7-4 shows typical antenna radiation patterns for the three transmitters in both Azimuth and Elevation planes.
TX Output Power Across Azimuth
TX1
TX2
TX3
Angle
Angle
Angle
TX Output Power Across Elevation
TX1
TX2
TX3
Angle
Angle
Angle
Figure 7-4. Transmitter Antenna Radiation Pattern
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7.10.2 Antenna Positions
Figure 7-5 shows the placement and relative spacing of the antennas. Lambda corresponds to a frequency of
78.5 GHz.
RX4
RX3
RX2
RX1
‹/2
‹/2
TX1
TX2
TX3
‹/2
‹/2
MIMO Virtual
Antenna Array
PIN A1
Figure 7-5. Antenna Positions (Placement and Relative Spacing)
7.10.3 Power Supply Sequencing and Reset Timing
The AWR1843AOP device expects all external voltage rails and SOP lines to be stable before reset is
deasserted. Figure 7-6 describes the device wake-up sequence.
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SOP
Setup
Time
SOP
Hold time to
nRESET
DC power
MSS
BOOT
START
nRESET
ASSERT
tPGDEL
DC
Power
notOK
Stable before
nRESET
release
DC
Power
OK
QSPI
READ
VDDIN,
VIN_SRAM
VNWA
VIOIN_18
VIN18_CLK
VIOIN_18DIFF
VIN18_BB
VIN_13RF1
VIN_13RF2
VIOIN
SOP IO
Reuse
SOP IO‘s can be used as functional IO‘s
SOP[2.1.0]
nRESET
WARMRESET
OUTPUT
VBGAP
OUTPUT
CLKP, CLKM
Using Crystal
MCUCLK
OUTPUT (1)
QSPI_CS
OUTPUT
8 ms (XTAL Mode)
850 µs (REFCLK Mode)
A. MCU_CLK_OUT in autonomous mode, where AWR1843AOP application is booted from the serial flash, MCU_CLK_OUT is not
enabled by default by the device bootloader.
Figure 7-6. Device Wake-up Sequence
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7.10.4 Input Clocks and Oscillators
7.10.4.1 Clock Specifications
The AWR1843AOP requires external clock source (that is, a 40-MHz crystal or external clock) for initial boot and
as a reference for an internal APLL hosted in the device. An external crystal is connected to the device pins.
Figure 7-7 shows the crystal implementation.
Cf1
CLKP
Cp
40 MHz
CLKM
Cf2
Figure 7-7. Crystal Implementation
Note
The load capacitors, Cf1 and Cf2 in Figure 7-7, should be chosen such that Equation 1 is satisfied.
CL in the equation is the load specified by the crystal manufacturer. All discrete components used
to implement the oscillator circuit should be placed as close as possible to the associated oscillator
CLKP and CLKM pins.
C f2
CL = C f1
´
+CP
C
f1 +C f2
(1)
Table 7-5 lists the electrical characteristics of the clock crystal.
Table 7-5. Crystal Electrical Characteristics (Oscillator Mode)
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
pF
fP
Parallel resonance crystal frequency
40
CL
Crystal load capacitance
Crystal ESR
5
8
12
50
ESR
Ω
Temperature range Expected temperature range of operation
–40
140
°C
Frequency
Crystal frequency tolerance(1) (2)
tolerance
–200
200
200
ppm
µW
Drive level
50
(1) The crystal manufacturer's specification must satisfy this requirement.
(2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.
Table 7-6. External Clock Mode Specifications
SPECIFICATION
PARAMETER
UNIT
MIN
TYP
MAX
Frequency
40
MHz
adc patmV
(pp)
AC-Amplitude
700
1200
Phase Noise at 1 kHz
Phase Noise at 10 kHz
Phase Noise at 100 kHz
Phase Noise at 1 MHz
Duty Cycle
–132
–143
–152
–153
65
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
%
Input Clock:
External AC-coupled sine wave or DC-
coupled square wave
Phase Noise referred to 40 MHz
35
Freq Tolerance
–50
50
ppm
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7.10.5 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
7.10.5.1 Peripheral Description
The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (2 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate.
The MibSPI/SPI is normally used for communication between the microcontroller and external peripherals or
another microcontroller.
Standard SPI and MibSPI modules have the following features:
•
•
•
•
16-bit shift register
Receive buffer register
8-bit baud clock generator
SPICLK can be internally-generated (master mode) or received from an external clock source
(slave mode)
•
•
Each word transferred can have a unique format.
SPI I/Os not used in the communication can be used as digital input/output signals
7.10.5.2 MibSPI Transmit and Receive RAM Organization
The Multibuffer RAM is comprised of 256 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a 16-bit
transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer RAM can be
partitioned into multiple transfer group with variable number of buffers each.
Section 7.10.5.2.2 assumes the operating conditions stated in Section 7.10.5.2.1.
7.10.5.2.1 SPI Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input rise time
Input fall time
1
1
3
3
ns
ns
Output Conditions
CLOAD Output load capacitance
2
15
pF
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7.10.5.2.2 SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input)
NO.(1) (2) (3)
PARAMETER
MIN
25
TYP
MAX
256tc(VCLK)
UNIT
1
tc(SPC)M
Cycle time, SPICLK(4)
ns
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 3
0.5tc(SPC)M – 3
0.5tc(SPC)M – 10.5
0.5tc(SPC)M – 10.5
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
2(4)
3(4)
4(4)
5(4)
ns
ns
ns
ns
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 1)
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 0)
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 1)
td(SPCH-SIMO)M
td(SPCL-SIMO)M
tv(SPCL-SIMO)M
tv(SPCH-SIMO)M
Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0)
Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1)
CSHOLD = 0
(C2TDELAY+2)*tc(VCLK
) – 7.5
(C2TDELAY+2) *
tc(VCLK) + 7
Setup time CS active until SPICLK high
(clock polarity = 0)
CSHOLD = 1
CSHOLD = 0
CSHOLD = 1
(C2TDELAY +3) *
tc(VCLK) – 7.5
(C2TDELAY+3) *
tc(VCLK) + 7
6(5)
tC2TDELAY
ns
ns
(C2TDELAY+2)*tc(VCLK
) – 7.5
(C2TDELAY+2) *
tc(VCLK) + 7
Setup time CS active until SPICLK low
(clock polarity = 1)
(C2TDELAY +3) *
tc(VCLK) – 7.5
(C2TDELAY+3) *
tc(VCLK) + 7
Hold time, SPICLK low until CS inactive (clock polarity = 0)
Hold time, SPICLK high until CS inactive (clock polarity = 1)
0.5*tc(SPC)M
(T2CDELAY + 1)
*tc(VCLK) – 7
+
0.5*tc(SPC)M +
(T2CDELAY + 1) *
tc(VCLK) + 7.5
7(5)
tT2CDELAY
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(T2CDELAY + 1)
*tc(VCLK) – 7
(T2CDELAY + 1) *
tc(VCLK) + 7.5
tsu(SOMI-SPCL)M
tsu(SOMI-SPCH)M
th(SPCL-SOMI)M
th(SPCH-SOMI)M
Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
5
5
3
3
8(4)
ns
ns
Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
9(4)
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared (where x= 0 or 1).
(2) tc(MSS_VCLK) = main subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
(3) When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25ns, where PS is the prescale value set in the SPIFMTx.[15:8]
register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25ns.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
11
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1
4
5
Master Out Data Is Valid
SPISIMO
8
9
Master In Data
Must Be Valid
SPISOMI
Figure 7-8. SPI Master Mode External Timing (CLOCK PHASE = 0)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
SPICSn
Master Out Data Is Valid
6
7
Figure 7-9. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)
7.10.5.2.3 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output,
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SPISIMO = output, and SPISOMI = input)
NO.(1) (2) (3)
PARAMETER
MIN
25
TYP
MAX
256tc(VCLK)
UNIT
1
tc(SPC)M
Cycle time, SPICLK(4)
ns
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 3
0.5tc(SPC)M – 3
0.5tc(SPC)M – 10.5
0.5tc(SPC)M – 10.5
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
2(4)
ns
ns
ns
ns
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 1)
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 0)
3(4)
4(4)
5(4)
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 1)
td(SPCH-SIMO)M
td(SPCL-SIMO)M
tv(SPCL-SIMO)M
tv(SPCH-SIMO)M
tC2TDELAY
Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0)
Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1)
Setup time CS active until SPICLK high
(clock polarity = 0)
CSHOLD = 0
CSHOLD = 1
CSHOLD = 0
CSHOLD = 1
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+2) *
tc(VCLK) + 7.5
(C2TDELAY +
2)*tc(VCLK) – 7
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+2) *
tc(VCLK) + 7.5
(C2TDELAY +
2)*tc(VCLK) – 7
6(5)
ns
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+2) *
tc(VCLK) + 7.5
(C2TDELAY+2)*tc(V
CLK) – 7
Setup time CS active until SPICLK low
(clock polarity = 1)
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+3)*tc(V
CLK) – 7
(C2TDELAY+3) *
tc(VCLK) + 7.5
Hold time, SPICLK low until CS inactive (clock polarity = 0)
Hold time, SPICLK high until CS inactive (clock polarity = 1)
(T2CDELAY + 1)
*tc(VCLK) – 7.5
(T2CDELAY + 1)
*tc(VCLK) + 7
7(5)
8(4)
9(4)
tT2CDELAY
ns
ns
ns
(T2CDELAY + 1)
*tc(VCLK) – 7.5
(T2CDELAY + 1)
*tc(VCLK) + 7
tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
5
5
3
3
tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
th(SPCL-SOMI)M
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
th(SPCH-SOMI)M
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set ( where x = 0 or 1 ).
(2) tc(MSS_VCLK) = main subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
(3) When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where PS is the prescale value set in the SPIFMTx.
[15:8] register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25 ns.
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(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
Master Out Data Is Valid
Data Valid
SPISIMO
8
9
Master In Data
Must Be Valid
SPISOMI
Figure 7-10. SPI Master Mode External Timing (CLOCK PHASE = 1)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
SPICSn
Master Out Data Is Valid
6
7
Figure 7-11. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)
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7.10.5.3 SPI Slave Mode I/O Timings
7.10.5.3.1 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input,
and SPISOMI = output)
NO.(1) (2) (3)
PARAMETER
MIN
25
TYP
MAX
UNIT
1
tc(SPC)S
Cycle time, SPICLK(4)
ns
tw(SPCH)S
tw(SPCL)S
tw(SPCL)S
tw(SPCH)S
td(SPCH-SOMI)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
10
2(5)
ns
ns
10
10
3(5)
10
Delay time, SPISOMI valid after SPICLK high
(clock polarity = 0)
10
10
4(5)
ns
ns
td(SPCL-SOMI)S
th(SPCH-SOMI)S
th(SPCL-SOMI)S
td(SPCH-SOMI)S
Delay time, SPISOMI valid after SPICLK low (clock
polarity = 1)
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 0)
2
2
5(5)
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
Delay time, SPISOMI valid after SPICLK high
(clock polarity = 0; clock phase = 0) OR (clock
polarity = 1; clock phase = 1)
10
10
4(5)
5(5)
6(5)
7(5)
ns
ns
ns
ns
td(SPCL-SOMI)S
th(SPCH-SOMI)S
th(SPCL-SOMI)S
Delay time, SPISOMI valid after SPICLK low (clock
polarity = 1; clock phase = 0) OR (clock polarity =
0; clock phase = 1)
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 0; clock phase = 0) OR (clock
polarity = 1; clock phase = 1)
2
2
3
3
1
1
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 1; clock phase = 0) OR (clock
polarity = 0; clock phase = 1)
Setup time, SPISIMO before SPICLK low (clock
polarity = 0; clock phase = 0) OR (clock polarity =
1; clock phase = 1)
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK high (clock
tsu(SIMO-SPCH)S polarity = 1; clock phase = 0) OR (clock polarity =
0; clock phase = 1)
Hold time, SPISIMO data valid after SPICLK low
(clock polarity = 0; clock phase = 0) OR (clock
polarity = 1; clock phase = 1)
th(SPCL-SIMO)S
Hold time, SPISIMO data valid after SPICLK high
(clock polarity = 1; clock phase = 0) OR (clock
polarity = 0; clock phase = 1)
th(SPCL-SIMO)S
(1) The MASTER bit (SPIGCRx.0) is cleared ( where x = 0 or 1 ).
(2) The CLOCK PHASE bit (SPIFMTx.16) is either cleared or set for CLOCK PHASE = 0 or CLOCK PHASE = 1 respectively.
(3) tc(MSS_VCLK) = main subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
(4) When the SPI is in Slave mode, the following must be true: For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where
PS is the prescale value set in the SPIFMTx.[15:8] register bits.For PS values of 0: tc(SPC)S = 2tc(MSS_VCLK) ≥ 25 ns.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 7-12. SPI Slave Mode External Timing (CLOCK PHASE = 0)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 7-13. SPI Slave Mode External Timing (CLOCK PHASE = 1)
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7.10.5.4 Typical Interface Protocol Diagram (Slave Mode)
1. Host should ensure that there is a delay of two SPI clocks between CS going low and start of SPI clock.
2. Host should ensure that CS is toggled for every 16 bits of transfer through SPI.
Figure 7-14 shows the SPI communication timing of the typical interface protocol.
2 SPI clocks
CS
CLK
0x4321
0x1234
CRC
0x5678
0x8765
MOSI
MISO
IRQ
0xDCBA
0xABCD
CRC
16 bytes
Figure 7-14. SPI Communication
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7.10.6 LVDS Interface Configuration
The supported AWR1843AOP LVDS lane configuration is two Data lanes (LVDS_TXP/M), one Bit Clock lane
(LVDS_CLKP/M) and one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface is used for debugging. The
LVDS interface supports the following data rates:
•
•
•
•
•
•
•
900 Mbps (450 MHz DDR Clock)
600 Mbps (300 MHz DDR Clock)
450 Mbps (225 MHz DDR Clock)
400 Mbps (200 MHz DDR Clock)
300 Mbps (150 MHz DDR Clock)
225 Mbps (112.5 MHz DDR Clock)
150 Mbps (75 MHz DDR Clock)
Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data.
LVDS_TXP/M
LVDS_FRCLKP/M
Data bitwidth
LVDS_CLKP/M
Figure 7-15. LVDS Interface Lane Configuration And Relative Timings
7.10.6.1 LVDS Interface Timings
Trise
LVDS_CLK
Clock Jitter = 6sigma
LVDS_TXP/M
LVDS_FRCLKP/M
1100 ps
Figure 7-16. Timing Parameters
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UNIT
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Table 7-7. LVDS Electrical Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
max 1 pF lumped capacitive load on
LVDS lanes
Duty Cycle Requirements
48%
52%
peak-to-peak single-ended with 100 Ω
resistive load between differential pairs
Output Differential Voltage
250
450
mV
Output Offset Voltage
Trise and Tfall
1125
1275
mV
ps
20%-80%, 900 Mbps
900 Mbps
330
80
Jitter (pk-pk)
ps
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7.10.7 General-Purpose Input/Output
Section 7.10.7.1 lists the switching characteristics of output timing relative to load capacitance.
7.10.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)(1) (2)
PARAMETER
TEST CONDITIONS
CL = 20 pF
VIOIN = 1.8V
VIOIN = 3.3V
UNIT
2.8
6.4
9.4
2.8
6.4
9.4
3.3
6.7
9.6
3.1
6.6
9.6
3.0
6.9
10.2
2.8
6.6
9.8
3.3
7.2
10.5
3.1
6.6
9.6
tr
tf
tr
tf
Max rise time
CL = 50 pF
ns
CL = 75 pF
Slew control = 0
CL = 20 pF
CL = 50 pF
CL = 75 pF
CL = 20 pF
CL = 50 pF
CL = 75 pF
CL = 20 pF
CL = 50 pF
CL = 75 pF
Max fall time
Max rise time
Max fall time
ns
ns
ns
Slew control = 1
(1) Slew control, which is configured by PADxx_CFG_REG, changes behavior of the output driver (faster or slower output slew rate).
(2) The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.
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7.10.8 Controller Area Network Interface (DCAN)
The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that
efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is
ideal for applications operating in noisy and harsh environments that require reliable serial communication or
multiplexed wiring.
The DCAN has the following features:
•
•
•
•
•
•
•
•
•
•
Supports CAN protocol version 2.0 part A, B
Bit rates up to 1 Mbps
Configurable Message objects
Individual identifier masks for each message object
Programmable FIFO mode for message objects
Suspend mode for debug support
Programmable loop-back modes for self-test operation
Direct access to Message RAM in test mode
Supports two interrupt lines - Level 0 and Level 1
Automatic Message RAM initialization
7.10.8.1 Dynamic Characteristics for the DCANx TX and RX Pins
PARAMETER
MIN
TYP
MAX
15
UNIT
ns
td(CAN_tx)
td(CAN_rx)
Delay time, transmit shift register to CAN_tx pin(1)
Delay time, CAN_rx pin to receive shift register(1)
10
ns
(1) These values do not include rise/fall times of the output buffer.
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7.10.9 Controller Area Network - Flexible Data-rate (CAN-FD)
The CAN-FD module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications.
CAN FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD
devices can coexist on the same network without any conflict.
The CAN-FD has the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Conforms with CAN Protocol 2.0 A, B and ISO 11898-1
Full CAN FD support (up to 64 data bytes per frame)
AUTOSAR and SAE J1939 support
Up to 32 dedicated Transmit Buffers
Configurable Transmit FIFO, up to 32 elements
Configurable Transmit Queue, up to 32 elements
Configurable Transmit Event FIFO, up to 32 elements
Up to 64 dedicated Receive Buffers
Two configurable Receive FIFOs, up to 64 elements each
Up to 128 11-bit filter elements
Internal Loopback mode for self-test
Mask-able interrupts, two interrupt lines
Two clock domains (CAN clock / Host clock)
Parity / ECC support - Message RAM single error correction and double error detection (SECDED)
mechanism
•
Full Message Memory capacity (4352 words).
7.10.9.1 Dynamic Characteristics for the CANx TX and RX Pins
PARAMETER
MIN
TYP
MAX
UNIT
td(CAN_FD_tx)
td(CAN_FD_rx)
Delay time, transmit shift register to CAN_FD_tx
pin(1)
15
ns
Delay time, CAN_FD_rx pin to receive shift
register(1)
10
ns
(1) These values do not include rise/fall times of the output buffer.
7.10.10 Serial Communication Interface (SCI)
The SCI has the following features:
•
•
•
•
•
•
Standard universal asynchronous receiver-transmitter (UART) communication
Standard non-return to zero (NRZ) format
Double-buffered receive and transmit functions
Asynchronous or iso-synchronous communication modes with no CLK pin
Capability to use Direct Memory Access (DMA) for transmit and receive data
Two external pins: RS232_RX and RS232_TX
7.10.10.1 SCI Timing Requirements
MIN
TYP
921.6
MAX
UNIT
f(baud)
Supported baud rate at 20 pF
kHz
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7.10.11 Inter-Integrated Circuit Interface (I2C)
The inter-integrated circuit (I2C) module is a multimaster communication module providing an interface between
devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an I2C-bus™.
This module will support any slave or master I2C compatible device.
The I2C has the following features:
•
Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number 9398
393 40011)
– Bit/Byte format transfer
– 7-bit and 10-bit device addressing modes
– General call
– START byte
– Multi-master transmitter/ slave receiver mode
– Multi-master receiver/ slave transmitter mode
– Combined master transmit/receive and receive/transmit mode
– Transfer rates of 100 kbps up to 400 kbps (Phillips fast-mode rate)
Free data format
Two DMA events (transmit and receive)
DMA event enable/disable capability
Module enable/disable capability
The SDA and SCL are optionally configurable as general purpose I/O
Slew rate control of the outputs
Open drain control of the outputs
Programmable pullup/pulldown capability on the inputs
Supports Ignore NACK mode
•
•
•
•
•
•
•
•
•
Note
This I2C module does not support:
•
•
•
High-speed (HS) mode
C-bus compatibility mode
The combined format in 10-bit address mode (the I2C sends the slave address second byte every
time it sends the slave address first byte)
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7.10.11.1 I2C Timing Requirements(1)
STANDARD MODE
FAST MODE
UNIT
MIN
10
MAX
MIN
2.5
MAX
tc(SCL)
Cycle time, SCL
μs
μs
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low
(for a repeated START condition)
4.7
0.6
th(SCLL-SDAL)
Hold time, SCL low after SDA low
4
0.6
μs
(for a START and a repeated START condition)
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
μs
μs
μs
μs
μs
tw(SCLH)
Pulse duration, SCL high
tsu(SDA-SCLH)
th(SCLL-SDA)
tw(SDAH)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0
3.45(1)
0.9
Pulse duration, SDA high between STOP and START
conditions
4.7
1.3
tsu(SCLH-SDAH)
tw(SP)
Setup time, SCL high before SDA high
(for STOP condition)
4
0.6
0
μs
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
50
ns
(2) (3)
Cb
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the
SCL signal.
(3) Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.
SDA
tw(SDAH)
tsu(SDA-SCLH)
tw(SP)
tw(SCLL)
tr(SCL)
tsu(SCLH-SDAH)
tw(SCLH)
SCL
tc(SCL)
th(SCLL-SDAL)
tf(SCL)
th(SCLL-SDAL)
tsu(SCLH-SDAL)
th(SDA-SCLL)
Stop
Start
Repeated Start
Stop
Figure 7-17. I2C Timing Diagram
Note
•
•
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW
period (tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a Standard-
mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line tr max + tsu(SDA-SCLH)
.
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7.10.12 Quad Serial Peripheral Interface (QSPI)
The quad serial peripheral interface (QSPI™) module is a kind of SPI module that allows single, dual, or quad
read access to external SPI devices. This module has a memory mapped register interface, which provides a
direct interface for accessing data from external SPI devices and thus simplifying software requirements. The
QSPI works as a master only. The QSPI in the device is primarily intended for fast booting from quad-SPI flash
memories.
The QSPI supports the following features:
•
•
•
•
•
•
•
Programmable clock divider
Six-pin interface
Programmable length (from 1 to 128 bits) of the words transferred
Programmable number (from 1 to 4096) of the words transferred
Support for 3-, 4-, or 6-pin SPI interface
Optional interrupt generation on word or frame (number of words) completion
Programmable delay between chip select activation and output data from 0 to 3 QSPI clock cycles
Section 7.10.12.2 and Section 7.10.12.3 assume the operating conditions stated in Section 7.10.12.1.
7.10.12.1 QSPI Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input rise time
Input fall time
1
1
3
3
ns
ns
Output Conditions
CLOAD
Output load capacitance
2
15
pF
7.10.12.2 Timing Requirements for QSPI Input (Read) Timings(1) (2)
MIN
7.3
TYP
MAX
UNIT
ns
tsu(D-SCLK)
th(SCLK-D)
tsu(D-SCLK)
th(SCLK-D)
Setup time, d[3:0] valid before falling sclk edge (Q12)
Hold time, d[3:0] valid after falling sclk edge (Q13)
Setup time, final d[3:0] bit valid before final falling sclk edge
Hold time, final d[3:0] bit valid after final falling sclk edge
1.5
ns
7.3 – P(3)
1.5 + P(3)
ns
ns
(1) Clock Mode 0 (clk polarity = 0 ; clk phase = 0 ) is the mode of operation.
(2) The Device captures data on the falling clock edge in Clock Mode 0, as opposed to the traditional rising clock edge. Although
non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that
launch data on the falling edge in Clock Mode 0.
(3) P = SCLK period in ns.
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7.10.12.3 QSPI Switching Characteristics
NO.
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
PARAMETER(1) (2) (3)
Cycle time, sclk
MIN
25
TYP
MAX
UNIT
ns
tc(SCLK)
tw(SCLKL)
Pulse duration, sclk low
0.5*P – 3
0.5*P – 3
–M*P – 1
N*P – 1
–3.5
ns
tw(SCLKH)
Pulse duration, sclk high
ns
td(CS-SCLK)
td(SCLK-CS)
td(SCLK-D1)
tena(CS-D1LZ)
tdis(CS-D1Z)
td(SCLK-D1)
Delay time, sclk falling edge to cs active edge
Delay time, sclk falling edge to cs inactive edge
Delay time, sclk falling edge to d[0] transition
Enable time, cs active edge to d[0] driven (lo-z)
Disable time, cs active edge to d[0] tri-stated (hi-z)
–M*P + 2.5
N*P + 2.5
7
ns
ns
ns
–P – 4
–P +1
ns
–P – 4
–P +1
ns
Delay time, sclk first falling edge to first d[1] transition
(for PHA = 0 only)
ns
Q9
–3.5 – P
7 – P
(1) The Y parameter is defined as follows: If DCLK_DIV is 0 or ODD then, Y equals 0.5. If DCLK_DIV is EVEN then, Y equals
(DCLK_DIV/2) / (DCLK_DIV+1). For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty
cycle distortion. The HSDIVIDER on CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All
required details about clock division factor DCLK_DIV can be found in the device-specific Technical Reference Manual.
(2) P = SCLK period in ns.
(3) M = QSPI_SPI_DC_REG.DDx + 1, N = 2
Figure 7-18. QSPI Read (Clock Mode 0)
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PHA=0
cs
Q5
Q4
Q1
Q2
Q3
POL=0
sclk
Q8
Q6
Q6
Q7
Q9
Q6
Command
Bit n-1
Command
Bit n-2
Write Data
Bit 1
Write Data
Bit 0
d[0]
d[3:1]
SPRS85v_TIMING_OSPI1_04
Figure 7-19. QSPI Write (Clock Mode 0)
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7.10.13 ETM Trace Interface
Section 7.10.13.2 and List item.referenceTitle assume the recommended operating conditions stated in Section
7.10.13.1.
7.10.13.1 ETMTRACE Timing Conditions
MIN
TYP
MAX
UNIT
Output Conditions
CLOAD
Output load capacitance
2
20
pF
7.10.13.2 ETM TRACE Switching Characteristics
NO.
1
PARAMETER
Cycle time, TRACECLK period
Pulse Duration, TRACECLK High
Pulse Duration, TRACECLK Low
Clock and data rise time
MIN
TYP
MAX
UNIT
ns
tcyc(ETM)
th(ETM)
tl(ETM)
20
9
2
ns
3
9
ns
4
tr(ETM)
tf(ETM)
3.3
3.3
7
ns
5
Clock and data fall time
ns
td(ETMTRACE Delay time, ETM trace clock high to ETM data valid
1
1
ns
6
7
CLKH-
ETMDATAV)
td(ETMTRACE Delay time, ETM trace clock low to ETM data valid
7
ns
CLKl-
ETMDATAV)
tl(ETM)
th(ETM)
tr(ETM)
tf(ETM)
tcyc(ETM)
Figure 7-20. ETMTRACECLKOUT Timing
Figure 7-21. ETMDATA Timing
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7.10.14 Data Modification Module (DMM)
A Data Modification Module (DMM) gives the ability to write external data into the device memory.
The DMM has the following features:
•
•
Acts as a bus master, thus enabling direct writes to the 4GB address space without CPU intervention
Writes to memory locations specified in the received packet (leverages packets defined by trace mode of the
RAM trace port [RTP] module)
•
Writes received data to consecutive addresses, which are specified by the DMM (leverages packets defined
by direct data mode of RTP module)
•
•
Configurable port width (1, 2, 4, 8, 16 pins)
Up to 65 Mbit/s pin data rate
7.10.14.1 DMM Timing Requirements
MIN
TYP
MAX
UNIT
ns
tcyc(DMM)
tR
Clock period
15.4
1
Clock rise time
3
3
ns
tF
Clock fall time
1
ns
th(DMM)
tl(DMM)
tssu(DMM)
tsh(DMM)
tdsu(DMM)
tdh(DMM)
High pulse width
6
ns
Low pulse width
6
ns
SYNC active to clk falling edge setup time
DMM clk falling edge to SYNC deactive hold time
DATA to DMM clk falling edge setup time
DMM clk falling edge to DATA hold time
2
ns
3
ns
2
ns
3
ns
tl(DMM)
th(DMM)
tf
tr
tcyc(DMM)
Figure 7-22. DMMCLK Timing
tssu(DMM)
tsh(DMM)
DMMSYNC
DMMCLK
DMMDATA
tdsu(DMM)
tdh(DMM)
Figure 7-23. DMMDATA Timing
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7.10.15 JTAG Interface
Section 7.10.15.2 and Section 7.10.15.3 assume the operating conditions stated in Section 7.10.15.1.
7.10.15.1 JTAG Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input rise time
Input fall time
1
1
3
3
ns
ns
Output Conditions
CLOAD
Output load capacitance
2
15
pF
7.10.15.2 Timing Requirements for IEEE 1149.1 JTAG
NO.
MIN
TYP
MAX
UNIT
ns
1
tc(TCK)
Cycle time TCK
66.66
26.67
26.67
2.5
1a
1b
tw(TCKH)
Pulse duration TCK high (40% of tc)
Pulse duration TCK low(40% of tc)
Input setup time TDI valid to TCK high
Input setup time TMS valid to TCK high
Input hold time TDI valid from TCK high
Input hold time TMS valid from TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
ns
3
4
2.5
ns
18
ns
18
ns
7.10.15.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
NO.
PARAMETER
MIN
TYP
MAX
UNIT
2
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
0
25
ns
1
1a
1b
TCK
TDO
2
3
4
TDI/TMS
SPRS91v_JTAG_01
Figure 7-24. JTAG Timing
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8 Detailed Description
8.1 Overview
The AWR1843AOP is an Antenna-on-Package (AOP) device that includes the entire Millimeter Wave blocks and
analog baseband signal chain for three transmitters and four receivers, as well as a customer-programmable
MCU. This device is applicable as a radar-on-a-chip in use-cases with modest requirements for memory,
processing capacity and application code size. These could be cost-sensitive automotive applications that
are evolving from 24 GHz narrowband implementation and some emerging simple ultra-short-range radar
applications. Typical application examples for this device include Car Door Opener, Parking Assist, basic Blind
Spot Detect and so forth.
In terms of scalability, the AWR1843AOP device could be paired with a low-end external MCU, to address more
complex applications that might require additional memory for larger application software footprint and faster
interfaces.
8.2 Functional Block Diagram
Antennas are on Package
QSPI
SPI
Serial Flash interface
LNA
LNA
LNA
LNA
IF
IF
IF
IF
ADC
ADC
ADC
ADC
Cortex R4F
@ 200MHz
External MCU interface
(User programmable)
Digital
Front-End
PMIC control
SPI / I2C
DCAN
Data
RAM
Boot
ROM
Prog RAM
(Decimation
Filter Chain)
Primary Communication
Interfaces (Automotive)
CAN-FD
Radar Hardware
Accelerator
DMA
Debug
UARTs
For debug
Main Sub-System
(Customer Programmed)
Test/Debug
JTAG for debug/development
Phase
Shift
ADC
Buffer
PA
Mailbox
High-speed ADC output
interface (for recording)
LVDS
HIL
Ramp
Generator
Phase
Shift
Synth
(20 GHz)
PA
x3
High-speed input for hardware-in-
loop verification
C674x DSP
@600 MHz
Phase
Shift
PA
Radio (BIST)
Processor
6
L1P
(32kB)
L1D
(32kB)
L2
(256kB)
GPADC
(For RF Calibration
& Self-Test œ TI
Programmed)
DMA
CRC
Prog RAM
& ROM
Data
RAM
Temp
Osc.
Radar Data Memory
(L3)
DSP Sub-System
(Customer Programmed)
Radio Processor
Sub-System
(TI Programmed)
RF/Analog Sub-System
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8.3 Subsystems
8.3.1 RF and Analog Subsystem
The RF and analog subsystem includes the RF and analog circuitry – namely, the synthesizer, PA, LNA, mixer,
IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The three transmit
channels can be operated up to a maximum of two at a time (simultaneously) for transmit beamforming purpose
as required; whereas the four receive channels can all be operated simultaneously.
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8.3.1.1 Clock Subsystem
The AWR1843AOP clock subsystem generates 76 to 81 GHz from an input reference of 40-MHz crystal. It
has a built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF
synthesizer is then processed by an X4 multiplier to create the required frequency in the 76 to 81 GHz spectrum.
The RF synthesizer output is modulated by the timing engine block to create the required waveforms for effective
sensor operation.
The clean-up PLL also provides a reference clock for the host processor after system wakeup.
The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring the
quality of the generated clock.
Figure 8-1 describes the clock subsystem.
Self Test
RF SYNTH
Timing
SYNC_OUT
Engine
Lock Detect
SoC Clock
Clean-
Up PLL
x4
MULT
XO/
Slicer
CLK Detect
40 MHz
Figure 8-1. Clock Subsystem
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8.3.1.2 Transmit Subsystem
The AWR1843AOP transmit subsystem consists of three parallel transmit chains, each with independent phase
and amplitude control. All three transmitters can be used simultaneously. For AWR1843AOP, additional phase
shifters are associated with Tx channels, and these can programmed on a per chirp basis.
Each transmit chain can deliver a maximum of 16 dBm EIRP. The transmit chains also support programmable
backoff for system optimization.
Figure 8-2 describes the transmit subsystem.
Self Test
Loopback
Path
Antenna on
package
∆N
LO
6-bit linear phase
shifter
Figure 8-2. Transmit Subsystem (Per Channel)
8.3.1.3 Receive Subsystem
The AWR1843AOP receive subsystem consists of four parallel channels. A single receive channel consists of
an LNA, mixer, IF filtering, ADC conversion, and decimation. All four receive channels can be operational at the
same time an individual power-down option is also available for system optimization.
Unlike conventional real-only receivers, the AWR1843AOP device supports a complex baseband architecture,
which uses quadrature mixer and dual IF and ADC chains to provide complex I and Q outputs for each receiver
channel. The AWR1843AOP is targeted for fast chirp systems. The band-pass IF chain has configurable lower
cutoff frequencies above 175 kHz and can support bandwidths up to 10 MHz.
Figure 8-3 describes the receive subsystem.
Self Test
DAC
Loopback
Path
∆∑M
Antenna on
package
RSSI
I
LO
Q
∆∑M
DAC
Figure 8-3. Receive Subsystem (Per Channel)
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8.3.2 Processor Subsystem
Unified
128KB x 2
ROM
L2
Cache/
RAM
TCM A 512KB
TCM B 192KB
L1P
32KB
32KB
EDMA
Main
R4F
DSP
HIL
JTAG
CRC
HIL
L1d
DSP Interconnect œ 128 bit @ 200 MHz
Main Interconnect
BSS Interconnect
Data
Handshake
Memory
CRC
ADC Buffer
Mail
Box
MSS
DMA
L3
HWA
32KB
32KB Ping-Pong
1024 KB
(static sharing
with R4F Space)
Interconnect
LVDS
PWM,
PMIC
CLK
CAN
FD
I2C
QSPI
UART
CAN
SPI
Figure 8-4. Processor Subsystem
Figure 8-4 shows the block diagram for customer programmable processor subsystems in the AWR1843AOP
device. At a high level there are two customer programmable subsystems. Left hand side shows the
DSP Subsystem which contains TI's high-performance C674x DSP, a high-bandwidth interconnect for high
performance (128-bit, 200MHz) and associated peripherals – four DMAs for data transfer,
LVDS interface for Measurement data output, L3 Radar data cube memory, ADC buffers, CRC engine, and data
handshake memory (additional memory provided on interconnect).
The right side of the diagram shows the Main subsystem. Main subsystem as name suggests is the main device
and controls all the device peripherals and house-keeping activities of the device. Main subsystem contains
Cortex-R4F (MSS R4F) processor and associated peripherals and house-keeping components such as DMAs,
CRC and Peripherals (I2C, UART, SPIs, CAN, PMIC clocking module, PWM, and others) connected to Main
Interconnect through Peripheral Central Resource (PCR interconnect).
Details of the DSP CPU core can be found at http://www.ti.com/product/TMS320C6748.
HIL module is shown in both the subsystems and can be used to perform the radar operations feeding the
captured data from outside into the device without involving the RF subsystem. HIL on MSS is for controlling the
configuration and HIL on DSPSS for high speed ADC data input to the device. Both HIL modules uses the same
IOs on the device, one additional IO (DMM_MUX_IN) allows selecting either of the two.
8.3.3 Automotive Interface
The AWR1843AOP communicates with the automotive network over the following main interfaces:
•
CAN (2 interfaces available, one of them being CAN-FD)
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8.3.4 Main Subsystem Cortex-R4F Memory Map
Table 8-1 shows the main subsystem, Cortex-R4F memory map.
Note
There are separate Cortex-R4F addresses and DMA MSS addresses for the main subsystem. See the
Technical Reference Manual for a complete list.
Table 8-1. Main Subsystem, Cortex-R4F Memory Map
FRAME ADDRESS (HEX)
NAME
SIZE
DESCRIPTION
START
END
CPU Tightly-Coupled Memories
TCMA ROM
TCM RAM-A
0x0000_0000
0x0020_0000
0x0001_FFFF
128 KiB
Program ROM
Data RAM
0x0023_FFFF (or
0x0027_FFFF)
512 KiB
TCM RAM-B
0x0800_0000
0x0802_FFFF
192 KB
S/W Scratch Pad Memory
SW_ Buffer
0x0C20_0000
0x0C20_1FFF
8 KB
2 KB
188 B
2 KB
188 B
2 KB
188 B
S/W Scratchpad memory
System Peripherals
Mail Box
MSS<->RADARSS
0xF060_1000
0xF060_2000
0xF060_8000
0xF060_8060
0xF060_4000
0xF060_5000
0xF060_8400
0xF060_8300
0xF060_6000
0xF060_7000
0xF060_8200
0xF060_17FF
0xF060_27FF
0xF060_80FF
0xF060_86FF
0xF060_47FF
0xF060_57FF
0xF060_84FF
0xF060_83FF
0xF060_67FF
0xF060_7FFF
0xF060_82FF
RADARSS to MSS mailbox memory space
MSS to RADARSS mailbox memory space
MSS to RADARSS mailbox Configuration registers
RADARSS to MSS mailbox Configuration registers
DSPSS to MSS mailbox memory space
Mail Box
MSS<->DSPSS
MSS to DSPSS mailbox memory space
MSS to DSPSS mailbox Configuration registers
DSPSS to MSS mailbox Configuration registers
RADARSS to DSPSS mailbox memory space
DSPSS to RADARSS mailbox memory space
Mail Box
RADARSS<-
>DSPSS
RADARSS to DSPSS mailbox Configuration
registers
0xF060_8100
0xF060_81FF
DSPSS to RADARSS mailbox Configuration
registers
PRCM and Control
Module
0xFFFF_E100
0xFFFF_FF00
0xFFFF_EA00
0xFFFF_F800
0xFFF7_BC00
0xFFFF_F000
0xFCFF_F800
0xFCFF_F700
0xFCFF_F600
0xFFFF_FD00
0xFFFF_FC00
0xFFFF_EE00
0xFFFF_E2FF
0xFFFF_FFFF
0xFFFF_EBFF
0xFFFF_FBFF
0xFFF7_BDFF
0xFFFF_F3FF
0xFCFF_FBFF
0xFCFF_F7FF
0xFCFF_F6FF
0xFFFF_FEFF
0xFFFF_FCFF
0xFFFF_EEFF
756 B
256 B
512 KB
352 B
180 B
1 KB
TOP Level Reset, Clock management registers
MSS Reset, Clock management registers
IO Mux module registers
General-purpose control registers
GIO module configuration registers
DMA-1 module configuration registers
DMA-2 module configuration registers
DMM-1 module configuration registers
DMM-2 module configuration registers
VIM module configuration registers
RTI-A module configuration registers
RTI-B module configuration registers
GIO
DMA-1
DMA-2
DMM-1
DMM-2
VIM
1 KB
472 B
472 B
512 B
192 B
192 B
RTI-A/WD
RTI-B
Serial Interfaces and Connectivity
QSPI
0xC000_0000
0xC080_0000
0xFFF7_F400
0xC07F_FFFF
0xC0FF_FFFF
0xFFF7_F5FF
8 MB
116 B
512 B
QSPI –flash memory space
QSPI module configuration registers
MIBSPI-A module configuration registers
MIBSPI-A
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Table 8-1. Main Subsystem, Cortex-R4F Memory Map (continued)
FRAME ADDRESS (HEX)
NAME
MIBSPI-B
SIZE
DESCRIPTION
START END
0xFFF7_F600
0xFFF7_E500
0xFFF7_E700
0xFFF7_DC00
0xFFF7_C800
0xFFF7_A000
0xFFF7_D400
0xFFF7_F7FF
0xFFF7_E5FF
0xFFF7_E7FF
0xFFF7_DDFF
0xFFF7_CFFF
0xFFF7_A1FF
0xFFF7_D4FF
512 B
MIBSPI-B module configuration registers
SCI-A module configuration registers
SCI-B module configuration registers
CAN module configuration registers
CAN-FD module configuration registers
MCAN ECC module registers
SCI-A
148 B
148 B
512 B
768 B
452 B
112 B
SCI-B
CAN
CAN_FD(MCAN)
I2C
I2C module configuration registers
Interconnects
PCR-1
0xFFF7_8000
0xFCFF_1000
0xFFF7_87FF
0xFCFF_17FF
1 KiB
1 KiB
PCR-1 interconnect configuration port
PCR-2 interconnect configuration port
PCR-2
Safety Modules
CRC
0xFE00_0000
0xFFFF_E400
0xFFFF_E600
0xFFFF_EC00
0xFFFF_F400
0xFFFF_F500
0xFFFF_F600
0xFEFF_FFFF
0xFFFF_E5FF
0xFFFF_E7FF
0xFFFF_ECFF
0xFFFF_F4FF
0xFFFF_F5FF
0xFFFF_F6FF
16 KiB
464 B
284 B
44 B
CRC module configuration registers
PBIST module configuration registers
STC module configuration registers
DCC-A module configuration registers
DCC-B module configuration registers
ESM module configuration registers
CCMR4 module configuration registers
PBIST
STC
DCC-A
DCC-B
44 B
ESM
156 B
136 B
CCMR4
Security Modules
Crypto
0xFD00_0000
0XFDFF_FFFF
3 KiB
Crypto module configuration registers
Other Subsystems
DSS_TPTC0
DSS_REG
DSS_TPTC1
DSS_REG2
DSS_TPCC0
DSS_RTIA/WDT
DSS_SCI
0x5000 0000
0x5000 0400
0x5000 0800
0x5000 0C00
0x5001 0000
0x5002 0000
0x5003 0000
0x5004 0000
0x5007 0000
0x5009 0000
0x5009 0400
0x500A 0000
0x500D 0000
0x500F 0000
0x5000 0317
0x5000 075F
0x5000 0B17
0x5000 0EA3
0x5001 3FFF
0x5002 00BF
0x5003 0093
0x5004 011B
0x5007 0233
0x5009 0317
0x5009 0717
0x500A 3FFF
0x500D 005B
0x500F 00BF
0x511F FFFF
792 B
864 B
792 B
676 B
16 KB
192 B
148 B
284 B
564 B
792 B
792 B
16 KB
92 B
TPTC0 module configuration space
DSPSS control module registers
TPTC1 module configuration space
DSPSS control module registers
TPCC0 module configuration space
DSS_RTIA/WDT configuration space
SCI memory space
DSS_STC
DSS_CBUFF
DSS_TPTC2
DSS_TPTC3
DSS_TPCC1
DSS_ESM
DSS_RTIB
STC module configuration space
Common Buffer module configuration registers
TPTC2 module configuration space
TPTC3 module configuration space
TPCC1 module configuration space
ESM module configuration registers
RTI-B module configuration registers
L3 shared memory space
192 B
2 MB(1)
DSS_L3RAM Shared 0x5100 0000
memory
DSS_ADCBUF Buffer 0x5200 0000
DSS_CBUFF_FIFO 0x5202 0000
0x5200 7FFF
0x5202 3FFF
0x5208 7FFF
0x577F FFFF
32 KB
16 KB
32 KB
128 KB
ADC buffer memory space
Common buffer FIFO space
Handshake memory space
L2 RAM space
DSS_HSRAM1
0x5208 0000
DSS_DSP_L2_UMA 0x577E 0000
P1
DSS_DSP_L2_UMA 0x5780 0000
P0
0x5781 FFFF
0x57E0 7FFF
128 KB
32 KB
L2 RAM space
DSS_DSP_L1P
0x57E0 0000
L1 program memory space
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Table 8-1. Main Subsystem, Cortex-R4F Memory Map (continued)
FRAME ADDRESS (HEX)
START END
0x57F0 0000 0x57F0 7FFF
Peripheral Memories (System and Nonsystem)
NAME
SIZE
32 KB
DESCRIPTION
L1 data memory space
DSS_DSP_L1D
CAN RAM
0xFF1E_0000
0xFF50_0000
0xFFF8_0000
0xFCF8 1000
0xFFF8_2000
0xFF0C_0000
0xFF0C_0200
0xFF0E_0000
0xFF0E_0200
0xFF1F_FFFF
0xFF51_FFFF
0xFFF8_0FFF
0xFCF8_0FFF
0xFFF8_2FFF
0xFF0C_01FF
0xFF0C_03FF
0xFF0E_01FF
0xFF0E_03FF
128 KB
68 KB
4 KB
CAN RAM memory space
CAN-FD RAM
DMA1 RAM
CAN-FD RAM memory space
DMA1 RAM memory space
DMA2 RAM
4 KB
DMA2 RAM memory space
VIM RAM
2 KB
VIM RAM memory space
MIBSPIB-TX RAM
MIBSPIB-RX RAM
MIBSPIA-TX RAM
MIBSPIA- RX RAM
Debug Modules
Debug subsystem
0.5 KB
0.5 KB
0.5 KB
0.5 KB
MIBSPIB-TX RAM memory space
MIBSPIB-RX RAM memory space
MIBSPIA-TX RAM memory space
MIBSPIA- RX RAM memory space
0xFFA0_0000
0xFFAF_FFFF
244 KB
Debug subsystem memory space and registers
(1) 1024 KB memory within 2 MB memory space
8.3.5 DSP Subsystem Memory Map
Table 8-2 shows the DSP C674x memory map.
Table 8-2. DSP C674x Memory Map
Name
Frame Address (Hex)
Size
Description
Start
End
DSP Memories
DSP_L1D
0x00F0_0000
0x00E0_0000
0x00F0_7FFF
0x00E0_7FFF
32 KiB
32 KiB
L1 data memory space
DSP_L1P
L1 program memory
space
DSP_L2_UMAP0
DSP_L2_UMAP1
EDMA
0x0080_0000
0x007E_0000
0x0081_FFFF
0x007F_FFFF
128 KiB
128 KiB
L2 RAM space
L2 RAM space
TPCC0
0x0201_0000
0x020A_0000
0x0200 0000
0x0200 0800
0x0209_0000
0x0209_0400
0x0201_3FFF
0x020A_3FFF
0x0200 03FF
0x0200 0BFF
0x0209_03FF
0x0209_07FF
16 KiB
16 KiB
1 KiB
1 KiB
1 KiB
1 KiB
TPCC0 module
configuration space
TPCC1
TPTC0
TPTC1
TPTC2
TPTC3
TPCC1 module
configuration space
TPTC0 module
configuration space
TPTC1 module
configuration space
TPTC2 module
configuration space
TPTC3 module
configuration space
Control Registers
DSS_REG
0x0200_0400
0x0200_0C00
0x0200_07FF
0x0200_0FFF
864 B
624 B
DSPSS control module
registers
DSS_REG2
DSPSS control module
registers
System Memories
ADC Buffer
0x2100_0000
0x2100_7FFC
32 KiB
ADC buffer memory space
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Table 8-2. DSP C674x Memory Map (continued)
Name
Frame Address (Hex)
Size
Description
Start
End
CBUFF-FIFO
0x2102_0000
0x2102_3FFC
16 KiB
Common buffer FIFO
space
L3-Shared memory
HS-RAM
0x2000_0000
0x2108_0000
0x201F_FFFF
0x2108_7FFC
2 MB
L3 shared memory space
Handshake memory space
32 KiB
System Peripherals
RTI-A/WD
0x0202_0000
0x020F_0000
0x0207_0000
0x5060_1000
0x5060_2000
0x0460_8000
0x0202_00FF
0x020F_00FF
0x0207_03FF
0x5060_17FF
0x5060_27FF
0x0460_80FF
192 B
192 B
564 B
2 KiB
RTI-A module
configuration registers
RTI-B
RTI-B module
configuration registers
CBUFF
Common Buffer module
Configuration registers
Mail Box
MSS<->RADARSS
RADARSS to MSS
mailbox memory space
MSS to RADARSS
mailbox memory space
188 B
MSS to RADARSS
mailbox Configuration
registers
0x0460_8060
0x0460_86FF
RADARSS to MSS
mailbox Configuration
registers
Mail Box
MSS<->DSPSS
0x5060_4000
0x5060_5000
0x0460_8400
0x0460_8300
0x5060_6000
0x5060_7000
0x0460_8200
0x5060_47FF
0x5060_57FF
0x0460_84FF
0x0460_83FF
0x5060_67FF
0x5060_7FFF
0x0460_82FF
2 KiB
188 B
2 KiB
188 B
DSPSS to MSS mailbox
memory space
MSS to DSPSS mailbox
memory space
MSS to DSPSS mailbox
Configuration registers
DSPSS to MSS mailbox
Configuration registers
Mail Box
RADARSS<->DSPSS
RADARSS to DSPSS
mailbox memory space
DSPSS to RADARSS
mailbox memory space
RADARSS to DSPSS
mailbox Configuration
registers
0x0460_8100
0x0460_81FF
DSPSS to RADARSS
mailbox Configuration
registers
Safety Modules
ESM
0x020D_0000
0x2200_0000
0x0204_0000
92 B
ESM module
Configuration registers
CRC
STC
0x2200_03FF
0x0204_01FF
1 KiB
284 B
CRC module
Configuration registers
STC module Configuration
registers
Nonsystem Peripherals
SCI
0x0203_0000
0x0203_00FF
148 B
SCI module Configuration
registers
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8.4 Other Subsystems
8.4.1 ADC Channels (Service) for User Application
The AWR1843AOP device includes provision for an ADC service for user application, where the
GPADC engine present inside the device can be used to measure up to six external voltages. The ADC1, ADC2,
ADC3, ADC4, ADC5, and ADC6 pins are used for this purpose.
•
ADC itself is controlled by TI firmware running inside the BIST subsystem and access to it for customer’s
external voltage monitoring purpose is via ‘monitoring API’ calls routed to the BIST subsystem. This API
could be linked with the user application running on the MSS R4F.
•
BIST subsystem firmware will internally schedule these measurements along with other 1RF and Analog
monitoring operations. The API allows configuring the settling time (number of ADC samples to skip) and
number of consecutive samples to take. At the end of a frame, the minimum, maximum and average of the
readings will be reported for each of the monitored voltages.
GPADC Specifications:
•
•
•
•
625 Ksps SAR ADC
0 to 1.8V input range
10-bit resolution
For 5 out of the 6 inputs, an optional internal buffer is available. Without the buffer, the ADC has a switched
capacitor input load modeled with 5pF of sampling capacitance and 12pF parasitic capacitance (GPADC
channel 6, the internal buffer is not available).
5
ANALOG TEST 1-4,
ANAMUX
GPADC
5
VSENSE
Figure 8-5. ADC Path
8.4.1.1 GP-ADC Parameter
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TYP
1.8
UNIT
V
ADC supply
ADC unbuffered input voltage range
ADC buffered input voltage range(1)
ADC resolution
0 – 1.8
0.4 – 1.3
10
V
V
bits
LSB
LSB
LSB
LSB
Ksps
ns
ADC offset error
±5
ADC gain error
±5
ADC DNL
–1/+2.5
±2.5
625
ADC INL
ADC sample rate(2)
ADC sampling time(2)
400
1
GPADC structures are used for measuring the output of internal temperature sensors. The accuracy of these measurements is ±7°C
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TYP
10
2
UNIT
pF
ADC internal cap
ADC buffer input capacitance
ADC input leakage current
pF
3
uA
(1) Outside of given range, the buffer output will become nonlinear.
(2) ADC itself is controlled by TI firmware running inside the BIST subsystem. For more details please refer to the API calls.
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9 Monitoring and Diagnostics
9.1 Monitoring and Diagnostic Mechanisms
Below is the list given for the main monitoring and diagnostic mechanisms available in the AWR1843AOP.
Table 9-1. Monitoring and Diagnostic Mechanisms for AWR1843AOP
S No
Feature
Description
AWR1843AOP architecture supports hardware logic BIST (LBIST) engine self-test Controller
(STC). This logic is used to provide a very high diagnostic coverage (>90%) on the MSS
R4F CPU core and Vectored Interrupt Module (VIM) at a transistor level.
LBIST for the CPU and VIM need to be triggered by application code before starting the
functional safety application. CPU stays there in while loop and does not proceed further if a
fault is identified.
Boot time LBIST For MSS
R4F Core and associated
VIM
1
MSS R4F has three Tightly coupled Memories (TCM) memories TCMA, TCMB0 and
TCMB1. AWR1843AOP architecture supports a hardware programmable memory BIST
(PBIST) engine. This logic is used to provide a very high diagnostic coverage (March-13n)
on the implemented MSS R4F TCMs at a transistor level.
PBIST for TCM memories is triggered by Bootloader at the boot time before starting
download of application from Flash or peripheral interface. CPU stays there in while loop
and does not proceed further if a fault is identified.
Boot time PBIST for MSS
R4F TCM Memories
2
3
TCMs diagnostic is supported by Single error correction double error detection (SECDED)
ECC diagnostic. An 8-bit code word is used to store the ECC data as calculated over the
64-bit data bus. ECC evaluation is done by the ECC control logic inside the CPU. This
scheme provides end-to-end diagnostics on the transmissions between CPU and TCM. CPU
can be configured to have predetermined response (Ignore or Abort generation) to single
and double bit error conditions.
End to End ECC for MSS
R4F TCM Memories
Logical TCM word and its associated ECC code is split and stored in two physical SRAM
banks. This scheme provides an inherent diagnostic mechanism for address decode failures
in the physical SRAM banks. Faults in the bank addressing are detected by the CPU as an
ECC fault.
Further, bit multiplexing scheme implemented such that the bits accessed to generate a
logical (CPU) word are not physically adjacent. This scheme helps to reduce the probability
of physical multi-bit faults resulting in logical multi-bit faults; rather they manifest as multiple
single bit faults. As the SECDED TCM ECC can correct a single bit fault in a logical word,
this scheme improves the usefulness of the TCM ECC diagnostic.
MSS R4F TCM bit
multiplexing
4
Both these features are hardware features and cannot be enabled or disabled by application
software.
AWR1843AOP architecture supports Three Digital Clock Comparators (DCCs) and an
internal RCOSC. Dual functionality is provided by these modules – Clock detection and
Clock Monitoring.
DCCint is used to check the availability/range of Reference clock at boot otherwise the
device is moved into limp mode (Device still boots but on 10MHz RCOSC clock source.
This provides debug capability). DCCint is only used by boot loader during boot time. It is
disabled once the APLL is enabled and locked.
DCC1 is dedicated for APLL lock detection monitoring, comparing the APLL output divided
version with the Reference input clock of the device. Initially (before configuring APLL),
DCC1 is used by bootloader to identify the precise frequency of reference input clock
against the internal RCOSC clock source. Failure detection for DCC1 would cause the
device to go into limp mode.
5
Clock Monitor
DCC2 module is one which is available for user software . From the list of clock options
given in detailed spec, any two clocks can be compared. One example usage is to compare
the CPU clock with the Reference or internal RCOSC clock source. Failure detection is
indicated to the MSS R4F CPU via Error Signaling Module (ESM).
AWR1843AOP architecture supports the use of an internal watchdog that is implemented
in the real-time interrupt (RTI) module. The internal watchdog has two modes of operation:
digital watchdog (DWD) and digital windowed watchdog (DWWD). The modes of operation
are mutually exclusive; the designer can elect to use one mode or the other but not both at
the same time.
7
RTI/WD for MSS R4F
Watchdog can issue either an internal (warm) system reset or a CPU non-mask able
interrupt upon detection of a failure.
The Watchdog is enabled by the bootloader in DWD mode at boot time to track the boot
process. Once the application code takes up the control, Watchdog can be configured again
for mode and timings based on specific customer requirements.
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Table 9-1. Monitoring and Diagnostic Mechanisms for AWR1843AOP (continued)
S No
Feature
Description
Cortex-R4F CPU includes an MPU. The MPU logic can be used to provide spatial
separation of software tasks in the device memory. Cortex-R4F MPU supports 12 regions.
It is expected that the operating system controls the MPU and changes the MPU settings
based on the needs of each task. A violation of a configured memory protection policy
results in a CPU abort.
8
MPU for MSS R4F
AWR1843AOP architecture supports a hardware programmable memory BIST (PBIST)
engine for Peripheral SRAMs as well.
PBIST for peripheral SRAM memories can be triggered by the application. User can elect
PBIST for Peripheral interface to run the PBIST on one SRAM or on groups of SRAMs based on the execution time,
9
SRAMs - SPIs, CANs
which can be allocated to the PBIST diagnostic. The PBIST tests are destructive to memory
contents, and as such are typically run only at boot time. However, the user has the freedom
to initiate the tests at any time if peripheral communication can be hindered.
Any fault detected by the PBIST results in an error indicated in PBIST status registers.
Peripheral interface SRAMs diagnostic is supported by Single error correction double error
detection (SECDED) ECC diagnostic. When a single or double bit error is detected the
ECC for Peripheral interface MSS R4F is notified via ESM (Error Signaling Module). This feature is disabled after reset.
10
SRAMs – SPIs, CANs
Software must configure and enable this feature in the peripheral and ESM module. ECC
failure (both single bit corrected and double bit uncorrectable error conditions) is reported to
the MSS R4F as an interrupt via ESM module.
All the MSS peripherals (SPIs, CANs, I2C, DMAs, RTI/WD, DCCs, IOMUX etc.) are
connected to interconnect via Peripheral Central resource (PCR). This provides two
diagnostic mechanisms that can limit access to peripherals. Peripherals can be clock gated
per peripheral chip select in the PCR. This can be utilized to disable unused features such
that they cannot interfere. In addition, each peripheral chip select can be programmed to
limit access based on privilege level of transaction. This feature can be used to limit access
to entire peripherals to privileged operating system code only.
Configuration registers
protection for MSS
peripherals
11
These diagnostic mechanisms are disabled after reset. Software must configure and enable
these mechanisms. Protection violation also generates an ‘error’ that result in abort to MSS
R4F or error response to other masters such as DMAs.
AWR1843AOP architecture supports hardware CRC engine on MSS implementing the
below polynomials.
•
•
•
•
•
•
•
CRC16 CCITT – 0x10
CRC32 Ethernet – 0x04C11DB7
CRC64
CRC 32C – CASTAGNOLI – 0x1EDC6F4
CRC32P4 – E2E Profile4 – 0xF4ACFB1
CRC-8 – H2F Autosar – 0x2F
CRC-8 – VDA CAN – 0x1D
Cyclic Redundancy Check –
MSS
12
The read operation of the SRAM contents to the CRC can be done by CPU or by DMA.
The comparison of results, indication of fault, and fault response are the responsibility of the
software managing the test.
AWR1843AOP architecture supports MPUs on MSS DMAs. Failure detection by MPU is
reported to the MSS R4F CPU core as an interrupt via ESM.
13
14
MPU for DMAs
DSPSS’s high performance EDMAs also includes MPUs on both read and writes master
ports. EDMA MPUs supports 8 regions. Failure detection by MPU is reported to the DSP
core as an interrupt via local ESM.
AWR1843AOP architecture supports hardware logic BIST (LBIST) even for BIST R4F core
and associated VIM module. This logic provides very high diagnostic coverage (>90%) on
the BIST R4F CPU core and VIM.
This is triggered by MSS R4F boot loader at boot time and it does not proceed further if the
fault is detected.
Boot time LBIST For BIST
R4F Core and associated
VIM
AWR1843AOP architecture supports a hardware programmable memory BIST (PBIST)
engine for BIST R4F TCMs which provide a very high diagnostic coverage (March-13n)
on the BIST R4F TCMs.
PBIST is triggered by MSS R4F Bootloader at the boot time and it does not proceed further
if the fault is detected.
Boot time PBIST for BIST
R4F TCM Memories
15
16
BIST R4F TCMs diagnostic is supported by Single error correction double error detection
(SECDED) ECC diagnostic. Single bit error is communicated to the BIST R4FCPU while
double bit error is communicated to MSS R4F as an interrupt so that application code
becomes aware of this and takes appropriate action.
End to End ECC for BIST
R4F TCM Memories
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Table 9-1. Monitoring and Diagnostic Mechanisms for AWR1843AOP (continued)
S No
Feature
Description
Logical TCM word and its associated ECC code is split and stored in two physical SRAM
banks. This scheme provides an inherent diagnostic mechanism for address decode failures
in the physical SRAM banks and helps to reduce the probability of physical multi-bit faults
resulting in logical multi-bit faults.
BIST R4F TCM bit
multiplexing
17
AWR1843AOP architecture supports an internal watchdog for BIST R4F. Timeout condition
is reported via an interrupt to MSS R4F and rest is left to application code to either go for
SW reset for BIST SS or warm reset for the AWR1843AOP device to come out of faulty
condition.
18
19
20
RTI/WD for BIST R4F
AWR1843AOP architecture supports a hardware programmable memory BIST (PBIST)
engine for DSPSS’s L1P, L1D, L2 and L3 memories which provide a very high diagnostic
coverage (March-13n).
PBIST is triggered by MSS R4F Bootloader at the boot time and it does not proceed further
if the fault is detected.
Boot time PBIST for L1P,
L1D, L2 and L3 Memories
AWR1843AOP architecture supports Parity diagnostic on DSP’s L1P memory. Parity error is
reported to the CPU as an interrupt.
Note:- L1D memory is not covered by parity or ECC and need to be covered by application
level diagnostics.
Parity on L1P
AWR1843AOP architecture supports both Parity Single error correction double error
detection (SECDED) ECC diagnostic on DSP’s L2 memory. L2 Memory is a unified 256KB
of memory used to store program and Data sections for the DSP. A 12-bit code word is
used to store the ECC data as calculated over the 256-bit data bus (logical instruction fetch
size). The ECC logic for the L2 access is located in the DSP and evaluation is done by
the ECC control logic inside the DSP. This scheme provides end-to-end diagnostics on the
transmissions between DSP and L2. Byte aligned Parity mechanism is also available on L2
to take care of data section.
21
ECC on DSP’s L2 Memory
L3 memory is used as Radar data section in AWR1843AOP. AWR1843AOP architecture
supports Single error correction double error detection (SECDED) ECC diagnostic on L3
ECC on Radar Data Cube
(L3) Memory
memory. An 8-bit code word is used to store the ECC data as calculated over the 64-bit data
bus.
Failure detection by ECC logic is reported to the MSS R4F CPU core as an interrupt via
ESM.
22
23
AWR1843AOP architecture supports the use of an internal watchdog for BIST R4F that is
implemented in the real-time interrupt (RTI) module – replication of same module as used in
MSS. This module supports same features as that of RTI/WD for MSS/BIST R4F.
This watchdog is enabled by customer application code and Timeout condition is reported
via an interrupt to MSS R4F and rest is left to application code in MSS R4F to either go
for SW reset for DSP SS or warm reset for the AWR1843AOP device to come out of faulty
condition.
RTI/WD for DSP Core
AWR1843AOP architecture supports dedicated hardware CRC on DSPSS implementing the
below polynomials.
•
•
•
CRC16 CCITT - 0x10
CRC32 Ethernet - 0x04C11DB7
CRC64
24
25
CRC for DSP Sub-System
The read of SRAM contents to the CRC can be done by DSP CPU or by DMA. The
comparison of results, indication of fault, and fault response are the responsibility of the
software managing the test.
AWR1843AOP architecture supports MPUs for DSP memory accesses (L1D, L1P, and L2).
L2 memory supports 64 regions and 16 regions for L1P and L1D each. Failure detection by
MPU is reported to the DSP core as an abort.
MPU for DSP
AWR1843AOP architecture supports various temperature sensors all across the device
(next to power hungry modules such as PAs, DSP etc) which is monitored during the
inter-frame period.(1)
26
27
Temperature Sensors
Tx Power Monitors
AWR1843AOP architecture supports power detectors at the Tx output.(2)
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Table 9-1. Monitoring and Diagnostic Mechanisms for AWR1843AOP (continued)
S No
Feature
Description
When a diagnostic detects a fault, the error must be indicated. The AWR1843AOP
architecture provides aggregation of fault indication from internal monitoring/diagnostic
mechanisms using a peripheral logic known as the Error Signaling Module (ESM). The
ESM provides mechanisms to classify errors by severity and to provide programmable error
response.
ESM module is configured by customer application code and specific error signals can be
enabled or masked to generate an interrupt (Low/High priority) for the MSS R4F CPU.
AWR1843AOP supports Nerror output signal (IO) which can be monitored externally to
identify any kind of high severity faults in the design which could not be handled by the R4F.
Error Signaling
Error Output
28
Monitors Synthesizer’s frequency ramp by counting (divided-down) clock cycles and
comparing to ideal frequency ramp. Excess frequency errors above a certain threshold, if
any, are detected and reported.
Synthesizer (Chirp) frequency
monitor
29
30
AWR1843AOP architecture supports a ball break detection mechanism based on
Impedance measurement at the TX output(s) to detect and report any large deviations that
can indicate a ball break.
Monitoring is done by TIs code running on BIST R4F and failure is reported to the MSS R4F
via Mailbox.
Ball break detection for TX
ports (TX Ball break monitor)
It is completely up to customer SW to decide on the appropriate action based on the
message from BIST R4F.
Built-in TX to RX loopback to enable detection of failures in the RX path(s), including Gain/
Noise figure, inter-RX balance, etc.
31
32
33
34
RX loopback test
Built-in IF (square wave) test tone input to monitor IF filter’s frequency response and detect
failure.
IF loopback test
Provision to detect ADC saturation due to excessive incoming signal level and/or
interference.
RX saturation detect
Boot time LBIST for DSP core
AWR1843AOP device supports boot time LBIST for the DSP Core. LBIST can be triggered
by the MSS R4F application code during boot time.
(1) Monitoring is done by the TI's code running on BIST R4F. There are two modes in which it could be configured to report the
temperature sensed via API by customer application.
a. Report the temperature sensed after every N frames
b. Report the condition once the temperature crosses programmed threshold.
It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4Fvia Mailbox.
(2) Monitoring is done by the TI's code running on BIST R4F.
There are two modes in which it could be configured to report the detected output power via API by customer application.
a. Report the power detected after every N frames
b. Report the condition once the output power degrades by more than configured threshold from the configured.
It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4F.
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9.1.1 Error Signaling Module
When a diagnostic detects a fault, the error must be indicated. AWR1843AOP architecture provides aggregation
of fault indication from internal diagnostic mechanisms using a peripheral logic known as the error signaling
module (ESM). The ESM provides mechanisms to classify faults by severity and allows programmable error
response. Below is the high level block diagram for ESM module.
Low Priority
Low Priority
Interrupt
Interrupy
Handing
Error Group 1
Interrupt Enable
High Priority
Interrupt
Handing
High Priority
Interrupy
Interrupt Priority
Error Group 2
Error Group 3
Nerror Enable
Error Signal
Handling
Device Output
Pin
Figure 9-1. ESM Module Diagram
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10 Applications, Implementation, and Layout
Note
Information in the following Applications section is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI's customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
Application information can be found on AWR Application web page.
10.2 Reference Schematic
The reference schematic and power supply information can be found in the AWR1843AOP EVM Documentation.
Listed for convenience are: Design Files, Schematics, Layouts, and Stack up for PCB.
•
•
Altium AWR1843AOP EVM Design Files
AWR1843AOP EVM Schematic Drawing, Assembly Drawing, and Bill of Materials
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions follow.
11.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for example,
AWR1843AOP). Texas Instruments recommends two of three possible prefix designators for its support tools:
TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
P
Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
null Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package
type (for example, ALP0180A), the temperature range (for example, blank is the default commercial temperature
range). Figure 11-1 provides a legend for reading the complete device name for any AWR1843AOP device.
For orderable part numbers of AWR1843AOP devices in the ALP0180 package types, see the Package Option
Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the AWR1843AOP Device Errata.
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1
8
43
A
R
B
G
ALP
AWR
Qualification
Blank= no special qual
Q1 = AEC-Q100
Tray or Tape & Reel
R = Tape & Reel
Blank = Tray
Package
ALP = 180-Ball FCBGA, Rev2.0
Prefix
XA = Pre-production Automotive
AWR = Production Automotive
Generation
1 = 77 GHz Band
6 = 60 GHz Band
Variant
2 = FE
Security
4 = FE + FFT + MCU
6 = FE + MCU + DSP
8 = FE + MCU + FFT + DSP
G = General
S = Secure
Num RX/TX Channels
RX = 1,2,3,4
TX = 1,2,3
Silicon PG Revision
A = Rev2.0
Features
Blank = baseline
R = Antenna on Package (AoP)
Safety Level
Q = Non-Functional Safety
B = Functional Safety Compliant, ASIL-B
Figure 11-1. Device Nomenclature
Note
The silicon revision information, Rev2.0, is different from the device revision information, ES1.0,
mentioned in the Errata document. The device revision information ES1.0 is related to both silicon and
package revisions.
11.2 Tools and Software
Models
AWR1843AOP IBIS model IO buffer information model for the IO buffers of the device. For simulation on a
circuit board, see IBIS Open Forum.
11.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
The current documentation that describes the DSP, related peripherals, and other technical collateral follows.
Errata
AWR1843AOP device errata Describes known advisories, limitations, and cautions on silicon and provides
workarounds.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
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Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
12.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
CAUTION
The following package information is subject to change without notice.
Note
Variability in the color (or appearance) of Texas Instrument’s (TI’s) Antenna-on-Package (AoP) product
is normal and expected. This variation is not indicative of any degradation or variability to the
performance specifications of the AoP products.
12.2 Tray Information for ALP, 15 × 15 mm
Package
Type
Package
Name
Unit Array
Matrix
Max Temp.
(°C)
L
W
(mm)
K0
(mm)
P1
(mm)
CL
(mm)
CW
(mm)
Device
Pins
SPQ
(mm)
AWR1843ARBGALPQ1
AWR1843ARBSALPQ1
FCBGA
FCBGA
ALP
ALP
180
180
126
126
7x18
7x18
150
150
315
315
135.9
135.9
7.62
7.62
17.2
17.2
11.30
11.30
16.35
16.35
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PACKAGE OPTION ADDENDUM
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6-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AWR1843ARBGALPQ1
AWR1843ARBGALPRQ1
AWR1843ARBSALPQ1
AWR1843ARBSALPRQ1
XA1843ARBGALP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
ALP
ALP
ALP
ALP
ALP
180
180
180
180
180
126
RoHS & Green
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
AWR1843 BG
1000 RoHS & Green
126 RoHS & Green
1000 RoHS & Green
TBD
Call TI
Call TI
Call TI
Call TI
AWR1843 BG
AWR1843 BS
AWR1843 BS
1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Nov-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
ALP0180A
FCBGA - 0.965 mm max height
S
C
A
L
E
1
.
1
0
0
PLASTIC BALL GRID ARRAY
15.1
14.9
B
A
BALL A1
CORNER
15.1
14.9
0.965 MAX
C
SEATING PLANE
0.2 C
0.53
0.27
13.6 TYP
SYMM
(0.7)
(0.7)
V
U
T
(2.85)
(4.03)
R
P
N
M
L
K
J
SYMM
(9.29)
13.6
TYP
(6.94)
H
G
F
E
D
C
(0.15) TYP
ALL AROUND
B
A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
0.8 TYP
0.612
0.512
180X
0.8 TYP
(7.1)
(3.58)
(2.85)
0.15
0.08
C A B
C
(9.29)
4225336/A 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ALP0180A
FCBGA - 0.965 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
180X ( 0.4)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
A
(0.8) TYP
B
C
D
E
F
G
H
SYMM
J
K
L
M
N
P
R
T
U
V
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 6X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED METAL
(
0.4)
(
0.4)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
METAL EDGE
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225336/A 09/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
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EXAMPLE STENCIL DESIGN
ALP0180A
FCBGA - 0.965 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
180X ( 0.4)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
A
(0.8) TYP
B
C
D
E
F
G
H
SYMM
J
K
L
M
N
P
R
T
U
V
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 6X
4225336/A 09/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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