AMC1400-Q1 [TI]

具有高 CMTI 的汽车类 ±250mV 输入、精密电压检测增强型隔离式放大器;


型号：	AMC1400-Q1
厂家：	TEXAS INSTRUMENTS
描述：	具有高 CMTI 的汽车类 ±250mV 输入、精密电压检测增强型隔离式放大器放大器
文件：	总33页 (文件大小：1818K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AMC1400-Q1

ZHCSPH8 –JULY 2022

AMC1400-Q1 采用15mm 扩展型SOIC 封装的

TLA7312 高阻抗2V 输入增强型隔离放大器

1 特性

3 说明

• 符合面向汽车应用的AEC-Q100 标准：

– 温度等级1：–40°C 至+125°C，T_A

• 提供功能安全型

AMC1400-Q1 是一款隔离式精密放大器，此放大器的

输出与输入电路由抗电磁干扰性能极强的隔离栅隔开。

该隔离栅经认证可提供高达 7.5 kV_RMS的增强型电隔

离，符合 DIN EN IEC 60747-17 (VDE 0884-17) 和

UL1577 标准，并且可支持高达2 kV_RMS的工作电压。

– 有助于进行功能安全系统设计的文档

• ±250mV 输入电压范围，针对使用分流电阻器测量

电流进行了优化

• 固定增益：8.2 V/V

• 低直流误差：

该隔离层可将系统中以不同共模电压电平运行的各器件

隔开，防止高电压冲击导致低压侧器件电气损坏或对操

作员造成伤害。

– 失调电压误差：±0.2mV（最大值）

– 温漂±0.9µV/°C（最大值）

– 增益误差：±0.3%（最大值）

– 增益漂移：±30ppm/°C（最大值）

– 非线性度：0.03%（最大值）

• 高侧和低侧以3.3V 或5V 电压运行

• 高侧电源缺失检测功能

AMC1400-Q1 的输入针对直接连接低阻抗分流电阻器

或其他具有低信号电平的低阻抗电压源的情况进行了优

化。出色的直流精度和低温漂移支持精确的电压检测，

适用于直流/直流转换器、太阳能或风力涡轮机逆变

器、交流电机驱动器或其他必须在高电压、高海拔或高

度污染环境下运行的应用。

AMC1400-Q1 采用宽体 8 引脚 SOIC 封装，符合面向

汽车应用的 AEC-Q100 标准，并支持 –40°C 至

+125°C 的温度范围。

• 高CMTI：100kV/µs（最小值）

• 低EMI，符合CISPR-11 和CISPR-25 标准

• 安全相关认证：

封装信息⁽¹⁾

– 符合DIN EN IEC 60747-17 (VDE 0884-17) 标

准的7000V_PK增强型隔离

– 符合UL1577 标准且长达1 分钟的7500V_RMS

隔离

封装尺寸（标称值）

器件型号

封装

SOIC (8)

AMC1400-Q1

6.40 mm × 14.00 mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 基于分流电阻器的电流感应，可用于：

– HEV/EV 充电桩

– HEV/EV 车载充电器(OBC)

– HEV/EV 直流/直流转换器

– HEV/EV 牵引逆变器

High-side supply

(3.3 V or 5 V)

Low-side supply

(3.3 V or 5 V)

AMC1400-Q1

VDD1

INP

VDD2

OUTP

+250 mV

–250 mV

0 V

V_CMout

±2.05 V

ADC

INN

OUTN

GND2

GND1

典型应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBASAI2

AMC1400-Q1

ZHCSPH8 –JULY 2022

www.ti.com.cn

Table of Contents

7.1 Overview...................................................................17

7.2 Functional Block Diagram.........................................17

7.3 Feature Description...................................................17

7.4 Device Functional Modes..........................................19

8 Application and Implementation..................................20

8.1 Application Information............................................. 20

8.2 Typical Application.................................................... 20

8.3 Best Design Practices...............................................25

8.4 Power Supply Recommendations.............................26

8.5 Layout....................................................................... 27

9 Device and Documentation Support............................28

9.1 Documentation Support............................................ 28

9.2 接收文档更新通知..................................................... 28

9.3 支持资源....................................................................28

9.4 Trademarks...............................................................28

9.5 Electrostatic Discharge Caution................................28

9.6 术语表....................................................................... 28

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Power Ratings.............................................................5

6.6 Insulation Specifications............................................. 6

6.7 Safety-Related Certifications...................................... 7

6.8 Safety Limiting Values.................................................7

6.9 Electrical Characteristics.............................................8

6.10 Switching Characteristics..........................................9

6.11 Timing Diagram.........................................................9

6.12 Insulation Characteristics Curves........................... 10

6.13 Typical Characteristics............................................ 11

7 Detailed Description......................................................17

Information.................................................................... 28

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

July 2022

Initial Release

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5 Pin Configuration and Functions

VDD1

INP

VDD2

OUTP

OUTN

GND2

INN

GND1

Not to scale

图5-1. DWL Package, 8-Pin SOIC (Top View)

表5-1. Pin Functions

NAME

TYPE

DESCRIPTION

NO.

VDD1

INP

High-side power

Analog input

High-side power supply.⁽¹⁾

Noninverting analog input. Either INP or INN must have a DC current path to GND1

to define the common-mode input voltage.⁽²⁾

Inverting analog input. Either INP or INN must have a DC current path to GND1 to

define the common-mode input voltage.⁽²⁾

INN

Analog input

GND1

GND2

OUTN

OUTP

VDD2

High-side ground

Low-side ground

Analog output

High-side analog ground.

Low-side analog ground.

Inverting analog output.

Noninverting analog output.

Low-side power supply.⁽¹⁾

Analog output

Low-side power

(1) See the Power Supply Recommendations section for power-supply decoupling recommendations.

(2) See the Layout section for details.

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6 Specifications

6.1 Absolute Maximum Ratings

see⁽¹⁾

MIN

–0.3

MAX

UNIT

High-side VDD1 to GND1

6.5

Power-supply voltage

Low-side VDD2 to GND2

–0.3

Analog input voltage

Output voltage

Input current

INP, INN

VDD1 + 0.5

VDD2 + 0.5

GND1 –6

GND2 –0.5

–10

OUTP, OUTN

Continuous, any pin except power-supply pins

Junction, T_J

Storage, T_stg

150

Temperature

°C

150

–65

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions . If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾, HBM ESD classification Level 2

Charged-device model (CDM), per AEC Q100-011, CDM ESD classification Level C6

V_(ESD)

Electrostatic discharge

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

POWER SUPPLY

High-side power supply

Low-side power supply

ANALOG INPUT

V_ClippingDifferential input voltage before clipping output

VDD1 to GND1

VDD2 to GND2

5.5

3.3

±320

V_IN= V_INP–V_INN

V_FSR

V_CM

Specified linear differential full-scale voltage

Operating common-mode input voltage

250

–250

VDD1 –

2.1

(V_INP+ V_INN) / 2 to GND1

–0.16

ANALOG OUTPUT

C_LOAD

R_LOAD

Capacitive load

On OUTP or OUTN to GND2

OUTP to OUTN

500

250

kΩ

Capacitive load

Resistive load

On OUTP or OUTN to GND2

TEMPERATURE RANGE

T_ASpecified ambient temperature

125

°C

–40

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6.4 Thermal Information

DWL (SOIC)

8 PINS

63.2

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)Junction-to-case (top) thermal resistance

26.1

R_θJB

Ψ_JT

Junction-to-board thermal resistance

28.5

Junction-to-top characterization parameter

Junction-to-board characterization parameter

7.8

26.8

Ψ_JB

R_θJC(bot)Junction-to-case (bottom) thermal resistance

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Power Ratings

PARAMETER

TEST CONDITIONS

VALUE

UNIT

P_D

Maximum power dissipation (both sides) VDD1 = VDD2 = 5.5 V

VDD1 = 3.6 V

Maximum power dissipation (high-side)

VDD1 = 5.5 V

P_D1

VDD2 = 3.6 V

P_D2

Maximum power dissipation (low-side)

VDD2 = 5.5 V

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UNIT

6.6 Insulation Specifications

over operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VALUE

GENERAL

CLR

External clearance⁽¹⁾

External creepage⁽¹⁾

Shortest pin-to-pin distance through air

≥14.7

≥15.7

CPG

Shortest pin-to-pin distance across the package surface

Minimum internal gap (internal clearance) of the double

insulation

DTI

CTI

Distance through insulation

µm

≥21

Comparative tracking index

Material group

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

≥600

I-IV

I-III

Rated mains voltage ≤600 V_RMS

Rated mains voltage ≤1000 V_RMS

Overvoltage category

per IEC 60664-1

DIN EN IEC 60747-17 (VDE 0884-17)⁽²⁾

Maximum repetitive peak

V_IORM

At AC voltage

2800

V_PK

isolation voltage

At AC voltage (sine wave)

2000

2800

V_RMS

V_DC

Maximum-rated isolation

V_IOWM

working voltage

At DC voltage

V_TEST= V_IOTM, t = 60 s (qualification test)

V_TEST= 1.2 × V_IOTM, t = 1 s (100% production test)

Tested in air, 1.2/50-µs waveform per IEC 62368-1

10600

12720

9800

Maximum transient

V_IOTM

V_PK

isolation voltage

V_IMP

Maximum impulse voltage⁽³⁾

V_PK

Maximum surge

Tested in oil (qualification test),

1.2/50-µs waveform per IEC 62368-1

V_IOSM

12800

≤5

isolation voltage⁽⁴⁾

Method a, after input/output safety test subgroups 2 and 3,

V_ini= V_IOTM, t_ini= 60 s, V_pd(m)= 1.2 × V_IORM, t_m= 10 s

Method a, after environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s, V_pd(m)= 1.6 × V_IORM, t_m= 10 s

≤5

q_pd

Apparent charge⁽⁵⁾

Method b1, at routine test (100% production) and

preconditioning (type test), V_ini= V_IOTM, t_ini= 1 s, V_pd(m)= 1.875

× V_IORM, t_m= 1 s

≤5

Barrier capacitance,

input to output⁽⁶⁾

C_IO

R_IO

V_IO= 0.5 V_PPat 1 MHz

~1.5

V_IO= 500 V at T_A= 25°C

> 10¹²

> 10¹¹

> 10⁹

Insulation resistance,

input to output⁽⁶⁾

V_IO= 500 V at 100°C ≤T_A≤125°C

V_IO= 500 V at T_S= 150°C

Pollution degree

Climatic category

55/125/21

UL1577

V_TEST= V_ISO= 7500 V_RMS, t = 60 s (qualification),

V_TEST= 1.2 × V_ISO= 9000 V_RMS, t = 1 s (100% production test)

V_ISO

Withstand isolation voltage

7500

V_RMS

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be

taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the

printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques

such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured

by means of suitable protective circuits.

(3) Testing is carried out in air to determine the surge immunity of the package.

(4) Testing is carried in oil to determine the intrinsic surge immunity of the isolation barrier.

(5) Apparent charge is electrical discharge caused by a partial discharge (pd).

(6) All pins on each side of the barrier are tied together, creating a two-pin device.

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6.7 Safety-Related Certifications

VDE

DIN EN IEC 60747-17 (VDE 0884-17),

EN IEC 60747-17,

DIN EN IEC 62368-1 (VDE 0868-1),

EN IEC 62368-1,

Recognized under 1577 component recognition program

IEC 62368-1 Clause : 5.4.3 ; 5.4.4.4 ; 5.4.9

Reinforced insulation

Single protection

Certificate number: 40040142 (pending)

File number: E181974

6.8 Safety Limiting Values

Safety limiting⁽¹⁾intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure

of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to over-

heat the die and damage the isolation barrier potentially leading to secondary system failures.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

_θJA= 63.2°C/W, VDDx = 3.6 V,

550

T_J= 150°C, T_A= 25°C

_θJA= 63.2°C/W, VDDx = 5.5 V,

T_J= 150°C, T_A= 25°C

_θJA= 63.2°C/W, T_J= 150°C, T_A= 25°C

I_S

Safety input, output, or supply current

360

P_S

T_S

Safety input, output, or total power

Maximum safety temperature

1980

150

°C

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The I_S

and P_Sparameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of I_Sand P_S. These

limits vary with the ambient temperature, T_A.

The junction-to-air thermal resistance, R_θJA, in the Thermal Information table is that of a device installed on a high-K test board for

leaded surface-mount packages. Use these equations to calculate the value for each parameter:

T_J= T_A+ R_θJA× P, where P is the power dissipated in the device.

T_J(max)= T_S= T_A+ R_θJA× P_S, where T_J(max)is the maximum junction temperature.

P_S= I_S× VDD_max, where VDD_maxis the maximum supply voltage for high-side and low-side.

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6.9 Electrical Characteristics

minimum and maximum specifications apply from T_A= –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP

= –250 mV to +250 mV, and INN = GND1; typical specifications are at T_A= 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

ANALOG INPUT

V_OS

Input offset voltage^{(1) (2)}

Input offset drift^{(1) (2) (4)}

T_A= 25°C, INP = INN = GND1

±0.01

±0.1

–100

–98

0.2

–0.2

–0.9

TCV_OS

0.9 µV/°C

f_IN= 0 Hz, V_{CM min}≤V_CM≤V_{CM max}

f_IN= 10 kHz, V_{CM min}≤V_CM≤V_{CM max}

INN = GND1

CMRR

Common-mode rejection ratio

R_IN

R_IND

I_IB

Single-ended input resistance

Differential input resistance

Input bias current

kΩ

INP = INN = GND1; I_IB= (I_IBP+ I_IBN) / 2

µA

–41

–30

±5

–24

I_IO

Input offset current

I_IO= I_IBP–I_IBN; INP = INN = GND1

INN = GND1, f_IN= 275 kHz

f_IN= 275 kHz

C_IN

C_IND

Single-ended input capacitance

Differential input capacitance

ANALOG OUTPUT

Nominal gain

8.2

±0.04%

±5

V/V

E_G

Gain error⁽¹⁾

T_A= 25°C

0.3%

–0.3%

–30

TCE_G

Gain drift^{(1) (5)}

30 ppm/°C

0.03%

Nonlinearity⁽¹⁾

±0.01%

–85

–0.03%

THD

SNR

Total harmonic distortion⁽³⁾

f_IN= 10 kHz

INP = INN = GND1, f_IN= 0 Hz,

BW = 100 kHz brickwall filter

Output noise

230

µV_RMS

f_IN= 1 kHz, BW = 10 kHz

f_IN= 10 kHz, BW = 100 kHz

PSRR vs VDD1, at DC

81.5

Signal-to-noise ratio

–100

PSRR vs VDD1,

100-mV and 10-kHz ripple

–96

–106

–86

PSRR

Power-supply rejection ratio⁽²⁾

PSRR vs VDD2, at DC

PSRR vs VDD2,

100-mV and 10-kHz ripple

V_CMout

Common-mode output voltage

1.39

1.44

1.49

2.52

V_OUT= (V_OUTP–V_OUTN);

|V_IN| = |V_INP–V_INN| > |V_Clipping

V_CLIPout

Clipping differential output voltage

±2.49

–2.52

V_Failsafe

Failsafe differential output voltage

Output bandwidth

VDD1 missing

kHz

–2.63

–2.57

310

–2.53

250

R_OUT

Output resistance

On OUTP or OUTN

< 0.2

On OUTP or OUTN, sourcing or sinking,

INN = INP = GND1, outputs shorted to

either GND2 or VDD2

Output short-circuit current

CMTI

Common-mode transient immunity

100

150

kV/µs

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6.9 Electrical Characteristics (continued)

minimum and maximum specifications apply from T_A= –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP

= –250 mV to +250 mV, and INN = GND1; typical specifications are at T_A= 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER SUPPLY

VDD1 rising

2.5

2.4

2.7

2.6

2.45

2.0

6.3

7.2

5.3

5.9

2.9

VDD1 undervoltage detection

threshold

VDD1_UV

VDD2_UV

IDD1

VDD1 falling

2.8

VDD2 rising

2.2

2.65

2.2

VDD2 undervoltage detection

threshold

VDD2 falling

1.85

8.5

9.8

3.0 V ≤VDD1 ≤3.6 V

4.5 V ≤VDD1 ≤5.5 V

3.0 V ≤VDD2 ≤3.6 V

4.5 V ≤VDD2 ≤5.5 V

High-side supply current

Low-side supply current

7.2

8.1

IDD2

(1) The typical value includes one standard deviation (sigma) at nominal operating conditions.

(2) This parameter is input referred.

(3) THD is the ratio of the rms sum of the amplitudes of first five higher harmonics to the amplitude of the fundamental.

(4) Offset error temperature drift is calculated using the box method, as described by the following equation:

TCV_OS= (Value_MAX- Value_MIN) / TempRange

(5) Gain error temperature drift is calculated using the box method, as described by the following equation:

TCE_G(ppm) = (Value_MAX- Value_MIN) / (Value_(T=25℃)x TempRange) x 10⁶

6.10 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

1.3

MAX

UNIT

µs

t_r

t_f

Output signal rise time

Output signal fall time

µs

V_INxto V_OUTxsignal delay (50% - 10%)

V_INxto V_OUTxsignal delay (50% - 50%)

V_INxto V_OUTxsignal delay (50% - 90%)

Unfiltered output

1.5

2.1

µs

Unfiltered output

1.6

2.5

µs

VDD1 step to 3.0 V with VDD2 ≥3.0 V,

to V_OUTP, V_OUTNvalid, 0.1% settling

t_AS

Analog settling time

500

µs

6.11 Timing Diagram

250 mV

INP - INN

– 250 mV

t_f

t_r

OUTN

OUTP

V_CMout

50% - 10%

50% - 50%

50% - 90%

图6-1. Rise, Fall, and Delay Time Definition

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6.12 Insulation Characteristics Curves

600

VDD1 = VDD2 = 3.6 V

VDD1 = VDD2 = 5.5 V

500

400

300

200

100

125

150

T_A(°C)

D069

图6-3. Thermal Derating Curve for Safety-Limiting Power per

图6-2. Thermal Derating Curve for Safety-Limiting Current per

VDE

T_Aup to 150°C, stress-voltage frequency = 60 Hz, isolation working voltage = 2000 V_RMS, operating lifetime = 34 year

图6-4. Reinforced Isolation Capacitor Lifetime Projection

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6.13 Typical Characteristics

at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and f_IN= 10 kHz (unless otherwise noted)

200

150

100

200

150

100

VDD1

VDD2

Device 1

Device 2

Device 3

-50

-100

-150

-200

-100

-150

-200

3.5

4.5

VDDx (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D027

D026

图6-5. Input Offset Voltage vs Supply Voltage

图6-6. Input Offset Voltage vs Temperature

-20

-70

-75

-80

-40

-85

-60

-90

-95

-80

-100

-105

-110

-100

-120

0.001

0.01

0.1

f_IN(kHz)

100

1000

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D038

D039

图6-7. Common-Mode Rejection Ratio vs Input Frequency

图6-8. Common-Mode Rejection Ratio vs Temperature

-23

-25

-27

-29

-31

-33

-35

-37

-39

-41

-5

-15

-25

-35

-45

-0.5

0.5

1.5

2.5

3.5

4.5

VDD1 (V)

5.5

V_CM(V)

D003

D004

图6-9. Input Bias Current vs Common-Mode Input Voltage

图6-10. Input Bias Current vs High-Side Supply Voltage

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6.13 Typical Characteristics (continued)

at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and f_IN= 10 kHz (unless otherwise noted)

-23

-25

-27

-29

-31

-33

-35

-37

-39

-41

0.3

0.2

0.1

-0.1

-0.2

-0.3

VDD1

3.5

4.5

VDDx (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D020

D005

图6-12. Gain Error vs Supply Voltage

图6-11. Input Bias Current vs Temperature

0.3

0.2

0.1

Device 1

Device 2

Device 3

-5

-10

-15

-20

-25

-30

-35

-40

-0.1

-0.2

-0.3

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

100

1000

f_IN(kHz)

D021

D007

图6-13. Gain Error vs Temperature

图6-14. Normalized Gain vs Input Frequency

0°

4.5

OUTN

OUTP

-45°

-90°

3.5

-135°

-180°

-225°

-270°

-315°

-360°

2.5

1.5

0.5

100

1000

-350

-250

-150

-50

150

Differential Input Voltage (mV)

250

350

f_IN(kHz)

D008

D006

图6-15. Output Phase vs Input Frequency

图6-16. Output Voltage vs Input Voltage

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6.13 Typical Characteristics (continued)

at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and f_IN= 10 kHz (unless otherwise noted)

0.03

0.025

0.02

0.03

0.02

0.01

VDD1

VDD2

0.015

0.01

0.005

-0.005

-0.01

-0.015

-0.02

-0.025

-0.03

-0.01

-0.02

-0.03

-250 -200 -150 -100 -50

Differential Input Voltage (mV)

50 100 150 200 250

3.5

4.5

VDDx (V)

5.5

D028

D029

图6-17. Nonlinearity vs Input Voltage

图6-18. Nonlinearity vs Supply Voltage

0.03

0.02

0.01

-70

-75

Device 1

Device 2

Device 3

VDD1

VDD2

-80

-85

-0.01

-0.02

-0.03

-90

-95

-100

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

3.5

4.5

VDDx (V)

5.5

D030

D056

图6-19. Nonlinearity vs Temperature

图6-20. Total Harmonic Distortion vs Supply Voltage

-70

-75

10000

1000

100

-80

-85

-90

Device 1

Device 2

Device 3

-95

-100

0.1

Frequency (kHz)

100

1000

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D017

D059

图6-22. Input-Referred Noise Density vs Frequency

图6-21. Total Harmonic Distortion vs Temperature

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6.13 Typical Characteristics (continued)

at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and f_IN= 10 kHz (unless otherwise noted)

77.5

VDD1

VDD2

72.5

67.5

62.5

3.5

4.5

VDDx (V)

5.5

100

150

|V_INP- V_INN| (mV)

200

250

300

D034

D032

图6-24. Signal-to-Noise Ratio vs Supply Voltage

图6-23. Signal-to-Noise Ratio vs Input Voltage

77.5

-20

-40

-60

72.5

67.5

-80

Device 1

Device 2

Device 3

62.5

-100

VDD2

VDD1

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

-120

0.001

0.01

0.1

Ripple Frequency (kHz)

100

1000

D041

图6-25. Signal-to-Noise Ratio vs Temperature

图6-26. Power-Supply Rejection Ratio vs Ripple Frequency

1.49

1.48

1.47

1.46

1.45

1.44

1.43

1.42

1.41

1.4

1.49

1.48

1.47

1.46

1.45

1.44

1.43

1.42

1.41

1.4

1.39

3.5

4.5

VDD2 (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D009

D010

图6-27. Output Common-Mode Voltage vs Low-Side Supply

图6-28. Output Common-Mode Voltage vs Temperature

Voltage

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6.13 Typical Characteristics (continued)

at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and f_IN= 10 kHz (unless otherwise noted)

360

340

320

300

280

260

240

360

340

320

300

280

260

240

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

3.5

4.5

VDD2 (V)

5.5

D012

D011

图6-30. Output Bandwidth vs Temperature

图6-29. Output Bandwidth vs Low-Side Supply Voltage

8.5

7.5

6.5

5.5

4.5

IDD1 vs VDD1

IDD2 vs VDD2

IDD1

IDD2

3.5

4.5

VDDx (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D043

D044

图6-31. Supply Current vs Supply Voltage

图6-32. Supply Current vs Temperature

3.5

2.5

1.5

0.5

3.5

4.5

VDD2 (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D065

D066

图6-33. Output Rise and Fall Time vs Low-Side Supply

图6-34. Output Rise and Fall Time vs Temperature

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6.13 Typical Characteristics (continued)

at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and f_IN= 10 kHz (unless otherwise noted)

3.8

3.4

3.8

3.4

50% - 90%

50% - 50%

50% - 10%

50% - 90%

50% - 50%

50% - 10%

2.6

2.2

1.8

1.4

2.6

2.2

1.8

1.4

0.6

0.2

0.6

0.2

3.5

4.5

VDD2 (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D067

D068

图6-35. V_INto V_OUTSignal Delay vs Low-Side Supply Voltage

图6-36. V_INto V_OUTSignal Delay vs Temperature

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7 Detailed Description

7.1 Overview

The AMC1400-Q1 is a fully differential, precision, isolated amplifier. The input stage of the device consists of a

fully differential amplifier that drives a second-order, delta-sigma (ΔΣ) modulator. The modulator converts the

analog input signal into a digital bitstream that is transferred across the isolation barrier that separates the high-

side from the low-side. On the low-side, the received bitstream is processed by a fourth-order analog filter that

outputs a differential signal at the OUTP and OUTN pins that is proportional to the input signal.

The SiO₂-based, capacitive isolation barrier supports a high level of magnetic field immunity, as described in the

ISO72x Digital Isolator Magnetic-Field Immunity application report. The digital modulation used in the AMC1400-

Q1 to transmit data across the isolation barrier, and the isolation barrier characteristics itself, result in high

reliability and common-mode transient immunity.

7.2 Functional Block Diagram

VDD1

VDD2

OUTP

OUTN

GND2

AMC1400-Q1

Diagnostics

Analog Filter

INP

ΔΣ Modulator

INN

GND1

7.3 Feature Description

7.3.1 Analog Input

The differential amplifier input stage of the AMC1400-Q1 feeds a second-order, switched-capacitor, feed-forward

ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors with a differential input

impedance of R_IND. The modulator converts the analog input signal into a bitstream that is transferred across the

isolation barrier, as described in the Isolation Channel Signal Transmission section.

There are two restrictions on the analog input signals INP and INN. First, if the input voltages V_INPor V_INN

exceed the range specified in the Absolute Maximum Ratings table, the input currents must be limited to the

absolute maximum value, because the electrostatic discharge (ESD) protection turns on. In addition, the linearity

and parametric performance of the device are ensured only when the analog input voltage remains within the

linear full-scale range (V_FSR) and within the common-mode input voltage range (V_CM), as specified in the

Recommended Operating Conditions table.

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7.3.2 Isolation Channel Signal Transmission

The AMC1400-Q1 uses an on-off keying (OOK) modulation scheme, as shown in 图 7-1, to transmit the

modulator output bitstream across the SiO₂-based isolation barrier. The transmit driver (TX) shown in the

Functional Block Diagram transmits an internally-generated, high-frequency carrier across the isolation barrier to

represent a digital one and does not send a signal to represent a digital zero. The nominal frequency of the

carrier used inside the AMC1400-Q1 is 480 MHz.

The receiver (RX) on the other side of the isolation barrier recovers and demodulates the signal and provides the

input to the fourth-order analog filter. The AMC1400-Q1 transmission channel is optimized to achieve the highest

level of common-mode transient immunity (CMTI) and lowest level of radiated emissions caused by the high-

frequency carrier and RX/TX buffer switching.

Internal Clock

Modulator Bitstream

on High-side

Signal Across Isolation Barrier

Recovered Sigal

on Low-side

图7-1. OOK-Based Modulation Scheme

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7.3.3 Analog Output

The AMC1400-Q1 offers a differential analog output comprised of the OUTP and OUTN pins. For differential

input voltages (V_INP–V_INN) in the range from –250 mV to +250 mV, the device provides a linear response with

a nominal gain of 8.2. For example, for a differential input voltage of 250 mV, the differential output voltage

(V_OUTP– V_OUTN) is 2.05 V. At zero input (INP shorted to INN), both pins output the same common-mode output

voltage V_CMout, as specified in the Electrical Characteristics table. For absolute differential input voltages greater

than 250 mV but less than 320 mV, the differential output voltage continues to increase in magnitude but with

reduced linearity performance. The outputs saturate at a differential output voltage of V_CLIPout, as shown in 图

7-2, if the differential input voltage exceeds the V_Clippingvalue.

Maximum input range before clipping (V_Clipping

)

Linear input range (V_FSR

)

V_OUTN

V_CLIPout

V_OUTP

V_FAILSAFE

V_CMout

– 320 mV

– 250 mV

320 mV

250 mV

Differential Input Voltage (V_INP– V_INN

)

图7-2. Output Behavior of the AMC1400-Q1

The AMC1400-Q1 offers a fail-safe feature that simplifies diagnostics on a system level. 图 7-2 shows the fail-

safe mode, in which the AMC1400-Q1 outputs a negative differential output voltage that does not occur under

normal operating conditions. The fail-safe output is active in two cases:

• When the high-side supply is missing or below the VDD1_UVthreshold

• When the common-mode input voltage, that is V_CM= (V_INP+ V_INN) / 2, exceeds the common-mode

overvoltage detection level V_CMov

Use the maximum V_FAILSAFEvoltage specified in the Electrical Characteristics table as a reference value for fail-

safe detection on a system level.

7.4 Device Functional Modes

The AMC1400-Q1 is operational when the power supplies VDD1 and VDD2 are applied, as specified in the

Recommended Operating Conditions table.

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8 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

With its stretched SOIC package, the AMC1400-Q1 is specifically designed for isolated, high precision, shunt-

based current sensing in applications with 800-V and higher working voltages. This device is designed for

operating in harsh environments with a high pollution degree or high altitudes.

8.2 Typical Application

图 8-1 depicts a simplified block diagram of a DC/DC converter for an 800-V battery system where the

AMC1400-Q1 is used to measure the input current on the high-voltage side. The DC bus current flows through a

shunt resistor (RSHUNT) and produces a voltage drop that is sensed by the AMC1400-Q1. The AMC1400-Q1

outputs a differential analog voltage that is proportional to the input signal and galvanically isolated from the

high-voltage side. The differential output voltage is typically routed to an analog-to-digital converter (ADC) of a

microcontroller (MCU) to complete the current-sensing signal chain. The AMC1411-Q1 is used in the same

application for measuring the DC bus voltage. Both devices share a common high-side power supply based on

the SN6501-Q1 push-pull driver and a transformer that supports the desired isolation voltage ratings.

The stretched SOIC package, differential input, differential output, and the high common-mode transient

immunity (CMTI) of the AMC1400-Q1 ensure reliable and accurate operation in high-noise environments while

meeting IEC standards for reinforced isolation at 1 kV and higher working voltages.

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+V_BUS

V12V

DC/DC

RSHUNT

– V_BUS

C12 1 µF

C11 100 nF

R12 10

C14 1 µF

AMC1400-Q1

C13 100 nF

VDD1

VDD2

OUTP

OUTN

GND2

INP

to RC filter / ADC

C15

10 nF

R11 10

INN

GND1

C22 1 µF

C24 1 µF

AMC1411-Q1

C21 100 nF

C23 100 nF

VDD1

VDD2

OUTP

OUTN

GND2

to RC filter / ADC

C25 100 pF

SHTDN

GND1

TPS76350-Q1

SN6501-Q1

GND

VCC

V_OUT= 5 V

OUT

GND

10 μF 100 nF

10 μF

100 nF 4.7 μF

图8-1. Using the AMC1400-Q1 for Current Sensing in a Typical Application

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8.2.1 Design Requirements

表8-1 lists the parameters for this typical application.

表8-1. Design Requirements

PARAMETER

DC bus voltage

VALUE

1000 V (maximum)

Overvoltage category

Pollution degree

Altitude

≤4000 m

3.3 V or 5 V

10 A

High-side supply voltage

Low-side supply voltage

Transient peak DC/DC input current

Nominal DC/DC input current

Voltage drop across RSHUNT for a linear response

Maximum voltage drop across RSHUNT before clipping

4 A

±250 mV (maximum)

±320 mV (maximum)

8.2.2 Detailed Design Procedure

The value of the shunt resistor (RSHUNT) is selected such that the transient peak input current to the DC/DC

converter (10 A) produces a voltage drop across the shunt resistor that matches the linear full-scale input range

of the AMC1400-Q1 (250 mV). Consider the following two restrictions when selecting the value of the shunt

resistor:

• The voltage drop across the shunt caused by the nominal-rated DC link current range must not exceed the

recommended differential input voltage range for a linear response: |V_SHUNT| ≤|V_FSR

• The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes

a clipping output: |V_SHUNT| ≤|V_Clipping

In this example, a 25-mΩ shunt resistor is selected (RSHUNT = 250 mV / 10 A).

At the nominal-rated current, the power dissipation in the shunt resistor is R × I²= 25 mΩ × (4 A)²= 0.4 W. For

surface-mounted shunts, the heat is mainly dissipated via the device terminals and the printed circuit board

(PCB) traces. The power rating of a shunt is typically specified for a 70°C terminal temperature and derated for

higher temperatures. This rating ensures that the shunt itself does not exceed its specified maximum operating

temperature at the rated power dissipation. Careful PCB design is required not to exceed the terminal

temperature at the rated power dissipation. Using wide copper traces to spread the heat over a larger area of the

PCB, heat sinks, and air flow can improve the thermal design.

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8.2.2.1 Insulation Coordination

Electrical insulation must be designed to withstand the rated impulse voltage, temporary overvoltage, and the

working voltage. In addition, the physical distance between exposed metal parts on the high- and low-voltage

sides must meet the minimum creepage and clearance requirements for the rated working voltage and transient

overvoltages.

The ISO 17409:2020 standard specifies that an electrical road vehicle must be designed to withstand a minimum

impulse voltage of 2500 V. The minimum clearance to support a 2500-V impulse voltage is 1.5 mm for basic

isolation and 3.0 mm for reinforced isolation, according to Table F.2 of the IEC60664-1 standard. The equipment

is designed to operate at altitudes up to 4000 m above sea level and the minimum clearance must be increased

to 1.29 × 3 mm = 4 mm (rounded up). The factor of 1.29 is taken from table A.2 of the IEC60664-1 standard. The

AMC1400-Q1 provides a minimum clearance of 14.7 mm and easily meets the requirement.

The maximum temporary overvoltage, a voltage that must be sustained for 60 s, is typically determined be the

formula 2 × V_WM+ 1000 V, where V_WMis the maximum working voltage that can occur under normal operating

conditions. In this example, V_WMequals the maximum DC bus voltage (1000 V) and the maximum temporary

overvoltage is calculated to be 3000 V_PK(2 × 1000 V + 1000 V = 3000 V). If the overvoltage test (also known as

the HiPot test) is performed for 1 s only, the test voltage must be multiplied with a factor of 1.2 times and

becomes 3600 V (1.2 × 3000 V = 3600 V). The minimum clearance to support a 3600-V temporary overvoltage

is 5.5 mm for basic isolation and 8.0 mm for reinforced isolation. These values are taken from Table 9 of the

IEC61800-5-1 standard. The equipment is designed to operate at altitudes up to 4000 m above sea level and the

minimum clearance must be increased to 1.29 × 8 mm = 10.5 mm (rounded up). The factor of 1.29 is taken from

Table A.2 of the IEC60664-1 standard. The AMC1400-Q1 provides a minimum clearance of 14.7 mm and easily

meets the requirement.

The working voltage in this example is 1000 V_DCand is lower than the maximum working voltage (V_IOWM) of

2800 V_DC) that the AMC1400-Q1 supports.

Finally, the minimum creepage distance for a working voltage of 1000 V_DC, insulating material group I, pollution

degree 2, and reinforced isolation is 2 × 5 mm = 10 mm according to IEC60664-1 Table F.4. The 5-mm value for

the 1000-V basic insulation is doubled for reinforced isolation. The AMC1400-Q1 provides a minimum creepage

of 15.7 mm and provides significant margin against the minimum requirement.

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8.2.2.2 Input Filter Design

Place an RC filter in front of the isolated amplifier to improve the signal-to-noise performance of the signal path.

Design the input filter such that:

• The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency (20

MHz) of the ΔΣmodulator

• The input bias current does not generate a significant voltage drop across the DC impedance of the input

filter

• The impedances measured from the analog inputs are equal

For most applications, the structure shown in 图8-2 achieves excellent performance.

AMC1400-Q1

VDD1

VDD2

OUTP

OUTN

GND2

10 nF

INP

INN

GND1

图8-2. Differential Input Filter

8.2.2.3 Differential to Single-Ended Output Conversion

图 8-3 shows an example of a TLV9001-Q1-based signal conversion and filter circuit for systems using single-

ended input ADCs to convert the analog output voltage into digital. With R1 = R2 = R3 = R4, the output voltage

equals (V_OUTP– V_OUTN) + V_REF. Tailor the bandwidth of this filter stage to the bandwidth requirement of the

system and use NP0-type capacitors for best performance. For most applications, R1 = R2 = R3 = R4 = 3.3 kΩ

and C1 = C2 = 330 pF yields good performance.

AMC1400-Q1

VDD1

VDD2

OUTP

OUTN

GND2

INP

–

ADC

To MCU

INN

TLV9001-Q1

GND1

V_REF

图8-3. Connecting the AMC1400-Q1 Output to a Single-Ended Input ADC

For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see the

18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data

Acquisition Block (DAQ) Optimized for Lowest Power reference guides, available for download at www.ti.com.

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8.2.3 Application Curve

One important aspect of a power-stage design is the effective detection of an overcurrent condition to protect the

switching devices and passive components from damage. To power off the system quickly in the event of an

overcurrent condition, a low delay caused by the isolated amplifier is required. 图 8-4 shows the typical full-scale

step response of the AMC1400-Q1.

VOUTN

VOUTP

VIN

图8-4. Step Response of the AMC1400-Q1

8.3 Best Design Practices

Do not leave the inputs of the AMC1400-Q1 unconnected (floating) when the device is powered up. If the device

inputs are left floating, the input bias current may drive the inputs to a positive value that exceeds the operating

common-mode input voltage and the output voltage may not be valid.

Connect the high-side ground (GND1) to INN, either by a hard short or through a resistive path. A DC current

path between INN and GND1 is required to define the input common-mode voltage. Take care not to exceed the

input common-mode range, as specified in the Recommended Operating Conditions table. For best accuracy,

route the ground connection as a separate trace that connects directly to the shunt resistor rather than shorting

GND1 to INN directly at the input to the device. See the Layout section for more details.

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8.4 Power Supply Recommendations

The AMC1400-Q1 does not require any specific power-up sequencing. The high-side power supply (VDD1) is

decoupled with a low-ESR, 100-nF capacitor (C1) parallel to a low-ESR, 1-µF capacitor (C2). The low-side

power supply (VDD2) is equally decoupled with a low-ESR, 100-nF capacitor (C3) parallel to a low-ESR, 1-µF

capacitor (C4). Place all four capacitors (C1, C2, C3, and C4) as close to the device as possible.

The ground reference for the high-side (GND1) is derived from the end of the shunt resistor, which is connected

to the negative input (INN) of the device. For best DC accuracy, use a separate trace (as shown in 图 8-5) to

make this connection instead of shorting GND1 to INN directly at the device input. If a four-terminal shunt is

used, the device inputs are connected to the inner leads and GND1 is connected to the outer lead on the INN-

side of the shunt.

INP

VDD1

VDD2

C2 1 µF

C1 100 nF

R2 10

C4 1 µF

AMC1400-Q1

C3 100 nF

VDD1

VDD2

OUTP

OUTN

GND2

INP

to RC filter / ADC

10 nF

R1 10

INN

GND1

图8-5. Decoupling of the AMC1400-Q1

Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they

experience in the application. Multilayer ceramic capacitors (MLCCs) typically exhibit only a fraction of their

nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting

these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is

higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves

that greatly simplify component selection.

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AMC1400-Q1

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8.5 Layout

8.5.1 Layout Guidelines

图 8-6 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as

possible to the AMC1400-Q1 supply pins) and placement of the other components required by the device. For

best performance, place the shunt resistor close to the INP and INN inputs of the AMC1400-Q1 and keep the

layout of both connections symmetrical.

The ground pin (GND1) of the AMC1400-Q1 is connected to the same end of the shunt resistor that is connected

to the negative input pin (INN) of the AMC1400-Q1. If a four-pin shunt is used, the input pins (INN and INP) of

the AMC1400-Q1 are connected to the inner leads, and the GND1 pin is connected to the outer lead on the INN-

side of the shunt resistor. To minimize offset and improve accuracy, route the ground connection as a separate

trace that connects directly to the shunt resistor rather than shorting GND1 to INN directly at the input to the

device.

8.5.2 Layout Example

Clearance area, to be kept free of

any conductive materials.

INP

to RC filter / ADC

OUTP

OUTN

GND2

AMC1400-Q1

INN

GND1

Top Metal

Inner or Bottom Layer Metal

Via

图8-6. Recommended Layout of the AMC1400-Q1

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9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Isolation Glossary application note

• Texas Instruments, Semiconductor and IC Package Thermal Metrics application note

• Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application note

• Texas Instruments, TLV900x-Q1 Low-Power RRIO 1-MHz Automotive Operational Amplifier data sheet

• Texas Instruments, TPS763xx-Q1 Low-Power, 150-mA, Low-Dropout Linear Regulators data sheet

• Texas Instrument, SN6501-Q1 Transformer Driver for Isolated Power Supplies data sheet

• Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise

reference guide

• Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Power reference

guide

• Texas Instruments, Isolated Amplifier Voltage Sensing Excel Calculator design tool

• Texas Instruments, Best in Class Radiated Emissions EMI Performance with the AMC1300B-Q1 Isolated

Amplifier technical white paper

9.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

9.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

30-Sep-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

AMC1400QDWLRQ1

ACTIVE

SOIC

DWL

500

RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 125

1400Q

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OUTLINE

DWL0008A

SOIC - 4.034 mm max height

PLASTIC SMALL OUTLINE

SEATING PLANE

17.4

17.1

PIN 1 ID AREA

0.1 C

6X 1.27

6.5

6.3

NOTE 3

3.81

0.51

0.31

(3.634)

14.1

13.9

NOTE 4

0.25

A B C

4.034 MAX

0.33

0.13

TYP

SEE DETAIL A

(1.625)

0.25

GAGE PLANE

0.3

0.1

1.1

0.6

0 -8

DETAIL A

TYPICAL

4224743/A 01/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0,15 mm per side.

4. This dimension does not include interlead flash.

www.ti.com

EXAMPLE BOARD LAYOUT

DWL0008A

SOIC - 4.034 mm max height

PLASTIC SMALL OUTLINE

(14.25)

SYMM

(14.6)

8X (1.875)

8X (2)

SYMM

8X (0.6)

SYMM

(R0.05)

TYP

(R0.05)

TYP

(1.27)

(16.475)

(16.25)

LAND PATTERN EXAMPLE

PCB CLEARANCE & CREEPAGE OPTIMIZED

EXPOSED METAL SHOWN

SCALE:3X

LAND PATTERN EXAMPLE

STANDARD

EXPOSED METAL SHOWN

SCALE:3X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

EXPOSED METAL

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224743/A 01/2019

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DWL0008A

SOIC - 4.034 mm max height

PLASTIC SMALL OUTLINE

8X (2)

SYMM

8X (0.6)

6X (1.27)

(16.25)

SOLDER PASTE EXAMPLE

STANDARD

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

SYMM

8X (1.875)

8X (0.6)

SYMM

6X (1.27)

(16.475)

SOLDER PASTE EXAMPLE

PCB CLEARANCE & CREEPAGE OPTIMIZED

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

4224743/A 01/2019

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

AMC1400-Q1 [TI]

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