ALM2402F-Q1 [TI]

汽车类双通道高输出电流运算放大器;


型号：	ALM2402F-Q1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类双通道高输出电流运算放大器放大器运算放大器
文件：	总33页 (文件大小：2695K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ALM2402F-Q1

ZHCSJP5B –MAY 2019 –REVISED OCTOBER 2021

具有高电流输出、用于旋转变压器励磁的

ALM2402F-Q1 汽车类双路运算放大器

1 特性

3 说明

• 符合面向汽车应用的AEC-Q100 标准：

– 温度等级1：–40°C 至+125°C，T_A

• 提供功能安全

ALM2402F-Q1 是一款双电源运算放大器，其特性和性

能使该器件更适合基于旋转变压器的汽车应用。该器件

具有高增益带宽和压摆率以及连续高输出电流驱动功

能，从而成为提供现代旋转变压器所需的低失真和差分

高振幅激励的理想之选。在易受故障影响的电线上驱动

模拟信号时，电流限制和过热检测功能可增强整体系统

稳健性。

– 可帮助进行功能安全系统设计的文档

• 低失调电压：1mV（典型值）

• 高输出电流驱动：400mA 持续电流（每通道）

– 取代分立式运算放大器和晶体管

• 两个电源的宽电源电压范围（最高16V）

• 过热关断

ALM2402F-Q1 的轨到轨输出通过低 R_ds(on)PMOS 和

NMOS 晶体管实现，可保持较低的功率耗散。具有散

热焊盘和低 R_θJA的小型 HTSSOP 封装使用户能够向

负载提供高电流，同时最大程度地减小布板空间。当用

于现代混合动力和电动汽车时，该最小化的布板空间是

ALM2402F-Q1 提供的主要优势之一。

• 电流限制

• 实现低I_Q应用的关断引脚

• 在大容性负载下保持稳定

• 2MHz 增益带宽，具有3.4V/µs 的压摆率

• 内部射频/EMI 滤波器

通过本页底部的最大输出电压与频率间的关系图，可

确定ALM2402F-Q1 的最大输出电压。

• 封装：14 引脚HTSSOP (PWP)

2 应用

器件信息⁽¹⁾

• 基于旋转变压器的汽车应用

• 逆变器和电机控制

• 制动系统

封装尺寸（标称值）

器件型号

封装

ALM2402F-Q1

HTSSOP (14)

5.00mm × 4.40mm

• 电动助力转向(EPS)

• 后视镜模块

• 汽车电子视镜

(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。

• 伺服驱动器功率级模块

V_{CC_OUT}

V_s= 12 V

V_s= 4.5 V

V_CC

V_{CC_O1}

IN1+

IN1–

ALM2402F-Q1

OUT1

OPAMP

–

OTF1

GND

简化版原理图

100

1k 10k

Frequency (Hz)

100k

10M

D013

最大输出电压与频率间的关系

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBOS927

ALM2402F-Q1

ZHCSJP5B –MAY 2019 –REVISED OCTOBER 2021

www.ti.com.cn

Table of Contents

7.4 Device Functional Modes..........................................17

8 Application and Implementation..................................18

8.1 Application Information............................................. 18

8.2 Typical Application.................................................... 19

9 Power Supply Recommendations................................23

10 Layout...........................................................................24

10.1 Layout Guidelines................................................... 24

10.2 Layout Example...................................................... 24

11 Device and Documentation Support..........................25

11.1 Documentation Support.......................................... 25

11.2 接收文档更新通知................................................... 25

11.3 支持资源..................................................................25

11.4 Trademarks............................................................. 25

11.5 Electrostatic Discharge Caution..............................25

11.6 术语表..................................................................... 25

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics: V_S= 12 V...........................5

6.6 Electrical Characteristics: V_S= 5 V.............................6

6.7 Typical Characteristics................................................8

7 Detailed Description......................................................14

7.1 Overview...................................................................14

7.2 Functional Block Diagram.........................................14

7.3 Feature Description...................................................15

Information.................................................................... 25

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (September 2019) to Revision B (October 2021)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 向特性部分添加了功能安全的项目符号..............................................................................................................1

Changes from Revision * (May 2019) to Revision A (September 2019)

Page

• 将器件状态从预告信息（预发布）更改为量产数据（正在供货）.......................................................................1

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5 Pin Configuration and Functions

IN(1)œ

IN(1)+

GND

OUT(1)

VS_O(1)

OTF/SH_DN

IN(2)+

Thermal

Pad

IN(2)œ

VS_O(2)

OUT(2)

GND

Not to scale

图5-1. PWP (14-Pin HTSSOP) Package, Top View

表5-1. Pin Functions

I/O

DESCRIPTION

NAME

GND

NO.

6, 14

Input

Ground pin (both ground pins must be used and connected together on board)

Noninverting op amp input terminal 1

Noninverting op amp input terminal 2

Inverting op amp input terminal 1

Inverting op amp input terminal 2

No internal connection (do no connect)

Overtemperature flag and shutdown (see 表7-1 for truth table)

Op amp output 1

IN(1)+

IN(2)+

IN(1)–

IN(2)–

7, 8

—

Input/output

Output

Input

OTF/SH_DN

OUT(1)

OUT(2)

Op amp output 2

Gain stage supply pin

VS_O(1)

VS_O(2)

Input

Output stage supply pin

Input

Output stage supply pin

Connect the exposed thermal pad to ground for best thermal performance. Do not connect

the thermal pad to any pin other than GND. The thermal pad can also be left floating.

Thermal pad

—

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

–0.3

MAX

UNIT

Input supply voltage, V_S= (V+) –(V–)

Output supply voltage, V_{S_O}

Positive and negative input to GND voltage

Overtemperature flag pin current

Overtemperature flag pin voltage

Output short-circuit⁽²⁾

Continuous

–40

Continuous

125

Operating temperature

°C

Junction temperature

150

Storage temperature, T_stg

150

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Short-circuit to ground; one amplifier per package. Long-term, short-circuit operation leads to an elevated die temperature and a

shorter lifetime, and places the amplifier into open-loop operation. Prolonged open-loop operation (especially at high temperatures and

supplies) can lead to a shift in the dc electrical characteristics, such as offset voltage (see the Open-Loop and Closed-Loop Operation

section).

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

HBM ESD Classification Level 2

±2000

V_(ESD)

Electrostatic discharge

Charge Device Model (CDM), per AEC Q100-011

CDM ESD Classification Level C5

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

NOM

MAX

UNIT

Input supply voltage, V_S= (V+) –V(–)

Output supply voltage, V_{S_O}

Continous output current (sourcing) ⁽¹⁾

Continous output current (sinking) ⁽¹⁾

OTF input high voltage (op amp on or full operational state)

OTF input low voltage (op amp off or shutdown state)

Postitive and negative input to GND voltage

Overtemperature flag pin voltage

400

0.35

Specified temperature

125

°C

–40

(1) Current Limit must be taken into consideration when choosing maximum output current.

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6.4 Thermal Information

ALM2402FQ1

THERMAL METRIC⁽¹⁾

PWP (TSSOP)

14 PINS

46.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

°C/W

R_θJC(top)

R_θJB

33.0

Junction-to-board thermal resistance

27.6

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.5

ψ_JT

27.4

ψ_JB

R_θJC(bot)

2.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics: V_S= 12 V

at T_A= 25°C, V_S= V_{S_O1}= V_{S_O2}= 12 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, V_OTF= 5 V, and V_O= V_S/ 2 (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

±1

±7

V_OS

Input offset voltage

μV/°C

±15

T_A= –40°C to +125°C

dV_OS/dT

PSRR

Input offset voltage drift

T_A= –40°C to +125°C

V_S= 10 V to 16 V

Input offset voltage versus

power supply

V_S= 10 V to 16 V, T_A= –40°C to +125°C

INPUT BIAS CURRENT

±3.5

±2

±15

±140

±12

I_B

Input bias current

T_A= –40°C to +125°C

I_OS

Input offset current

Input voltage noise

±35

NOISE

5.5

115

μV_PP

µV_RMS

f = 0.1 Hz to 10 Hz

e_N

i_N

Input voltage noise density f = 1 kHz

nV/√Hz

fA/√Hz

Input current noise

f = 1 kHz

INPUT VOLTAGE RANGE

V_CM

Common-mode voltage

V_S> 8.2 V

0.2

0.2 V < V_CM< 7 V

Common-mode rejection

ratio

CMRR

T_A= –40℃to +125℃, 0.2 V < V_CM< 7 V

OPEN-LOOP GAIN

0.3 V < V_O< (V_S) –1.5 V,

R_L= 10 kΩ

A_OL

Open-loop voltage gain

T_A= –40°C to +125°C

FREQUENCY RESPONSE

GBW

t_S

Gain-bandwidth product

C_L= 15 pF

2.1

3.4

2.4

MHz

V/μs

μs

Slew rate

5-V step, G = +1 V/V, C_L= 50 pF

To 0.1%, 5-V step , G = +1 V/V

V_IN× (–1) × gain > V_S

Settling time

Overload recovery time

μs

(V+) = 11 V, (V–) = –5 V, V_O= 6 V_PP, G = +2 V/V, f = 1

kHz,

R_L= 100 Ω

Total harmonic distortion +

noise

THD+N

–73

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6.5 Electrical Characteristics: V_S= 12 V (continued)

at T_A= 25°C, V_S= V_{S_O1}= V_{S_O2}= 12 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, V_OTF= 5 V, and V_O= V_S/ 2 (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT

T_A= 25°C

0.3

0.5

T_A= –40°C to +125℃,

I_SOURCE= 200 mA

130

300

Positive rail, V_ID= 100 mV

T_A= –40°C to +125℃,

I_SOURCE= 100 mA

0.4

150

0.6

Voltage output swing from

rail

V_o

T_A= 25°C

TA = –40°C to +125℃,

I_SINK= 200 mA

200

550

Negative rail, V_ID= 100 mV

T_A= –40°C to +125℃,

I_SINK= 100 mA

100

200

Sinking (short to supply)

Sourcing (short to ground)

540

750

I_SC

Short-circuit current

POWER SUPPLY

I_O= 0 A, T_A= 25℃

Quiescent current per

amplifier

I_Q

I_O= 0 A, T_A= –40°C to +125°C

V_{OTF/SH_DN}= 0 V

0.5

TEMPERATURE

Thermal shutdown

165

159

°C

Thermal shutdown

recovery

Overtemperature fault low

voltage

V_{OL_OTF}

400

R_PULLUP= 2.5 kΩ, V_PULLUP= 5.0 V

V_{IH_OTF}

V_{IL_OTF}

Amplifier enable voltage

Amplifier disable voltage

0.35

6.6 Electrical Characteristics: V_S= 5 V

at T_A= 25°C, V_S= V_{S_O1}= V_{S_O2}= 5 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, V_OTF= 5 V, and V_O= V_S/ 2 (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

T_A= 25°C

±1

±7

V_OS

Input offset voltage

±15

T_A= –40°C to +125°C

V_S= 4.5 V to 10 V

dV_OS/dT

Input offset voltage drift

μV/°C

Input offset voltage versus

power supply

PSRR

V_{S =}4.5 V to 10 V,

T_A= –40°C to +125°C

INPUT BIAS CURRENT

T_A= 25°C

0.5

±2

±30

±2

I_B

Input bias current

T_A= –40°C to +125°C

T_A= 25°C

I_OS

Input offset current

±9

T_A= –40°C to +125°C

NOISE

5.5

115

μV_PP

µV_RMS

Input voltage noise

f = 0.1 Hz to 10 Hz

e_N

i_N

Input voltage noise density f = 1 kHz

Input current noise f = 1 kHz

nV/√Hz

fA/√Hz

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6.6 Electrical Characteristics: V_S= 5 V (continued)

at T_A= 25°C, V_S= V_{S_O1}= V_{S_O2}= 5 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, V_OTF= 5 V, and V_O= V_S/ 2 (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT VOLTAGE RANGE

V_CM

Common-mode voltage

0.2

(V+) –1.2

0.2 V < V_CM< (V+) –1.2 V

Common-mode rejection

ratio

CMRR

T_A= –40℃to +125℃,

0.2 V < V_CM< (V+) –1.2 V

OPEN-LOOP GAIN

T_A= 25°C

0.3 V < V_O< (V_S) –1.5 V,

R_L= 10 kΩ

A_OL

Open-loop voltage gain

T_A= –40°C to +125°C

FREQUENCY RESPONSE

GBW

t_S

Gain-bandwidth product

C_L= 15 pF

1.3

1.7

MHz

2-V step, G = +1 V/V,

C_L= 50 pF

Slew rate

V/μs

Settling time

To 0.1%, 2-V step , G = +1 V/V

μs

Overload recovery time

V_IN× (–1) × gain > V_S

V_S= 5 V, V_O= 2.82 V_PP, G = +2 V/V,

f = 1 kHz, R_L= 100 Ω

Total harmonic distortion +

noise

THD+N

–73

OUTPUT

T_A= 25°C

0.3

0.5

T_A= –40°C to +125℃,

I_SINK= 200 mA

130

300

Positive rail, V_ID= 100 mV

T_A= –40°C to +125℃,

I_SINK= 100 mA

0.4

150

0.6

Voltage output swing from

rail

V_o

T_A= 25°C

TA = –40°C to +125℃,

I_SINK= 200 mA

200

575

Negative rail, V_ID= 100 mV

T_A= –40°C to +125℃,

I_SINK= 100 mA

100

200

Sinking (short to supply)

Sourcing (short to ground)

500

550

I_SC

Short-circuit current

POWER SUPPLY

4.5

I_O= 0 A, T_A= 25℃

Quiescent current per

amplifier

I_Q

I_O= 0 A, T_A= –40°C to +125°C

V_{OTF/SH_DN}= 0 V

0.5

TEMPERATURE

Thermal shutdown

165

159

°C

Thermal shutdown

recovery

Overtemperature fault low

voltage

V_{OL_OTF}

400

R_PULLUP= 2.5 kΩ, V_PULLUP= 5.0 V

V_{IH_OTF}

V_{IL_OTF}

Amplifier enable voltage

Amplifier disable voltage

0.35

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6.7 Typical Characteristics

at T_A= 25°C, V_S= 12 V, V_CM= V_{S_O1}= V_{S_O2}= V_S/2, and R_L= 10 kΩ(unless otherwise noted)

-40 èC

25 èC

-10

-20

-30

125 èC

-6

-5

-4

-3

-2

-1

Input Common-mode Voltage (V)

-120

-100

-80

-60

-40

-20

Offset Voltage Drift (µV/èC)

D017

D001

5 typical units

图6-2. Offset Voltage

图6-1. Offset Voltage Drift

vs Input Common-Mode Voltage

Production Distribution

120

180

Gain

Phase

100

150

120

-1

-2

-3

-4

-5

-20

-30

Supply Voltage (V)

100m

100

Frequency (Hz)

10k

100k

10M

D018

D002

5 typical units

C_LOAD= 200 nF

R_L= 50 Ω

图6-3. Offset Voltage vs Power Supply

图6-4. Open-Loop Gain and Phase

vs Frequency

V_S= 12 V

V_S= 4.5 V

G = +1

G = -1

G = +10

-10

-20

100

Load Capacitance (pF)

1000

100

10k 100k

Frequency (Hz)

10M

D003

D004

Gain = 1 V/V

图6-5. Phase Margin vs Capacitive Load

图6-6. Closed-Loop Gain vs Frequency

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6.7 Typical Characteristics (continued)

at T_A= 25°C, V_S= 12 V, V_CM= V_{S_O1}= V_{S_O2}= V_S/2, and R_L= 10 kΩ(unless otherwise noted)

100

120

100

PSRR+, V_S= 12 V

PSRR-, V_S= 12 V

PSRR+, V_S= 4.5 V

PSRR-, V_S= 4.5 V

V_S= 12 V

V_S= 4.5 V

100

1k 10k

Frequency (Hz)

100k

10M

100

1k 10k

Frequency (Hz)

100k

10M

D005

D006

图6-7. PSRR vs Frequency

图6-8. CMRR vs Frequency

-40

-60

-80

R_LOAD= 100 W

R_LOAD= 10K W

R_LOAD= 100 W

R_LOAD= 10K W

0.1

0.01

0.1

0.01

-60

-80

0.001

-100

0.001

-100

10m

100m

Output Amplitude (V_RMS

100

Frequency (Hz)

10k

)

D011

D010

Input signal

Measurement

V_O= 8 V_PP

Gain = 2 V/V

Measurement

frequency =1 kHz bandwidth = 80 kHz

bandwidth = 80 kHz

图6-10. THD+N vs Output Amplitude

图6-9. THD+N Ratio vs Frequency

V_s= 12 V

V_s= 4.5 V

I_B

I_OS

-8

-16

-6

-4.5

-3

-1.5

Input Common-mode Voltage (V)

1.5

100

1k 10k

Frequency (Hz)

100k

10M

D019

D013

图6-12. Input Bias Current

图6-11. Maximum Output Voltage

vs Common-Mode Voltage

vs Frequency

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6.7 Typical Characteristics (continued)

at T_A= 25°C, V_S= 12 V, V_CM= V_{S_O1}= V_{S_O2}= V_S/2, and R_L= 10 kΩ(unless otherwise noted)

4.5

-40 èC

25 èC

3.5

I_B

85 èC

2.5

I_B

125 èC

1.5

I_OS

0.5

-5

0.2

0.4 0.6

Output Current (A)

0.8

-40

-20

100 120 140

Temperature (èC)

D022

D020

图6-14. Output Voltage Swing

图6-13. Input Bias Current vs Temperature

vs Output Source Current

-1.5

-3

130

125

120

115

110

105

100

85 èC

-40 èC

125 èC

-4.5

-6

25 èC

0.2

0.4

Output Current (A)

0.6

0.8

-40

-20

100 120 140

Temperature (èC)

D024

D025

图6-15. Output Voltage Swing

图6-16. CMRR vs Temperature

vs Output Sink Current

Time (1 s/div)

-40

-20

100 120 140

Temperature (èC)

D027

D026

图6-18. 0.1-Hz to 10-Hz Noise

图6-17. PSRR vs Temperature

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6.7 Typical Characteristics (continued)

at T_A= 25°C, V_S= 12 V, V_CM= V_{S_O1}= V_{S_O2}= V_S/2, and R_L= 10 kΩ(unless otherwise noted)

10000

1000

100

3.5

2.5

1.5

0.5

Supply Voltage (V)

100m

100 1k

Frequency (Hz)

10k

100k

D028

D007

5 typical units

V_O= 8 V_PP

图6-20. Quiescent Current vs Power Supply

图6-19. Input Voltage Spectral Noise Density vs Frequency

4.5

V_S= 12 V

V_S= 16 V

3.5

2.5

V_S= 4.5 V

1.5

-40

-20

100 120 140

-40

-20

100 120 140

Temperature (èC)

D029

D030

5 typical units

R_L= 100 Ω

图6-21. Quiescent Current vs Temperature

图6-22. Open-Loop Gain vs Temperature

100000

10000

1000

100

R_ISO= 0

R_ISO= 25

R_ISO= 50

-5

100

Capactiance (pF)

1000

100m

100

Frequency (Hz)

10k

100k

10M

D032

D012

10-mV output step

Gain = –1 V/V

图6-24. Small-Signal Overshoot

图6-23. Open-Loop Output Impedance

vs Capacitive Load

vs Frequency

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6.7 Typical Characteristics (continued)

at T_A= 25°C, V_S= 12 V, V_CM= V_{S_O1}= V_{S_O2}= V_S/2, and R_L= 10 kΩ(unless otherwise noted)

V_IN(V), V_S= 12 V

R_ISO= 0

R_ISO= 25

R_ISO= 50

V_OUT(V), V_S= 12 V

V_IN(V), V_S= 4.5 V

V_OUT(V), V_S= 4.5 V

100

Capactiance (pF)

1000

Time (100 ms/div)

D033

D034

10-mV output step

Gain = 1 V/V

图6-25. Small-Signal Overshoot

图6-26. No Phase Reversal

vs Capacitive Load

V_IN

V_OUT, R_LOAD= 10K W

V_OUT, R_LOAD= 50 W

V_OUT

V_IN

Time (5 ms/div)

Time (1 ms/div)

D035

D036

V_S= 4.5 V

V_IN= 10 mV_PP

图6-27. Negative Overload Recovery

图6-28. Small-Signal Step Response

0.9

0.85

0.8

Faling

Rising

Sourcing

0.75

0.7

0.65

0.6

0.55

0.5

Sinking

0.45

0.4

0.35

-40

-20

100 120 140

Time (1 ms/div)

Temperature (èC)

D041

D040

V_IN= 5 V

图6-30. Short-Circuit Current vs Temperature

图6-29. Settling Time

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6.7 Typical Characteristics (continued)

at T_A= 25°C, V_S= 12 V, V_CM= V_{S_O1}= V_{S_O2}= V_S/2, and R_L= 10 kΩ(unless otherwise noted)

160

150

140

130

120

110

100

10M

100M

Frequency (Hz)

10G

D015

PRF = –10 dBm

图6-31. EMIRR vs Frequency

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7 Detailed Description

7.1 Overview

The ALM2402F-Q1 is a dual-power op amp qualified for use in automotive applications. Key features for this

device are low offset voltage, high output current drive capability, and high FPBW capability. The device also

offers protection features such as thermal shutdown and current limit. The 14-pin HTSSOP package minimizes

board space and power dissipation.

7.2 Functional Block Diagram

V_CC

VS_O(1)

PMOS Current Limiting and

Biasing

IN(1)+

OUT(1)

EMI

OTA

Rejection

NMOS Current Limiting and

Biasing

IN(1)œ

GND

OTF/SH_DN

V_CC

Internal

Thermal Detection

Circuitry

V_CC

VS_O(2)

PMOS Current Limiting and

Biasing

IN(2)+

OUT(2)

EMI

OTA

Rejection

NMOS Current Limiting and

Biasing

IN(2)œ

GND

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7.3 Feature Description

7.3.1 OTF/SH_DN

The overtemperature and shutdown (OTF/SH_DN) pin is a bidirectional pin that allows both op amps to be put

into a low I_Qstate (~500 µA) when forced low or less than V_{IL_OTF}. As a result of this pin being bidirectional, and

the respective enable and disable functionality, this pin must be pulled high or greater than V_{IH_OTF}through a

pullup resistor; see the Electrical Characteristics table.

When the junction temperature of ALM2402F-Q1 exceeds the limits specified in the Recommended Operating

Conditions table, the OTF/SH_DN pin goes low to alert the application that both the outputs have turned off

because of an overtemperature event. Also, the OTF pin goes low if VS_O1 and VS_O2 are 0 V. In case of an

overtemperature event, the op amps are shut down even if OTF/SH_DN is forced high.

When OTF/SH_DN is pulled low and the op amps are shut down, the op amps are in an open loop, even when

there is negative feedback applied. This occurrence is due to the loss of the open-loop gain in the op amps when

the biasing is disabled. See 节7.4.1 for more details on open- and closed-loop considerations.

7.3.2 Output Stage Supply Voltage

The ALM2402F-Q1 uses three power rails. VS powers the op-amp signal path (OTA) and protection circuitry.

VS_O1 and VS_O2 power the output high side driver. Each supply can operate at separate voltage levels

(higher or lower). The minimum and maximum values listed in the Recommended Operating Conditions table are

voltages that enable the ALM2402F-Q1 to properly function at or near the specification listed in Electrical

Characteristics table.

7.3.3 Current-Limit and Short-Circuit Protection

Each op amp in the ALM2402F-Q1 has separate internal current limiting for the PMOS (high-side) and NMOS

(low-side) output transistors. If the output is shorted to ground then the PMOS (high-side) current limit is

activated, and limits the current to 750 mA nominally. If the output is shorted to supply then the NMOS (low-side)

current limit is activated and limits the current to 550 mA nominally at 25°C. The current limit value decreases

with increasing temperature as a result of the temperature coefficient of a base-emitter junction voltage.

Similarly, the current limit value increases at low temperatures.

In the case of short-to-ground scenarios, a programmable current limit for the PMOS (high-side) is achieved by

adding resistance between VS_O(x), where x = 1 or 2, and the supply VS. The added current limit resistor

reduces the drain-source voltage across the PMOS output transistor, thus reducing the output current drive

capability. For a desired current limit (I_LIMIT), an appropriate current limiting resistor (R_limit) is selected using

Equation 1.

R_LIMIT= (VS -1.5) / I_LIMIT

(1)

When current is limited, the safe limits for the die temperature must be taken in to account; see the

Recommended Operating Conditions and Absolute Maximum Ratings tables. With too much power dissipation,

the die temperature can surpass thermal shutdown limits; the op amp shuts down and reactivates after the die

has fallen below thermal limits. However, do not continuously operate the device in thermal hysteresis for long

periods of time (see the Absolute Maximum Ratings table).

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7.3.4 Input Common-Mode Overvoltage Clamps

The input common mode range of the ALM2402F-Q1 is between (V–) + 0.2 V and (V+) – 1.2 V (see the

Electrical Characteristics table). Staying within this range allows the op amps to perform and operate within the

specification listed in the Electrical Characteristics. Operating beyond these limits can cause distortion and

nonlinearities.

In order for the inputs to tolerate high voltages in the event of a short to supply, Zener diodes have been added

(see 图7-1). The current into this Zener diode is limited through internal resistors (10 kΩeach). When operating

near or above the Zener voltage (7 V), the additional voltage error caused by the mismatch in internal resistors

must be taken in to account. In unity gain configurations, the op amp forces both gate voltages to be equal to the

Zener voltage on the positive input pin, and ideally both Zeners sink the same amount of current and force the

output voltage to be equal to V_IN. However, in reality, R_Nand R_Pand V_Zbetween both Zener diodes do not

perfectly match, and have some percentage difference between their values. This occurrence leads to the output

being V_O= V_IN× (ΔR + ΔV_Z) .

ALM2402F-Q1

R_N

–

R_P

V_IN

–

图7-1. Schematic Including Input Clamps

7.3.5 Thermal Shutdown

If the die temperature exceeds safe limits, all outputs are disabled, and the OTF/SH_DN pin is driven low. After

the die temperature has fallen to a safe level, operation automatically resumes. The OTF/SH_DN pin is released

after operation has resumed.

When operating the die at a high temperature, the op amp toggles on and off between the thermal shutdown

hysteresis. In this event, the safe limits for the die temperature must be taken in to account; see the

Recommended Operating Conditions and Thermal Conditions tables. Do not continuously operate the device in

thermal hysteresis for long periods of time; see the Recommended Operating Conditions table.

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7.3.6 Output Stage

Designed as a high-voltage, high current operational amplifier, the ALM2402F-Q1 device delivers a robust output

drive capability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail output

swing capability. For resistive loads up to 10 kΩ, the output swings typically to within 5 mV of either supply rail

regardless of the power-supply voltage applied. Different load conditions change the ability of the amplifier to

swing close to the rails.

Each output transistor has internal reverse diodes between drain and source that conduct if the output is forced

greater than the supply or less than ground (reverse current flow). These diodes can be used as flyback

protection in inductive-load driving applications. Limit the use of these diodes to pulsed operation to minimize

junction temperature overheating due to (V_F× I_F). Internal current limiting circuitry does not operate when current

is flown in the reverse direction and the reverse diodes are active.

7.3.7 EMI Susceptibility and Input Filtering

Op amps vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If conducted

EMI enters the op amp, the dc offset observed at the amplifier output may shift from the nominal value while EMI

is present. This shift is a result of signal rectification associated with the internal semiconductor junctions. While

all op-amp pin functions can be affected by EMI, the signal input pins are likely to be the most susceptible. The

ALM2402F-Q1 incorporates an internal input low-pass filter that reduces the amplifiers response to EMI. Both

common-mode and differential mode filtering are provided by this filter.

Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational

amplifier over a broad frequency spectrum extending from 10 MHz to 990 MHz. The EMI rejection ratio (EMIRR)

metric allows op amps to be directly compared by the EMI immunity. Detailed information can also be found in

the EMI Rejection Ratio of Operational Amplifiers application report, available for download from www.ti.com.

7.4 Device Functional Modes

7.4.1 Open-Loop and Closed-Loop Operation

As a result of the very high open-loop dc gain of the ALM2402F-Q1, the device functions as a comparator in

open-loop for most applications. As noted in the Electrical Characteristics table, the majority of electrical

characteristics are verified in negative feedback, closed-loop configurations. Certain dc electrical characteristics,

like offset, may have a higher drift across temperature and lifetime when continuously operated in open loop

over the lifetime of the device.

7.4.2 Shutdown

When the OTF/SH_DN pin is left floating or is grounded, the op amp shuts down to a low I_Qstate and does not

operate; the op amp outputs go to a high-impedance state. See the OTF/SH_DN section for more detailed

information on the OTF/SH_DN pin.

表7-1. Shutdown Truth Table

NAME

LOGIC STATE

OP AMP STATE

Operating

High ( > VIH_OTF see Recommended Operating Conditions)

Low ( < VIL_OTF see Recommended Operating Conditions)

OTF/SH_DN

Shutdown (low I_Qstate)

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8 Application and Implementation

Note

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The ALM2402F-Q1 is a dual-power op amp with performance and protection features that are optimal for many

applications. For op amps, there are many general design consideration that must taken into account. The

following sections describe what to consider for most closed-loop applications, and gives a specific example of

the ALM2402F-Q1 being used in a motor-drive application.

8.1.1 Capacitive Load and Stability

The ALM2402F-Q1 is designed to be used in applications where driving a capacitive load is required. As with all

op amps, specific instances can occur where the ALM2402F-Q1 device can become unstable. The particular op-

amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing

whether or not an amplifier is stable in operation. An op amp in the unity-gain (1 V/V) buffer configuration that

drives a capacitive load exhibits a greater tendency to be unstable than an amplifier operated at a higher-noise

gain. The capacitive load, in conjunction with the op-amp output resistance, creates a pole within the feedback

loop that degrades the phase margin. The degradation of the phase margin increases as the capacitive loading

increases. When operating in the unity-gain configuration, the ALM2402F-Q1 remains stable with a pure

capacitive load up to approximately 1 nF. Increasing the amplifier closed-loop gain allows the amplifier to drive

increasingly larger capacitance. This increased capability is evident when observing the overshoot response of

the amplifier at higher voltage gains.

One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain

configuration is to insert a small resistor, typically 100 mΩto 10 Ω, in series with the output (R_S), as shown in 图

8-1. This resistor significantly reduces the overshoot and ringing associated with large capacitive loads.

V+

R_S

V_OUT

C_L

R_L

V_IN

图8-1. Capacitive Load Drive

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8.2 Typical Application

Resolver

Rotor

COSINE

Sensing

Coil

Excitation

Coil

Vbias

ALM2402F-Q1

C_BL

SINE

Sensing

Coil

C_BL

V+

V–

excite–

V+

V–

excite+

Resolver-to-Digital

Converter

图8-2. Resolver-Based Application

High-power ac and brushless DC (BLDC) motor-drive applications need angular and position feedback in order

to efficiently and accurately drive the motor. Position feedback can be achieved by using optical encoders, hall

sensors, or resolvers. Resolvers are the goto choice when environmental or longevity requirements are

challenging and extensive.

A resolver acts like a transformer with one primary coil and two secondary coils. The primary coil, or excitation

coil, is located on the rotor of the resolver. As the rotor of the resolver spins, the excitation coil induces a current

into the sine and cosine sensing coils. These coils are oriented 90 degrees from one another, and produce a

vector position read by the resolver to digital converter chip.

Resolver excitation coils can have a very low dc resistance (< 100 Ω), requiring a sink and a source of up to 200

mA from the excitation driver. The ALM2402F-Q1 can source and sink this current while providing current limiting

and thermal shutdown protection. Incorporating these protections in a resolver design can increase the life of the

end product.

The fundamental design steps and ALM2402F-Q1 benefits shown in this application example can be applied to

other inductive load applications, such as dc and servo motors.

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8.2.1 Design Requirements

For this design example, use the parameters listed in 表8-1 as the input parameters.

表8-1. Design Parameters

DESIGN PARAMETER

Ambient temperature range

Available supply voltages

EMC capacitance (CL)

EXAMPLE VALUE

–40°C to +125°C

12 V

50 nF

Excitation input voltage range

Excitation frequency

2 V_RMSto 7 V_RMS

10 kHz

8.2.2 Detailed Design Procedure

When using the ALM2402F-Q1 in a resolver application, determine:

• Resolver excitation input impedance or resistance and inductance: Z_O= 100 + j188; (R = 100 Ωand L = 3

mH)

• Resolver transformation ration (V_EXC/ V_SINCOS): 0.5 V/V at 10 kHz

• Package and R_θJA: HTSSOP, 46.5°C/W

• Op amp maximum junction temperature: 150°C

• Op amp bandwidth: 1.3 MHz

• Op amp Slew Rate: 1.2 V/µs

8.2.2.1 Resolver Excitation Input (Op Amp Output)

Like a transformer, a resolver needs an alternating current input to function properly. The resolver receives

alternating current from the primary coil (excitation input) and creates a multiple of this input current on the

secondary sides (SIN, COS ports). When determining how to generate this alternating current, make sure to

understand the op amp abilities and limitations. For the excitation input, the resolver input impedance, stability

RMS voltage, and desired frequency must be taken in to account.

8.2.2.1.1 Excitation Voltage

The resolver primary winding or excitation coil can be driven by a single-ended op amp output with the other side

of the coil grounded, or differentially as shown in 图 8-2. A differential drive offers higher voltage (double) on to

the excitation coil, while not using as much output voltage headroom from the op amp. This larger output voltage

due to the differential drive leads to lower distortion on the output signal.

For this example, the resolver impedance is specified from 2 V_RMSand 7 V_RMSup to 20-kHz maximum

frequency. To highlight use with a 7 V_RMSresolver, an excitation voltage of 10 V_PPis applied from each channel

of the ALM2402F-Q1. The op amp is set in an inverting gain = –2 V/V, while applying an adequate common-

mode bias. These conditions give the required 7 V_RMSdifferential output (3.5 V_RMSper each op amp channel) to

the resolver primary winding without running into any op-amp headroom issues.

Another consideration for excitation is op-amp power dissipation. As described in the Power Dissipation and

Thermal Reliability section, power dissipation from the op amp can be lowered by driving the output peak

voltages close to the supply and ground voltages. With the very low V_OH/V_OLof the ALM2402F-Q1, lower power

dissipation is easily accomplished. See the Output Stage section for a further description of the rail-rail output

stage.

8.2.2.1.2 Excitation Frequency

The excitation frequency is chosen based on the desired secondary-side output signal resolution. The excitation

signal is similar to a sampling pulse in ADCs, with the real information being in the envelope created by the rotor.

With a GBW of 1.3 MHz, the ALM2402F-Q1 has more than enough open-loop gain at 10 kHz to create negligible

closed-loop gain error.

Along with GBW, the ALM2402F-Q1 has optimal THD and SR performance to achieve 10-V_PPoutput per

channel.

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8.2.2.1.3 Excitation Impedance

Knowledge of the primary-side impedance is very important when choosing an op amp for this application. As

shown in 图 8-3, the excitation coil looks like an inductance in series with a resistance. Often, these values are

not given, or are given as a function of frequency or phase angle, and must by calculated from the Cartesian or

polar form. This calculation is a trivial task.

After the coil resistance is determined, the maximum or peak-peak current needed from ALM2402F-Q1 is

determined using Equation 2:

V_PP

I_OUT

R_L

(2)

In this example, the peak-to-peak output current equates to approximately 100 mA. Each op amp handles the

peak current, with one op amp sinking current while the other op amp is sourcing current. Knowledge of the op

amp current is very important when determining the device power dissipation, a topic that is discussed in Power

Dissipation and Thermal Reliability.

C_EMC

Excitation Coil

Model

–

R_CRS

L_EXC

Vbias

ALM2402F-Q1

C_CRS

R_L

–

C_EMC

图8-3. Excitation Coil Implementation

As shown in 图8-3, designers often add a resistor (R_CRS) in series with a capacitor (C_CRS) to eliminate crossover

distortion. This distortion occurs as a result of the biasing of BJTs in a discrete implementation. With the

ALM2402F-Q1 rail-rail output and high-output current drive capability, this configuration is rarely needed.

Common practice is to also add EMC capacitors to the op-amp outputs to help shield other devices on the PCB

from the radiation created by the motor and resolver. When choosing C_EMC, make sure to take the stability of the

op amp into account.

8.2.2.2 Resolver Output

As mentioned in 节 8.2.2.1.2, the excitation signal is similar to a sampling pulse in ADCs, with the real

information being in the envelope created by the rotor. Equation 3, Equation 4, and Equation 5 show the

behavior of the sin and cos outputs. The excitation signal is attenuated and enveloped by the voltage created

from the electromagnetic response of the rotating rotor. The resolver analog-output-to-digital converter filters out

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the excitation signal, and processes the sine and cosine angles produced by the rotor. Hence, signal integrity or

the sine and cosine envelope is most important in resolver design; although, some trade-offs in signal integrity of

the excitation signal can be made for cost or convenience. Often, a square wave or sawtooth signal is used to

accomplish excitation, as opposed to a sine wave.

V_EXC= V_PPìsin(2pft)

(3)

(4)

(5)

V_SIN= T_Rì V_PPìsin(2pft)ìsin(q)

V_COS= T_Rì V_PPìsin(2pft)ìcos(q)

8.2.2.3 Power Dissipation and Thermal Reliability

Power dissipation is critical to many industrial and automotive applications. Resolvers are typically chosen over

other position feedback techniques because of reliability and accuracy in harsh conditions and high

temperatures.

The ALM2402F-Q1 is capable of high output current with power-supply voltages up to 16 V. Internal power

dissipation increases when operating at high supply voltages. The power dissipated in the op amp (P_OPA) is

calculated using Equation 6:

VO(X)

P_OPA= (V⁺- VO(X))ìI_OUT= (V⁺- VO(X))ì

R_L

(6)

To calculate the worst-case power dissipation in the op amp, the ac and dc cases must be considered

separately.

In the case of constant output current (dc) to a resistive load, the maximum power dissipation in the op amp

occurs when the output voltage is half the positive supply voltage. This calculation assumes that the op amp is

sourcing current from the positive supply to a grounded load. If the op amp sinks current from a grounded load,

modify Equation 7 to include the negative supply voltage instead of the positive.

VO(X) (VO(X))²

P_{OPA(MAX _DC)}= P_OPA

(

) =

4R_L

(7)

The maximum power dissipation in the op amp for a sinusoidal output current (ac) to a resistive load occurs

when the peak output voltage is 2/π times the supply voltage, given symmetrical supply voltages, as shown in

Equation 8:

2VO(X)

2∂(VO(X))²

p²∂R_L

P_{OPA(MAX _ AC)}= P_OPA

(

) =

(8)

After the total power dissipation is determined, the junction temperature at the worst expected ambient

temperature case must be determined by using Equation 9:

T_J(MAX)= P_OPAìR_qJA+ T_A(MAX)

(9)

8.2.2.3.1 Improving Package Thermal Performance

The value of R_θJAdepends on the PCB layout. An external heat sink, a cooling mechanism such as a cold air

fan, or both, can help reduce R_θJAand thus improve device thermal capabilities. See TI’s design support web

page at www.ti.com/thermal for general guidance on improving device thermal performance.

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8.2.3 Application Curves

The THD+N performance for the circuit described in the Excitation Voltage section is measured for a 10-kHz, 10-

_PPoutput signal from each op-amp channel. These measurement results are displayed in 表8-2.

表8-2. Maximum Output Power and THD+N

LOAD IMPEDANCE

MAXIMUM OUTPUT POWER

(mW)

THD+N AT MAXIMUM OUTPUT POWER

(dB)

(Ω)

100

292

–50

图8-4 shows the THD+N performance for different input signal frequencies with a measurement bandwidth of 80

kHz. 图 8-5 shows the circuit response with load capacitances of up to 100 nF. Using a larger resistor in series

with the output, as shown in 节8.1.1 further improves phase margin.

-40

-60

-80

-100

100

G -1

G -2

R_ISO= 0

R_ISO= 5

R_ISO= 10

0.1

0.01

0.001

100

1000

Capactiance (pF)

10000

100000

100

Frequency (Hz)

10k

D043

D044

图8-5. Small-Signal Overshoot vs Capacitive Load

图8-4. THD+N vs Frequency

9 Power Supply Recommendations

The ALM2402F-Q1 is specified for continuous operation from 4.5 V to 16 V (±2.25 V to ±8 V) for V_S, and 3 V to

16V (±1.5 V to ±8 V) for V_{S_O(X)}; many specifications apply from –40°C to +125°C.

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-

impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout

Guidelines section.

CAUTION

Supply voltages larger than 18 V can permanently damage the device (see the Absolute Maximum

Ratings).

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10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the

operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance

power sources local to the analog circuitry.

– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as

close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single

supply applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital

and analog grounds, paying attention to the flow of the ground current. For more detailed information, see

Circuit Board Layout Techniques.

• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If

keeping the traces separate is not possible, then cross the sensitive trace perpendicular, as opposed to in

parallel with the noisy trace.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

10.2 Layout Example

This layout does not verify optimum thermal impedance performance. See TI’s design support web page at

www.ti.com/thermal for general guidance on improving device thermal performance.

图10-1. ALM2402F-Q1 Layout Example

Submit Document Feedback

Product Folder Links: ALM2402F-Q1

ALM2402F-Q1

ZHCSJP5B –MAY 2019 –REVISED OCTOBER 2021

www.ti.com.cn

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following: Texas Instruments, ALM2402F-Q1 Evaluation Module user's guide

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: ALM2402F-Q1

PACKAGE OPTION ADDENDUM

www.ti.com

25-Oct-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ALM2402FQPWPRQ1

ACTIVE

HTSSOP

PWP

2000 RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 125

A2402FQ

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ALM2402FQPWPRQ1 HTSSOP PWP

2000

330.0

12.4

6.9

5.6

1.6

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP PWP 14

SPQ

Length (mm) Width (mm) Height (mm)

356.0 356.0 35.0

ALM2402FQPWPRQ1

2000

Pack Materials-Page 2

GENERIC PACKAGE VIEW

PWP 14

4.4 x 5.0, 0.65 mm pitch

PowerPAD TSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224995/A

www.ti.com

PACKAGE OUTLINE

PWP0014H

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

6.6

6.2

TYP

SEATING PLANE

PIN 1 ID

AREA

0.1 C

12X 0.65

5.1

4.9

3.9

NOTE 3

0.30

14X

0.19

4.5

4.3

0.1

C A B

SEE DETAIL A

(0.15) TYP

4X (0.28)

NOTE 5

4X (0.1)

NOTE 5

THERMAL

PAD

0.25

GAGE PLANE

2.86

2.02

1.2 MAX

0.15

0.05

0 - 8

0.75

0.50

DETAIL A

(1)

TYPICAL

1.82

0.98

4224353/A 07/2018

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ and may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0014H

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(3.4)

NOTE 9

SOLDER MASK

DEFINED PAD

(1.82)

SYMM

SEE DETAILS

14X (1.5)

14X (0.45)

(1.1)

TYP

SYMM

(2.86)

(5)

NOTE 9

12X (0.65)

(

0.2) TYP

VIA

(R0.05) TYP

(1.1) TYP

METAL COVERED

BY SOLDER MASK

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-14

/A 07/2018

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0014H

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(1.82)

BASED ON

0.125 THICK

STENCIL

14X (1.5)

(R0.05) TYP

14X (0.45)

(2.86)

SYMM

BASED ON

0.125 THICK

STENCIL

12X (0.65)

SEE TABLE FOR

METAL COVERED

BY SOLDER MASK

SYMM

(5.8)

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

2.03 X 3.20

1.86 X 2.86 (SHOWN)

1.66 X 2.61

0.125

0.15

0.175

1.54 X 2.42

4224353/A 07/2018

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

ALM2402F-Q1 [TI]

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