ADS5525IRGZRG4 [TI]
12-bit, 170 MSPS ADC with User selectable DDR LVDS or Parallel CMOS outputs 48-VQFN -40 to 85;
| 型号： | ADS5525IRGZRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-bit, 170 MSPS ADC with User selectable DDR LVDS or Parallel CMOS outputs 48-VQFN -40 to 85 双倍数据速率 转换器 |
| 文件： | 总58页 (文件大小：2019K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS5525
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SLWS191B–JULY 2006–REVISED MAY 2007
12-BIT, 170 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
Wireless Communications Infrastructure
Software Defined Radio
Power Amplifier Linearization
802.16d/e
Test and Measurement Instrumentation
High Definition Video
•
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•
•
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Maximum Sample Rate: 170 MSPS
12-Bit Resolution
No Missing Codes
Total Power Dissipation 1.1 W
Internal Sample and Hold
70.5-dBFS SNR at 70-MHz IF
84-dBc SFDR at 70-MHz IF
11 bits ENOB Minimum at 70-MHz IF
Medical Imaging
Radar Systems
Double Data Rate (DDR) LVDS and Parallel
CMOS Output Options
DESCRIPTION
ADS5525 is a high performance 12-bit, 170-MSPS
A/D converter. It offers state-of-the art functionality
and performance using advanced techniques to
minimize board space. Using an internal sample and
hold and low jitter clock buffer, the ADC supports
both high SNR and high SFDR at high input
frequencies. It features programmable gain options
that can be used to improve SFDR performance at
lower full-scale analog input ranges.
•
•
•
Programmable Gain up to 6 dB for SNR/SFDR
Trade-Off at High IF
Reduced Power Modes at Lower Sample
Rates
Supports input clock amplitude down to
400 mVPP
•
•
•
•
Clock Duty Cycle Stabilizer
No External Reference Decoupling Required
Internal and External Reference Support
In a compact 48-pin QFN, the device offers fully
differential LVDS DDR (Double Data Rate) interface
while parallel CMOS outputs can also be selected.
Flexible output clock position programmability is
available to ease capture and trade-off setup for hold
times. At lower sampling rates, the ADC can be
operated at scaled down power with no loss in
performance. ADS5525 includes an internal
reference, while eliminating the traditional reference
pins and associated external decoupling. The device
also supports an external reference mode.
Programmable Output Clock position to ease
data capture
•
•
3.3-V Analog and Digital Supply
48-QFN Package (7 mm × 7 mm)
The device is specified over the industrial
temperature range (-40°C to 85°C).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
ADS5525
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SLWS191B–JULY 2006–REVISED MAY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
CLKP
CLKOUTP
CLKOUTM
CLOCKGEN
CLKM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
Digital
Encoder
and
INP
INM
12-Bit
ADC
D6_D7_P
D6_D7_M
SHA
Serializer
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
Control
Interface
VCM
Reference
OVR
ADS5525
LVDS MODE
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
TRANSPORT
MEDIA,
QUANTITY
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
PRODUCT
Tape and Reel,
250
ADS5525IRGZT
ADS5525IRGZR
ADS5525
QFN-48(2)
RGZ
–40°C to 85°C
AZ5525
Tape and Reel,
2500
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 25.41°C/W (0 LFM air flow), θJC
= 16.5°C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in x 3 in (7.62 cm x 7.62 cm)
PCB.
2
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SLWS191B–JULY 2006–REVISED MAY 2007
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
–0.3 V to 3.9
UNIT
V
Supply voltage range, AVDD
Supply voltage range, DRVDD
–0.3 V to 3.9
V
Voltage between AGND and DRGND
-0.3 to 0.3
V
Voltage between AVDD to DRVDD
-0.3 to 3.3
V
Voltage applied to VCM pin (in external reference mode)
Voltage applied to analog input pins, INP and INM
Voltage applied to input clock pins, CLKP and CLKM
-0.3 to 1.8
V
–0.3 V to minimum (3.6, AVDD + 0.3 V)
-0.3 V to AVDD + 0.3 V
–40 to 85
V
V
TA
Operating free-air temperature range
Operating junction temperature range
Storage temperature range
°C
°C
°C
TJ
125
Tstg
–65 to 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
SUPPLIES
Analog supply voltage, AVDD
Digital supply voltage, DRVDD
ANALOG INPUTS
3
3
3.3
3.3
3.6
3.6
V
V
Differential input voltage range
2
1.5 ±0.1
1.5
VPP
V
Input common-mode voltage
Voltage applied on VCM in external reference mode
1.45
1.55
V
CLOCK INPUT
Input clock sample rate
(1)
DEFAULT SPEED mode
LOW SPEED mode
50
1
170
60
MSPS
Input clock amplitude differential (V(CLKP) - V(CLKM)
)
Sine wave, ac-coupled
LVPECL, ac-coupled
0.4
1.5
1.6
VPP
VPP
VPP
V
LVDS, ac-coupled
0.7
LVCMOS, single-ended, ac-coupled
3.3
Input clock duty cycle (See Figure 33)
DIGITAL OUTPUTS
35%
50%
65%
CL
Maximum external load capacitance from each output pin to DRGND
CMOS mode
5
5
LVDS mode, without internal termination (default
after reset)
pF
(2)
LVDS mode, with 100 Ω internal termination
10
RL
Differential load resistance between the LVDS output pairs (LVDS mode)
Operating free-air temperature
100
Ω
–40
85
°C
(1) See section on Low Sampling Frequency Operation for more information
(2) See section on LVDS Buffer Internal Termination for more information
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ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V, sampling rate = 170 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock
duty cycle, –1 dBFS differential analog input, internal reference mode, db gain, DDR LVDS data output (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
12
bits
ANALOG INPUT
Differential input voltage range
Differential input capacitance
Analog input bandwidth
2
7
VPP
pF
–3 dB, source impedance 50 Ω
500
MHz
Analog input common mode current
(per input pin)
280
µA
REFERENCE VOLTAGES
V(REFB)
V(REFT)
∆V(REF)
VCM
Internal reference bottom voltage
Internal reference top voltage
Internal reference error
Internal reference mode
Internal reference mode
V(REFT) - V(REFB)
0.5
2.5
±25
1.5
±4
V
V
-60
60
mV
V
Common mode output voltage
VCM output current capability
Internal reference mode
Internal reference mode
mA
DC ACCURACY
No Missing Codes
Assured
0.5
DNL
INL
Differential non-linearity
Integral non-linearity
Offset error
–0.6
-1.6
-10
0.6
1.6
10
LSB
LSB
± 1
5
mV
Offset temperature coefficient
0.002
±1
ppm/°C
%FS
%FS
∆%/°C
mV/V
Gain error due to internal reference error alone (∆V(REF)/ 2.0V) %
Gain error excluding internal reference error(1)
Gain temperature coefficient
-3
-2
3
2
±1
0.01
0.6
PSRR
DC Power supply rejection ratio
POWER SUPPLY
I(AVDD)
I(DRVDD)
ICC
Analog supply current
281
51
mA
mA
LVDS mode, IO = 3.5 mA,
RL = 100 Ω, CL = 5 pF
Digital supply current
Total supply current
LVDS mode
LVDS mode
332
mA
W
Total power dissipation
1.1 1.275
In STANDBY mode with input clock
stopped
Standby power
100
100
150
150
mW
mW
Clock stop power
With input clock stopped
(1) Gain error is specified from design and characterization; it is not tested in production.
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SLWS191B–JULY 2006–REVISED MAY 2007
ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V, sampling rate = 170 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock
duty cycle, –1 dBFS differential analog input, internal reference mode, db gain, DDR LVDS data output (unless otherwise
noted)
PARAMETER
AC CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FIN = 10 MHz
FIN = 40 MHz
FIN = 70 MHz
FIN = 100 MHz
FIN = 150 MHz
71.2
71
68.5
70.5
70.3
69.9
69.1
67.9
68.3
67.3
0.39
87
SNR
Signal to noise ratio
dBFS
LSB
dBc
0 dB gain, 2 VPP FS(1)
FIN = 225 MHz
FIN = 300 MHz
3 dB gain, 1.4 VPP FS
0 dB gain, 2 VPP FS
3 dB gain, 1.4 VPP FS
RMS output noise
Inputs tied to common-mode
FIN = 10 MHz
FIN = 40 MHz
85
FIN = 70 MHz
75
68
75
84
FIN = 100 MHz
82
SFDR
Spurious free dynamic range
FIN = 150 MHz
80
0 dB gain, 2 VPP FS
74
FIN = 225 MHz
FIN = 300 MHz
3 dB gain, 1.4 VPP FS
0 dB gain, 2 VPP FS
3 dB gain, 1.4 VPP FS
77
70
72
FIN = 10 MHz
FIN = 40 MHz
FIN = 70 MHz
FIN = 100 MHz
FIN = 150 MHz
71
70.6
69.8
69.6
69.2
67.6
66.4
66
SINAD Signal to noise and distortion ratio
dBFS
0 dB gain, 2 VPP FS
3 dB gain, 1.4 VPP FS
0 dB gain, 2 VPP FS
3 dB gain, 1.4 VPP FS
FIN = 225 MHz
FIN = 300 MHz
65
FIN = 10 MHz
FIN = 40 MHz
FIN = 70 MHz
FIN = 100 MHz
FIN = 150 MHz
92
91
90
89
HD2
Second harmonic
87
dBc
0 dB gain, 2 VPP FS
3 dB gain, 1.4 VPP FS
0 dB gain, 2 VPP FS
3 dB gain, 1.4 VPP FS
76
FIN = 225 MHz
FIN = 300 MHz
79
73
76
(1) FS = Full scale range
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SLWS191B–JULY 2006–REVISED MAY 2007
ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V, sampling rate = 170 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock
duty cycle, –1 dBFS differential analog input, internal reference mode, db gain, DDR LVDS data output (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
87
84
82
82
80
74
77
70
72
92
92
91
90
90
88
86
85
82
79
79
78
72
68
11.5
11.3
95
MAX
UNIT
FIN = 10 MHz
FIN = 40 MHz
FIN = 70 MHz
FIN = 100 MHz
FIN = 150 MHz
75
HD3
Third harmonic
dBc
0 dB gain, 2 VPP FS
FIN = 225 MHz
FIN = 300 MHz
3 dB gain, 1.4 VPP FS
0 dB gain, 2 VPP FS
3 dB gain, 1.4 VPP FS
FIN = 10 MHz
FIN = 40 MHz
FIN = 70 MHz
FIN = 100 MHz
FIN = 150 MHz
FIN = 225 MHz
FIN = 300 MHz
FIN = 10 MHz
FIN = 40 MHz
FIN = 70 MHz
FIN = 100 MHz
FIN = 150 MHz
FIN = 225 MHz
FIN = 300 MHz
FIN = 10 MHz
FIN = 70 MHz
Worst harmonic (other than HD2, HD3)
dBc
73
THD
Total harmonic distortion
dBc
bits
ENOB
Effective number of bits
11.0
FIN1 = 49.99 MHz, FIN2 = 46.09 MHz, -7 dBFS
each tone
IMD
Two-tone intermodulation distortion
dBFS
dBc
FIN1 = 134.99 MHz, FIN2 = 130.09 MHz, -7 dBFS
each tone
90
35
1
PSRR
AC power supply rejection ratio
Voltage overload recovery time
30 MHz, 200 mVPP signal on 3.3-V supply
Recovery to 1% (of final value) for 6-dB overload
with sine-wave input at Nyquist frequency
Clock
cycles
6
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DIGITAL CHARACTERISTICS(1)
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1 AVDD = DRVDD = 3.3 V, IO = 3.5 mA, RL = 100 Ω(2)
PARAMETER
DIGITAL INPUTS
TEST CONDITIONS
MIN
TYP
MAX UNIT
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Input capacitance
2.4
V
0.8
V
33
–33
4
µA
µA
pF
DIGITAL OUTPUTS – CMOS MODE
High-level output voltage
Low-level output voltage
Output capacitance
3.3
0
V
V
Output capacitance inside the device, from each output to
ground
2
pF
DIGITAL OUTPUTS – LVDS MODE
High-level output voltage
1375
1025
350
mV
mV
mV
mV
Low-level output voltage
Output differential voltage, |VOD
|
225
VOS Output offset voltage, single-ended Common-mode voltage of OUTP and OUTM
1200
Output capacitance inside the device, from either output to
Output capacitance
ground
2
pF
(1) All LVDS and CMOS specifications are characterized, but not tested at production.
(2) IO refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair.
TIMING CHARACTERISTICS – LVDS AND CMOS MODES(1)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
DRVDD = 3.3 V, sampling frequency = 170 MSPS, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF(2), IO = 3.5 mA,
RL = 100 Ω(3), no internal termination, unless otherwise noted.
For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data
sheet.
PARAMETER
Aperture delay
Aperture jitter
TEST CONDITIONS
MIN
TYP
1.2
MAX
UNIT
ns
ta
tj
150
fs rms
Time to valid data after coming out of
STANDBY mode
100
100
Wake-up time
µs
Time to valid data after stopping and
restarting the input clock
clock
cycles
Latency
14
(1) Timing parameters are specified by design and characterization and not tested in production.
(2) CL is the effective external single-ended load capacitance between each output pin and ground.
(3) IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair.
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TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)
For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data
sheet.
PARAMETER
DDR LVDS MODE(4)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tsu
Data setup time(5)
Data valid (6) to zero-cross of CLKOUTP
1.3
0.5
1.8
1.0
ns
ns
Zero-cross of CLKOUTP to data becoming
invalid(6)
th
Data hold time(5)
Input clock rising edge zero-cross to output
clock rising edge zero-cross
tPDI
Clock propagation delay
LVDS bit clock duty cycle
3.9
4.6
5.3
ns
Duty cycle of differential clock,
(CLKOUTP-CLKOUTM)
80 ≤ Fs ≤ 170 MSPS
50%
Rise time measured from –50 mV to 50 mV
Fall time measured from 50 mV to –50 mV
1 ≤ Fs ≤ 170 MSPS
tr,
tf
Data rise time,
Data fall time
50
50
100
100
200
ps
Rise time measured from –50 mV to 50 mV
Fall time measured from 50 mV to –50 mV
1 ≤ Fs ≤ 170 MSPS
tCLKRISE
tCLKFALL
,
Output clock rise time,
Output clock fall time
200
1
ps
Output enable (OE) to valid
data delay
tOE
Time to valid data after OE becomes active
µs
PARALLEL CMOS MODE
tsu Data setup time
(5)
(5)
Data valid(7) to 50% of CLKOUT rising edge
2.5
0.8
3.3
1.2
ns
ns
50% of CLKOUT rising edge to data
becoming invalid(7)
th
Data hold time
Input clock rising edge zero-cross to 50% of
CLKOUT rising edge
tPDI
Clock propagation delay
Output clock duty cycle
1.9
2.7
3.5
ns
Duty cycle of output clock (CLKOUT)
80 ≤ Fs ≤ 170 MSPS
45%
Rise time measured from 20% to 80% of
DRVDD
Fall time measured from 80% to 20% of
DRVDD
tr,
tf
Data rise time,
Data fall time
0.8
0.4
1.5
0.8
2
ns
1 ≤ Fs ≤ 170 MSPS
Rise time measured from 20% to 80% of
DRVDD
Fall time measured from 80% to 20% of
DRVDD
tCLKRISE
tCLKFALL
,
Output clock rise time,
Output clock fall time
1.2
50
ns
ns
1 ≤ Fs ≤ 170 MSPS
Output enable (OE) to valid
data delay
tOE
Time to valid data after OE becomes active
(4) Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load.
(5) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear
as reduced timing margin.
(6) Data valid refers to logic high of +50 mV and logic low of –50 mV.
(7) Data valid refers to logic high of 2 V and logic low of 0.8 V
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N+17
N+16
N+4
N+3
N+15
N+2
Sample
N
N+1
N+14
Input
Signal
ta
CLKP
Input
Clock
CLKM
CLKOUTM
CLKOUTP
tsu
th
tPDI
14 Clock Cycles
DDR
LVDS
Output Data
DXP, DXM
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E – Even Bits D0,D2,D4,D6,D8,D10
O – Odd Bits D1,D3,D5,D7,D9,D11
N–14
N–13
N–12
N–11
N–10
N–1
N
N+1
N+2
tPDI
CLKOUT
tsu
Parallel
CMOS
14 Clock Cycles
th
Output Data
D0–D11
N–14
N–13
N–12
N–11
N–10
N–1
N
N+1
N+2
Figure 1. Latency
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CLKM
CLKP
Input
Clock
tPDI
CLKOUTP
CLKOUTM
Output
Clock
th
tsu
tsu
th
Dn(1)
Dn+1(2)
Output
Data Pair
Dn_Dn+1_P,
Dn_Dn+1_M
(1)Dn – Bits D0, D2, D4, D6, D8, D10
(2)Dn+1 – Bits D1, D3, D5, D7, D9, D11
Figure 2. LVDS Mode Timing
CLKM
Input
Clock
CLKP
tPDI
Output
Clock
CLKOUT
th
tsu
Dn(1)
Output
Data
Dn
(1)Dn – Bits D0–D11
Figure 3. CMOS Mode Timing
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DEVICE CONFIGURATION
ADS5525 offers flexibility with several programmable features that are easily configured.
The device can be configured independently using either a parallel interface control or a serial interface
programming.
In addition, the device supports a third configuration mode, where both the parallel interface and the serial
control registers are used. In this mode, the priority between the parallel and serial interfaces is determined by a
priority table (Table 2). If this additional level of flexibility is not required, the user can select either the serial
interface programming or the parallel interface control.
PARALLEL CONFIGURATION ONLY
To place the device in parallel configuration mode, keep RESET tied to high (DRVDD). Pins DFS, MODE, SEN,
SCLK and SDATA are used to directly control certain modes of the ADC. The device is configured by connecting
the parallel pins to the correct voltage levels (as described in Table 3 to Table 7). The voltage levels can be
derived by using a resistor string as illustrated in Figure 4.There is no need to apply reset.
In this mode, SEN, SCLK and SDATA function as parallel interface control pins. Frequently used functions are
controlled in this mode—standby, selection between LVDS/CMOS output format, internal/external reference,
two's complement/straight binary output format, and position of the output clock edge.
Table 1 has a description of the modes controlled by the four parallel pins.
Table 1. Parallel Pin Definition
PIN
DFS
CONTROL MODES
DATA FORMAT and the LVDS/CMOS output interface
MODE
SEN
Internal or external reference
CLKOUT edge programmability
SCLK
SDATA
LOW SPEED mode control for low sampling frequencies (< 50 MSPS)
STANDBY mode – Global (ADC, internal references and output buffers are powered down)
SERIAL INTERFACE CONFIGURATION ONLY
To exercise this mode, the serial registers must first be reset to their default values, and the RESET pin must be
kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and are used to access the
internal registers of ADC. The registers are reset either by applying a pulse on the RESET pin, or by a high
setting on the <RST> bit (D1 in register 0x6C). The serial interface section describes the register programming
and register reset in more detail.
Since the parallel pins DFS and MODE are not used in this mode, they must be tied to ground.
CONFIGURATION USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS
For increased flexibility, an additional configuration mode is supported. A combination of serial interface registers
and parallel pin controls (DFS, MODE) are used to configure the device.
To exercise this mode, the serial registers must first be reset to their default values, and the RESET pin must be
kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and are used to access the
internal registers of ADC. The registers are reset either by applying a pulse on RESET pin or by a high setting
on the <RST> bit (D1 in register 0x6C). The serial interface section describes the register programming and
register reset in more detail.
The parallel interface control pins DFS and MODE are used, and their function is determined by the appropriate
voltage levels as described in Table 6 and Table 7. The voltage levels can be derived by using a resistor string
as illustrated in Figure 4. Since some functions are controlled using both the parallel pins and serial registers,
the priority between the two is determined by a priority table (Table 2).
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Table 2. Priority Between Parallel Pins and Serial Registers
PIN
FUNCTIONS SUPPORTED
PRIORITY
When using the serial interface, bit <REF> (register 0x6D, bit D4) controls this mode, ONLY
if the MODE pin is tied low.
MODE
Internal/External reference
When using the serial interface, bit <DF> (register 0x63, bit D3) controls this mode, ONLY if
the DFS pin is tied low.
DATA FORMAT
LVDS/CMOS
DFS
When using the serial interface, bit <ODI> (register 0x6C, bits D3-D4) controls LVDS/CMOS
selection independent of the state of DFS pin
AVDD
(2/3) AVDD
R
(2/3) AVDD
GND
AVDD
R
R
(1/3) AVDD
(1/3) AVDD
To Parallel Pin
Figure 4. Simple Scheme to Configure Parallel Pins
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DESCRIPTION OF PARALLEL PINS
Table 3. SCLK Control Pin
SCLK (Pin 29)
DESCRIPTION
0
DEFAULT SPEED - Must be used for sampling frequency > 50 MSPS
LOW SPEED - Must be used for sampling frequency <= 50 MSPS
DRVDD
Table 4. SDATA Control Pin
SDATA (Pin 28)
DESCRIPTION
0
Normal operation (Default)
DRVDD
STANDBY. This is a global power down, where ADC, internal references and the output buffers are powered down.
Table 5. SEN Control Pin
SEN (Pin 27)
0
DESCRIPTION
CMOS mode: CLKOUT edge later by (3/12)Ts (1); LVDS mode: CLKOUT edge aligned with data transition
CMOS mode: CLKOUT edge later by (2/12)Ts (1); LVDS mode: CLKOUT edge aligned with data transition
CMOS mode: CLKOUT edge later by (1/12)Ts (1); LVDS mode: CLKOUT edge earlier by (1/12)Ts
(1/3)DRVDD
(2/3)DRVDD
DRVDD
(1)
Default CLKOUT position
(1) Ts = 1/Sampling Frequency
Table 6. DFS Control Pin
DFS (Pin 6)
DESCRIPTION
0
2's complement data and DDR LVDS output (Default)
2's complement data and parallel CMOS output
(1/3)DRVDD
(2/3)DRVDD
DRVDD
Offset binary data and parallel CMOS output
Offset binary data and DDR LVDS output
Table 7. MODE Control Pin
MODE (Pin 23)
0
DESCRIPTION
Internal reference
External reference
External reference
Internal reference
(1/3)AVDD
(2/3)AVDD
AVDD
SERIAL INTERFACE
The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After device
power-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET
(of width greater than 10 ns).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge
when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data is loaded in
multiples of 16-bit words within a single active SEN pulse.
The first 8 bits form the register address and the remaining 8 bits form the register data. The interface can work
with SCLK frequency from 20 MHz down to very low speeds (few Hertz) and with non-50% SCLK duty cycle.
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REGISTER INITIALIZATION
After power-up, the internal registers must be reset to their default values. This is done in one of two ways:
1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns)
as shown in Figure 5.
OR
2. By applying software reset. Using the serial interface, set the <RST> bit (D1 in register 0x6C) to high.
This initializes the internal registers to their default values and then self-resets the <RST> bit to low. In
this case the RESET pin is kept low.
Register Address
Register Data
SDATA
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
t(DH)
D1
D0
t(SCLK)
t(DSU)
SCLK
t(SLOADH)
t(SLOADS)
SEN
RESET
T0109-01
Figure 5. Serial Interface Timing Diagram
SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V (unless otherwise noted)
MIN
TYP
MAX
20
UNIT
fSCLK
tSLOADS
tSLOADH
tDSU
SCLK frequency
> DC
MHz
ns
SEN to SCLK setup time
SCLK to SEN hold time
SDATA setup time
SDATA hold time
25
25
25
25
ns
ns
tDH
ns
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RESET TIMING
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V (unless otherwise noted)
PARAMETER
Power-on delay
Reset pulse width
Register write delay
Power-up time
TEST CONDITIONS
MIN
5
TYP
MAX
UNIT
ms
ns
t1
Delay from power-up of AVDD and DRVDD to RESET pulse active
Pulse width of active RESET signal
t2
10
25
t3
Delay from RESET disable to SEN active
ns
tPO
Delay from power-up of AVDD and DRVDD to output stable
6.5
ms
Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
T0108-01
NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.
For parallel interface operation, RESET has to be tied permanently HIGH.
Figure 6. Reset Timing Diagram
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SERIAL REGISTER MAP
Table 8 gives a summary of all the modes that can be programmed through the serial interface.
Table 8. Summary of Functions Supported by Serial Interface(1)(2)
REGISTER
ADDRESS
IN HEX
REGISTER FUNCTIONS
D4 D3
A7 - A0
D7
D6
D5
D2
D1
D0
<DATA POSN>
OUTPUT DATA
POSITION
<CLKOUT POSN>
OUTPUT CLOCK POSITION PROGRAMMABILITY
62
PROGRAMMABILITY
<LOW SPEED>
ENABLE LOW
SAMPLING
FREQUENCY
OPERATION
<DF>
DATA FORMAT -
2's COMP or
STRAIGHT
BINARY
<STBY>
GLOBAL
POWER
DOWN
63
65
<TEST PATTERN> – ALL 0S, ALL 1s,
TOGGLE, RAMP, CUSTOM PATTERN
68
69
6A
6B
<GAIN> GAIN PROGRAMMING <GAIN> - 1 dB to 6 dB
<CUSTOM A> CUSTOM PATTERN (D7 TO D0)
<CUSTOM B> CUSTOM PATTERN (D13 TO D8)
<CLKIN GAIN> INPUT CLOCK BUFFER GAIN PROGRAMMABILITY
<RST>
<ODI> OUTPUT DATA INTERFACE
SOFTWARE
6C
- DDR LVDS or PARALLEL CMOS
RESET
<REF>
INTERNAL or
EXTERNAL
REFERENCE
6D
<SCALING> POWER SCALING
<DATA TERM>
INTERNAL TERMINATION – DATA
OUTPUTS
<LVDS CURR>
LVDS CURRENT
PROGRAMMABILITY
<CLKOUT TERM>
INTERNAL TERMINATION – OUTPUT CLOCK
7E
7F
<CURR DOUBLE>
LVDS CURRENT
DOUBLE
(1) The unused bits in each register (shown by blank cells in above table) must be programmed as ‘0’.
(2) Multiple functions in a register can be programmed in a single write operation.
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DESCRIPTION OF SERIAL REGISTERS
Each register function is explained in detail below.
Table 9. Serial Register A
A7 - A0 (hex)
D7
D6
D5
D4
D3
D2
D1
D0
<DATA POSN>
OUTPUT DATA
POSITION
<CLKOUT POSN>
OUTPUT CLOCK POSITION PROGRAMMABILITY
62
PROGRAMMABILITY
D4 - D0
<CLKOUT POSN> Output clock position programmability
00001
Default CLKOUT position after reset. Setup/hold timings with this clock
position are specified in the timing characteristics table.
XX011
XX101
XX111
01XX1
10XX1
11XX1
CMOS – Rising edge later by (1/12) Ts
LVDS – Rising edge earlier by (1/12) Ts
CMOS – Rising edge later by (3/12) Ts
LVDS – Rising edge aligned with data transition
CMOS – Rising edge later by (2/12) Ts
LVDS – Rising edge aligned with data transition
CMOS – Rising edge later by (1/12) Ts
LVDS – Rising edge earlier by (1/12) Ts
CMOS – Rising edge later by (3/12) Ts
LVDS – Rising edge aligned with data transition
CMOS – Rising edge later by (2/12) Ts
LVDS – Rising edge aligned with data transition
D6 – D5
<DATA POSN> Output Switching Noise and Data Position
Programmability (Only in CMOS mode)
00
Data Position 1 - Default output data position after reset. Setup/hold
timings with this data position are specified in the timing
characteristics table.
01
10
11
Data Position 2 - Setup time increases by (2/36) Ts
Data Position 3 - Setup time increases by (5/36) Ts
Data Position 4 - Setup time decreases by (6/36) Ts
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Table 10. Serial Register B
A7 - A0 (hex)
D7
D6
D5
D4
D3
D2
D1
D0
<DF>
DATA
FORMAT
2's COMP or
STRAIGHT
BINARY
<LOW SPEED>
ENABLE LOW
SAMPLING
FREQUENCY
OPERATION
<STBY>
GLOBAL
POWER
DOWN
63
D3
0
<DF> Output data format
2's complement
1
Straight binary
D4
0
<LOW SPEED> Low sampling frequency operation
Default SPEED mode for 50 < Fs ≤ 190 MSPS
Low SPEED mode 1≤ Fs ≤ 50 MSPS
1
D7
0
<STBY> Global standby
Normal operation
1
Global power down (includes ADC, internal references and output buffers)
Table 11. Serial Register C
A7 - A0 (hex)
D7
D6
D5
D4
D3
D2
D1
D0
<TEST PATTERNS>— ALL 0S, ALL 1s,
TOGGLE, RAMP, CUSTOM PATTERN
65
D7 - D5
000
<TEST PATTERN> Outputs selected test pattern on data lines
Normal operation
All 0s
001
010
All 1s
011
Toggle pattern – alternate 1s and 0s on each data output and across
data outputs
100
101
111
Ramp pattern – Output data ramps from 0x0000 to 0x3FFF by one
code every clock cycle
Custom pattern – Outputs the custom pattern in CUSTOM PATTERN
registers A and B
Unused
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Table 12. Serial Register D
A7 - A0 (hex)
D7
D6
D5
D4
D3
D2
D1
D0
68
<GAIN> GAIN PROGRAMMING <GAIN> - 1 dB to 6 dB
D3 - D0
1000
1001
1010
1011
1100
1101
1110
<GAIN> Gain programmability
0 dB gain, default after reset
1 dB
2 dB
3 dB
4 dB
5 dB
6 dB
Table 13. Serial Register E
A7 - A0 (hex)
D7
D6
D5
D4
<CUSTOM A> CUSTOM PATTERN (D7 TO D0)
<CUSTOM B> CUSTOM PATTERN (D13 TO D8)
D3
D2
D1
D0
69
6A
Reg 69
Reg 6A
D7 – D0
D5 – D0
Program bits D7 to D0 of custom pattern
Program bits D13 to D8 of custom pattern
Table 14. Serial Register F
A7 - A0 (hex)
D7
D6
D5
D4
D3
D2
D1
D0
6B
<CLKIN GAIN> INPUT CLOCK BUFFER GAIN PROGRAMMABILITY
D5 - D0
110010
101010
100110
100000
100011
<CLKIN GAIN> Clock buffer gain
Gain 4, maximum gain
Gain 3
Gain 2
Gain1, default after reset
Gain 0 minimum gain
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Table 15. Serial Register G
A7 - A0 (hex)
D7
D6
D5
D4
D3
D2
D1
D0
<ODI> OUTPUT DATA
INTERFACE - DDR LVDS OR
PARALLEL CMOS
<RST>
SOFTWARE
RESET
6C
D1
<RST> Software resets the ADC
1
Resets all registers to default values
D4 - D3
00
<ODI> Output Interface
DDR LVDS outputs, default after reset
DDR LVDS outputs
01
11
Parallel CMOS outputs
Table 16. Serial Register H
A7 - A0
D7
D6
D5
D4
D3
D2
D1
D0
<REF> INTERNAL or
EXTERNAL REFERENCE
6D
<SCALING> POWER SCALING
D4
0
<REF> Reference
Internal reference
1
External reference mode, force voltage on Vcm to set reference.
D7 - D5
001
<SCALING> Power scaling modes
Use for Fs > 150 MSPS, default after reset
Power Mode 1, use for 105 < Fs ≤ 150 MSPS
Power Mode 2, use for 50 < Fs ≤ 105
Power Mode 3, use for Fs ≤ 50 MSPS
011
101
111
Table 17. Serial Register I
A7 - A0
D7
D6
D5
D4
D3
D2
D1
D0
<LVDS CURR> LVDS
CURRENT
PROGRAMMABILITY
<DATA TERM> INTERNAL TERMINATION –
<CLKOUT TERM> INTERNAL
TERMINATION – OUTPUT CLOCK
7E
DATA OUTPUTS
D1 - D0
00
<LVDS CURR> LVDS buffer current programming
3.5 mA, default
2.5 mA
01
10
4.5 mA
11
1.75 mA
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D4 - D2
<CLKOUT TERM> LVDS internal termination for output
clock pin (CLKOUT)
000
001
010
011
100
101
110
111
No internal termination
325
200
125
170
120
100
75
D7 - D5
<DATA TERM> LVDS internal termination for output
data pins
000
001
010
011
100
101
110
111
No internal termination
325
200
125
170
120
100
75
Table 18. Serial Register J
A7 - A0
D7
D6
D5
D4
D3
D2
D1
D0
<CURR DOUBLE> LVDS
CURRENT DOUBLE
7F
D7 - D6
00
<CURR DOUBLE> LVDS buffer current double
Value specified by <LVDS CURR>
2x data, 2x clockout currents
01
10
1x data, 2x clockout currents
11
2x data, 4x clockout currents
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PIN CONFIGURATION (LVDS MODE)
RGZ PACKAGE
(TOP VIEW)
1
36
35
34
33
32
31
30
29
28
27
26
25
DRGND
DRVDD
OVR
DRGND
DRVDD
NC
2
Thermal Pad
3
4
CLKOUTM
CLKOUTP
DFS
NC
5
NC
6
NC
7
OE
RESET
SCLK
SDATA
SEN
8
AVDD
9
AGND
CLKP
10
11
12
CLKM
AVDD
AGND
AGND
Figure 7. LVDS Mode Pinout
PIN ASSIGNMENTS – LVDS Mode
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
PIN NAME
AVDD
DESCRIPTION
8, 18, 20,
22, 24, 26
Analog power supply
I
6
6
9, 12, 14,
17, 19, 25
AGND
Analog ground
I
CLKP, CLKM
INP, INM
Differential clock input
I
I
10, 11
15, 16
2
2
Differential analog input
Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on this pin sets
the internal references.
VCM
IREF
I/O
I
13
21
1
1
Current-set resistor, 56.2-kΩ resistor to ground.
Serial interface RESET input.
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin, or by using
the software reset option. See the SERIAL INTERFACE section.
In parallel interface mode, the user has to tie the RESET pin permanently HIGH.
(SDATA and SEN are used as parallel pin controls in this mode)
The pin has an internal 100-kΩ pull-down resistor.
RESET
I
30
1
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PIN CONFIGURATION (LVDS MODE) (continued)
PIN ASSIGNMENTS – LVDS Mode (continued)
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
PIN NAME
DESCRIPTION
SCLK
This pin functions as serial interface clock input when RESET is low.
It functions as LOW SPEED mode control pin when RESET is tied high. Tie SCLK
to LOW for Fs > 50MSPS and SCLK to HIGH for Fs ≤ 50MSPS. See Table 3.
The pin has an internal 100-kΩ pull-down resistor.
I
29
1
This pin functions as serial interface data input when RESET is low.
It functions as STANDBY control pin when RESET is tied high.
SDATA
SEN
I
I
28
27
1
1
See Table 4 for detailed information.
The pin has an internal 100 kΩ pull-down resistor.
This pin functions as serial interface enable input when RESET is low.
It functions as CLKOUT edge programmability when RESET is tied high. See
Table 5 for detailed information.
The pin has an internal 100-kΩ pull-up resistor to DRVDD.
Output buffer enable input, active high. The pin has an internal 100-kΩ pull-up
resistor to DRVDD.
OE
I
I
I
7
6
1
1
1
Data Format Select input. This pin sets the DATA FORMAT (Twos complement or
Offset binary) and the LVDS/CMOS output mode type. See Table 6 for detailed
information.
DFS
MODE
Mode select input. This pin selects the Internal or External reference mode. See
Table 7 for detailed information.
23
CLKOUTP
CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
OVR
Differential output clock, true
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
5
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
4
Differential output clock, complement
Differential output data D0 and D1 multiplexed, true
Differential output data D0 and D1 multiplexed, complement.
Differential output data D2 and D3 multiplexed, true
Differential output data D2 and D3 multiplexed, complement
Differential output data D4 and D5 multiplexed, true
Differential output data D4 and D5 multiplexed, complement
Differential output data D6 and D7 multiplexed, true
Differential output data D6 and D7 multiplexed, complement
Differential output data D8 and D9 multiplexed, true
Differential output data D8 and D9 multiplexed, complement
Differential output data D10 and D11 multiplexed, true
Differential output data D10 and D11 multiplexed, complement
Out-of-range indicator, CMOS level signal
38
37
40
39
42
41
44
43
46
45
48
47
3
DRVDD
Digital and output buffer supply
2, 35
1, 36
DRGND
Digital and output buffer ground
I
NC
Do not connect
31, 32, 33,
34
PAD
Connect the pad to ground plane. See Board Design Considerations in application
0
1
information.
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PIN CONFIGURATION (CMOS MODE)
RGZ PACKAGE
(TOP VIEW)
1
36
35
34
33
32
31
30
29
28
27
26
25
DRGND
DRVDD
OVR
DRGND
DRVDD
NC
2
Thermal Pad
3
4
UNUSED
CLKOUT
DFS
NC
5
NC
6
NC
7
OE
RESET
SCLK
SDATA
SEN
8
AVDD
AGND
CLKP
9
10
11
12
CLKM
AGND
AVDD
AGND
Figure 8. CMOS Mode Pinout
PIN ASSIGNMENTS – CMOS Mode
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
PIN NAME
AVDD
DESCRIPTION
8, 18, 20,
22, 24, 26
Analog power supply
Analog ground
I
6
6
9, 12, 14, 17,
19, 25
AGND
I
CLKP, CLKM Differential clock input
I
I
10, 11
15, 16
2
2
INP, INM
Differential analog input
Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on this pin sets
the internal references.
VCM
I/O
I
13
21
1
1
IREF
Current-set resistor, 56.2-kΩ resistor to ground.
Serial interface RESET input.
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin, or by using
the software reset option. See the SERIAL INTERFACE section.
RESET
SCLK
I
I
30
29
1
1
In parallel interface mode, the user has to tie RESET pin permanently HIGH.
(SDATA and SEN are used as parallel pin controls in this mode).
The pin has an internal 100-kΩ pull-down resistor.
This pin functions as serial interface clock input when RESET is low.
It functions as LOW SPEED mode control pin when RESET is tied high. Tie SCLK
to LOW for Fs > 50MSPS and SCLK to HIGH for Fs ≤ 50MSPS. See Table 3.
The pin has an internal 100-kΩ pull-down resistor.
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PIN CONFIGURATION (CMOS MODE) (continued)
PIN ASSIGNMENTS – CMOS Mode (continued)
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
PIN NAME
DESCRIPTION
This pin functions as serial interface data input when RESET is low. It functions as
STANDBY control pin when RESET is tied high.
SDATA
I
I
28
27
1
1
See Table 4 for detailed information.
The pin has an internal 100 kΩ pull-down resistor.
This pin functions as serial interface enable input when RESET is low. It functions
as CLKOUT edge programmability when RESET is tied high. See Table 5 for
detailed information.
SEN
The pin has an internal 100-kΩ pull-up resistor to DRVDD.
Output buffer enable input, active high. The pin has an internal 100-kΩ pull-up
resistor to DRVDD.
OE
I
I
I
7
6
1
1
1
Data Format Select input. This pin sets the DATA FORMAT (Twos complement or
Offset binary) and the LVDS/CMOS output mode type. See Table 6 for detailed
information.
DFS
MODE
Mode select input. This pin selects the internal or external reference mode. See
Table 7 for detailed information.
23
CLKOUT
D0
CMOS output clock
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
5
37
38
39
40
41
42
43
44
45
46
47
48
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
4
CMOS output data D0
CMOS output data D1
CMOS output data D2
CMOS output data D3
CMOS output data D4
CMOS output data D5
CMOS output data D6
CMOS output data D7
CMOS output data D8
CMOS output data D9
CMOS output data D10
CMOS output data D11
Out-of-range indicator, CMOS level signal
Digital and output buffer supply
Digital and output buffer ground
Unused pin in CMOS mode
Do not connect
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
OVR
DRVDD
DRGND
UNUSED
NC
2, 35
1, 36
4
I
31, 32, 33,
34
PAD
Connect the pad to ground plane. See Board Design Considerations in application
0
1
information.
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TYPICAL CHARACTERISTICS
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 170 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
FFT for 10 MHz INPUT SIGNAL
FFT for 40 MHz INPUT SIGNAL
SFDR = 88.65 dBc,
0
-20
-40
0
-20
-40
SFDR = 89.80 dBc,
SNR = 71.41 dBFS,
SINAD = 71.25 dBFS
SNR = 71.33 dBFS,
SINAD = 71.16 dBFS
-60
-80
-60
-80
-100
-100
-120
-140
-120
-140
0
0
0
10
20
30
40
50
60
70
80
80
80
0
0
0
10
20
30
40
50
60
70
80
80
80
f - Frequency - MHz
f - Frequency - MHz
Figure 9.
Figure 10.
FFT for 70 MHz INPUT SIGNAL
FFT for 100 MHz INPUT SIGNAL
0
-20
-40
0
-20
-40
SFDR = 86.07 dBc,
SNR = 71.13 dBFS,
SINAD = 70.85 dBFS
SFDR = 87.39 dBc,
SNR = 70.88 dBFS,
SINAD = 70.68 dBFS
-60
-80
-60
-80
-100
-100
-120
-140
-120
-140
10
20
30
40
50
60
70
10
20
30
40
50
60
70
f - Frequency - MHz
f - Frequency - MHz
Figure 11.
Figure 12.
FFT for 130 MHz INPUT SIGNAL
FFT for 150 MHz INPUT SIGNAL
0
-20
-40
0
-20
-40
SFDR = 89.78 dBc,
SNR = 70.36 dBFS,
SINAD = 70.23 dBFS
SFDR = 90.25 dBc,
SNR = 70.65 dBFS,
SINAD = 70.53 dBFS
-60
-80
-60
-80
-100
-100
-120
-140
-120
-140
10
20
30
40
50
60
70
10
20
30
40
50
60
70
f - Frequency - MHz
f - Frequency - MHz
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 170 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
FFT for 210 MHz INPUT SIGNAL
FFT for 230 MHz INPUT SIGNAL
0
-20
-40
0
-20
-40
SFDR = 77.54 dBc,
SNR = 69.61 dBFS,
SINAD = 68.43 dBFS
SFDR = 81.24 dBc,
SNR = 69.86 dBFS,
SINAD = 68.97 dBFS
-60
-80
-60
-80
-100
-100
-120
-140
-120
-140
0
0
0
10
10
10
20
30
40
50
60
70
80
80
80
0
10
20
30
40
50
60
70
80
f - Frequency - MHz
f - Frequency - MHz
Figure 15.
Figure 16.
FFT for 300 MHz INPUT SIGNAL
FFT for 375 MHz INPUT SIGNAL
0
-20
-40
0
-20
-40
SFDR = 68.54 dBc,
SNR = 66.82 dBFS,
SINAD = 63.52 dBFS
SFDR = 73.30 dBc,
SNR = 68.83 dBFS,
SINAD = 66.65 dBFS
-60
-80
-60
-80
-100
-100
-120
-140
-120
-140
20
30
40
50
60
70
0
10
20
30
40
50
60
70
80
f - Frequency - MHz
f - Frequency - MHz
Figure 17.
Figure 18.
FFT for 500 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
-20
-40
0
f
f
= 49.99 MHz, -7 dBFS,
= 46.09 MHz, -7 dBFS,
SFDR = 59.99 dBc,
SNR = 65.50 dBFS,
SINAD = 58.00 dBFS
IN1
-20
-40
IN2
2-Tone IMD, 98 dBFS
-60
-80
-60
-80
-100
-100
-120
-140
-120
-140
20
30
40
50
60
70
0
10
20
30
40
50
60
70
80
f - Frequency - MHz
f - Frequency - MHz
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 170 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
SFDR vs INPUT FREQUENCY
94
90
86
0
f
f
= 134.99 MHz, -7 dBFS,
= 130.09 MHz, -7 dBFS,
IN1
-20
-40
IN2
2-Tone IMD, 90 dBFS
82
78
74
70
-60
-80
-100
66
62
58
-120
-140
0
50 100 150 200 250 300 350 400 450 500
0
10
20
30
40
50
60
70
80
f
- Input Frequency - MHz
f - Frequency - MHz
IN
Figure 21.
Figure 22.
SNR vs INPUT FREQUENCY
LVDS Mode
SNR vs INPUT FREQUENCY
72
71
70
69
68
67
66
65
72
DDR LVDS
71
70
69
68
67
66
65
64
63
CMOS Data
Position 3
CMOS Data
Position 2
CMOS Data
Position 1
CMOS Data
Position 4
10 20 30 40 50 70 100 130 170 230 300
0
50 100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
fIN − Input Frequency − MHz
Figure 23.
Figure 24.
SFDR vs GAIN
SNR vs GAIN
96
92
72
71
Input Adjusted to -1 dBFS
for Each Gain Setting
3 dB
0 dB
5 dB
4 dB
1 dB
2 dB
3 dB
70
69
68
6 dB
88
84
4 dB
5 dB
1 dB
0 dB
2 dB
67
66
6 dB
80
76
10 40 70 100 130 160 190 220 250 280 300
10 40 70 100 130 160 190 220 250 280 300
fIN − Input Frequency − MHz
fIN − Input Frequency − MHz
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 170 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
PERFORMANCE vs AVDD
PERFORMANCE vs DRVDD
71.5
71.3
71.1
70.9
86
85
71.5
71.3
71.1
70.9
87
86
85
SFDR
SFDR
fIN = 70 MHz
fIN = 70 MHz
AVDD = 3.3 V
84
83
DRVDD = 3.3 V
84
SNR
SNR
70.7
70.5
83
82
70.7
70.5
82
81
3
3.1
3.2
AV
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
- Supply Voltage - V
DRVDD − Supply Voltage − V
DD
Figure 27.
Figure 28.
SNR vs SAMPLING FREQUENCY
ACROSS POWER SCALING MODES
PERFORMANCE vs TEMPERATURE
87
72
72
71
70
69
68
67
66
65
64
Power Mode 1
fIN = 70 MHz
86
85
71.6
71.2
SFDR
Default
SNR
84
70.8
Power Mode 2
83
82
70.4
70
Power Mode 3
fIN = 70 MHz
140 160 180
−40
−15
10
35
50
85
TA − Free-Air Temperature − oC
40
60
80
100
120
FS − Sampling Frequency − MSPS
Figure 29.
Figure 30.
PERFORMANCE vs
INPUT AMPLITUDE
PERFORMANCE vs CLOCK AMPLITUDE
90
88
86
105
74
73
72
74
73
72
71
70
69
68
67
66
FIN = 10 MHz
95
85
75
65
55
45
35
25
SFDR (dBFS)
SFDR
SNR
71
70
69
84
82
80
78
SNR (dBFS)
SFDR (dBc)
68
67
66
65
76
74
72
f
= 150 MHz
IN
Sine Wave Input Clock
fIN = 10 MHz
−10
−60
−50
−40
−30
−20
0
0.18 0.48 0.78 1.08 1.38 1.68 1.98 2.28 2.58 2.88 3.18
Input Clock Amplitude − V
PP
Input Amplitude − dBFS
Figure 31.
Figure 32.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 170 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
OUTPUT NOISE HISTOGRAM WITH
INPUTS SHORTED TO COMMON-MODE
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
92
90
100
90
80
70
60
50
40
30
72
fIN = 10 MHz
71.5
SFDR
71
88
86
70.5
70
SNR
20
10
0
84
82
69.5
35
40
45
50
55
60
65
Input Clock Duty Cycle − %
Output Code
Figure 33.
Figure 34.
PERFORMANCE IN EXTERNAL REFERENCE MODE
COMMON-MODE REJECTION RATIO vs FREQUENCY
-35
98
86
73
-40
72
SFDR
-45
-50
-55
-60
71
84
82
SNR
70
69
68
80
78
-65
-70
1.4
1.45
1.5
1.55
1.6
0
20
40
60
80
100
Voltage Forced on the CM Pin − V
f - Frequency of AC Common-Mode Voltage - MHz
Figure 35.
Figure 36.
POWER DISSIPATION vs
SAMPLING FREQUENCY (DDR LVDS)
DRVDD CURRENT vs
SAMPLING FREQUENCY (Parallel CMOS)
1.21
1.16
1.11
1.06
1.01
0.96
0.91
90
80
70
60
50
40
30
20
10
0
LVDS Mode
CMOS
10-pF Load Cap
Default
DDR LVDS
Power Mode 1
0.86
0.81
0.76
0.71
0.66
0.61
CMOS
0-pF Load Cap
Power Mode 2
CMOS
5-pF Load Cap
Power Mode 3
60 80 100 120 140 160 180
0
20
40
10
30
50
70
90 110 130 150 170
FS − Sampling Frequency − MSPS
f − Frequency − MSPS
Figure 37.
Figure 38.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 170 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
170
70
160
69
150
67
140
68
130
120
66
110
70
69
100
67
68
90
80
70
60
50
40
71
69
66
68
67
70
71
50
10
100
150
66
200
250
300
350
400
450
500
f
- Input Frequency - MHz
IN
64
65
67
68
SNR - dBFS
69
70
71
Figure 39. SNR Contour in dBFS
170
60
70
65
90
160
150
140
130
120
110
100
90
75
85
85
80
55
85
75
90
65
70
60
95
85
75
80
90
80
70
70
60
90
80
50
75
85
40
10
50
100
150
200
250
300
350
400
450
500
95
f
- Input Frequency - MHz
IN
50
55
60
65
70
75
80
85
90
SFDR - dBc
Figure 40. SFDR Contour in dBc
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APPLICATION INFORMATION
THEORY OF OPERATION
ADS5525 is a low power 12-bit 170 MSPS pipeline ADC in a CMOS process. ADS5525 is based on switched
capacitor technology and runs off a single 3.3-V supply. The conversion process is initiated by a rising edge of
the external input clock. Once the signal is captured by the input sample and hold, the input sample is
sequentially converted by a series of lower resolution stages, with the outputs combined in a digital correction
logic block. At every clock edge, the sample propagates through the pipeline resulting in a data latency of 14
clock cycles. The output is available as 12-bit data, in DDR LVDS or CMOS and coded in either straight offset
binary or binary 2’s complement format.
ANALOG INPUT
The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in
Figure 41.
This differential topology results in good ac-performance even for high input frequencies at high sampling rates.
The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V, available on VCM
pin 13. For a full-scale differential input, each input pin (INP, INM) has to swing symmetrically between VCM +
0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing. The maximum swing is determined by the
internal reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal).
Sampling
Switch
Lpkg
6 nH
Sampling
Capacitor
R-C-R Filter
INP
Ron
15 W
25 W
Csamp
3.2 pF
Cbond
2 pF
Cpar2
1 pF
50 W
4 pF
50 W
Resr
200 W
Ron
10 W
Cpar1
0.8 pF
Lpkg
6 nH
Csamp
3.2 pF
Ron
15 W
25 W
INM
Sampling
Capacitor
Cbond
2 pF
Cpar2
1 pF
Resr
200 W
Sampling
Switch
Figure 41. Input Stage
The input sampling circuit has a 3-dB bandwidth that extends up to 500 MHz, see Figure 42 (measured from the
input pins to the voltage across the sampling capacitors).
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APPLICATION INFORMATION (continued)
Transfer Function - ADC Only
ADC Input Impedance, ZI
500
450
400
350
300
250
200
150
100
2
0
-2
-4
-6
-8
-10
-12
-14
-16
50
0
0
100 200 300 400 500 600 700 800 900 1000
f − Frequency − MHz
0
100 200 300 400 500 600 700 800 900 1000
f − Frequency − MHz
Figure 42. Analog Input Bandwidth
(Data From Actual Silicon)
Figure 43. Impedance Looking Into INP, INM
(Data From Simulation)
Drive Circuit Requirements
A 5-Ω resistor in series with each input pin is recommended to damp out ringing caused by the package
parasitics. It is also necessary to present a low impedance (< 50 Ω) for the common-mode switching currents.
For example, this is achieved by using two resistors from each input terminated to the common-mode voltage
(VCM).
In addition to the above ADC requirements, the drive circuit may have to be designed to provide a low insertion
loss over the desired frequency range and matched impedance to the source. For this, the ADC input
impedance has to be considered, see Figure 43.
Example Drive Circuits
A configuration suitable for low input frequency ranges (< 100 MHz) is shown in Figure 44. Note the 5-Ω series
resistors and the low common-mode impedance (using 25-Ω resistors terminated to VCM). In addition, the circuit
has low insertion loss, and good impedance match at low input frequencies, see Figure 45.
ADS5525
ADT1-1WT
0.1 mF
5 W
INP
25 W
0.1 mF
25 W
INM
5 W
1:1
S11, Z
I
VCM
Figure 44. Configuration for Low Input Frequencies
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APPLICATION INFORMATION (continued)
S11
0
-10
-20
-30
-40
-50
-60
-70
0
50
100
150
200
250
f − Frequency − MHz
Transfer Function − Source To ADC Output
(Including the Transformer)
Frequency (100 kHz to 500 MHz)
3
1
Frequency = 100 MHz
S(1, 1) = 0.11/-1.19E2
Impedance = 44.07 - j8.63
-1
-3
-5
-7
-9
0
50
100
150
200
250
f − Frequency − MHz
Figure 45. S11, Input Impedance and Transfer Function for the Configuration in Figure 44
For high input frequencies, the previous configuration has been modified to improve the insertion loss and
impedance matching (see Figure 46). The S11 curve shows that the matching is good from 100 MHz to
300 MHz.
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APPLICATION INFORMATION (continued)
ADS5525
INP
12 nH
(Note A)
TC4-1W
TC4-1W
0.1 mF
5 W
50 W
50 W
0.1 mF
INM
12 nH
(Note A)
5 W
1:2
2:1
S11, Z
I
VCM
A. Includes transformer leakage inductances.
Figure 46. Drive Circuit at High Input Frequencies
S11
0
-5
-10
-15
-20
-25
0
100 200 300 400 500 600 700 800 900 1000
f − Frequency − MHz
Transfer Function − Source to ADC Output
(Including the Transformer)
Frequency (100 kHz to 500 MHz)
2
0
Frequency = 200 MHz
S(1, 1) = 0.09/50.92
Impedance = 55.57 + j8.03
-2
-4
-6
-8
-10
0
50 100 150 200 250 300 350 400 450 500
f − Frequency − MHz
Figure 47. S11, Input Impedance and Transfer Function for the Configuration in Figure 46
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APPLICATION INFORMATION (continued)
Using RF Transformer-Based Drive Circuits
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection. Some examples of input configurations using RF
transformers suitable for low and high input frequencies are shown in Figure 46 and Figure 47.
The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated on
the secondary side. Putting the termination on the secondary side helps to shield the kickbacks caused by the
sampling circuit from the RF transformer’s leakage inductances. The termination is accomplished by two
resistors connected in series, with the center point connected to the 1.5 V common-mode (VCM pin 13). The
value of the termination resistors (connected to common-mode) has to be low (< 100 Ω) to provide a
low-impedance path for the ADC common-mode switching current.
At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results
in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps
minimize this mismatch, and good performance is obtained for high frequency input signals. An additional
termination resistor pair (enclosed within the shaded box in Figure 46) may be required between the two
transformers to improve the balance between the P and M sides. The center point of this termination must be
connected to ground. (Note that the drive circuit has to be tuned to account for this additional termination, to get
the desired S11 and impedance match).
Using Differential Amplifier Drive Circuits
Figure 48 shows a drive circuit using a differential amplifier (TI's THS4509) to convert a single-ended input to
differential output that can be interface to the ADC analog input pins. In addition to the single-ended to
differential conversion, the amplifier also provides gain (10 dB in Figure 48). RFIL helps to isolate the amplifier
outputs from the switching input of the ADC. Together with CFIL it also forms a low-pass filter that band-limits the
noise (& signal) at the ADC input. As the amplifier output is ac-coupled, the common-mode voltage of the ADC
input pins is set using two 200 Ω resistors connected to VCM.
The amplifier output can also be dc-coupled. Using the output common-mode control of the THS4509, the ADC
input pins can be biased to 1.5V. In this case, use +4 V and -1 V supplies for the THS4509 so that its output
common-mod evoltage (1.5 V) is at mid-supply.
RF
+VS
0.1 mF
RFIL
500 W
5 W
0.1 mF 10 mF
0.1 mF
INP
RS
RG
CFIL
200 W
0.1 mF
RT
CM THS4509
RG
200 W
5 W
CFIL
RFIL
INM
0.1 mF
500 W
RS || RT
VCM ADS5525
0.1 mF
–VS
0.1 mF 10 mF
0.1 mF
RF
Figure 48. Drive Circuit using THS4509
See the EVM User Guide (SLWU028) for more information.
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APPLICATION INFORMATION (continued)
Input Common-Mode
To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-µF low-inductance capacitor
connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC
sinks a common-mode current in the order of 280 µA (at 170 MSPS). Equation 1 describes the dependency of
the common-mode current and the sampling frequency.
(280 mA) x Fs
170 MSPS
(1)
This equation helps to design the output capability and impedance of the CM driving circuit accordingly.
Reference
ADS5525 has built-in internal references REFP and REFM, requiring no external components. Design schemes
are used to linearize the converter load seen by the references; this and the integration of the requisite
reference capacitors on-chip eliminates the need for external decoupling. The full-scale input range of the
converter can be controlled in the external reference mode as explained below. The internal or external
reference modes can be selected by controlling the MODE pin 23 (see Table 7 for details) or by programming
the serial interface register bit <REF> (Table 16).
INTREF
Internal
Reference
VCM
INTREF
EXTREF
REFM
REFP
ADS5525
Figure 49. Reference Section
Internal Reference
When the device is in internal reference mode, the REFP and REFM voltages are generated internally.
Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog
input pins.
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APPLICATION INFORMATION (continued)
External Reference
When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on
the VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential
input voltage corresponding to full-scale is given by Equation 2.
Full−scale differential input pp + (Voltage forced on VCM) 1.33
(2)
In this mode, the 1.5 V common-mode voltage to bias the input pins has to be generated externally. There is no
change in performance compared to internal reference mode.
Low Sampling Frequency Operation
For best performance at high sampling frequencies, ADS5525 uses a clock generator circuit to derive internal
timing for the ADC. The clock generator operates from 170 MSPS down to 50 MSPS in the DEFAULT SPEED
mode. The ADC enters this mode after applying reset (with serial interface configuration) or by tying SCLK pin to
low (with parallel configuration).
For low sampling frequencies (below 50 MSPS), the ADC must be put in the LOW SPEED mode. This mode
can be entered by:
•
•
setting the register bit <LOW SPEED> (Table 10) through the serial interface, OR
tying the SCLK pin to high (see Table 3) using the parallel configuration.
Clock Input
ADS5525 clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), with
little or no difference in performance between configurations. The common-mode voltage of the clock inputs is
set to VCM using internal 5-kΩ resistors as shown in Figure 50. This allows the use of transformer-coupled drive
circuits for sine wave clock, or ac-coupling for LVPECL, LVDS clock sources (Figure 51 and Figure 52)
VCM
VCM
5 kW
5 kW
CLKP
CLKM
Figure 50. Internal Clock Buffer
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APPLICATION INFORMATION (continued)
For best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to
common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with
0.1-µF capacitors, as shown in Figure 51.
0.1 mF
CLKP
Differential Sine-Wave
or PECL or LVDS
Clock Input
0.1 mF
CLKM
ADS5525
Figure 51. Differential Clock Driving Circuit
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin 11) connected to ground with
a 0.1-µF capacitor, as shown in Figure 52.
0.1 mF
CMOS Clock Input
CLKP
0.1 mF
CLKM
ADS5525
Figure 52. Single-Ended Clock Driving Circuit
For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode
noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass
filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a
non-50% duty cycle clock input. Figure 33 shows the performance variation of the ADC versus clock duty cycle
Clock Buffer Gain
When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is
increased. Therefore, using a large amplitude clock is recommended. In addition, the clock buffer has a
programmable gain option to amplify the input clock. The clock buffer gain can be set by programming the
register bits <CLK GAIN> (Table 14). The clock buffer gain decreases monotonically from Gain 4 to Gain 0
settings.
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APPLICATION INFORMATION (continued)
Programmable Gain
ADS5525 has programmable gain from 0 dB to 6 dB in steps of 1 dB. The corresponding full-scale input range
varies from 2 VPP down to 1 VPP, with 0 dB being the default gain. At high IF, this is especially useful as the
SFDR improvement is significant with marginal degradation in SNR.
The gain can be programmed using the chapter bits <GAIN> (Table 12).
Table 19. Full-scale Range Across Gains
Gain
0 dB
1 dB
2 dB
3 dB
4 dB
5 dB
6 dB
Corresponding full-scale range, Vpp
2.00
1.78
1.59
1.42
1.26
1.12
1.00
Power Down
ADS5525 has three power-down modes – global STANDBY, output buffer disabled, and input clock stopped.
Global STANDBY
This mode can be initiated by controlling SDATA (pin 28) or by setting the register bit <STBY> (Table 10 )
through the serial interface. In this mode, the A/D converter, reference block and the output buffers are powered
down and the total power dissipation reduces to about 100 mW. The output buffers are in high impedance state.
The wake-up time from the global power down to data becoming valid normal mode is maximum 100 µs.
Output Buffer Disable
The output buffers can be disabled using OE pin 7 in both the LVDS and CMOS modes, reducing the total
power by about 100 mW. With the buffers disabled, the outputs are in high impedance state. The wake-up time
from this mode to data becoming valid in normal mode is maximum 1 µs in LVDS mode and 50 ns in CMOS
mode.
Input Clock Stop
The converter enters this mode when the input clock frequency falls below 1 MSPS. The power dissipation is
about 100 mW and the wake-up time from this mode to data becoming valid in normal mode is maximum
100 µs.
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Power Scaling Modes
ADS5525 has a power scaling mode in which the device can be operated at reduced power levels at lower
sampling frequencies with no difference in performance. (See Figure 30)(1) There are four power scaling modes
for different sampling clock frequency ranges, using the serial interface register bits <SCALING> (Table 16).
Only the AVDD power is scaled, leaving the DRVDD power unchanged.
Table 20. Power Scaling vs Sampling Speed
Sampling Frequency
MSPS
Analog Power
(Typical)
Power Scaling Mode
Analog Power in Default Mode
> 150
105 to 150
50 to 105
< 50
Default
928 mW at 170 MSPS
841 mW at 150 MSPS
670 mW at 105 MSPS
525 mW at 50 MSPS
928 mW at 170 MSPS
917 mW at 150 MSPS
830 mW at 105 MSPS
760 mW at 50 MSPS
Power Mode 1
Power Mode 2
Power Mode 3
(1) The performance in the power scaling modes is from characterization and not tested in production.
Power Supply Sequence
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated inside the device. Externally, they can be driven from separate supplies or from a single supply.
Digital Output Information
ADS5525 provides 12-bit data, an output clock synchronized with the data and an out-of-range indicator that
goes high when the output reaches the full-scale limits. In addition, output enable control (OE pin 7) is provided
to power down the output buffers and put the outputs in high-impedance state.
Output Interface
Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can be
selected using the DFS (see Table 6) or the serial interface register bit <ODI> (Table 15).
DDR LVDS Outputs
In this mode, the 12 data bits and the output clock are available as LVDS (Low Voltage Differential Signal)
levels. Two successive data bits are multiplexed and output on each LVDS differential pair as shown in
Figure 53. So, there are 6LVDS output pairs for the 12 data bits and 1 LVDS output pair for the output clock.
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Pins
CLKOUTP
CLKOUTM
Output Clock
D0_D1_P
D0_D1_M
Data Bits D0. D1
Data Bits D2, D3
Data Bits D4, D5
Data Bits D6, D7
Data Bits D8, D9
Data Bits D10, D11
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
OVR
Out-of-Range Indicator
ADS5525
Figure 53. DDR LVDS Outputs
Even data bits D0, D2, D4, D6, D8 and D10 are output at the falling edge of CLKOUTP and the odd data bits
D1, D3, D5, D7, D9 and D11 are output at the rising edge of CLKOUTP. Both the rising and falling edges of
CLKOUTP have to be used to capture all the 12 data bits (see Figure 54).
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CLKOUTP
CLKOUTM
D0_D1_P,
D0_D1_M
D0
D2
D1
D3
D5
D7
D9
D11
D0
D2
D1
D3
D5
D7
D9
D11
D2_D3_P,
D2_D3_M
D4_D5_P,
D4_D5_M
D4
D4
D6_D7_P,
D6_D7_M
D6
D6
D8_D9_P,
D8_D9_M
D8
D8
D10_D11_P,
D10_D11_M
D10
D10
Sample N
Sample N+1
Figure 54. DDR LVDS Interface
LVDS Buffer Current Programmability
The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, this results in a 350-mV
single-ended voltage swing (700-mVPP differential swing). The LVDS buffer currents can also be programmed to
2.5 mA, 4.5 mA, and 1.75 mA using the register bits <LVDS CURR> (Table 17). In addition, there exists a
current double mode, where this current is doubled for the data and output clock buffers (register bits <CURR
DOUBLE>) (Table 18).
LVDS Buffer Internal Termination
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. The termination resistances available are – 325, 200, and 170 Ω (nominal with
±20% variation). Any combination of these three terminations can be programmed; the effective termination is
the parallel combination of the selected resistances. This results in eight effective terminations from open (no
termination) to 75 Ω.
The internal termination helps to absorb any reflections coming from the receiver end, improving the signal
integrity. With 100-Ω internal and 100-Ω external termination, the voltage swing at the receiver end is halved
(compared to no internal termination). The voltage swing can be restored by using the LVDS current double
mode. Figure 55 shows the eye diagram of one of the LVDS data outputs with a 10-pF load capacitance (from
each pin to ground) and 100-Ω termination enabled. The terminations can be programmed using register bits
<DATA TERM> and <CLKOUT TERM> (Table 17).
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Figure 55. Eye Diagram of LVDS Data Output with INTERNAL Termination
Parallel CMOS
In this mode, the 12 data outputs and the output clock are available as 3.3-V CMOS voltage levels. Each data
bit and the output clock is available on a separate pin in parallel. By default, the data outputs are valid during the
rising edge of the output clock. The output clock is CLKOUT (pin 5).
CMOS Mode Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin (see Figure 38). The maximum DRVDD current occurs when each output bit toggles between 0 and 1
every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be
determined by the average number of output bits switching, which is a function of the sampling frequency and
the nature of the analog input signal.
Digital current due to CMOS output switching = CL x VDRVDD x (N x FAVG
)
where CL = load capacitance, N x FAVG = average number of output bits switching
Figure 38 shows the current with various load capacitances across sampling frequencies at 2MHz analog input
frequency.
Output Switching Noise and Data Position Programmability (in CMOS mode ONLY)
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant
of sampling and degrade the SNR. To minimize this, the device includes programmable options to move the
output data transitions with respect to the output clock. This can be used to position the data transitions at the
optimum place away from the sampling instant and improve the SNR. Figure 24 shows the variation of SNR for
different CMOS output data positions at 190 MSPS.
Note that the optimum output data position varies with the sampling frequency. The data position can be
programmed using the register bits <DATA POSN> (Table 9).
It is recommended to put series resistors (50 to 100 Ω) on each output line placed very close to the converter
pins. This helps to isolate the outputs from seeing large load capacitances and in turn reduces the amount of
switching noise. For example, the data in Figure 24 was taken with 50 Ω series resistors on each output line.
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Output Clock Position Programmability
In both the LVDS and CMOS modes, the output clock can be moved around its default position. This can be
done using SEN pin 27 (as described in Table 5) or using the serial interface register bits <CLKOUT POSN>
(Table 9). Using this allows to trade-off the setup and hold times leading to reliable data capture. There also
exists an option to align the output clock edge with the data transition.
Note that programming the output clock position also affects the clock propagation delay times.
Output Data Format
Two output data formats are supported – 2's complement and offset binary. They can be selected using the DFS
(pin 6) or the serial interface register bit <DF> (Table 10).
Overvoltage Signal
When the input voltage exceeds the full-scale range of the ADC, OVR (pin 3) goes high, and the output code is
clamped to the appropriate full-scale level for the duration of the overload. For a positive overdrive, the output
code is 0xFFF in offset binary output format, and 0x7FF in 2's complement output format. For a negative input
overdrive, the output code is 0x000 in offset binary output format and 0x800 in 2's complement output format.
Figure 56 shows the behavior of OVR during the overload. Note that OVR and the output code react to the
overload after a latency of 14 clock cycles.
Figure 56. OVR During Input Overvoltage
Output Timing
For the best performance at high sampling frequencies, ADS5525 uses a clock generator circuit to derive
internal timing for ADC. This results in optimal setup and hold times of the output data and 50% output clock
duty cycle for sampling frequencies from 80 MSPS to 170 MSPS. See Table 21 for timing information above 80
MSPS.
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(1)
Table 21. Timing Characteristics (80 MSPS to 170 MSPS)
tsu DATA SETUP TIME, ns
th DATA HOLD TIME, ns
TYP
tPDI CLOCK PROPAGATION DELAY, ns
Fs, MSPS
MIN
TYP
MAX
MIN
MAX
MIN
TYP
MAX
DDR LVDS
150
1.6
2.0
3.6
2.1
2.5
4.1
0.6
0.8
1.6
1.1
1.3
2.1
4.3
4.5
4.7
5
5.7
5.9
6.7
130
5.2
5.7
80
PARALLEL CMOS
150
130
80
2.8
3.3
6
3.6
4.1
7
1.2
1.7
3.7
1.6
2.1
4.1
1.7
1.1
2.5
1.9
12
3.3
2.7
10.8
13.2
(1) Timing parameters are specified by design and characterization and not tested in production.
Below 80 MSPS, the setup and hold times do not scale with the sampling frequency. The output clock duty cycle
also progressively moves away from 50% as the sampling frequency is reduced from 80 MSPS.
See Table 22 for detailed timings at sampling frequencies below 80 MSPS. Figure 57 shows the clock duty cycle
across sampling frequencies in the DDR LVDS and CMOS modes.
(1)
Table 22. Timing Characteristics (1 MSPS to 80 MSPS)
tsu DATA SETUP TIME, ns
MIN TYP MAX
th DATA HOLD TIME, ns
TYP
tPDI CLOCK PROPAGATION DELAY, ns
Fs, MSPS
MIN
1.6
MAX
MIN
TYP
5.7
12
MAX
DDR LVDS
1 to 80
3.6
PARALLEL CMOS
1 to 80
6
3.7
(1) Timing parameters are specified by design and characterization and not tested in production.
100
90
80
70
60
DDR LVDS
50
40
CMOS
30
20
10
0
0
20
40 60
80 100 120 140 160 180
Sampling Frequency − MHz
Figure 57. Output Clock Duty Cycle (typical) vs Sampling Frequency
The latency of ADS5525 is 14 clock cycles from the sampling instant (input clock rising edge). In the LVDS
mode, the latency remains constant across sampling frequencies. In the CMOS mode, the latency is 14 clock
cycles above 80 MSPS and 13 clock cycles below 80 MSPS.
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Board Design Considerations
Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital and clock sections of
the board are cleanly partitioned. Refer to the EVM User Guide (SLWU028) for details on layout and grounding.
Supply Decoupling
As the ADS5525 already includes internal decoupling, minimal external decoupling can be used without loss in
performance. Note that decoupling capacitors can help to filter external power supply noise, so the optimum
number of capacitors would depend on the actual application. The decoupling capacitors should be placed very
close to the converter supply pins.
It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching
noise from sensitive analog circuitry. In case only a single 3.3V supply is available, it should be routed first to
AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before
being routed to DRVDD.
Series Resistors on Data Outputs
It is recommended to put series resistors (50 to 100 Ω) on each output line placed very close to the converter
pins. This helps to isolate the outputs from seeing large load capacitances and in turn reduces the amount of
switching noise.
Exposed Thermal Pad
It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal
performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and
QFN/SON PCB Attachment (SLUA271).
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low
frequency value.
Aperture Delay
The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling
occurs.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width)
to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential
sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate
The maximum sampling rate at which certified operation is given. All parametric testing is performed at this
sampling rate unless otherwise noted.
Minimum Conversion Rate
The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the
deviation of any single step from this ideal value, measured in units of LSBs
Integral Nonlinearity (INL)
The INL is the deviation of the ADC’s transfer function from a best fit line determined by a least squares curve fit
of that transfer function, measured in units of LSBs.
Gain Error
The gain error is the deviation of the ADC’s actual input full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
Offset Error
The offset error is the difference, given in number of LSBs, between the ADC’s actual average idle channel
output code and the ideal average idle channel output code. This quantity is often mapped into mV.
Temperature Drift
The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree
Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter
across the TMIN to TMAX range by the difference TMAX–TMIN
.
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DEFINITION OF SPECIFICATIONS (continued)
Signal-to-Noise Ratio
SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc
and the first nine harmonics.
P
P
s
SNR + 10Log10
N
(4)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding dc.
P
s
SINAD + 10Log10
P
) P
N
D
(5)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Effective Number of Bits (ENOB)
The ENOB is a measure of a converter’s performance as compared to the theoretical limit based on quantization
noise.
SINAD * 1.76
ENOB +
6.02
(6)
(7)
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD).
P
P
s
THD + 10Log10
N
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic).
SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion
IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral
component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in units of dBc (dB to carrier) when the
absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the
fundamental is extrapolated to the converter’s full-scale range.
DC Power Supply Rejection Ratio (DC PSRR)
The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is
typically given in units of mV/V.
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DEFINITION OF SPECIFICATIONS (continued)
AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR is the measure of rejection of variations in the supply voltage of the ADC. If ∆VSUP is the change in
the supply voltage and ∆VOUT is the resultant change in the ADC output code (referred to the input), then
DVOUT
PSRR = 20Log10
(Expressed in dBc)
DVSUP
(8)
Common Mode Rejection Ratio (CMRR)
CMRR is the measure of rejection of variations in the input common-mode voltage of the ADC. If ∆Vcm is the
change in the input common-mode voltage and ∆VOUT is the resultant change in the ADC output code (referred
to the input), then
DVOUT
10
CMRR = 20Log
(Expressed in dBc)
DVCM
(9)
Voltage Overload Recovery
The number of clock cycles taken to recover to less than 1% error for a 6-dB overload on the analog inputs. A
6-dBFS sine wave at Nyquist frequency is used as the test stimulus.
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ADS5525 Revision history
Revision
Date
Description
A
8/06
Changes to the Clock Inputs of the Recommended Operating Conditions table.
Changes to the Timing Characteristics table.
New text for the Device Mode Configuration
Added SLCK pin to the Parallel Configuration Only section.
Added SCLK Control in Table 3 to the Description of Parallel Pins.
Additions to Table 8, <LOW SPEED> information.
Revised Typical Characteristics graphs.
B
5/07
Changed the SCLK Pin description.
Changed Analog Input information and Figures.
Changed Drive Circuit and Example Drive Circuit information and Figures.
Added Using RF Transformer-Based Drive Circuits information.
Added Overvoltage Signal and Figure 56.
Revised description of Serial Registers, and application information section
Added thermal pad to Figure 7 and Figure 8
Added Using Differential Amplifier Drive Circuits to the application information section
Added CMOS mode Power Dissipation to the application information section
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PACKAGE OPTION ADDENDUM
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10-Feb-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
VQFN
VQFN
Drawing
ADS5525IRGZ25
ADS5525IRGZR
PREVIEW
ACTIVE
RGZ
48
48
25
TBD
Call TI
Call TI
RGZ
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ADS5525IRGZRG4
ADS5525IRGZT
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
RGZ
RGZ
RGZ
48
48
48
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ADS5525IRGZTG4
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Dec-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS5525IRGZR
ADS5525IRGZT
VQFN
VQFN
RGZ
RGZ
48
48
2500
250
330.0
330.0
16.4
16.4
7.3
7.3
7.3
7.3
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Dec-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS5525IRGZR
ADS5525IRGZT
VQFN
VQFN
RGZ
RGZ
48
48
2500
250
333.2
333.2
345.9
345.9
28.6
28.6
Pack Materials-Page 2
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Applications
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Amplifiers
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
www.ti.com/audio
Data Converters
DLP® Products
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www.ti.com/automotive
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Communications and
Telecom
DSP
dsp.ti.com
Computers and
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www.ti.com/computers
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
Consumer Electronics
Energy
www.ti.com/consumer-apps
www.ti.com/energy
Logic
Industrial
www.ti.com/industrial
Power Mgmt
Microcontrollers
RFID
power.ti.com
Medical
www.ti.com/medical
microcontroller.ti.com
www.ti-rfid.com
Security
www.ti.com/security
Space, Avionics &
Defense
www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprf
Video and Imaging
Wireless
www.ti.com/video
www.ti.com/wireless-apps
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