ADS1174 [TI]
Quad/Octal, Simultaneous Sampling, 16-Bit Analog-to-Digital Converters; 四/八通道,同步采样, 16位模拟至数字转换器型号: | ADS1174 |
厂家: | TEXAS INSTRUMENTS |
描述: | Quad/Octal, Simultaneous Sampling, 16-Bit Analog-to-Digital Converters |
文件: | 总35页 (文件大小:1031K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ADS1178
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SBAS373–OCTOBER 2007
Quad/Octal, Simultaneous Sampling, 16-Bit Analog-to-Digital Converters
1
FEATURES
DESCRIPTION
234
•
Synchronously Sample Four/Eight Channels
•
•
Selectable Operating Modes:
High-Speed: 52kSPS Data Rate, 30mW/ch
Low-Power: 10kSPS Data Rate, 8mW/ch
The ADS1174 (quad) and ADS1178 (octal) are
multiple delta-sigma (ΔΣ) analog-to-digital converters
(ADCs) with data rates up to 52k samples-per-second
(SPS), which allow synchronous sampling of four and
eight channels. These devices use identical
packages, permitting drop-in expandability.
AC Performance:
25kHz Bandwidth
97dB SNR
The delta-sigma architecture offers near ideal 16-bit
ac performance (97dB SNR, –105dB THD, 1LSB
linearity) combined with 0.005dB passband ripple,
and linear phase response.
–105dB THD
•
Digital Filter:
Linear Phase Response
Passband Ripple: ±0.005dB
Stop Band Attenuation: 100dB
The high-order, chopper- stabilized modulator
achieves very low drift (4μV/°C offset, 4ppm/°C gain)
and low noise (1LSBPP). The on-chip finite impulse
•
Selectable SPI™ or Frame Sync Serial
Interface
response (FIR) filter provides
a usable signal
•
•
•
•
•
•
Simple Pin-Driven Control
Low Sampling Aperture Error
Specified from –40°C to +105°C
Analog Supply: 5V
bandwidth up to 90% of the Nyquist rate with 100dB
of stop band attenuation while suppressing modulator
and signal out-of-band noise.
Two operating modes allow for optimization of speed
and power: High-speed mode (32mW/Ch at 52kSPS),
and Low-power mode (8mW/Ch at 10kSPS).
I/O Supply: 1.8V to 3.3V
Digital Core Supply: 1.8V
A
SYNC input control pin allows the device
conversions to be started and synchronized to an
external event. SPI and Frame-Sync serial interfaces
are supported. The device is fully specified over the
extended industrial range (–40°C to +105°C) and is
available in an HTQFP-64 PowerPAD™ package.
APPLICATIONS
•
•
•
•
3-Phase Power Monitors
Defibrillators and ECG Monitors
Coriolis Flow Meters
Vibration/Modal Analysis
VREFP VREFN AVDD DVDD
IOVDD
VREFP VREFN AVDD
DVDD
IOVDD
DS
DS
DS
DS
Input1
Input2
Input3
Input4
Input1
Input2
Input3
Input4
Input5
Input6
Input7
Input8
SPI
and
SPI
and
DRDY/FSYNC
SCLK
DRDY/FSYNC
SCLK
DS
DS
DS
Frame-
Sync
Frame-
Sync
DOUT[4:1]
DIN
DOUT[8:1]
DIN
Interface
Interface
Four
Digital
Filters
DS
Eight
Digital
Filters
TEST[1:0]
FORMAT[2:0]
CLK
TEST[1:0]
FORMAT[2:0]
CLK
DS
Control
Logic
Control
Logic
DS
DS
DS
SYNC
SYNC
PWDN[4:1]
CLKDIV
MODE
PWDN[8:1]
CLKDIV
MODE
AGND
DGND
AGND
DGND
ADS1174
ADS1178
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
PowerPAD is a trademark of Texas Instruments.
SPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2007, Texas Instruments Incorporated
ADS1174
ADS1178
www.ti.com
SBAS373–OCTOBER 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
ADS1174, ADS1178
–0.3 to +6.0
UNIT
V
AVDD to AGND
DVDD, IOVDD to DGND
AGND to DGND
–0.3 to +3.6
V
–0.3 to +0.3
V
100, Momentary
10, Continuous
–0.3 to AVDD + 0.3
–0.3 to DVDD + 0.3
+150
mA
mA
V
Input Current
Analog Input to AGND
Digital Input or Output to DGND
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
V
°C
°C
°C
–40 to +105
–60 to +150
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
2
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Product Folder Link(s): ADS1174 ADS1178
ADS1174
ADS1178
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SBAS373–OCTOBER 2007
ELECTRICAL CHARACTERISTICS
All specifications at TA = –40°C to +105°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V,
VREFN = 0V, and all channels active, unless otherwise noted.
ADS1174, ADS1178
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Full-scale input voltage (FSR(1)
Absolute input voltage
)
VIN = (AINP – AINN)
AINP or AINN to AGND
VCM = (AINP + AINN)/2
±VREF
V
V
AGND – 0.1
AVDD + 0.1
Common-mode input voltage
2.5
28
V
High-Speed mode
Low-Power mode
kΩ
kΩ
Differential input impedance
140
DC PERFORMANCE
Resolution
No missing codes
Differential input
16
Bits
SPS
SPS
LSB
mV
High-Speed mode
Low-Power mode
52,734
10,547
0.5
Data rate (fDATA
)
Integral nonlinearity (INL)
Offset error
TBD
TBD
0.150
1.8
Offset drift
μV/°C
mV
Offset match
Gain error
TBD
0.1
TBD
TBD
%
Gain drift
2
ppm/°C
%
Gain match
TBD
1
Noise
Shorted input
fCM = 60Hz
f = 60Hz
LSBPP
dB
Common-mode rejection
100
80
AVDD
DVDD
dB
Power-supply rejection
f = 60Hz
80
dB
AC PERFORMANCE
Crosstalk
VIN = 1kHz, –0.5dBFS
VIN = 1kHz, –0.5dBFS
107
200
dB
ps
dB
dB
dB
dB
Hz
Hz
dB
Hz
s
Sampling aperture match
Signal-to-noise ratio (SNR) (unweighted)
97
Total harmonic distortion (THD)(2)
Spurious-free dynamic range
Passband ripple
High-Speed mode
–105
–108
±0.005
Passband
0.453 fDATA
0.49 fDATA
–3dB Bandwidth
Stop band attenuation
Stop band
100
0.547 fDATA
63.453 fDATA
Group delay
38/fDATA
76/fDATA
Settling time (latency)
Complete settling
s
(1) FSR = full-scale range = 2VREF
(2) THD includes the first nine harmonics of the input signal.
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SBAS373–OCTOBER 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = –40°C to +105°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V,
VREFN = 0V, and all channels active, unless otherwise noted.
ADS1174, ADS1178
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE REFERENCE INPUTS
Reference input voltage (VREF
)
VREF = VREFP – VREFN
0.5
AGND – 0.1
VREFN + 0.5
2.5
3.1
VREFP – 0.5
AVDD + 0.1
V
V
Negative reference input (VREFN)
Positive reference input (VREFP)
V
High-Speed mode
Low-Power mode
High-Speed mode
Low-Power mode
2.6
13
kΩ
kΩ
ADS1174
Reference Input impedance
1.3
6.5
ADS1178
Reference Input impedance
DIGITAL INPUT/OUTPUT (IOVDD = 1.8V to 3.6V)
VIH
0.7 IOVDD
DGND
IOVDD
0.3 IOVDD
IOVDD
0.2 IOVDD
±10
V
V
VIL
VOH
IOH = 5mA
IOL = 5mA
0.8 IOVDD
DGND
V
VOL
V
Input leakage
0 < VIN DIGITAL < IOVDD
μA
MHz
Master clock rate (fCLK
POWER SUPPLY
AVDD
)
0.1
27
4.75
1.65
1.65
5
1.8
3.3
22
5
5.25
1.95
3.6
V
DVDD
V
IOVDD
V
High-Speed mode
Low-Power mode
Power-Down mode
High-Speed mode
Low-Power mode
Power-Down mode
High-Speed mode
Low-Power mode
Power-Down mode
High-Speed mode
Low-Power mode
Power-Down mode
High-Speed mode
Low-Power mode
Power-Down mode
High-Speed mode
Low-Power mode
Power-Down mode
High-Speed mode
Low-Power mode
High-Speed mode
Low-Power mode
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
μA
mA
mA
μA
mA
mA
μA
mA
mA
μA
μA
μA
μA
μA
μA
μA
mW
mW
mW
mW
ADS1174
AVDD current
1
40
9
ADS1178
AVDD current
1
9
ADS1174
DVDD current
2.5
1
17
4.5
1
ADS1178
DVDD current
100
100
1
ADS1174
IOVDD current
150
150
1
ADS1178
IOVDD current
125
32
225
60
ADS1174
Power dissipation
ADS1178
Power dissipation
4
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ADS1174
ADS1178
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SBAS373–OCTOBER 2007
ADS1174/ADS1178 PIN ASSIGNMENTS
PAP PACKAGE
HTQFP-64
(TOP VIEW)
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AINP2
AINN2
AINP1
AINN1
AVDD
AGND
DGND
TEST0
TEST1
AINN7(1)
AINP7(1)
AINN8(1)
AINP8(1)
AVDD
3
4
5
6
AGND
7
PWDN1
PWDN2
PWDN3
PWDN4
PWDN5(1)
PWDN6(1)
PWDN7(1)
PWDN8(1)
MODE
8
ADS1174/ADS1178
9
NOTE: (1) Boldface pin names are for ADS1178 only;
10
11
12
13
14
15
16
CLKDIV
SYNC
see pin descriptions.
DIN
DOUT8(1)
DOUT7(1)
DOUT6(1)
DOUT5(1)
(PowerPAD Outline)
IOVDD
ADS1174/ADS1178 PIN DESCRIPTIONS
PIN
NAME
NO.
FUNCTION
DESCRIPTION
6, 43, 54,
58, 59
AGND
Analog ground
Analog ground; connect to DGND using a single plane.
AINP1
AINP2
AINP3
AINP4
AINP5
AINP6
AINP7
AINP8
3
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
1
63
61
51
49
47
45
ADS1178: AINP[8:1] Positive analog input, channels 8 through 1.
ADS1174: AINP[8:5] Connected to internal ESD rails. The inputs may float.
AINP[4:1] Positive analog input, channels 4 through 1.
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SBAS373–OCTOBER 2007
ADS1174/ADS1178 PIN DESCRIPTIONS (continued)
PIN
NAME
AINN1
AINN2
AINN3
AINN4
AINN5
AINN6
AINN7
AINN8
AVDD
VCOM
VREFN
VREFP
CLK
NO.
FUNCTION
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
DESCRIPTION
4
2
64
ADS1178: AINN[8:1] Negative analog input, channels 8 through 1.
62
52
ADS1174: AINN[8:5] Connected to internal ESD rails. The inputs may float.
AINN[4:1] Negative analog input, channels 4 through 1.
50
48
46
5, 44, 53, 60
Analog power supply Analog power supply (4.75V to 5.25V).
55
57
56
27
Analog output
Analog input
Analog input
Digital input
AVDD/2 Unbuffered analog output.
Negative reference input.
Positive reference input.
Master clock input (maximum 27MHz).
CLK input divider control:
1 = 27MHz
0 = 13.5MHz (high-speed) / 5.4MHz (low-power)
CLKDIV
10
Digital input
DGND
DIN
7, 21, 24, 25
Digital ground
Digital input
Digital ground power supply.
Daisy-chain data input.
12
20
19
18
17
16
15
14
13
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
DOUT1 is TDM data output (TDM mode).
ADS1178: DOUT[8:1] Data output for channels 8 through 1.
ADS1174: DOUT[8:5] Internally connected to active circuitry; outputs are driven.
DOUT[4:1] Data output for channels 4 through 1.
DRDY/
FSYNC
29
Digital input/output
Frame-Sync protocol: frame clock input; SPI protocol: data ready output.
DVDD
26
32
Digital power supply Digital core power supply (+1.65V to +1.95V).
Digital input
FORMAT0
FORMAT1
FORMAT2
IOVDD
FORMAT[2:0] Selects between Frame-Sync/SPI protocol, TDM/discrete data
31
Digital input
Digital input
outputs, fixed/dynamic position TDM data, and modulator mode/normal operating
mode.
30
22, 23, 33
Digital power supply I/O power supply (+1.65V to +3.6V).
MODE:
0 = High-Speed mode
1 = Low-Power mode.
MODE
34
Digital input
MODE1
PWDN1
PWDN2
PWDN3
PWDN4
PWDN5
PWDN6
PWDN7
PWDN8
SCLK
33
42
41
40
39
38
37
36
35
28
11
8
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
ADS1178: PWDN[8:1] Power-down control for channels 8 through 1.
ADS1174: PWDN[8:5] must = 0V.
PWDN[4:1] Power-down control for channels 4 through 1.
Serial clock input.
SYNC
Synchronize input (all channels).
TEST0
TEST1
TEST[1:0] Test mode select:
00 = normal operation
11 = boundary scan test mode
9
6
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ADS1178
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SBAS373–OCTOBER 2007
TIMING CHARACTERISTICS: SPI FORMAT
tCLK
tCPW
CLK
· · ·
tCPW
tCD
tCONV
DRDY
SCLK
tSD
tDS
tS
tSPW
tSPW
tDOPD
tMSBPD
tDOHD
Bit 15 (MSB)
Bit 14
tDIST
Bit 13
DOUT
DIN
tDIHD
TIMING REQUIREMENTS: SPI FORMAT
For TA = –40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V.
SYMBOL
tCLK
PARAMETER
MIN
37
TYP
MAX
UNIT
CLK period (1/fCLK
)
10,000
ns
tCPW
CLK positive or negative pulse width
15
ns
(1)
tCONV
Conversion period (1/fDATA
)
256
2560
12
CLK periods
(2)
tCD
Falling edge of CLK to falling edge of DRDY
Falling edge of DRDY to rising edge of first SCLK to retrieve data
DRDY falling edge to DOUT MSB valid (propagation delay)
Falling edge of SCLK to rising edge of DRDY
SCLK period
22
18
ns
(2)
tDS
1
CLK period
tMSBPD
ns
ns
ns
ns
ns
ns
ns
ns
(2)
tSD
(3)
tS
tCLK
0.4tCLK
10
tSPW
SCLK positive or negative pulse width
0.6tCLK
31
(2)(4)
tDOHD
SCLK falling edge to new DOUT invalid (hold time)
SCLK falling edge to new DOUT valid (propagation delay)
New DIN valid to falling edge of SCLK (setup time)
Old DIN valid to falling edge of SCLK (hold time)
(2)
tDOPD
tDIST
6
6
(4)
tDIHD
(1) Depends on MODE[1:0] and CLKDIV selection. See Table 5 (fCLK/fDATA).
(2) Load on DRDY and DOUT = 20pF.
(3) For best performance, use fSCLK/fCLK ratios of 1, 1/2, 1/4, 1/8, etc.
(4) tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and
ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4ns.
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SBAS373–OCTOBER 2007
TIMING CHARACTERISTICS: FRAME-SYNC FORMAT
tCPW
tCLK
CLK
tCPW
tCF
tFRAME
tFPW
tFPW
FSYNC
tFS
tS
tSPW
tSF
SCLK
DOUT
DIN
tSPW
tMSBPD
Bit 15 (MSB)
tDOPD
tDOHD
Bit 13
Bit 14
tDIST
tDIHD
TIMING REQUIREMENTS: FRAME-SYNC FORMAT
For TA = –40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V.
SYMBOL
tCLK
PARAMETER
MIN
TYP
MAX
UNIT
ns
CLK period (1/fCLK
)
37
10,000
tCPW
tCF
CLK positive or negative pulse width
15
ns
Falling edge of CLK to falling edge of SCLK
–0.35 tCLK
0.35 tCLK
ns
(1)
tFRAME
tFPW
tFS
Frame period (1/fDATA
)
256
2560 CLK periods
FSYNC positive or negative pulse width
1
SCLK periods
Rising edge of FSYNC to rising edge of SCLK
Rising edge of SCLK to rising edge of FSYNC
SCLK period(2)
5
ns
ns
ns
tSF
5
tCLK
tS
tSPW
SCLK positive or negative pulse width
0.4 tSCLK
6
0.6 tSCLK
ns
ns
ns
ns
ns
ns
(3)(4)
tDOHD
SCLK falling edge to old DOUT invalid (hold time)
SCLK falling edge to new DOUT valid (propagation delay)
FSYNC rising edge to DOUT MSB valid (propagation delay)
New DIN valid to falling edge of SCLK (setup time)
Old DIN valid to falling edge of SCLK (hold time)
(3)
tDOPD
28
28
tMSBPD
tDIST
6
6
(4)
tDIHD
(1) Depends on MODE[1:0] and CLKDIV selection. See Table 5 (fCLK/fDATA).
(2) tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and
ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4ns.
(3) SCLK must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of fCLK
(4) Load on DOUT = 20pF.
.
8
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SBAS373–OCTOBER 2007
OVERVIEW
To allow tradeoffs between speed and power, two
modes of operation are supported: High-Speed and
Low-Power. Table 1 summarizes the performance of
each mode.
The ADS1174 (quad) and ADS1178 (octal) are 16-bit,
delta-sigma ADCs. They offer the combination of
excellent linearity, low noise, and low power
consumption. Figure 1 shows the block diagram. Note
that both devices are the same, except the ADS1174
has four ADCs, and the ADS1178 has eight ADCs.
The pinout and package of the ADS1178 is
compatible with the ADS1174, permitting drop-in
expandability. The converters are comprised of either
four (ADS1174) or eight (ADS1178) advanced,
6th-order, chopper-stabilized, delta-sigma modulators
followed by low-ripple, linear phase FIR filters. The
In High-Speed mode, the data rate is 52kSPS, and in
Low-Power mode, the power dissipation is only
8mW/channel at 10.5kSPS.
The ADS1174/78 is configured by simply setting the
appropriate I/O pins—there are no registers to
program. Data is retrieved over a serial interface that
supports both SPI and Frame-Sync formats. The
ADS1174/78 has a daisy-chainable output and the
ability to synchronize externally, so it can be used
conveniently in systems requiring more than eight
channels.
modulators measure the differential input signal, VIN
=
(AINP – AINN), against the differential reference,
VREF = (VREFP – VREFN). The digital filters receive
the modulator signal and provide a low-noise digital
output.
VREFP
AVDD
VREFN
DVDD
IOVDD
R
S
VCOM
VREF
R
VIN1
DS
AINP1
AINN1
Digital
Filter1
DRDY/FSYNC
SPI
S
S
Modulator1
SCLK
DOUT[4:1]/[8:1](1)
and
Frame-Sync
Interface
DIN
VIN2
DS
AINP2
AINN2
Digital
Filter2
Modulator2
TEST[1:0]
FORMAT[2:0]
CLK
Control
Logic
SYNC
PWDN[4:1]/[8:1](1)
AINP4/8(1)
AINN4/8(1)
VIN4/8
DS
Modulator4/8(1)
Digital
Filter4/8(1)
CLKDIV
S
MODE
AGND
DGND
NOTE: (1) The ADS1174 has four channels; the ADS1178 has eight channels.
Figure 1. ADS1174/ADS1178 Block Diagram
Table 1. Operating Mode Performance Summary
POWER DISSIPATION
PER CHANNEL(1)
(mW)
DATA RATE
(SPS)
PASSBAND
(Hz)
SNR
(dB)
NOISE
(LSBPP)
MODE
High-Speed
Low-Power
52,734
10,547
23,889
4,536
97
97
1
1
32
8
(1) Measured with all channels operating.
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FUNCTIONAL DESCRIPTION
Because the input signal is sampled at a very high
rate, input signal aliasing does not occur until the
input signal frequency is at the modulator sampling
rate. This high sampling rate greatly relaxes the
requirement of external antialiasing filters allowing
very low passband phase errors.
The ADS1174 and ADS1178 are delta/sigma ADCs
consisting of independent converters that digitize
input signals in parallel. The ADS1174 consists of
four independent converters, while the ADS1178 has
eight independent converters.
The converter is composed of two main functional
blocks to perform the ADC conversions: the
modulator and the digital filter. The modulator
samples the input signal together with sampling the
reference voltage to produce a 1's density output
stream. The density of the output stream is
proportional to the analog input level relative to the
reference voltage. The pulse stream is filtered by the
internal digital filter where the output conversion
result is produced.
SAMPLING APERTURE MATCHING
The converters of the ADS1174/78 operate from the
same CLK input. The CLK input controls the timing of
the modulator sampling instant. The converter is
designed such that the sampling skew, or modulator
sampling aperture match, between channels is
controlled to within 200ps. Furthermore, the digital
filters are synchronized to start the convolution phase
at the same modulator clock cycle. This design
results in excellent phase match among the
ADS1174/78 channels.
In operation, the signal inputs and reference inputs
are sampled by the modulator at a high rate (typically
64x higher than the final output data rate). The
quantization noise of the modulator is moved to a
higher frequency range where the internal digital filter
removes it. This process results in very low levels of
noise within the signal passband.
The phase match of one four-channel ADS1174 to
that of another ADS1174 may not have the same
degree of sampling match (the same is true for the
8-channel ADS1178). As a result of manufacturing
variations, differences in internal propagation delay of
the internal CLK signal coupled with differences of
the arrival of the external CLK signal to each device
may cause larger sampling match errors. Equal
length CLK traces or external clock distribution
devices can be used to control the arrival of the CLK
signals to help reduce the sampling match error.
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FREQUENCY RESPONSE
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
The digital filter sets the overall frequency response.
The filter uses a multi-stage FIR topology to provide
linear phase with minimal passband ripple and high
stop band attenuation. The oversampling ratio of the
digital filter (that is, the ratio of the modulator
sampling to the output data rate: fMOD/fDATA) is 64 for
both High-Speed and Low-Power modes.
Figure 2 shows the frequency response of the
ADS1174/78 normalized to fDATA. Figure 3 shows the
passband ripple. The transition from passband to stop
band is illustrated in Figure 4. The overall frequency
response repeats at 64x multiples of the modulator
frequency fMOD, as shown in Figure 5.
0.45
0.47
0.49
0.51
0.53
0.55
Normalized Input Frequency (fIN/fDATA
)
Figure 4. Transition Band Response
0
-20
20
-40
0
-20
-60
-40
-80
-60
-100
-120
-140
-80
-100
-120
-140
-160
0
0.2
0.4
0.6
0.8
1.0
Normalized Input Frequency (fIN/fDATA
)
0
16
32
48
64
Figure 2. Frequency Response
Input Frequency (fIN/fDATA
)
Figure 5. Frequency Response Out to fMOD
0.02
0
These image frequencies, if present in the signal and
not externally filtered, will fold back (or alias) into the
passband, causing errors. Table 2 lists the degree of
image rejection versus external antialiasing filter
order. The stop band of the ADS1174/78 provides
100dB attenuation of frequencies that begin just
-0.02
-0.04
-0.06
-0.08
-0.10
beyond the passband and continue out to fMOD
.
Placing an antialiasing, low-pass filter in front of the
ADS1174/78 inputs is recommended to limit possible
high-amplitude, out-of-band signals and noise.
0
0.1
0.2
0.3
0.4
0.5
0.6
Table 2. Antialiasing Filter Order Image Rejection
Normalized Input Frequency (fIN/fDATA
)
ANTIALIASING FILTER
ORDER
IMAGE REJECTION (dB)
(f–3dB at fDATA
)
Figure 3. Passband Response
1
2
3
39
75
111
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PHASE RESPONSE
DATA FORMAT
The ADS1174/78 incorporates a multiple stage, linear
phase digital filter. Linear phase filters exhibit
constant delay time versus input frequency (constant
group delay), which means the time delay from any
instant of the input signal to the same instant of the
output data is constant, and is independent of input
signal frequency. This behavior results in essentially
zero phase errors when analyzing multi-tone signals.
The ADS1174/78 outputs 16 bits of data in two’s
complement format.
A positive full-scale input produces an ideal output
code of 7FFFh, and the negative full-scale input
produces an ideal output code of 8000h. The output
clips at these codes for signals exceeding full-scale.
Table 3 summarizes the ideal output codes for
different input signals.
SETTLING TIME
Table 3. Ideal Output Code versus Input Signal
As with frequency and phase response, the digital
filter also determines settling time. Figure 6 shows
the output settling behavior after a step change on
the analog inputs normalized to conversion periods.
The X-axis is given in units of conversion. Note that
after the step change on the input occurs, the output
data changes very little prior to 30 conversion
periods. The output data is fully settled after 76
conversion periods.
INPUT SIGNAL VIN
(AINP – AINN)
IDEAL OUTPUT CODE(1)
≥ +VREF
7FFFh
) VREF
215 * 1
0
0001h
0000h
* VREF
215 * 1
FFFFh
8000h
215
ǒ
Ǔ
v −VREF
215 1
Final Value
100
(1) Excludes effects of noise, INL, offset, and gain errors.
Fully Settled Data
at 76 Conversions
Initial Value
0
0
10
20
30
40
50
60
70
80
Conversions (1/fDATA
)
Figure 6. Step Response
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ANALOG INPUTS (AINP, AINN)
The ADS1174/78 measures each differential input
signal VIN = (AINP – AINN) against the common
differential reference VREF = (VREFP – VREFN). The
AVDD AGND
S1
most positive measurable differential input is +VREF
,
AINP
AINN
which produces the most positive digital output code
of 7FFFh. Likewise, the most negative measurable
differential input is –VREF, which produces the most
negative digital output code of 8000h.
S2
9pF
S1
For optimum performance, the inputs of the
ADS1174/78 are intended to be driven differentially.
For single-ended input applications, one of the inputs
(AINP or AINN) can be driven while the other input is
fixed (typically, to AGND or +2.5V); fixing the input to
+2.5V permits bipolar operation, thereby using the full
range of the converter.
AGND AVDD
ESD Protection
Figure 7. Equivalent Analog Input Circuitry
While the ADS1174/78 measures the differential input
signal, the absolute input voltage is also important.
This is the voltage on either input (AINP or AINN)
with respect to AGND. The range for this voltage is:
tSAMPLE = 1/fMOD
ON
S1
OFF
ON
–0.1V < (AINN or AINP) < AVDD + 0.1V
S2
OFF
If either input is taken below –0.4V or above (AVDD +
0.4), ESD protection diodes on the inputs may turn
on.
Figure 8. S1 and S2 Switch Timing for Figure 7
If these conditions are possible, external Schottky
clamp diodes or series resistors may be required to
limit the input current to safe levels (see Absolute
Maximum Ratings table).
Table 4. Modulator Frequency (fMOD) versus Mode
Selection
MODE SELECTION
CLKDIV
fMOD
fCLK/8
fCLK/4
fCLK/40
fCLK/8
The ADS1174/78 is a high-performance ADC. For
optimum performance, it is critical that the appropriate
circuitry be used to drive the ADS1174/78 inputs. See
the Applications Information section for the
recommended circuits.
1
0
1
0
High-Speed
Low-Power
The ADS1174/78 uses switched-capacitor circuitry to
measure the input voltage. Internal capacitors are
charged by the inputs and then discharged. Figure 7
shows a conceptual diagram of these circuits. Switch
S2 represents the net effect of the modulator circuitry
in discharging the sampling capacitor; the actual
implementation is different. The timing for switches S1
and S2 is shown in Figure 8. The sampling time
The average load presented by the switched
capacitor input can be modeled with an effective
differential impedance, as shown in Figure 9. Note
that the effective impedance is a function of fMOD
.
AINP
(tSAMPLE
) is the inverse of modulator sampling
Zeff = 14kW ´ (6.75MHz/fMOD
)
frequency (fMOD) and is a function of the mode, the
CLKDIV input, and frequency of CLK, as shown in
Table 4.
AINN
Figure 9. Effective Input Impedances
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VOLTAGE REFERENCE INPUTS
(VREFP, VREFN)
If these conditions are possible, external Schottky
clamp diodes or series resistors may be required to
limit the input current to safe levels (see Absolute
Maximum Ratings table).
The voltage reference for the ADS1174/78 ADC is
the differential voltage between VREFP and VREFN:
VREF = (VREFP – VREFN). The voltage reference is
common to the four channels. The reference inputs
use a structure similar to that of the analog inputs
with the equivalent circuitry on the reference inputs
shown in Figure 10. As with the analog inputs, the
load presented by the switched capacitor can be
modeled with an effective impedance, as shown in
Figure 11. However, the reference input impedance
depends on the number of active (enabled) channels
in addition to fMOD. As a result of the change of
reference input impedance caused by enabling and
disabling channels, the regulation and settling time of
the external reference should be noted, so as not to
affect the readings of other channels.
Note that the valid operating range of the reference
inputs is limited to the following:
–0.1V ≤ VREFN ≤ VREFP – 0.5V
VREFN + 0.5V ≤ VREFP ≤ AVDD + 0.1V
A high-quality reference voltage with the appropriate
drive strength is essential for achieving the best
performance from the ADS1174/78. Noise and drift
on the reference degrade overall system
performance. See the Application Information section
for example reference circuits.
CLOCK INPUT (CLK)
The ADS1174/78 requires a clock input for operation.
Each ADS1174/78 converter operates from the same
clock input. At the maximum data rate, the clock input
can be either 27MHz or 13.5MHz (5.4MHz, low
power), determined by the setting of the CLKDIV
input. The selection of the external clock frequency
(fCLK) does not affect the resolution (the oversampling
ratio, OSR, remains fixed) or power dissipation of the
ADS1174/78. However, using a slower fCLK can
reduce the power consumption of an external clock
driver. The output data rate scales with clock
frequency, down to a minimum clock frequency of
fCLK = 100kHz. Table 5 summarizes the ratio of clock
input frequency (fCLK) to data rate (fDATA), maximum
data rate and corresponding maximum clock input for
the two operating modes.
VREFP
VREFN
AGND
AVDD
AGND
AVDD
ESD
Protection
Figure 10. Equivalent Reference Input Circuitry
Table 5. Clock Input Options
VREFP
VREFN
MODE
SELECTION
fCLK
(MHz)
DATA RATE
(SPS)
CLKDIV fCLK/fDATA
27
13.5
27
1
0
1
0
512
256
High-Speed
Low-Power
52,734
10,547
5.2kW
Zeff
=
´ (6.75MHz/fMOD)
2,560
512
N
5.4
N = number of active channels.
As with any high-speed data converter, a high-quality,
low-jitter clock is essential for optimum performance.
Crystal clock oscillators are the recommended clock
source. Make sure to avoid excess ringing on the
clock input; keeping the clock trace as short as
possible using a 50Ω series resistor, placed close to
the source end, often helps.
Figure 11. Effective Reference Impedance
ESD diodes protect the reference inputs. To keep
these diodes from turning on, make sure the voltages
on the reference pins do not go below AGND by
more than 0.4V, and likewise do not exceed AVDD by
0.4V.
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MODE SELECTION (MODE)
SYNCHRONIZATION (SYNC)
The ADS1174/78 supports two modes of operation:
High-Speed and Low-Power. These modes offer
optimization of speed or power. The mode selection
is determined by the status of the digital input MODE
pins, as shown in Table 6. The ADS1174/78
constantly monitors the status of the MODE pin
during operation.
The ADS1174/78 can be synchronized by pulsing the
SYNC pin low and then returning the pin high. When
the pin goes low, the conversion process stops, and
the internal counters used by the digital filter are
reset. When the SYNC pin returns high, the
conversion process restarts. Synchronization allows
the conversion to be aligned with an external event,
such as a reference timing pulse.
Table 6. Mode Selection
Since the converters of the ADS1174/78 operate in
parallel from the same master clock and use the
same SYNC input control, they are, by default, in
synchronization with each other. The sampling
aperture match among the channels is 200ps
(typical). However, the synchronization of multiple
ADS1174/78s is somewhat different. At device
power-on, variations in internal reset thresholds from
device to device may result in uncertainty in
conversion timing.
(1)
MODE
MODE SELECTION
High-Speed
MAX fDATA
52,734
0
1
Low-Power
10,547
(1) fCLK = 27MHz (CLKDIV = 1).
When using the SPI protocol, DRDY is held high after
a mode change occurs until settled (or valid) data are
ready, as shown in Figure 12 and Table 7.
In Frame-Sync protocol, the DOUT pins are held low
after a mode change occurs until settled data are
ready, as shown in Figure 12 and Table 7. Data can
be read from the device to detect when DOUT
changes to logic 1, indicating valid data.
The SYNC pin can be used to synchronize multiple
ADS1174/78s to within the same CLK cycle.
Figure 13 illustrates the timing requirement of SYNC
and CLK in SPI format.
See Figure 14 for the Frame-Sync format timing
requirement.
MODE[1:0]
Pins
ADS1174/78 Previous
Mode
New Mode
tNDR-SPI
Mode
SPI
DRDY
Protocol
New Mode
Valid Data Ready
tNDR-FS
Frame-Sync
DOUT
Protocol
New Mode
Valid Data on DOUT
Figure 12. Mode Change Timing
Table 7. Mode Change
SYMBOL
tNDR-SPI
tNDR-FS
DESCRIPTION
MIN
TYP
MAX
129
UNITS
Time for new data to be ready (SPI)
Conversions (1/fDATA
Conversions (1/fDATA
)
)
Time for new data to be ready (Frame-Sync)
127
128
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After synchronization, indication of valid data
depends on the whether SPI or Frame-Sync format
was used.
In the Frame-Sync format, DOUT goes low as soon
as SYNC is taken low; see Figure 14. After SYNC is
returned high, DOUT stays low while the digital filter
is settling. Once valid data are ready for retrieval,
DOUT begins to output valid data. For proper
synchronization, FSYNC, SCLK, and CLK must be
established before taking SYNC high, and must then
remain running.
In the SPI format, DRDY goes high as soon as SYNC
is taken low; see Figure 13. After SYNC is returned
high, DRDY stays high while the digital filter is
settling. Once valid data are ready for retrieval,
DRDY goes low.
tCSHD
CLK
tSCSU
tSYN
SYNC
tNDR
DRDY
Figure 13. Synchronization Timing for SPI Protocol
Table 8. SPI Protocol
SYMBOL
tCSHD
tSCSU
tSYN
DESCRIPTION
MIN
10
5
TYP
MAX
UNITS
CLK to SYNC hold time
SYNC to CLK setup time
Synchronize pulse width
Time for new data to be ready
ns
ns
1
CLK periods
Conversions (1/fDATA)
tNDR
129
tCSHD
CLK
tSCSU
tSYN
SYNC
FSYNC
DOUT
tNDR
Valid Data
Figure 14. Synchronization Timing for Frame-Sync Protocol
Table 9. Frame-Sync Protocol
SYMBOL
tCSHD
tSCSU
tSYN
DESCRIPTION
MIN
10
5
TYP
MAX
UNITS
CLK to SYNC hold time
SYNC to CLK setup time
Synchronize pulse width
Time for new data to be ready
ns
ns
1
CLK periods
Conversions (1/fDATA)
tNDR
127
128
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POWER-DOWN (PWDN)
2. Wait for 129/fDATA after taking the PWDN pins
high.
The ADS1174/78 measurement channels can be
independently powered down by use of the PWDN
inputs. To enter the power-down mode, take the
respective PWDN pin low. Power-down occurs after
two fCLK cycles have elapsed. This delay guards
against false transitions caused by external noise. To
exit power-down, return the corresponding PWDN pin
high. Note that when all channels are powered down,
the ADS1174/78 enters a microwatt (μW) power state
where all internal biasing is powered-down. In this
event, the TEST[1:0] input pins must be driven; all
other input pins can float (the ADS1174/78 outputs
remain driven).
3. Detect for non-zero data in the powered-up
channel.
After powering-up one or more channels, the
channels are synchronized to each other. It is not
necessary to use the SYNC pin to synchronize them.
When a channel is powered down in TDM data
format, the data for the powered-down channel will
either be forced to zero (fixed-position TDM data
mode) or be replaced by shifting the data from the
next channel into the vacated data position
(dynamic-position TDM data mode).
As shown in Figure 15 and Table 10, a maximum of
129 conversion cycles must elapse before reading
data after exiting power-down. The data from
channels already running are not affected. The user
software can perform the required delay time in the
following ways:
In discrete data format, the data are always forced to
zero.
When
powering-up
a
channel
in
dynamic-position TDM data format mode, the channel
data remain packed until the data are ready, at which
time the data frame is expanded to include the
just-powered channel data. See the Data Format
section for details.
1. Count the number of data conversions after
taking the PWDN pin high.
· · ·
· · ·
CLK
tPDWN
tNDR
PWDN
DRDY/FSYNC(1)
DOUT
(Discrete Data Output Mode)
Post Power-Up Data
Normal Position
DOUT1
(TDM Mode, Dynamic Position)
Normal Position
Data Shift Position
DOUT1
(TDM Mode, Fixed Position)
Normal Position
Data Remain in Position
Normal Position
NOTE: (1) In SPI protocol, the timing occurs on the falling edge of DRDY/FSYNC. Powering down all channels forces DRDY/FSYNC high.
Figure 15. Power-Down Timing
Table 10. Power-Down Timing
SYMBOL
DESCRIPTION
MIN
2
TYP
MAX
UNITS
tPDWN
PDWN pulse width to enter Power-Down mode
Time for new data to be ready (SPI)
Time for new data to be ready (Frame-Sync)
CLK periods
129
128
130
129
Conversions (1/fDATA
Conversions (1/fDATA
)
)
tNDR
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FORMAT[2:0]
recommended to keep SCLK as clean as possible to
prevent glitches from accidentally shifting the data.
SCLK may be run as fast as the CLK frequency.
SCLK may be either in free-running or stop-clock
Data can be read from the ADS1174/78 with two
serial interface protocols (SPI or Frame-Sync) and
several options of data formats (TDM/Discrete and
Fixed/Dynamic data positions). The FORMAT[2:0]
inputs are used to select among the options. Table 11
lists the available options. See the DOUT Modes
section for details of the DOUT modes and data
positions.
operation
between
conversions.
For
best
performance, use fSCLK/fCLK ratios of 1, 1/2, 1/4, 1/8,
etc. NOTE: One CLK period is required after DRDY
falls, to start shifting data (see Timing Requirements:
SPI Format ).
DRDY/FSYNC (SPI Format)
Table 11. Data Output Format
In the SPI format, this pin functions as the DRDY
output. It goes low when data are ready for retrieval
and then returns high on the falling edge of the first
subsequent SCLK. If data are not retrieved (that is,
SCLK is held low), DRDY will pulse high just before
the next conversion data are ready, as shown in
Figure 16. The new data are loaded within one CLK
cycle before DRDY goes low. All data must be shifted
out before this time to avoid being overwritten.
INTERFACE
PROTOCOL
DOUT
MODE
DATA
POSITION
FORMAT[2:0]
000
001
010
011
100
101
SPI
SPI
TDM
TDM
Dynamic
Fixed
—
SPI
Discrete
TDM
Frame-Sync
Frame-Sync
Frame-Sync
Dynamic
Fixed
—
TDM
Discrete
1/fCLK
1/fDATA
SERIAL INTERFACE PROTOCOLS
DRDY
Data are retrieved from the ADS1174/78 using the
serial interface. Two protocols are available: SPI and
Frame-Sync. The same pins are used for both
interfaces: SCLK, DRDY/FSYNC, DOUT[4:1] (or
DOUT[8:1] for the ADS1178), and DIN. The
FORMAT[2:0] pins select the desired interface
protocol.
SCLK
Figure 16. DRDY Timing with No Readback
DOUT
In Discrete Data Output mode, the conversion data
are output on the individual DOUT pins (DOUT1,
DOUT2, etc.), whereas in TDM mode, data are output
only on DOUT1. The MSB data are valid on
DOUT[4:1]/[8:1] when DRDY goes low. The
subsequent bits are shifted out with each falling edge
of SCLK. If daisy-chaining (TDM mode), the data
shifted in using DIN will appear on DOUT1 after all
channel data have been shifted out.
SPI SERIAL INTERFACE
The SPI-compatible format is a simple read-only
interface. Data ready for retrieval are indicated by the
falling DRDY output and are shifted out on the falling
edge of SCLK, MSB first. The interface can be
daisy-chained using the DIN input when using
multiple ADS1174/78s. See the Daisy-Chaining
section for more information.
DIN
SCLK
This input is used when multiple ADS1174/78s are to
be daisy-chained together. The DOUT1 pin of the first
device connects to the DIN pin of the next, etc. It can
be used with either the SPI or Frame-Sync formats.
Data are shifted in on the falling edge of SCLK. When
using only one ADS1174/78, tie DIN low. See the
Daisy-Chaining section for more information.
The serial clock (SCLK) features a Schmitt-triggered
input and shifts out data on DOUT on the falling
edge. It also shifts in data on the falling edge on DIN
when this pin is being used for daisy-chaining. The
device shifts data out on the falling edge and the user
typically shifts this data in on the rising edge. Even
though the SCLK input has hysteresis, it is
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DRDY/FSYNC (Frame-Sync Format)
FRAME-SYNC SERIAL INTERFACE
In Frame-Sync format, this pin is used as the FSYNC
input. The frame-sync input (FSYNC) sets the frame
period which must be same as the data rate. The
required number of fCLK cycles to each FSYNC period
depends on the mode selection and the CLKDIN
input. Table 5 indicates the number of CLK cycles to
each frame (fCLK/fDATA). If the FSYNC period is not
the proper value, data readback will be corrupted.
Frame-Sync format is similar to the interface often
used on audio ADCs. It operates in slave
fashion—the user must supply framing signal FSYNC
(similar to the left/right clock on stereo audio ADCs)
and the serial clock SCLK (similar to the bit clock on
audio ADCs). The data is output MSB first or
left-justified. When using Frame-Sync format, the
FSYNC and SCLK inputs must be continuously
running with the required relationships shown in the
Frame-Sync Timing Requirements.
DOUT
In Discrete Data Output mode, the conversion data
are shifted out on the individual DOUT pins (DOUT1,
DOUT2, etc.), whereas in TDM mode, data are output
only on DOUT1. The MSB data become valid on
DOUT[4:1]/[8:1] on the SCLK rising edge prior to
FSYNC going high. The subsequent bits are shifted
out with each falling edge of SCLK. If daisy-chaining
(TDM mode), the data shifted in using DIN will appear
on DOUT1 after all channel data have been shifted
out (that is, 4 channels × 16 bits per channel = 64 bits
for the ADS1174, and 8 channels × 16 bits per
channel = 128 bits for the ADS1178).
SCLK
The serial clock (SCLK) features a Schmitt-triggered
input and shifts out data on DOUT on the falling
edge. It also shifts in data on the falling edge on DIN
when this pin is being used for daisy-chaining. Even
though SCLK has hysteresis, it is recommended to
keep SCLK as clean as possible to prevent glitches
from accidentally shifting the data. When using
Frame-Sync format, SCLK must run continuously. If it
is shut down, the data readback will be corrupted.
The number of SCLKs within a frame period (FSYNC
clock) can be any power of two ratio of clock cycles
(1, 1/2, 1/4, etc.), as long as the number of cycles is
sufficient to shift the data output from all channels
within one data frame.
DIN
This input is used when multiple ADS1174/78s are to
be daisy-chained together. It can be used with either
SPI or Frame-Sync formats. Data are shifted in on
the falling edge of SCLK. When using only one
ADS1174/78, tie DIN low. See the Daisy-Chaining
section for more information.
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DOUT MODES
output from another ADS1174, ADS1178, or other
compatible device. Note that when all channels of the
ADS1174/78 are powered-down, the interface is
For both SPI and Frame-Sync interface protocols,
either the data are shifted out through individual
channel DOUT pins in a parallel data format (Discrete
mode), or the data for all channels are shifted out in
series through common pin DOUT1 (TDM mode).
powered-down,
rendering
the
DIN
input
powered-down as well. When one or more channels
of the device are powered-down, the data format of
the TDM mode can be fixed or dynamic.
TDM Mode
TDM Mode, Fixed-Position Data
In TDM (time division multiplexed) data output mode,
the data for all channels are shifted out, in series, on
a single pin (DOUT1). As shown in Figure 17, the
data from channel 1 are shifted out first, followed by
channel 2 data, etc. After the data from the last
channel are shifted out (channel 4 for the ADS1174
or channel 8 for the ADS1178), the data from the DIN
input follow. The DIN is used to daisy-chain the data
In this TDM data output mode, the data position of
the channels remains fixed, regardless of whether
channels are disabled. If a channel is powered-down,
data are forced to zero but occupies the same
position within the data stream. Figure 18 shows the
data stream with channel
powered-down.
1
and channel
3
SCLK
1
2
15
16
17
31
32
33
47
CH3
CH3
49
63
64
65
66
67
113
127
128
129
130
131
48
DOUT1
(ADS1174)
CH1
CH1
CH2
CH4
DIN
CH5
DOUT1
(ADS1178)
CH2
CH4
CH8
DIN
DRDY
(SPI)
FSYNC
(Frame-Sync)
Figure 17. TDM Mode (All Channels Enabled)
113
127
128
129
130
131
SCLK
1
2
15
16
17
31
32
33
47
48
49
63
64
65
66
67
DOUT1
(ADS1174)
CH1
CH1
CH2
CH3
CH4
DIN
DOUT1
(ADS1178)
CH2
CH3
CH4
CH5
CH8
DIN
DRDY
(SPI)
FSYNC
(Frame-Sync)
Figure 18. TDM Mode, Fixed-Position Data (Channels 1 and 3 Shown Powered-Down)
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TDM Mode, Dynamic Position Data
Discrete Data Output Mode
In this TDM data output mode, when a channel is
powered-down, the data from higher channels shift
one position in the data stream to fill the vacated data
slot. Figure 19 shows the data stream with channel 1
and channel 3 powered-down.
In Discrete data output mode, the channel data are
shifted out in parallel using individual channel data
output pins DOUT[4:1] for the ADS1174, or
DOUT[8:1] for the ADS1178. After the 16th SCLK,
the channel data are forced to zero. The data are
also forced to zero for powered-down channels.
Figure 20 depicts the data format.
SCLK
1
2
15
16
17
31
32
33
34
35
80
81
95
96
97
98
99
DOUT1
(ADS1174)
CH2
CH4
DIN
CH5
DOUT1
(ADS1178)
CH2
CH4
CH8
DIN
DRDY
(SPI)
FSYNC
(Frame- Sync)
Figure 19. TDM Mode, Dynamic Position Data (Channels 1 and 3 Shown Powered-Down)
1
2
14
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
15
16
SCLK
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
ADS1178 Only
DRDY
(SPI)
FSYNC
(Frame-Sync)
Figure 20. Discrete Data Output Mode
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SBAS373–OCTOBER 2007
DAISY-CHAINING
The maximum number of channels that may be
daisy-chained in this way is limited by the frequency
of fSCLK, the mode selection, and the CLKDIV input.
The frequency of fSCLK must be high enough to
completely shift the data out from all channels within
one fDATA period. Table 12 lists the maximum number
Multiple ADS1174/78s can be daisy-chained together
to simplify the serial interface connections. The
DOUT1 data output pin of one ADS1174/78 is
connected to the DIN of the next ADS1174/78. As
Figure 21 illustrates, the DOUT1 pin of device 1
provides the output data to a controller, and the DIN
of device 2 is grounded. Figure 22 describes the data
format when reading data back in a daisy-chain
configuration.
of daisy-chained channels when fSCLK = fCLK
.
ADS1178
ADS1178
U2
U1
SYNC
CLK
SYNC
CLK
SYNC
CLK
DRDY
DRDY Output from Device 1
DIN2
DIN
DOUT1
DIN
DOUT1
Serial Data from Devices 1 and 2
SCLK
SCLK
SCLK
Figure 21. Daisy-Chaining of Two ADS1178s, SPI Protocol (FORMAT[2:0] = 011 or 100)
SCLK
1
2
17
18
33
34
49
50
65
66
129
130
145
146
257
258
DOUT1
CH1, U1
CH2, U1
CH3, U1
CH4, U1
CH5, U1
CH1, U2
CH2, U2
DIN2
DRDY
(SPI)
FSYNC
(Frame-Sync)
Figure 22. Daisy-Chain Data Format of Figure 21
Table 12. Maximum Channels in a Daisy-Chain (fSCLK = fCLK
)
MODE SELECTION
CLKDIV
MAXIMUM NUMBER OF CHANNELS
1
0
1
0
32
16
High-Speed
160
32
Low-Power
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To increase the number of data channels possible in
a chain, a segmented DOUT scheme may be used,
producing two data streams. Figure 23 illustrates four
ADS1178s, with a pair of ADS1178s daisy-chained
together. The channel data of each daisy-chained
pair is shifted out in parallel and is received by the
processor through independent data channels.
Whether the interface protocol is SPI or Frame-Sync,
it is recommended to synchronize all devices by tying
the SYNC inputs together. When synchronized in SPI
protocol, it is only necessary to monitor the DRDY
output of one ADS1178.
In Frame-Sync interface protocol, the data from all
devices are ready on the rising edge of FSYNC.
Since DOUT1 and DIN are both shifted on the falling
edge of SCLK, the propagation delay on DOUT1
creates a setup time for DIN. Minimize the skew in
SCLK to avoid timing violations.
SYNC
CLK
Serial
Data
from
Devices
ADS1178
ADS1178
ADS1178
ADS1178
3 and 4
U4
U3
U2
U1
SYNC
SYNC
SYNC
SYNC
Serial
Data
CLK
CLK
CLK
CLK
DOUT1
DOUT1
from
DIN
DOUT1
DIN
DIN
DOUT1
DIN
Devices
1 and 2
FSYNC
SCLK
FSYNC
SCLK
FSYNC
SCLK
FSYNC
SCLK
SCLK
FSYNC
Figure 23. Segmented DOUT Daisy-Chain, Frame-Sync Protocol (FORMAT[2:0] = 000 or 001)
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POWER-UP SEQUENCE
Figure 24 shows the power-up sequence of the
ADS1174/78. The power supplies can be sequenced
in any order. Each supply has an internal reset circuit
where the outputs are summed together to generate
an internal global power-on reset. After the supplies
have exceeded the reset thresholds, 218 fCLK cycles
are counted before the converter initiates the
conversion process. After all the fCLK cycles are
counted, the data for 128 conversions is suppressed
by the ADS1174/78 to allow output of fully-settled
data. In SPI protocol, DRDY is held high during this
interval. In frame-sync protocol, DOUT is forced to
zero. The power supplies should be applied before
any analog or digital pin is driven.
The ADS1174/78 has three power supplies: AVDD,
DVDD, and IOVDD. AVDD is the analog supply that
powers the modulator, DVDD is the digital supply that
powers the digital core, and IOVDD is the digital I/O
power supply. The IOVDD and DVDD power supplies
can be tied together if desired. To achieve rated
performance, it is critical that the power supplies are
bypassed with 0.1μF and +10μF capacitors placed as
close as possible to the supply pins. A single 1μF
ceramic capacitor may be substituted in place of the
two capacitors.
AVDD
DVDD
IOVDD
3.5V Nom(1)
1V Nom(1)
1V Nom(1)
Internal Reset
CLK
218
fCLK
128
fDATA
DRDY
(SPI)
DOUT
(Frame-Sync)
Valid Data
NOTE: (1) The power-supply reset thresholds are approximate.
Figure 24. Power-Up Sequence
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BOUNDARY SCAN TEST[1:0] INPUTS
Therefore, if using boundary scan tests, the
ADS1174/78 digital I/O should connect to
a
The Boundary Scan test mode feature of the
ADS1174/78 allows continuity testing of the digital I/O
pins. In this mode, the normal functions of the digital
pins are disabled and routed to each other as pairs
through internal logic, as shown in Table 13. Note
that some of the digital input pins become outputs.
JTAG-compatible device. The analog input, power
supply, and ground pins remain connected as normal.
The test mode is engaged by the setting the pins
TEST[1:0] = 11. For normal converter operation, set
TEST[1:0] = 00.
VCOM OUTPUT
Table 13. Test Mode Pin Map (TEST[1:0] = 11)
The VCOM pin is an analog output of approximately
AVDD/2. This voltage may be used to set the
common-mode voltage of the input buffers. However,
the pin must be buffered. A 0.1μF capacitor to AGND
is recommended to reduce noise pick-up.
TEST MODE PIN MAP(1)
INPUT PINS
PWDN1
OUTPUT PINS
DOUT1
PWDN2
DOUT2
PWDN3
DOUT3
PWDN4
DOUT4
(2)
PWDN5
DOUT5(2)
DOUT6(2)
DOUT7(2)
DOUT8(2)
DIN
ADS1174/ADS1178
OPA350
(2)
PWDN6
VCOM » (AVDD/2)
0.1mF
(2)
PWDN7
(2)
PWDN8
MODE
NOTE: Buffer is required if VCOM is used for any purpose.
FORMAT0
FORMAT1
FORMAT2
CLKDIV
DRDY/FSYNC
SCLK
Figure 25. VCOM Output
(1) The CLK input does not have a test output; SYNC = 1 and is
an output.
(2) ADS1178 only.
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APPLICATION INFORMATION
5. Reference Inputs: It is recommended to use a
minimum 10μF tantalum with a 0.1μF ceramic
capacitor directly across the reference inputs,
VREFP and VREFN. The reference input should
be driven by a low-impedance source. For best
performance, the reference should have less than
3μVRMS in-band noise. For references with noise
higher than this, external reference filtering may
be necessary.
To obtain the specified performance from the
ADS1174/78, the following layout and component
guidelines should be considered.
1. Power Supplies: The device requires three
power supplies for operation: DVDD, IOVDD, and
AVDD. The range for DVDD is 1.65V to 1.95V;
the range of IOVDD is 1.65V to 3.6V; and AVDD
is restricted to 4.75V to 5.25V. For all supplies,
use a 10μF tantalum capacitor, bypassed with a
0.1μF ceramic capacitor, placed close to the
device pins. Alternatively, a single 10μF ceramic
capacitor can be used. The supplies should be
relatively free of noise and should not be shared
with devices that produce voltage spikes (such as
relays, LED display drivers, etc.). If a switching
power supply source is used, the voltage ripple
should be low (< 2mV) and the switching
frequency outside the passband of the converter.
The power supplies may be sequenced in any
order.
6. Analog Inputs: The analog input pins must be
driven differentially to achieve specified
performance.
A
true differential driver or
transformer (for ac applications) can be used for
this purpose. Route the analog inputs tracks
(AINP, AINN) as a pair from the buffer to the
converter using short, direct tracks and away
from digital tracks.
A 1nF to 10nF capacitor should be used directly
across the analog input pins, AINP and AINN. A
low-k dielectric (such as COG or film type) should
be used to maintain low THD. Capacitors from
each analog input to ground can be used. They
should be no larger than 1/10 the size of the
difference capacitor (typically 100pF) to preserve
the AC common-mode performance.
2. Ground Plane: A single ground plane connecting
both AGND and DGND pins can be used. If
separate digital and analog grounds are used,
connect the grounds together at the converter.
3. Digital Inputs: It is recommended to
source-terminate the digital inputs to the device
with 50Ω series resistors. The resistors should be
placed close to the driving end of the digital
source (oscillator, logic gates, DSP, etc.) This
placement helps to reduce ringing on the digital
lines, which may lead to degraded ADC
performance.
7. Component Placement: Place the power supply,
analog input, and reference input bypass
capacitors as close as possible to the device
pins. This layout is particularly important for the
small-value ceramic capacitors. Surface-mount
components are recommended to avoid the
higher inductance of leaded components.
4. Analog/Digital Circuits: Place analog circuitry
(input buffer, reference) and associated tracks
together, keeping them away from digital circuitry
(DSP, microcontroller, logic). Avoid crossing
digital tracks across analog tracks to reduce
noise coupling and crosstalk.
Figure 26 to Figure 28 illustrate basic connections
and interfaces that can be used with the
ADS1174/78.
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OPA1632
+3.3V
ADS1174
TMS320VC5509
AINP1
AINN1
IOVDD
DVDD (I/O)
Input1
Input2
Input3
Input4
2.2nF(2)
2.2nF(2)
2.2nF(2)
2.2nF(2)
10mF(1)
50W
CLK
CLKOUT (27MHz)
AINP2
AINN2
50W
DRDY/FSYNC
SCLK
50W
McBSP
PORT
50W
CVDD
(CORE)
AINP3
AINN3
+1.6V
DOUT1
DOUT2
DOUT3
DOUT4
SYNC
200MHz
AINP4
AINN4
+5V
PWDN1
PWDN2
PWDN3
PWDN4
I/O
AVDD
DVDD
+
10mF(1)
+1.8V
10mF(1)
20kW
100W
OPA350
VREFP
VREFN
1kW
100mF
100W
0.1mF(1)
+
+3.3V
10mF
0.1mF(1)
REF1004
CLKDIV
MODE
+
(27MHz clock input selected)
VCOM
0.1mF(1)
TEST0
TEST1
DIN
JTAG
Device(3)
(Low-Power, Frame-Sync, TDM,
and Fixed-Position data selected.)
47W
Buffered
VCOM
Output
FORMAT2
FORMAT1
OPA350
AGND
DGND
+3.3V
FORMAT0
(1) Indicates ceramic capacitors.
(2) Indicates COG ceramic capacitors.
(3) Optional. For boundary scan test, the ADS1174 digital I/O should connect to a JTAG-compatible device.
Figure 26. ADS1174 Basic Connection Drawing
1kW
1kW
1kW
249W
VIN
2.7nF(2)
+15V(1)
10nF(2)
+15V(1)
Buffered
VCOM
Output
Buffered
VCOM
Output
49.9W
49.9W
49.9W
49.9W
AINP
AINN
AINP
AINN
VOCM
VOCM
OPA1632
VIN
OPA1632
0.1mF
0.1mF
-15V(1)
-15V(1)
VO DIFF = 0.25 ´ VIN
VO COMM = VREF
10nF(2)
2.7nF(2)
1kW
249W
1kW
1kW
(1) Bypass with 10mF and 0.1mF capacitors.
NOTES:
(1) Bypass with 10mF and 0.1mF capacitors.
NOTES:
(2) 15nF for Low-Speed mode.
(2) 56nF for Low-Speed mode.
Figure 27. Basic Differential Input Signal Interface
Figure 28. Basic Single-Ended Input Signal
Interface
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SBAS373–OCTOBER 2007
PowerPAD THERMALLY-ENHANCED
PACKAGING
die pad to be attached to the PCB using standard
flow soldering techniques. This soldering allows
efficient attachment to the PCB and permits the board
structure to be used as a heat-sink for the package.
Using a thermal pad identical in size to the die pad
and vias connected to the PCB ground plane, the
board designer can now implement power packaging
without additional thermal hardware (for example,
external heat sinks) or the need for specialized
assembly instructions.
The PowerPAD concept is implemented in standard
epoxy resin package material. The integrated circuit
is attached to the leadframe die pad using thermally
conductive epoxy. The package is molded so that the
leadframe die pad is exposed at a surface of the
package. This exposure provides an extremely low
thermal resistance to the path between the IC
junction and the exterior case. The external surface
of the leadframe die pad is located on the printed
circuit board (PCB) side of the package, allowing the
Figure 29 illustrates a cross-section view of a
PowerPAD package.
Mold Compount
(Epoxy)
IC Die
Wire Bond
Wire Bond
Leadframe Die Pad
Exposed at Base of Package
Die Attach Epoxy
(thermally conductive)
Leadframe
Figure 29. Cross-Section View of a PowerPAD Thermally-Enhanced Package
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PowerPAD PCB Layout Considerations for the
ADS1174/78
The via connections to the thermal pad and internal
ground plane should be plated completely around the
hole, as opposed to the typical web or spoke thermal
relief connection. Plating entirely around the thermal
via provides the most efficient thermal connection to
the ground plane.
Figure 30 shows the recommended layer structure for
thermal management when using
a PowerPad
package on a 4-layer PCB design. Note that the
thermal pad is placed on both the top and bottom
sides of the board. The ground plane is used as the
heat-sink, while the power plane is thermally isolated
from the thermal vias.
Additional PowerPAD Package Information
Texas Instruments publishes the PowerPAD
Thermally Enhanced Package Application Report (TI
literature number SLMA002), available for download
at www.ti.com, which provides a more detailed
discussion of PowerPAD design and layout
considerations. Before attempting a board layout with
the ADS1174/78, it is recommended that the
hardware engineer and/or layout designer be familiar
with the information contained in this document.
Figure 31 shows the required thermal pad etch
pattern for the 64-lead HTQFP package used for the
ADS1174/78. Nine 13mil (0.33mm) thermal vias
plated with one ounce of copper are placed within the
thermal pad area for the purpose of connecting the
pad to the ground plane layer. The ground plane is
used as a heatsink in this application. It is very
important that the thermal via diameter be no larger
than 13mils in order to avoid solder wicking during
the reflow process. Solder wicking results in thermal
voids that reduce heat dissipation efficiency and
hamper heat flow away from the IC die.
Package
Thermal Pad
Component
Traces
13mils (0.33mm)
Component (top) Side
Ground Plane
Thermal Via
Power Plane
Thermal Isolation
(power plane only)
Solder (bottom) Side
Package
Thermal Pad
(bottom trace)
Figure 30. Recommended PCB Structure for a 4-Layer Board
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Package Outline
Thermal Pad
40mils (1mm)
40mils (1mm)
118mils (3mm)
316mils (8mm)
Thermal Via
13mils (0.33mm)
316mils (8mm)
Figure 31. Thermal Pad Etch and Via Pattern for the 64-Lead HTQFP Package
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
ADS1174IPAPR
ADS1174IPAPT
ADS1178IPAPR
ADS1178IPAPT
PREVIEW
PREVIEW
PREVIEW
PREVIEW
HTQFP
HTQFP
HTQFP
HTQFP
PAP
64
64
64
64
1000
250
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
PAP
PAP
1000
250
PAP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
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