ADC0834CIWMX [TI]
4-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO14, 0.300 INCH, PLASTIC, SOP-14;
| 型号： | ADC0834CIWMX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO14, 0.300 INCH, PLASTIC, SOP-14 |
| 文件： | 总13页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
AD0834 . . . N PACKAGE
(TOP VIEW)
• 8-Bit Resolution
• Easy Microprocessor Interface or Stand-
Alone Operation
V+
CS
V
DI
1
2
3
4
5
6
7
14
13
12
11
10
9
CC
• Operates Ratiometrically or With 5-V
Reference
CH0
CLK
• 4- or 8-Channel Multiplexer Options With
CH1
CH2
SARS
DO
Address Logic
• Shunt Regulator Allows Operation With
CH3
REF
High-Voltage Supplies
DGTL GND
ANLG GND
8
• Input Range 0 to 5 V With Single 5-V
ADC0838 . . . N PACKAGE
(TOP VIEW)
Supply
• Remote Operation With Serial Data Link
• Inputs and Outputs are Compatible With
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
V
CC
V+
CS
DI
CLK
SARS
DO
SE
REF
ANLG GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TTL and MOS
• Conversion Time of 32 µs at
f
= 250 kHz
clock
• Designed to Be Interchangeable With
National Semiconductor ADC0834 and
ADC0838
TOTAL UNADJUSTED ERROR
DEVICE
A SUFFIX
± 1 LSB
± 1 LSB
B SUFFIX
± 1/2 LSB
± 1/2 LSB
DGTL GND
ADC0834
ADC0838
ADC0838 . . . FN PACKAGE
(TOP VIEW)
description
These devices are 8-bit successive- approxima-
tion analog-to-digital converters, each with an
input-configurable
multichannel
multi-
3
2
1
20 19
18
CS
CH3
CH4
CH5
CH6
CH7
4
5
6
7
8
plexer and serial input/output. The serial input/
output is configured to interface with standard shift
registers or microprocessors. Detailed informa-
tion on interfacing with most popular microproces-
sors is readily available from the factory.
DI
17
16
15
14
CLK
SARS
DO
9 10 11 12 13
The ADC0834 (4-channel) and ADC0838
(8-channel) multiplexer is software configured
forsingle-ended or differential inputs as well as
pseudo-differential input assignments. The differ-
ential analog voltage input allows for common-
mode rejection or offset of the analog zero input
voltage value. In addition, the voltage reference
input can be adjusted to allow encoding any
smaller analog voltage span to the full 8 bits of
resolution.
The ADC0834AC, ADC0834BC, ADC0838AC, and ADC0838BC are characterized for operation from 0°C to
70°C. The ADC0834AI, ADC0834BI, ADC0838AI, and ADC0838BI are characterized for operation from –40°C
to 85°C.
Copyright 1986, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Start
Flip-Flop
CS
CLK
CS
CLK
SARS
DI
R
D
(see Note A)
S
R
5-Bit Shift Register
CLK
SELECT0 SELECT1 ODD\EVEN SGL\DIF START
ADC0838
Only
SE
To Internals
Circuits
CLK
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
ADC0834
S
R
Analog
MUX
Time
Delay
ADC0838
EN
CS
CS
Comparator
CS
R
CS
R
CS
EN
R
CLK
CLK
REF
SAR
Ladder
EOC
Logic
DO
9-Bit
Shift
Register
Bits 0–7
Bits 0–7
Bit 1
and
and
D
Decoder
Latch
To Internal
LSB
First
Circuits
MSB
First
V
CC
One
Shot
7 V
V +
7 V
NOTE A: For the ADC0834, DI is input directly to the D input of SELECT 1; SELECT 0 is forced to a high.
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
functional description
The ADC0834 and ADC0838 use a sample data comparator structure that converts differential analog inputs
by a successive-approximation routine. Operation of both devices is similar with the exception of SE, an analog
common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal
and is compared to ground (single-ended), to an adjacent input (differential), or to a common terminal
(pseudo-differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative
(–) polarity. If the signal input applied to the assigned positive terminal is less than the signal on the negative
terminal, the converter output is all zeros.
Channel selection and input configuration are under software control using a serial data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A particular input configuration is assigned during the multiplexer addressing sequence. The multiplexer
address is shifted into the converter through the data input (DI) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single-ended or differential. When the input is
differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel
pairs . For example, channel 0 and channel 1 may be selected as a differential pair. These channels cannot act
differentially with any other channel. In addition to selecting the differential mode, the polarity may also be
selected. Either channel of the channel pair may be designated as the negative or positive input.
The common input on the ADC0838 can be used for a pseudo-differential input. In this mode, the voltage on
the common input is considered to be the negative differential input for all channel inputs. This voltage can be
any reference potential common to all channel inputs. Each channel input can then be selected as the positive
differential input. This feature is useful when all analog circuits are biased to a potential other than ground.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversionprocess. Aclockinputisthenreceivedfromtheprocessor. Oneachlow-to-hightransitionoftheclock
input, the data on DI is clocked into the multiplexer address shift register. The first logic high on the input is the
start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of the clock
input, the start bit and assignment word are shifted through the shift register. When the start bit is shifted into
the start location of the multiplexer register, the input channel is selected and conversion starts. The SAR Status
output (SARS) goes high to indicate that a conversion is in progress, and DI to the multiplexer shift register is
disabled the duration of the conversion.
An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. The
data output DO comes out of the high-impedance state and provides a leading low for this one clock period of
multiplexer settling time. The SAR comparator compares successive outputs from the resistive ladder with the
incoming analog signal. The comparator output indicates whether the analog input is greater than or less than
the resistive ladder output. As the conversion proceeds, conversion data is simultaneously output from the DO
output pin, with the most significant bit (MSB) first.
After eight clock periods, the conversion is complete and the SARS output goes low.
The ADC0834 outputs the least-significant-bit-first data after the MSB-first data stream. If SE is held high on
the ADC0838, the value of the least significant bit (LSB) will remain on the data line. When SE is forced low,
the data is then clocked out as LSB-first data. (To output LSB first, SE must first go low, then the data stored
in the 9-bit shift register outputs LSB first.) When CS goes high, all internal registers are cleared. At this time
the output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low
transition followed by address information.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
functional description (continued)
DI and DO can be tied together and controlled by a bidirectional processor I/O bit received on a single wire.
This is possible because DI is only examined during the multiplexer addressing interval and DO is still in a
high-impedance state.
Detailed information on interfacing to most popular microprocessors is readily available from the factory.
sequence of operation
ADC0834
1
2
3
4
5
6
7
10
11
12
13
14
15
18
19
20
21
CLK
t
conv
t
su
CS
DI
t
su
+Sign
Bit
Select
CH Bit 1
Start
Bit SGL Odd
Don’t Care
DIF Even
1
Hi-Z
SARS
Max
Settling
Time
MSB-First Data
LSB-First Data
Hi-Z
Hi-Z
MSB
7
LSB
0
MSB
7
DO
6
2
1
1
2
6
ADC0834 MUX ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS
ODD/EVEN
CHANNEL NUMBER
SELECT BIT 1
O
1
2
3
SGL/DIF
+
–
L
L
L
L
L
L
+
–
–
+
L
H
L
–
+
H
H
H
+
H
H
H
H
L
L
+
L
H
L
+
H
H
+
H
H = high level, L = low level, – or + = polarity of selected input pin
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
sequence of operation
ADC0838
1
2
3
4
5
6
7
8
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
CLK
t
t
su
conv
CS
MUX
Addressing
t
SU
+
SEL SEL
Sign Bit1 Bit0
SGL Odd
DIF Even
1
1
0
Start
Bit
DI
Dont Care
0
HI-Z
HI-Z
SARS
SE
MUX Settling
Time
LSB-First Data
MSB-First Data
HI-Z
DO
HI-Z
LSB
1
MSB
7
MSB
7
6
2
0
1
2
3
4
5
6
SE Used to Control LSB First Data
SE
MUX Settling
Time
LSB-Held
LSB
MSB-First Data
LSB-First Data
MSB
7
DO
MSB
7
6
2
1
0
1
2
3
4
5
6
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
ADC0838 MUX ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS
SELECTED CHANNEL NUMBER
SELECT
0
1
–
1
2
3
COM
SGL/DIF
ODD/EVEN
1
L
0
L
0
+
2
+
3
4
+
5
6
+
–
+
7
L
L
L
L
L
H
L
–
+
L
L
H
H
L
–
+
L
L
H
L
–
+
L
H
H
H
H
L
–
+
+
L
L
H
L
–
+
L
H
H
L
–
+
L
H
L
H
H
H
H
H
H
H
H
–
–
–
–
–
–
–
–
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
+
L
H
L
+
H
H
+
H
+
H = high level, L = low level, – or + = polarity of selected input
absolute maximum ratings over recommended operating free-air temperature range (unless
otherwise noted)
Supply voltage, V
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
CC
Input voltage range: Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V
CC
Input current: V+ input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 mA
Any other input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
Total input current for package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Operating free-air temperature range: AC and BC suffixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
AI and BI suffixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260°C
NOTES: 1. All voltage values, except differential voltages, are with respect to the network ground terminal.
2. Internal zener diodes are connected from the V
input to ground and from the V+ input to ground. The breakdown voltage of each
CC
zener diode is approximately 7 V. One zener diode can be used as a shunt regulator and connects to V
through a regular diode.
CC
Whenthe voltage regulator powers the converter, this zener and regular diode combination ensures that the V
than the zener breakdown voltage. A series resist or is recommended to limit current into the V+ input.
input (6.4 V) is less
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
recommended operating conditions
MIN NOM MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5
6.3
CC
IH
High-level input voltage
V
Low-level input voltage
0.8
400
60
V
IL
f
Clock frequency
10
40
kHz
%
clock
Clock duty cycle (see Note 3)
Pulse duration, CS high
t
t
t
220
350
90
ns
ns
ns
wH(CS)
Setup time, CS low, SE low, or data valid before clock↑
Hold time, data valid after clock↑
su
h
AC and BC suffixes
Operating free-air temperature
0
70
85
T
A
°C
AI and BI suffixes
–40
NOTE 3: The clock duty cycle range ensures proper operation at all clock frequencies. If a clock frequency is used outside the recommended
duty cycle range, the minimum pulse duration (high or low) is 1 µs.
electrical characteristics over recommended range of operating free-air temperature,
V
= V+ = 5 V, f
= 250 kHz (unless otherwise noted)
CC
clock
digital section
AC, BC SUFFIX
AI, BI SUFFIX
†
PARAMETER
TEST CONDITIONS
UNIT
‡
TYP
‡
TYP
MIN
2.8
MAX MIN
MAX
V
V
V
V
V
V
V
V
V
= 4.75 V,
= 4.75 V,
= 5.25 V,
I
I
I
= –360 µA
= –10 µA
= 1.6 mA
2.4
CC
CC
CC
OH
OH
OH
V
V
High-levl output voltage
V
OH
4.6
4.5
Low-levl output voltage
0.34
1
0.4
1
V
OL
I
I
I
I
High-level input current
= 5 V
= 0
0.005
–0.005
–14
0.005
–0.005
–14
16
µA
µA
mA
mA
IH
IH
IL
Low-level input current
–1
–6.5
8
–1
IL
High-leveloutput(source)current
Low-level output (sink) current
T
A
T
A
= 25°C
= 25°C
= 25°C
= 25°C
–6.5
8
OH
OL
OH = 0,
= V
,
16
OL
CC
= 5 V,
= 0,
T
0.01
3
0.01
–0.01
5
3
High-impedance-state output
current (DO or SARS)
O
O
A
I
OZ
µA
T
A
–0.01
–3
–3
C
C
Input capacitance
Output capacitance
pF
pF
i
5
o
†
‡
All parameters are measured under open-loop conditions with zero common-mode input voltage (unless otherwise specified).
All typical values are at V = V+ = 5 V, T = 25°C.
CC
A
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
electrical characteristics over recommended range of operating free-air temperature,
V
= V + = 5 V, f
= 250 kHz (unless otherwise noted) (continued)
CC
clock
analog and converter section
†
‡
TYP
PARAMETER
TEST CONDITIONS
MIN
–0.05
to
MAX
UNIT
V
ICR
Common-mode input voltage range
See Note 3
V
V
CC
+0.05
On-channel
Off-channel
On-channel
Off–channel
V = 5 V
1
I
V = 0
I
V = 0
I
V = 5 V
I
–1
–1
1
I
Standby input current (see Note 4)
Input resistance to reference ladder
µA
kΩ
I(stdby)
r
1.3
2.4
5.9
i(REF)
total device
†
‡
PARAMETER
TEST CONDITIONS
I = 15 mA at V+ pin, See Note 2
MIN TYP
MAX
8.5
UNIT
V
V
Z
Internal zener diode breakdown voltage
Supply current
6.3
7
1
I
I
2.5
mA
CC
†
‡
All parameters are measured under open-loop conditions with zero common-mode input voltage.
All typical values are at V
= 5 V, V+ = 5 V, T = 25°C.
A
CC
NOTES: 4. Internal zener diodes are connected from the V
input to ground and from the V+ input to ground. The breakdown voltage of each
through a regular diode.
CC
zener diode is approximately 7 V. One zener diode can be used as a shunt regulator and connects to V
CC
Whenthe voltage regulator powers the converter, this zener and regular diode combination ensures that the V
than the zener breakdown voltage. A series resistor is recommended to limit current into the V+ input.
input (6.4 V) is less
CC
5. If channel IN– is more positive than channel IN+, the digital output code will be 0000 0000. Connected to each analog input are two
on-chip diodes that conduct forward current for analog input voltages one diode drop above V .Care must be taken during testing
CC
levels (4.5 V) because high-level analog input voltage (5 V) can, especially at high temperatures, cause this input diode
at low V
CC
to conduct and cause errors for analog input s that are near full-scale. As long as the analog voltage does not exceed the supply
voltagebymorethan50mV, theoutputcodewillbecorrect. Toachieveanabsolute0Vto5Vinputvoltagerangerequiresaminimum
V
CC
of 4.950 V for all variations of temperature and load.
6. Standby input currents are currents going into or out of the on or off channels when the A/D converter is not performing conversion
and the clock is in a high or low steady-state condition.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
operating characteristicsV+=5V, f
=250kHz, t =t =20ns, T =25°C (unless otherwise noted)
clock
r
f
A
AI, AC SUFFIX
BI, BC SUFFIX
MIN TYP MAX
PARAMETER
Supply-voltage variation error
Total unadjusted error (see Note 6)
Common-mode error
TEST CONDITIONS
UNIT
LSB
LSB
LSB
LSB
MIN
TYP
MAX
V
= 4.75 V to 5.25 V
= 5 V,
= MIN to MAX
±1/16
±1/4
±1/16
±1/16
±1/4
±1/2
±1/4
1
CC
V
T
ref
±1
A
Differential mode
= 5 V to internal I = 15 mA at V+ pin,
±1/16
±1/4
1
Change in zero-error from V
CC
I
V
zener diode operation (see Note 2)
= 5 V, V
open
CC
ref
Propagation delay time, output MSB-first data
650
250
125
1500
600
250
500
650 1500
t
t
t
C
= 100 pF
ns
ns
pd
L
data after CLK↓, (see Note 7)
Output disable time,
LSB-first data
250
125
600
250
500
C
C
= 10 pF, R = 10 kΩ
L
L
L
dos
conv
DO or SARS after CS↑
= 100 pF, R = 2 kΩ
L
Conversion time (multiplexer addressing
time not included)
clock
periods
8
8
†
All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the
appropriate value specified under recommended operating conditions.
NOTES:2. InternalzenerdiodesareconnectedfromtheV
inputtogroundandfromtheV+inputtoground. Thebreakdownvoltageofeachzener
through a regular diode. When
input (6.4 V) is less than
CC
diode is approximately 7 V. One zener diode can be used as a shunt regulator and connects to V
CC
the voltage regulator powers the converter, this zener and regular diode combination ensures that the V
the zener breakdown voltage. A series resistor is recommended to limit current into the V+ input.
6. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
CC
7. Themostsignificantbit(MSB)dataisoutputdirectlyfromthecomparatorandthereforerequiresadditionaldelaytoallowforcomparatorresponse
time.
PARAMETER MEASUREMENT INFORMATION
V
CC
CLK
CS
50%
50%
GND
t
su
t
su
V
CC
0.4 V
2 V
GND
t
h
t
h
V
CC
2 V
DI
0.4 V
0.4 V
GND
Figure 1. Data Input Timing
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
PARAMETER MEASUREMENT INFORMATION
V
CC
50%
50%
CLK
DO
GND
t
pd
t
pd
V
CC
50%
50%
GND
t
su
V
CC
50%
SE
GND
Figure 2. Data Output Timing
V
CC
Test
Point
S1
S2
R
L
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
t
r
t
r
V
V
CC
CC
90%
90%
10%
50%
CS
CS
50%
10%
GND
GND
t
t
dis
dis
V
–V
CC
CC
S1 open
S2 closed
90%
S1 open
S2 closed
DO and SARS
DO and SARS
10%
GND
GND
VOLTAGE WAVEFORMS
NOTE A: C includes probe and jig capacitance.
VOLTAGE WAVEFORMS
L
Figure 3. Output Disable Time Test Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
TYPICAL CHARACTERISTICS
UNADJUSTED OFFSET ERROR
vs
LINEARITY ERROR
vs
REFERENCE VOLTAGE
REFERENCE VOLTAGE
16
14
1.5
V
I(+)
= V
= 0 V
V
= 5 V
= 250 kHz
= 25°C
I(–)
CC
f
T
clock
A
1.25
12
1
10
8
0.75
6
4
0.5
0.25
2
0
0
0.01
0.1
1
10
0
1
2
3
4
5
V
ref
– Reference Voltage – V
V
ref –
Reference Voltage – V
Figure 4
Figure 5
LINEARITY ERROR
vs
LINEARITY ERROR
vs
FREE-AIR TEMPERATURE
CLOCK FREQUENCY
0.5
3
V
= 5 V
= 5 V
V
ref
clock
= 5 V
= 250 kHz
ref
V
CC
f
2.5
0.45
2
0.4
1.5
85°C
0.35
1
25°C
0.3
–40°C
0.5
0.25
0
–50
–25
0
25
50
75
100
0
100
200
300
400
500
600
T
A
– Free-Air Tempertature – °C
f
– Clock Frequency – kHz
clock
Figure 6
Figure 7
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
CLOCK FREQUENCY
1.5
1.5
f
= 250 kHz
clock
CS = High
V
T
A
= 5 V
= 25°C
CC
V
= 5.5 V
= 5 V
CC
1
V
CC
1
0.5
V
CC
= 4.5 V
0.5
–50
0
–25
0
25
50
75
100
0
100
200
300
400
500
T
A
– Free-Air Temperature — °C
f
– Clock Frequency – kHz
clock
Figure 8
Figure 9
OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
25
V
CC
= 5 V
20
15
10
5
I
(V = 5 V)
OL OL
–I = 0 V)
(V
OH OH
–I = 2.4 V)
(V
OH OH
I
(V
= 0.4 V)
0
OL OL
0
–50
–25
25
50
75
100
T
A
– Free-Air Temperature – °C
Figure 10
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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