ADC08351 [NSC]
8-Bit, 42 MSPS, 40 mW A/D Converter; 8位， 42 MSPS ， 40毫瓦的A / D转换器
| 型号： | ADC08351 |
| 厂家： | 
National Semiconductor |
| 描述： | 8-Bit, 42 MSPS, 40 mW A/D Converter |
| 文件： | 总15页 (文件大小：495K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2000
ADC08351
8-Bit, 42 MSPS, 40 mW A/D Converter
General Description
Features
n Low Input Capacitance
n Internal Sample-and-Hold Function
n Single +3V Operation
n Power Down Feature
n TRI-STATE® Outputs
The ADC08351 is an easy to use low power, low cost, small
size, 42 MSPS analog-to-digital converter that digitizes sig-
nals to 8 bits. The ADC08351 uses an unique architecture
that achieves 7.2 Effective Bits with a 4.4 MHz input and
42 MHz clock frequency and 6.8 Effective Bits with a 21 MHz
input and 42 MHz clock frequency. Output formatting is
straight binary coding.
Key Specifications
To minimize system cost and power consumption, the
ADC08351 requires minimal external components and in-
cludes input biasing to allow optional a.c. input signal cou-
pling. The user need only provide a +3V supply and a clock.
Many applications require no separate reference or driver
components.
n Resolution
8 Bits
42 MSPS (min)
7.2 Bits (typ)
n Maximum Sampling Frequency
@
n ENOB fCLK = 42 MHz, fIN = 4.4 MHz
n Guaranteed No Missing Codes
The excellent dc and ac characteristics of this device, to-
gether with its low power consumption and +3V single supply
operation, make it ideally suited for many video and imaging
applications, including use in portable equipment. Total
power consumption is reduced to less than 7 mW in the
power-down mode. Furthermore, the ADC08351 is resistant
to latch-up and the outputs are short-circuit proof.
n Power Consumption
40 mW (typ); 48 mW (max)
(Excluding Reference Current)
Applications
n Video Digitization
n Digital Still Cameras
n Set Top Boxes
n Digital Camcorders
n Communications
n Medical Imaging
n Personal Computer Video
n CCD Imaging
Fabricated on a 0.35 micron CMOS process, the ADC08351
is offered in TSSOP and is designed to operate over the
commercial temperature range of −20˚C to +85˚C.
n Electro-Optics
Pin Configuration
DS100895-1
Ordering Information
ADC08351CIMTC
ADC08351CIMTCX
TSSOP
TSSOP (tape & reel)
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation
DS100895
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ADC08351 Block Diagram
DS100895-2
Pin Descriptions and Equivalent Circuits
Pin
Symbol
Equivalent Circuit
Description
No.
Analog signal input. Conversion range is 0.5 VP-P to
0.68 VA.
17
VIN
Positive reference voltage input. Operating range of
this voltage is 0.75V to VA. This pin should be
bypassed with a 10 µF tantalum or aluminum
electrolytic capacitor and a 0.1 µF ceramic chip
capacitor.
14
VREF
CMOS/TTL compatible digital input that, when low,
enables the digital outputs of the ADC08351. When
high, the outputs are in a high impedance state.
1
OE
CMOS/TTL compatible digital clock input. VIN is
sampled on the falling edge of CLK input.
12
CLK
CMOS/TTL compatible digital input that, when high,
puts the ADC08351 into the power down mode,
where it consumes minimal power. When this pin is
low, the ADC08351 is in the normal operating
mode.
15
PD
Conversion data digital output pins. D0 is the LSB,
D7 is the MSB. Valid data is output just after the
rising edge of the CLK input. These pins are
enabled by bringing the OE pin low.
3 thru
10
D0–D7
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2
Pin Descriptions and Equivalent Circuits (Continued)
Pin
Symbol
Equivalent Circuit
Description
No.
Positive digital supply pin. Connect to a clean, quiet
voltage source of +3V. VA and VD should have a
common supply and be separately bypassed with a
10 µF tantalum or aluminum electrolytic capacitor
and a 0.1 µF ceramic chip capacitor. See Section
3.0 for more information.
11, 13
VD
The ground return for the digital supply. AGND and
DGND should be connected together close to the
ADC08351.
2, 20
16
DGND
Positive analog supply pin. Connected to a clean,
quiet voltage source of +3V. VA and VD should have
a common supply and be separately bypassed with
a 10 µF tantalum or aluminum electrolytic capacitor
and a 0.1 µF ceramic chip capacitor. See Section
3.0 for more information.
VA
The ground return for the analog supply. AGND and
DGND should be connected together close to the
ADC08351 package.
18, 19
AGND
3
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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Susceptibility (Note 5)
Human Body Model
4000V
200V
Machine Model
Soldering Temp., Infrared, 10 sec. (Note 6)
300˚C
Supply Voltage (VA, VD)
4.2V
Storage Temperature
−65˚C to +150˚C
Voltage on Any Input or
Output Pin
−0.3V to 4.2V
Operating Ratings (Notes 1, 2)
Ground Difference
(AGND–DGND)
Operating Temperature Range
Supply Voltage (VA, VD)
−20˚C TA ≤ +85˚C
±
100 mV
+2.7V to +3.6V
CLK, OE Voltage Range
−0.5 to (VA + 0.5V)
VD to DGND
Ground Difference
|DGND–AGND|
Digital Output Voltage (VOH, VOL
)
0V to 100 mV
±
±
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at TA = 25˚C
25 mA
50 mA
VIN Voltage Range (VP-P
)
0.5V to 0.68 VA
(Note 4)
Converter Electrical Characteristics
The following specifications apply for VA = VD = +3.0 VDC, VREF = 2.4V, VIN = 1.63 VP-P, OE = 0V, CL = 20 pF,
fCLK = 42 MHz, 50% duty cycle, unless otherwise specified.
Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Notes 7, 8)
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
Symbol
Parameter
Conditions
DC Accuracy
±
±
±
1.4
INL
Integral Non Linearity Error
Differential Non Linearity
0.7
0.6
LSB (max)
LSB (max)
LSB (min)
(max)
DNL
+1.3
−1.0
0
Missing Codes
EZ
Zero Scale Offset Error
Full Scale Offset Error
−17
−7
mV
EFS
mV
Video Accuracy
DP
DG
Differential Phase Error
Differential Gain Error
fCLK = 20 MHz, Video Ramp Input
fCLK = 20 MHz, Video Ramp Input
1.0
1.5
Degree
%
Analog Input and Reference Characteristics
(CLK LOW)
(CLK HIGH)
4
11
pF
pF
kΩ
MHz
V
CIN
VIN Input Capacitance
VIN = 1.5V + 0.7 Vrms
RIN
RIN Input Resistance
Full-Power Bandwidth
7.2
FPBW
120
0.735
VA
VREF
Reference Input Voltage
Reference Input Current
At pin 14
V
IREF
7.7
mA
Power Supply Characteristics
PD = Low
PD = High
10.5
1
mA
mA
IA
Analog Supply Current
Digital Supply Current
PD = Low, No Digital Output Load
PD = High
2.9
0.5
13.4
40.2
mA
ID
mA
Total Operating Current
Excluding Reference Current, VIN = 0 VDC
PD = Low (excluding reference current)
16
48
mA (max)
mW (max)
mW
Power Consumption (active)
<
Power Consumption (power
down)
7
PD = High (excluding reference current)
CLK, OE Digital Input Characteristics
VIH
VIL
IIH
Logical High Input Voltage
Logical Low Input Voltage
Logical High Input Current
Logic Low Input Current
Logic Input Capacitance
VD = VA = 3V
2.0
1.0
V (min)
V (max)
µA
VD = VA = 3V
VIH = VD = VA = 3.3V
VIL = 0V, VD = VA = 3.3V
10
−10
10
IIL
µA
CIN
pF
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4
Converter Electrical Characteristics (Continued)
The following specifications apply for VA = VD = +3.0 VDC, VREF = 2.4V, VIN = 1.63 VP-P, OE = 0V, CL = 20 pF,
fCLK = 42 MHz, 50% duty cycle, unless otherwise specified.
Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Notes 7, 8)
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
Symbol
Parameter
Conditions
Digital Output Characteristics
IOH High Level Output Current
IOL
VD = 2.7V, VOH = VD −0.5V
VD = 2.7V, OE = DGND, VOL = 0.4V
VD = 2.7V, IOH = −360 µA
−1.1
1.8
mA (min)
Low Level Output Current
High Level Output Voltage
Low Level Output Voltage
mA (min)
VOH
VOL
2.65
0.2
V
V
VD = 2.7V, IOL = 1.6 mA
IOZH
IOZL
,
±
TRI-STATE Output Current
OE = VD = 3.3V, VOH = 3.3V or VOL = 0V
10
µA
AC Electrical Characteristics
fC1
fC2
tOD
Maximum Conversion Rate
42
19
MHz (min)
MHz
Minimum Conversion Rate
Output Delay
2
CLK High to Data Valid
14
ns (max)
Clock
Cycles
Pipline Delay (Latency)
2.5
tDS
tOH
tEN
tDIS
Sampling (Aperture) Delay
Output Hold Time
CLK Low to Acquisition of Data
CLK High to Data Invalid
2
9
ns
ns
OE Low to Data Valid
OE High to High Z State
Loaded as in Figure 2
14
10
7.2
7.2
6.8
45
45
43
44
45
44
−57
−51
−46
57
54
49
ns
Loaded as in Figure 2
ns
fCLK = 30 MHz, fIN = 1 MHz
fCLK = 42 MHz, fIN = 4.4 MHz
fCLK = 42 MHz, fIN = 21 MHz
fCLK = 30 MHz, fIN = 1 MHz
fCLK = 42 MHz, fIN = 4.4 MHz
fCLK = 42 MHz, fIN = 21 MHz
fCLK = 30 MHz, fIN = 1 MHz
fCLK = 42 MHz, fIN = 4.4 MHz
fCLK = 42 MHz, fIN = 21 MHz
fCLK = 30 MHz, fIN = 1 MHz
fCLK = 42 MHz, fIN = 4.4 MHz
fCLK = 42 MHz, fIN = 21 MHz
fCLK = 30 MHz, fIN = 1 MHz
fCLK = 42 MHz, fIN = 4.4 MHz
fCLK = 42 MHz, fIN = 21 MHz
Bits
ENOB
SINAD
SNR
Effective Number of Bits
Signal-to-Noise & Distortion
Signal-to-Noise Ratio
Bits
6.1
38.5
41
Bits (min)
dB
dB
dB (min)
dB
dB
dB (min)
dB
THD
Total Harmonic Distortion
Spurious Free Dynamic Range
dB
−41
dB (min)
dB
SFDR
dB
41
dB (min)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DGND, or greater than V or V ), the current at that pin should
A
D
be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of
25 mA to two.
Note 4: The absolute maximum junction temperature (T max) for this device is 150˚C. The maximum allowable power dissipation is dictated by T max, the
J
J
junction-to-ambient thermal resistance (θ ), and the ambient temperature (T ), and can be calculated using the formula P MAX = (T max - T )/θ . For the 20-pin
JA
A
D
J
A
JA
TSSOP, θ is 135˚C/W, so P MAX = 926 mW at 25˚C and 481 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this
JA
D
device under normal operation will typically be about 68 mW (40 mW quiescent power + 23 mW reference ladder power + 5 mW due to 1 TTL loan on each digital
output). The values for maximum power dissipation listed above will be reached only when the ADC08351 is operated in a severe fault condition (e.g., when input
or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: All inputs are protected as shown below. Input voltage magnitudes up to 500 mV above the supply voltage or 500 mV below GND will not damage this device.
However, errors in the A/D conversion can occur if the input goes above V or below AGND by more than 300 mV. As an example, if V is 3.0 V , the full-scale
A
A
DC
input voltage must be ≤3.3 V
to ensure accurate conversions.
DC
5
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Converter Electrical Characteristics (Continued)
DS100895-6
Note 8: To guarantee accuracy, it is required that V and V be well bypassed. Each V and V pin must be decoupled with separate bypass capacitors.
A
D
A
D
Note 9: Typical figures are at T = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
J
Level).
Typical Performance Characteristics VA = VD = VD I/O = 3V, fCLK = 42 MHz, unless otherwise
specified
@
DNL 42 MSPS
DNL vs Sample Rate
DNL vs VA
DS100895-7
DS100895-10
DS100895-13
DS100895-8
DS100895-9
DNL vs Temperature
@
INL 42 MSPS
INL vs Sample Rate
DS100895-11
DS100895-12
INL vs VA
INL vs Temperature
SINAD and ENOB vs fIN
DS100895-14
DS100895-15
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6
Typical Performance Characteristics VA = VD = VD I/O = 3V, fCLK = 42 MHz, unless otherwise
specified (Continued)
SINAD and ENOB vs fCLK
SINAD and ENOB vs
Clock Duty Cycle
SNR vs fIN
DS100895-16
DS100895-18
DS100895-17
THD vs fIN
(ID) + (IA) vs fCLK
tOD vs VD
DS100895-19
DS100895-20
DS100895-21
@
Spectral Response 42 MSPS
DS100895-22
DIFFERENTIAL PHASE ERROR is the difference in the out-
put phase of a reconstructed small signal sine wave at two
different dc input levels.
Specification Definitions
ANALOG INPUT BANDWIDTH is a measure of the fre-
quency at which the reconstructed output fundamental drops
3 dB below its low frequency value for a full scale input. The
test is performed with fIN equal to 100 kHz plus integer mul-
tiples of fCLK. The input frequency at which the output is
−3 dB relative to the low frequency input signal is the full
power bandwidth.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD -
1.76)/6.02 and says that the converter is equivalent to a per-
fect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input. The test
is performed with fIN equal to 100KHz plus integer multiples
of fCLK The input frequency at which the output is —3 dB
relative to the low frequency input signal is the full power
bandwidth.
DIFFERENTIAL GAIN ERROR is the percentage difference
between the output amplitudes of a high frequency recon-
structed sine wave at two different dc input levels.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
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SIGNAL TO NOISE RATIO (SNR) is the ratio of the rms
value of the input signal to the rms value of the other spectral
components below one-half the sampling frequency, not in-
cluding harmonics or dc.
Specification Definitions (Continued)
FULL SCALE OFFSET ERROR is the difference between
the analog input voltage that just causes the output code to
transition to the full scale code (all 1’s in the case of the
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio of the rms value of the input signal to the
rms value of all of the other spectral components below half
the clock frequency, including harmonics but excluding dc.
ADC08351) and the ideal value of 11⁄
of VREF
2
LSB below the value
.
INTEGRAL NON-LINEARITY (INL) is a measure of the de-
viation of each individual code from a line drawn from zero
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
scale (1⁄
full scale (1⁄
2
LSB below the first code transition) through positive
LSB above the last code transition). The devia-
2
tion of any given code from this straight line is measured
from the center of that code value. The end point test method
is used.
TOTAL HARMONIC DISTORTION (THD) is the ratio of the
rms total of the first six harmonic components to the rms
value of the input signal.
OUTPUT DELAY is the time delay after the rising edge of
the input clock before the data update is present at the out-
put pins.
ZERO SCALE OFFSET ERROR is the difference between
OUTPUT HOLD TIME is the length of time that the output
data is valid after the rise of the input clock.
the analog input voltage that just causes the output code to
1
transition to the first code and the ideal value of
that transition.
⁄2 LSB for
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and the availability of that
conversion result at the output. New data is available at ev-
ery clock cycle, but the data lags the conversion by the pipe-
line delay.
SAMPLING (APERTURE) DELAY is that time required after
the fall of the clock input for the sampling switch to open. The
sample is effectively taken this amount of time after the fall of
the clock input.
Timing Diagram
DS100895-23
FIGURE 1. ADC08351 Timing Diagram
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8
Timing Diagram (Continued)
DS100895-24
FIGURE 2. tEN, tDIS Test Circuit
erably due to the quantization noise. However, the
Functional Description
ADC08351 will give adequate results in many applications
with signal levels down to about 0.5 VP-P (VREF = 0.735V).
Very good performance can be obtained with reference volt-
ages up to the supply voltage (VA = VREF = 3V, 2.04 VP-P).
The ADC08351 achieves 6.8 effective bits at 21 MHz input
frequency with 42 MHz clock frequency digitizing to eight bits
the analog signal at VIN that is within the nominal voltage
range of 0.5 VP-P to 0.68 VA.
As with all sampling ADCs, the opening and closing of the
switches associated with the sampling causes an output of
energy from the analog input, VIN. The reference ladder also
has switches associated with it, so the reference source
must be able to supply sufficient current to hold VREF steady.
Input voltages below 0.0665 times the reference voltage will
cause the output word to consist of all zeroes, while input
voltages above 3⁄
of the reference voltage will cause the out-
4
put word to consist of all ones. For example, with a VREF of
2.4V, input voltages below 160 mV will result in an output
word of all zeroes, while input voltages above 1.79V will re-
sult in an output word of all ones.
The analog input of the ADC08351 is self-biased with an
18 kΩ pull-up resistor to VREF and a 12 kΩ pull-down resistor
to AGND. This allows for either a.c. or d.c. coupling of the in-
put signal. These two resistors provide a convenient way to
ensure a signal that is less than full scale will be centered
within the input common mode range of the converter. How-
ever, the high values of these resistors and the energy com-
ing from this input means that performance will be improved
with d.c. coupling.
The output word rate is the same as the clock frequency.
Data is acquired at the falling edge of the clock and the digi-
tal equivalent of that data is available at the digital outputs
2.5 clock cycles plus tOD later. The ADC08351 will convert as
long as the clock signal is present at pin 12, but the data will
not appear at the outputs unless the OE pin 1 is low. The
digital outputs are in the high impedance state when the OE
pin or when the PD pin is high.
The driving circuit at the signal input must be able to sink and
source sufficient current at the signal frequency to prevent
distortion from being introduced at the input.
Applications Information
2.0 POWER SUPPLY CONSIDERATIONS
1.0 THE ADC REFERENCE AND THE ANALOG INPUT
A tantalum or aluminum electrolytic capacitor of 5 µF to
10 µF should be placed within a centimeter of each of the
A/D power pins, with a 0.1 µF ceramic chip capacitor placed
The capacitance seen at the input changes with the clock
level, appearing as 4 pF when the clock is low, and 11 pF
when the clock is high. Since a dynamic capacitance is more
difficult to drive than is a fixed capacitance, choose an ampli-
fier that can drive this type of load. The CLC409, CLC440,
LM6152, LM6154, LM6181 and LM6182 are good devices
for driving analog input of the ADC08351. Do not drive the in-
put beyond the supply rails.
within 1⁄
centimeter of each of the power pins. Leadless chip
2
capacitors are preferred because they provide lower lead in-
ductance than do their leaded counterparts.
While a single voltage source should be used for the analog
and digital supplies of the ADC08351, these supply pins
should be decoupled from each other to prevent any digital
noise from being coupled to the analog power pins. A ferrite
bead between the analog and digital supply pins would help
to isolate the two supplies.
The maximum peak-to-peak input level without clipping of
the reconstructed output is determined by the values of the
resistor string between VREF and AGND. The bottom of the
reference ladder has a voltage of 0.0665 times VREF, while
the top of the reference ladder has a voltage of 0.7468 times
The converter digital supply should not be the supply that is
used for other digital circuitry on the board. It should be the
same supply used for the A/D analog supply, decoupled from
the A/D analog supply pin, as described above. A common
analog supply should be used for both VA and VD, and each
of these pins should be separately bypassed with a 0.1 µF
ceramic capacitor and with low ESR a 10 µF capacitor.
VREF. The maximum peak-to-peak input level works out to
be about 68% of the value of VREF. The relationship between
the input peak-to-peak voltage and VREF is
As is the case with all high speed converters, the ADC08351
is sensitive to power supply noise. Accordingly, the noise on
We do not recommend opertaing with input levels below
1 VP-P because the signal-to-noise ratio will degrade consid-
9
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ADC08351 are required to meet data sheet limits. The ana-
log and digital grounds may be in the same layer, but should
be separated from each other and should never overlap
each other.
Applications Information (Continued)
the analog supply pin should be minimized, keeping it below
200 mVP-P at 100 kHz. Of course, higher frequency noise on
the power supply should be even more severely limited.
Capacitive coupling between the typically noisy digital
ground plane and the sensitive analog circuitry can lead to
poor performance that may seem impossible to isolate and
remedy. The solution is to keep the analog circuitry well
separated from the digital circuitry and from the digital
ground plane.
No pin should ever have a voltage on it that is in excess of
the supply voltages. This can be a problem upon application
of power to a circuit. Be sure that the supplies to circuits driv-
ing the CLK, OE, analog input and reference pins do not
come up any faster than does the voltage at the ADC08351
power pins.
3.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals is essen-
tial to ensure accurate conversion. Separate analog and
digital ground planes that are connected beneath the
DS100895-25
FIGURE 3. Layout example showing separate analog and digital ground planes connected below the ADC08351.
Generally, analog and digital lines should cross each other at
90 degrees to avoid getting digital noise into the analog path.
To maximize accuracy in video (high frequency) systems,
however, avoid crossing analog and digital lines altogether.
Furthermore, it is important to keep any clock lines isolated
from ALL other lines, including other digital lines. Even the
generally accepted 90 degree crossing should be avoided as
even a little coupling can cause problems at high frequen-
cies.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
ternal component (e.g., a filter capacitor) connected be-
tween the converter’s input and ground should be connected
to a very clean point in the analog ground plane.
Figure 3 gives an example of a suitable layout. All analog cir-
cuitry (input amplifiers, filters, reference components, etc.)
should be placed on or over the analog ground plane. All
digital circuitry and I/O lines should be placed over the digital
ground plane.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
All ground connections should have a low inductance path to
ground.
4.0 DYNAMIC PERFORMANCE
Be especially careful with the layout of inductors. Mutual in-
ductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, even with just a small part of their bodies beside each
other.
The ADC08351 is ac tested and its dynamic performance is
guaranteed. To meet the published specifications, the clock
source driving the CLK input must be free of jitter. For best
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10
5.0 TYPICAL APPLICATION CIRCUITS
Applications Information (Continued)
Figure 5 shows a simple interface for a low impedance
source located close to the converter. As discussed in Sec-
tion 1.0, the series capacitor is optional. Notice the isolation
of the ADC clock signal from the clock signals going else-
where in the system. The reference input of this circuit is
shown connected to the 3V supply.
ac performance, isolating the ADC clock from any digital cir-
cuitry should be done with adequate buffers, as with a clock
tree. See Figure 4.
It is good practice to keep the ADC clock line as short as
possible and to keep it well away from any other signals.
Other signals can introduce jitter into the clock signal. Even
lines with 90˚ crossings have capacitive coupling, so try to
avoid even these 90˚ crossings of the clock line.
Video ADCs tend to have input current transients that can
upset a driving source, causing distortion of the driving sig-
nal. The resistor at the ADC08351 input isolates the amplifi-
er’s output from the current transients at the input to the con-
verter.
When the signal source is not located close to the converter,
the signal should be buffered. Figure 6 shows an example of
an appropriate buffer. The amplifier provides a gain of two to
compensate for transmission losses.
Operational amplifiers have better linearity when they oper-
ate with gain, so the input is attenuated with the 68Ω and
30Ω resistors at the non-inverting input. The 330Ω resistor in
parallel with these two resistors provides for a 75Ω cable ter-
mination. Replacing this 330Ω resistor with one of 100Ω will
provide a 50Ω termination.
DS100895-26
FIGURE 4. Isolating the ADC Clock from Digital
Circuitry
The circuit shown has a nominal gain of two. You can provide
a gain adjustment by changing the 110Ω feedback resistor to
a 100Ω resistor in series with a 20Ω potentiometer.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have signifi-
cant impact upon system noise performance. The best logic
family to use in systems with A/D converters is one which
employs non-saturating transistor designs, or has low noise
characteristics, such as the 74HC(T) and 74AC(T)Q families.
The worst noise generators are logic families that draw the
largest supply current transients during clock or signal
edges, like the 74F and the 74AC(T) families. In general,
slower logic families, such as 74LS and 74HC(T) will pro-
duce less high frequency noise than do high speed logic
families, such as the 74F and 74AC(T) families.
The offset adjustment is used to bring the input signal within
the common mode range of the converter. If a fixed offset is
desired, the potentiometer and the 3.3k resistor may be re-
placed with a single resistor of 3k to 4k to the appropriate
supply. The resistor value and the supply polarity used will
depend upon the amount and polarity of offset needed.
The CLC409 shown in Figure 6 was chosen for a low cost
solution with good overall performance.
Figure 7 shows an inverting DC coupled circuit. The above
comments regarding Figure 6 generally apply to this circuit
as well.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
An effective way to control ground noise is by connecting the
analog and digital ground planes together beneath the ADC
with a copper trace that is narrow compared with the rest of
the ground plane. This narrowing beneath the converter pro-
vides a fairly high impedance to the high frequency compo-
nents of the digital switching currents, directing them away
from the analog pins. The relatively lower frequency analog
ground currents do not create a significant variation across
the impedance of this relatively narrow ground connection.
11
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Applications Information (Continued)
DS100895-27
FIGURE 5. AC Coupled Circuit for a Low Impedance Source Located Near the Converter
DS100895-28
FIGURE 6. Non-inverting Input Circuit for Remote Signal Source
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12
Applications Information (Continued)
DS100895-29
FIGURE 7. Inverting Circuit with Bias Adjust
ACCURATELY EVALUATING THE ADC
To ensure that the signal you are presenting to the ADC be-
ing evaluated is spectrally pure, use a bandpass filter be-
tween the signal generator and the ADC input. One such
possible filter is the elliptic filter shown in Figure 8.
If a signal that is spectrally impure is presented to the ADC,
the output from the ADC cannot be pure. Nearly all signal
generators in use today produce signals that are not spec-
trally pure enough to adequately evaluate present-day
ADCs. This is especially true at higher frequencies and at
high resolutions.
DS100895-31
FIGURE 8. This elliptic filter has a cutoff frequency of about 11MHz and is suitable for input frequencies of 5MHz to
10MHz. It should be driven by a generator of 75Ω source impedance and teminated with 75Ω. This termination may
be provided by the ADC evaluation circuit.
In addition to being used to eliminate undesired frequencies
from a desired signal, this filter can be used to filter a square
wave, reducing 3rd and higher harmonics to negligible lev-
els.
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 300 mV beyond the supply rails. That is, more
than 300 mV below the ground pins or 300 mV above the
supply pins. Exceeding these limits on even a transient basis
may cause faulty or erratic operation. It is not uncommon for
high speed digital circuits (e.g., 74F and 74AC devices) to
exhibit undershoot that goes more than a volt below ground
or above the power supply. Since these conditions are of
very short duration with very fast rise and fall times, they can
When evaluating dynamic performance of an ADC, repeat-
ability of measurements could be a problem unless coherent
sampling is used.
and ADC08351 evaluation system is available that can sim-
plify evaluation of thsi product.
13
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Using an inadequate amplifier to drive the analog input.
As explained in Section 2.0, the capacitance seen at the in-
put alternates between 4 pF and 11 pF with the clock. This
dynamic capacitance is more difficult to drive than a fixed ca-
pacitance, so care should be taken in choosing a driving de-
vice. The CLC409, CLC440, LM6152, LM6154, LM6181 and
LM6182 are good devices for driving the ADC08351. Also,
an amplifier with insufficient gain-bandwidth may limit the
overall frequency response of the overall circuit.
Applications Information (Continued)
inject noise into the system and may be difficult to detect with
an oscilloscope. A resistor of about 50Ω to 100Ω in series
with the offending digital input will usually eliminate the prob-
lem.
Care should be taken not to overdrive the inputs of the
ADC08351 (or any device) with a device that is powered
from supplies outside the range of the ADC08351 supply.
Such practice may lead to conversion inaccuracies and even
to device damage.
Using an operational amplifier in an insufficient gain
configuration to drive the analog input. Operational am-
plifiers, while some may be unity gain stable, generally ex-
hibit more distortion at low in-circuit gains than at higher
gains.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers have to charge for
each conversion, the more instantaneous digital current is
required from VD and DGND. These large charging current
spikes can couple into the analog section, degrading dy-
namic performance. While adequate bypassing and main-
taining separate analog and digital ground planes will reduce
this problem on the board, this coupling can still occur on the
ADC08351 die. Buffering the digital data outputs (with a
74ACQ541, for example) may be necessary if the data bus
to be driven is heavily loaded.
Using a clock source with excessive jitter, using exces-
sively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the sam-
pling interval to vary, causing excessive output noise and a
reduction in SNR performance. Simple gates with RC timing
is generally inadequate.
Not considering the timing relationships, especially tOD
.
Timing is always important and gets more critical with higher
speeds. If the output data is latched or looked at when that
data is in transition, you may see excessive noise and distor-
tion of the output signal.
Dynamic performance can also be improved by adding se-
ries resistors at each digital output, reducing the energy
coupled back into the converter output pins by limiting the
output slew rate. A reasonable value for these resistors is
about 47Ω.
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14
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead TSSOP
Order Number ADC08351CIMTC
NS Package Number MTC20
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相关型号：
ADC08351CIMTCX/NOPB
IC 1-CH 8-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PDSO20, TSSOP-20, Analog to Digital Converter
NSC
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