ADC0820CCWMX/NOPB [TI]
具有跟踪/保持功能的 8 位高速 µP 兼容型模数转换器 | DW | 20 | -40 to 85;
| 型号： | ADC0820CCWMX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有跟踪/保持功能的 8 位高速 µP 兼容型模数转换器 | DW | 20 | -40 to 85 转换器 模数转换器 |
| 文件： | 总25页 (文件大小：604K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC0820
ADC0820 8-Bit High Speed µP Compatible A/D Converter with Track/Hold
Function
Literature Number: SNAS529B
March 2004
ADC0820
8-Bit High Speed µP Compatible A/D Converter with
Track/Hold Function
General Description
Features
n Built-in track-and-hold function
n No missing codes
By using
a half-flash conversion technique, the 8-bit
ADC0820 CMOS A/D offers a 1.5 µs conversion time and
dissipates only 75 mW of power. The half-flash technique
consists of 32 comparators, a most significant 4-bit ADC and
a least significant 4-bit ADC.
n No external clocking
n Single supply—5 VDC
n Easy interface to all microprocessors, or operates
stand-alone
n Latched TRI-STATE output
n Logic inputs and outputs meet both MOS and T2L
voltage level specifications
The input to the ADC0820 is tracked and held by the input
sampling circuitry eliminating the need for an external
sample-and-hold for signals moving at less than 100 mV/µs.
For ease of interface to microprocessors, the ADC0820 has
been designed to appear as a memory location or I/O port
without the need for external interfacing logic.
n Operates ratiometrically or with any reference value
equal to or less than VCC
n 0V to 5V analog input voltage range with single 5V
supply
Key Specifications
n No zero or full-scale adjust required
n Overflow output available for cascading
n 0.3" standard width 20-pin DIP
n 20-pin molded chip carrier package
n 20-pin small outline package
j
Resolution
8 Bits
2.5 µs Max (RD Mode)
1.5 µs Max (WR-RD Mode)
75 mW Max
j
Conversion Time
j
j
Low Power
Total Unadjusted
Error
n 20-pin shrink small outline package (SSOP)
1
⁄2 LSB and 1 LSB
Connection and Functional Diagrams
Dual-In-Line, Small Outline
and SSOP Packages
Molded Chip Carrier
Package
00550133
00550101
Top View
© 2004 National Semiconductor Corporation
DS005501
www.national.com
Connection and Functional Diagrams (Continued)
00550102
FIGURE 1.
Ordering Information
Part Number
Total
Package
Temperature
Range
Unadjusted Error
ADC0820BCV
V20A—Molded Chip Carrier
0˚C to +70˚C
1
ADC0820BCWM
ADC0820BCN
ADC0820CCJ
ADC0820CCWM
ADC0820CIWM
ADC0820CCN
⁄2
LSB
M20B—Wide Body Small Outline
N20A—Molded DIP
0˚C to +70˚C
0˚C to +70˚C
−40˚C to +85˚C
0˚C to +70˚C
−40˚C to +85˚C
0˚C to +70˚C
J20A—Cerdip
M20B—Wide Body Small Outline
M20B—Wide Body Small Outline
N20A—Molded DIP
1 LSB
www.national.com
2
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Dual-In-Line Package (ceramic)
Surface Mount Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
300˚C
215˚C
220˚C
Supply Voltage (VCC
)
10V
Logic Control Inputs
−0.2V to VCC +0.2V
Operating Ratings (Notes 1, 2)
Voltage at Other Inputs and Output −0.2V to VCC +0.2V
Temperature Range
TMIN≤TA≤TMAX
−40˚C≤TA≤+85˚C
−40˚C≤TA≤+85˚C
0˚C≤TA≤70˚C
0˚C≤TA≤70˚C
0˚C≤TA≤70˚C
4.5V to 8V
Storage Temperature Range
Package Dissipation at TA = 25˚C
Input Current at Any Pin (Note 5)
Package Input Current (Note 5)
ESD Susceptability (Note 9)
−65˚C to +150˚C
875 mW
1 mA
ADC0820CCJ
ADC0820CIWM
ADC0820BCN, ADC0820CCN
ADC0820BCV
4 mA
900V
ADC0820BCWM, ADC0820CCWM
VCC Range
Lead Temp. (Soldering, 10 sec.)
Dual-In-Line Package (plastic)
260˚C
Converter Characteristics
The following specifications apply for RD mode (pin 7=0), VCC=5V, VREF(+)=5V,and VREF(−)=GND unless otherwise specified.
Boldface limits apply from TMIN to TMAX; all other limits TA=Tj=25˚C.
Parameter
Conditions
ADC0820BCN, ADC0820CCN
ADC0820BCV, ADC0820BCWM
ADC0820CCWM, ADC0820CIWM
Limit
Units
ADC0820CCJ
Typ
Tested Design
Typ
Tested
Limit
Design
Limit
(Note 6) Limit
Limit
(Note 6)
(Note 7) (Note 8)
(Note 7)
(Note 8)
Resolution
8
8
1
8
1
Bits
LSB
LSB
LSB
LSB
kΩ
Total Unadjusted
Error
ADC0820BCN, BCWM
ADC0820CCJ
⁄2
⁄
2
1
(Note 3)
ADC0820CCN, CCWM, CIWM
ADC0820CCMSA
1
1
1
1
Minimum Reference
Resistance
2.3
2.3
1.00
6
2.3
2.3
1.2
Maximum
5.3
6
kΩ
Reference
Resistance
Maximum VREF(+)
Input Voltage
Minimum VREF(−)
Input Voltage
Minimum VREF(+)
Input Voltage
Maximum VREF(−)
Input Voltage
Maximum VIN Input
Voltage
VCC
GND
VCC
VCC
V
V
V
V
V
V
GND
GND
VREF(−)
VREF(+)
VCC+0.1
GND−0.1
VREF(−)
VREF(+)
VCC+0.1
GND−0.1
VREF(−)
VREF(+)
VCC+0.1
GND−0.1
Minimum VIN Input
Voltage
Maximum Analog
Input Leakage
Current
CS =VCC
VIN=VCC
3
0.3
3
µA
µA
V
V
IN=GND
−3
1
−0.3
−3
1
1
Power Supply
Sensitivity
CC=5V 5%
1/16
⁄
4
1/16
⁄4
⁄
4
LSB
3
www.national.com
DC Electrical Characteristics
The following specifications apply for VCC=5V, unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other
limits TA=TJ=25˚C.
Parameter
Conditions
ADC0820BCN, ADC0820CCN
ADC0820BCV, ADC0820BCWM
ADC0820CCWM, ADC0820CIWM
Limit
Units
ADC0820CCJ
Typ
Tested
Limit
Design
Limit
Typ
Tested
Limit
(Note 7)
2.0
Design
Limit
(Note 8)
2.0
(Note 6)
(Note 6)
(Note 7) (Note 8)
V
IN(1), Logical “1”
VCC=5.25V
VCC=4.75V
CS , WR , RD
2.0
3.5
0.8
1.5
1
V
V
Input Voltage
IN(0), Logical “0”
Input Voltage
IN(1), Logical “1”
Input Current
Mode
3.5
3.5
V
CS , WR , RD
Mode
0.8
0.8
V
1.5
1.5
V
I
VIN(1)=5V; CS , RD
0.005
0.1
0.005
0.1
1
µA
µA
µA
µA
V
V
IN(1)=5V; WR
3
0.3
3
IN(1)=5V; Mode
50
200
−1
50
170
200
−1
IIN(0), Logical “0”
VIN(0)=0V; CS , RD , WR ,
Mode
−0.005
−0.005
Input Current
V
OUT(1), Logical “1” VCC=4.75V, IOUT=−360 µA;
2.4
4.5
0.4
2.8
4.6
2.4
4.5
0.4
V
V
V
Output Voltage
DB0–DB7, OFL , INT
VCC=4.75V, IOUT=−10 µA;
DB0–DB7, OFL , INT
VOUT(0), Logical “0” VCC=4.75V, IOUT=1.6 mA;
0.34
Output Voltage
IOUT, TRI-STATE
Output Current
DB0–DB7, OFL , INT , RDY
VOUT=5V; DB0–DB7, RDY
0.1
−0.1
−12
−9
3
−3
−6
−4.0
7
0.1
−0.1
−12
−9
0.3
−0.3
−7.2
−5.3
8.4
3
−3
−6
−4.0
7
µA
µA
V
OUT=0V; DB0–DB7, RDY
I
SOURCE, Output
Source Current
SINK, Output Sink
Current
VOUT=0V; DB0–DB7, OFL
INT
mA
mA
mA
I
VOUT=5V; DB0–DB7, OFL ,
INT , RDY
14
14
ICC, Supply Current CS =WR =RD =0
7.5
15
7.5
13
15
mA
AC Electrical Characteristics
The following specifications apply for VCC=5V, tr=tf=20 ns, VREF(+)=5V, VREF(−)=0V and TA=25˚C unless otherwise specified.
Typ
Tested
Limit
Design
Limit
Parameter
Conditions
Pin 7 = 0, Figure 2
(Note 6)
Units
(Note 7)
(Note 8)
2.5
t
t
CRD, Conversion Time for RD Mode
ACC0, Access Time (Delay from
1.6
µs
ns
Pin 7 = 0, Figure 2
tCRD+20
tCRD+50
Falling Edge of RD to Output Valid)
tCWR-RD, Conversion Time for
WR-RD Mode
Pin 7 = VCC; tWR = 600 ns,
1.52
µs
t
RD=600 ns; Figures 3, 4
t
t
t
WR, Write Time
Min
Max
Min
Pin 7 = VCC; Figures 3, 4
(Note 4) See Graph
600
600
ns
µs
ns
50
RD, Read Time
Pin 7 = VCC; Figures 3, 4
(Note 4) See Graph
<
ACC1, Access Time (Delay from
Pin 7 = VCC, tRD tI; Figure 3
Falling Edge of RD to Output Valid)
CL=15 pF
190
210
280
320
ns
ns
CL=100 pF
www.national.com
4
AC Electrical Characteristics (Continued)
The following specifications apply for VCC=5V, tr=tf=20 ns, VREF(+)=5V, VREF(−)=0V and TA=25˚C unless otherwise specified.
Typ
Tested
Limit
Design
Limit
Parameter
Conditions
(Note 6)
Units
(Note 7)
(Note 8)
>
t
ACC2, Access Time (Delay from
Pin 7 = VCC, tRD tI; Figure 4
Falling Edge of RD to Output Valid)
CL=15 pF
70
90
30
120
150
ns
ns
ns
CL=100 pF
t
ACC3, Access Time (Delay from
RPULLUP = 1k and CL = 15 pF
Rising Edge of RDY to Output
Valid)
tI, Internal Comparison Time
Pin 7=VCC; Figures 4, 5
CL=50 pF
800
100
1300
200
ns
ns
t
1H, t0H, TRI-STATE Control
RL=1k, CL=10 pF
(Delay from Rising Edge of RD to
Hi-Z State)
t
INTL, Delay from Rising Edge of
Pin 7 = VCC, CL= 50 pF
>
WR to Falling Edge of INT
tRD tI; Figure 4
tI
ns
ns
ns
<
tRD tI; Figure 3
tRD+200
125
tRD+290
225
t
INTH, Delay from Rising Edge of
RD to Rising Edge of INT
INTHWR, Delay from Rising Edge of
Figures 2, 3, 4
CL=50 pFc
t
Figure 5, CL=50 pF
175
270
ns
WR to Rising Edge of INT
tRDY, Delay from CS to RDY
Figure 2, CL=50 pF, Pin 7 =0
50
20
100
50
ns
ns
ns
t
t
ID, Delay from INT to Output Valid
RI, Delay from RD to INT
Figure 5
<
Pin 7=VCC, tRD tI
200
290
Figure 3
tP, Delay from End of Conversion
to Next Conversion
Figures 2, 3, 4, 5
(Note 4) See Graph
500
ns
Slew Rate, Tracking
0.1
45
5
V/µs
pF
CVIN, Analog Input Capacitance
COUT, Logic Output Capacitance
CIN, Logic Input Capacitance
pF
5
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified.
Note 3: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 4: Accuracy may degrade if t
or t
is shorter than the minimum value specified. See Accuracy vs. t
and Accuracy vs. t
graphs.
RD
WR
RD
WR
−
+
<
>
V ) the absolute value of current at that pin should be limited
Note 5: When the input voltage (V ) at any pin exceeds the power supply rails (V
V or V
IN
IN
IN
to 1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply boundaries with a 1 mA current limit to four.
Note 6: Typicals are at 25˚C and represent most likely parametric norm.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 9: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
5
www.national.com
TRI-STATE Test Circuits and Waveforms
t1H
00550103
00550104
t =20 ns
r
t0H
00550106
t =20 ns
r
00550105
Timing Diagrams
00550107
Note: On power-up the state of INT can be high or low.
FIGURE 2. RD Mode (Pin 7 is Low)
www.national.com
6
Timing Diagrams (Continued)
00550108
<
FIGURE 3. WR-RD Mode (Pin 7 is High and tRD tI)
00550109
>
FIGURE 4. WR-RD Mode (Pin 7 is High and tRD tI)
00550110
FIGURE 5. WR-RD Mode (Pin 7 is High)
Stand-Alone Operation
7
www.national.com
Typical Performance Characteristics
Logic Input Threshold Voltage vs. Supply Voltage
Conversion Time (RD Mode) vs. Temperature
00550134
00550135
Power Supply Current vs. Temperature
(not including reference ladder)
Accuracy vs. tWR
00550137
00550136
Accuracy vs. tRD
Accuracy vs. tp
00550139
00550138
www.national.com
8
Typical Performance Characteristics (Continued)
Accuracy vs. VREF [VREF=VREF(+)-VREF(-)]
tI, Internal Time Delay vs. Temperature
00550140
00550141
Output Current vs. Temperature
00550142
9
www.national.com
Description of Pin Functions
Pin Name
INT
Function
Pin Name
Function
9
WR-RD Mode
1
2
3
4
5
6
VIN
Analog input; range =GND≤VIN≤VCC
TRI-STATE data output—bit 0 (LSB)
TRI-STATE data output—bit 1
TRI-STATE data output—bit 2
TRI-STATE data output—bit 3
WR-RD Mode
INT going low indicates that the
conversion is completed and the data
result is in the output latch. INT will go
low, ∼800 ns (the preset internal time out,
tI) after the rising edge of WR (see Figure
4 ); or INT will go low after the falling
edge of RD , if RD goes low prior to the
800 ns time out (see Figure 3). INT is
reset by the rising edge of RD or CS (see
Figures 3, 4 ).
DB0
DB1
DB2
DB3
WR
/RDY
WR: With CS low, the conversion is
started on the falling edge of WR.
Approximately 800 ns (the preset internal
time out, tI) after the WR rising edge, the
result of the conversion will be strobed
into the output latch, provided that RD
does not occur prior to this time out (see
Figures 3, 4 ).
RD Mode
INT going low indicates that the
conversion is completed and the data
result is in the output latch. INT is reset by
the rising edge of RD or CS (see Figure
2 ).
RD Mode
RDY: This is an open drain output (no
internal pull-up device). RDY will go low
after the falling edge of CS; RDY will go
TRI-STATE when the result of the
conversion is strobed into the output latch.
It is used to simplify the interface to a
microprocessor system (see Figure 2 ).
Mode: Mode selection input—it is
internally tied to GND through a 50 µA
current source.
10 GND
Ground
11
V
REF(−) The bottom of resistor ladder, voltage
range: GND≤VREF(−)≤VREF(+) (Note 5)
REF(+) The top of resistor ladder, voltage range:
VREF(−)≤VREF(+)≤VCC (Note 5)
12
V
13 CS
CS must be low in order for the RD or
WR to be recognized by the converter.
TRI-STATE data output—bit 4
7
8
Mode
RD
14 DB4
15 DB5
16 DB6
17 DB7
18 OFL
TRI-STATE data output—bit 5
TRI-STATE data output—bit 6
RD Mode: When mode is low
TRI-STATE data output—bit 7 (MSB)
Overflow output—If the analog input is
higher than the VREF(+), OFL will be low
at the end of conversion. It can be used to
cascade 2 or more devices to have more
resolution (9, 10-bit). This output is always
active and does not go into TRI-STATE as
DB0–DB7 do.
WR-RD Mode: When mode is high
WR-RD Mode
With CS low, the TRI-STATE data outputs
(DB0-DB7) will be activated when RD
goes low (see Figure 5 ). RD can also be
used to increase the speed of the
converter by reading data prior to the
preset internal time out (tI, ∼800 ns). If this
is done, the data result transferred to
output latch is latched after the falling
edge of the RD (see Figures 3, 4 ).
RD Mode
19 NC
No connection
20 VCC
Power supply voltage
1.0 Functional Description
With CS low, the conversion will start with
RD going low, also RD will enable the
TRI-STATE data outputs at the completion
of the conversion. RDY going TRI-STATE
and INT going low indicates the
completion of the conversion (see Figure
2 ).
1.1 GENERAL OPERATION
The ADC0820 uses two 4-bit flash A/D converters to make
an 8-bit measurement (Figure 1 ). Each flash ADC is made
up of 15 comparators which compare the unknown input to a
reference ladder to get a 4-bit result. To take a full 8-bit
reading, one flash conversion is done to provide the 4 most
significant data bits (via the MS flash ADC). Driven by the 4
MSBs, an internal DAC recreates an analog approximation
of the input voltage. This analog signal is then subtracted
from the input, and the difference voltage is converted by a
second 4-bit flash ADC (the LS ADC), providing the 4 least
significant bits of the output data word.
The internal DAC is actually a subsection of the MS flash
converter. This is accomplished by using the same resistor
ladder for the A/D as well as for generating the DAC signal.
The DAC output is actually the tap on the resistor ladder
www.national.com
10
1.0 Functional Description (Continued)
which most closely approximates the analog input. In addi-
tion, the “sampled-data” comparators used in the ADC0820
provide the ability to compare the magnitudes of several
analog signals simultaneously, without using input summing
amplifiers. This is especially useful in the LS flash ADC,
where the signal to be converted is an analog difference.
00550112
1.2 THE SAMPLED-DATA COMPARATOR
• V = V
O
B
Each comparator in the ADC0820 consists of a CMOS in-
verter with a capacitively coupled input (Figures 6, 7 ). Ana-
log switches connect the two comparator inputs to the input
capacitor (C) and also connect the inverter’s input and out-
put. This device in effect now has one differential input pair.
A comparison requires two cycles, one for zeroing the com-
parator, and another for making the comparison.
• V on C = V1−V
B
• C = stray input node capacitor
S
• V = inverter input bias voltage
B
Zeroing Phase
FIGURE 6. Sampled-Data Comparator
In the first cycle, one input switch and the inverter’s feedback
switch (Figure 6 ) are closed. In this interval, C is charged to
the connected input (V1) less the inverter’s bias voltage (VB,
approximately 1.2V). In the second cycle (Figure 7 ), these
two switches are opened and the other (V2) input’s switch is
closed. The input capacitor now subtracts its stored voltage
from the second input and the difference is amplified by the
inverter’s open loop gain. The inverter’s input (VB') becomes
00550113
and the output will go high or low depending on the sign of
VB'−VB.
The actual circuitry used in the ADC0820 is a simple but
important expansion of the basic comparator described
above. By adding a second capacitor and another set of
switches to the input (Figure 8 ), the scheme can be ex-
panded to make dual differential comparisons. In this circuit,
the feedback switch and one input switch on each capacitor
(Z switches) are closed in the zeroing cycle. A comparison is
then made by connecting the second input on each capacitor
and opening all of the other switches (S switches). The
change in voltage at the inverter’s input, as a result of the
change in charge on each input capacitor, will now depend
on both input signal differences.
Compare Phase
FIGURE 7. Sampled-Data Comparator
00550145
00550114
FIGURE 8. ADC0820 Comparator (from MS Flash ADC)
1.3 ARCHITECTURE
input overrange. These two sets of comparators operate
alternately, with one group in its zeroing cycle while the other
is comparing.
In the ADC0820, one bank of 15 comparators is used in each
4-bit flash A/D converter (Figure 12 ). The MS (most signifi-
cant) flash ADC also has one additional comparator to detect
When a typical conversion is started, the WR line is brought
low. At this instant the MS comparators go from zeroing to
11
www.national.com
data which relate to interface timing. If an interrupt driven
scheme is desired, the user can wait for INT to go low before
reading the conversion result (Figure 10 ). INT will typically
go low 800 ns after WR’s rising edge. However, if a shorter
conversion time is desired, the processor need not wait for
INT and can exercise a read after only 600 ns (Figure 9 ). If
this is done, INT will immediately go low and data will appear
at the outputs.
1.0 Functional Description (Continued)
comparison mode (Figure 11 ). When WR is returned high
after at least 600 ns, the output from the first set of compara-
tors (the first flash) is decoded and latched. At this point the
two 4-bit converters change modes and the LS (least signifi-
cant) flash ADC enters its compare cycle. No less than 600
ns later, the RD line may be pulled low to latch the lower 4
data bits and finish the 8-bit conversion. When RD goes low,
the flash A/Ds change state once again in preparation for the
next conversion.
Figure 11 also outlines how the converter’s interface timing
relates to its analog input (VIN). In WR-RD mode, VIN is
measured while WR is low. In RD mode, sampling occurs
during the first 800 ns of RD. Because of the input connec-
tions to the ADC0820’s LS and MS comparators, the con-
verter has the ability to sample VIN at one instant (Section
2.4), despite the fact that two separate 4-bit conversions are
being done. More specifically, when WR is low the MS flash
is in compare mode (connected to VIN), and the LS flash is in
zero mode (also connected to VIN). Therefore both flash
ADCs sample VIN at the same time.
00550117
1.4 DIGITAL INTERFACE
<
FIGURE 9. WR-RD Mode (Pin 7 is High and tRD tI)
The ADC0820 has two basic interface modes which are
selected by strapping the MODE pin high or low.
RD Mode
With the MODE pin grounded, the converter is set to Read
mode. In this configuration, a complete conversion is done
by pulling RD low until output data appears. An INT line is
provided which goes low at the end of the conversion as well
as a RDY output which can be used to signal a processor
that the converter is busy or can also serve as a system
Transfer Acknowledge signal.
RD Mode (Pin 7 is Low)
00550118
>
FIGURE 10. WR-RD Mode (Pin 7 is High and tRD tI)
Stand-Alone
For stand-alone operation in WR-RD mode, CS and RD can
be tied low and a conversion can be started with WR. Data
will be valid approximately 800 ns following WR’s rising
edge.
WR-RD Mode (Pin 7 is High) Stand-Alone Operation
00550116
When in RD mode, the comparator phases are internally
triggered. At the falling edge of RD, the MS flash converter
goes from zero to compare mode and the LS ADC’s com-
parators enter their zero cycle. After 800 ns, data from the
MS flash is latched and the LS flash ADC enters compare
mode. Following another 800 ns, the lower 4 bits are recov-
ered.
WR then RD Mode
00550119
With the MODE pin tied high, the A/D will be set up for the
WR-RD mode. Here, a conversion is started with the WR
input; however, there are two options for reading the output
www.national.com
12
1.0 Functional Description (Continued)
00550120
Note: MS means most significant
LS means least significant
FIGURE 11. Operating Sequence (WR-RD Mode)
OTHER INTERFACE CONSIDERATIONS
Since the MS flash ADC enters its zeroing phase at the end
of a conversion (Section 1.3), a new conversion cannot be
started until this phase is complete. The minimum spec for
this time (tP, Figures 2, 3, 4, 5 ) is 500 ns.
In order to maintain conversion accuracy, WR has a maxi-
mum width spec of 50 µs. When the MS flash ADC’s
sampled-data comparators (Section 1.2) are in comparison
mode (WR is low), the input capacitors (C, Figure 8 ) must
hold their charge. Switch leakage and inverter bias current
can cause errors if the comparator is left in this phase for too
long.
13
www.national.com
Detailed Block Diagram
00550115
FIGURE 12.
www.national.com
14
The equivalent input circuit of the ADC0820 is shown in
Figure 14. When a conversion starts (WR low, WR-RD
mode), all input switches close, connecting VIN to thirty-one
1 pF capacitors. Although the two 4-bit flash circuits are not
both in their compare cycle at the same time, VIN still sees all
input capacitors at once. This is because the MS flash
converter is connected to the input during its compare inter-
val and the LS flash is connected to the input during its
zeroing phase (Section 1.3). In other words, the LS ADC
uses VIN as its zero-phase input.
2.0 Analog Considerations
2.1 REFERENCE AND INPUT
The two VREF inputs of the ADC0820 are fully differential and
define the zero to full-scale input range of the A to D con-
verter. This allows the designer to easily vary the span of the
analog input since this range will be equivalent to the voltage
difference between VIN(+) and VIN(−). By reducing
VREF(VREF=VREF(+)−VREF(−)) to less than 5V, the sensitivity
of the converter can be increased (i.e., if VREF=2V then 1
LSB=7.8 mV). The input/reference arrangement also facili-
tates ratiometric operation and in many cases the chip power
supply can be used for transducer power as well as the VREF
source.
The input capacitors must charge to the input voltage
through the on resistance of the analog switches (about 5 kΩ
to 10 kΩ). In addition, about 12 pF of input stray capacitance
must also be charged. For large source resistances, the
analog input can be modeled as an RC network as shown in
Figure 15. As RS increases, it will take longer for the input
capacitance to charge.
This reference flexibility lets the input span not only be varied
but also offset from zero. The voltage at VREF(−) sets the
input level which produces a digital output of all zeroes.
Though VIN is not itself differential, the reference design
affords nearly differential-input capability for most measure-
ment applications. Figure 13 shows some of the configura-
tions that are possible.
In RD mode, the input switches are closed for approximately
800 ns at the start of the conversion. In WR-RD mode, the
time that the switches are closed to allow this charging is the
time that WR is low. Since other factors force this time to be
at least 600 ns, input time constants of 100 ns can be
accommodated without special consideration. Typical total
input capacitance values of 45 pF allow RS to be 1.5 kΩ
without lengthening WR to give VIN more time to settle.
2.2 INPUT CURRENT
Due to the unique conversion techniques employed by the
ADC0820, the analog input behaves somewhat differently
than in conventional devices. The A/D’s sampled-data com-
parators take varying amounts of input current depending on
which cycle the conversion is in.
External Reference 2.5V Full-Scale
Power Supply as Reference
Input Not Referred to GND
00550121
00550122
00550123
FIGURE 13. Analog Input Options
15
www.national.com
occur. The comparators’ outputs are not latched while WR is
low, so at least 600 ns will be provided to charge the ADC’s
input capacitance. It is therefore not necessary to filter out
these transients by putting an external cap on the VIN termi-
nal.
2.0 Analog Considerations (Continued)
2.4 INHERENT SAMPLE-HOLD
Another benefit of the ADC0820’s input mechanism is its
ability to measure a variety of high speed signals without the
help of an external sample-and-hold. In a conventional SAR
type converter, regardless of its speed, the input must re-
1
main at least
⁄2 LSB stable throughout the conversion pro-
cess if full accuracy is to be maintained. Consequently, for
many high speed signals, this signal must be externally
sampled, and held stationary during the conversion.
Sampled-data comparators, by nature of their input switch-
ing, already accomplish this function to a large degree (Sec-
tion 1.2). Although the conversion time for the ADC0820 is
1
1.5 µs, the time through which VIN must be ⁄
2
LSB stable is
00550124
much smaller. Since the MS flash ADC uses VIN as its
“compare” input and the LS ADC uses VIN as its “zero” input,
the ADC0820 only “samples” VIN when WR is low (Sections
1.3 and 2.2). Even though the two flashes are not done
simultaneously, the analog signal is measured at one instant.
The value of VIN approximately 100 ns after the rising edge
of WR (100 ns due to internal logic prop delay) will be the
measured value.
FIGURE 14.
Input signals with slew rates typically below 100 mV/µs can
be converted without error. However, because of the input
time constants, and charge injection through the opened
comparator input switches, faster signals may cause errors.
Still, the ADC0820’s loss in accuracy for a given increase in
signal slope is far less than what would be witnessed in a
conventional successive approximation device. An SAR type
converter with a conversion time as fast as 1 µs would still
not be able to measure a 5V 1 kHz sine wave without the aid
of an external sample-and-hold. The ADC0820, with no such
help, can typically measure 5V, 7 kHz waveforms.
00550125
FIGURE 15.
2.3 INPUT FILTERING
It should be made clear that transients in the analog input
signal, caused by charging current flowing into VIN, will not
degrade the A/D’s performance in most cases. In effect the
ADC0820 does not “look” at the input when these transients
www.national.com
16
3.0 Typical Applications
8-Bit Resolution Configuration
00550126
9-Bit Resolution Configuration
00550127
17
www.national.com
3.0 Typical Applications (Continued)
Multiple Input Channels
Telecom A/D Converter
00550129
00550128
•
•
•
VIN=3 kHz max 4VP
No track-and-hold needed
Low power consumption
8-Bit 2-Quadrant Analog Multiplier
00550130
www.national.com
18
3.0 Typical Applications (Continued)
Fast Infinite Sample-and-Hold
00550131
19
www.national.com
www.national.com
20
Physical Dimensions inches (millimeters) unless otherwise noted
Hermetic Dual-In-Line Package (J)
Order Number ADC0820CCJ
NS Package Number J20A
SO Package (M)
Order Number ADC0820BCWM, ADC0820CCWM or ADC0820CIWM
NS Package Number M20B
21
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number ADC0820BCN or ADC0820CCN
NS Package Number N20A
Molded Chip Carrier Package (V)
Order Number ADC0820BCV
NS Package Number V20A
www.national.com
22
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification
(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
National Semiconductor
Americas Customer
Support Center
National Semiconductor
Europe Customer Support Center
Fax: +49 (0) 180-530 85 86
National Semiconductor
Asia Pacific Customer
Support Center
National Semiconductor
Japan Customer Support Center
Fax: 81-3-5639-7507
Email: new.feedback@nsc.com
Tel: 1-800-272-9959
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
Email: ap.support@nsc.com
Email: jpn.feedback@nsc.com
Tel: 81-3-5639-7560
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Audio
Applications
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
Medical
Security
Logic
Space, Avionics and Defense www.ti.com/space-avionics-defense
Transportation and Automotive www.ti.com/automotive
Power Mgmt
Microcontrollers
RFID
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明