ADC0820CNEN [NXP]
8-Bit, high-speed, mP-compatible A/D converter with track/hold function; 8位，高速， MP-兼容A / D转换器，采样/保持功能
| 型号： | ADC0820CNEN |
| 厂家： | 
NXP |
| 描述： | 8-Bit, high-speed, mP-compatible A/D converter with track/hold function |
| 文件： | 总14页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter
with track/hold function
ADC0820
DESCRIPTION
PIN CONFIGURATION
By using a half-flash conversion technique, the 8-bit ADC0820
CMOS A/D offers a 1.5µs conversion time while dissipating a
maximum 75mW of power. The half-flash technique consists of 31
comparators, a most significant 4-bit ADC and a least significant
4-bit ADC.
D, F, N Packages
V
1
2
20
19
18
17
16
15
14
13
12
11
V
DD
IN
DB0
NC
3
DB1
DB2
OFL
The input to the ADC0820 is tracked and held by the input sampling
circuitry, eliminating the need for an external sample-and-hold for
signals slewing at less than 100mV/µs.
4
DB7
DB6
5
DB3
WR/RDY
DB5
6
For ease of interface to microprocessors, the ADC0820 has been
designed to appear as a memory location or I/O port without the
need for external interfacing logic.
MODE
RD
DB4
CS
7
8
9
V
(+)
(–)
INT
REF
10
V
REF
GND
FEATURES
TOP VIEW
• Built-in track-and-hold function
• No missing codes
• No external clocking
APPLICATIONS
• Single supply—5V
DC
• Microprocessor-based monitoring and control systems
• Transducer/µP interface
• Process control
• Easy interface to all microprocessors, or operates stand-alone
• Latched 3-State outputs
• Logic inputs and outputs meet both MOS and TTL voltage level
specifications
• Logic analyzers
• Operates ratiometrically or with any reference value equal to or
• Test and measurement
less than V
DD
• 0V to 5V analog input voltage range with single 5V supply
• No zero- or full-scale adjust required
• Overflow output available for cascading
• 0.3″ standard width 20-pin DIP
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
0 to +70°C
ORDER CODE
ADC0820CNEN
ADC0820CNED
DWG #
0408B
1021B
20-Pin Plastic Dual In-Line Package (DIP)
20-Pin Plastic Small Outline (SO) package
0 to +70°C
568
August 31, 1994
853-1631 13721
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with
track/hold function
ADC0820
BLOCK DIAGRAM
OFL
DB7
DB6
DB5
V
(+)
OFL
4–BIT
FLASG
ADC
REF
(4MSBs)
DB4
V
V
(–)
(+)
REF
REF
V
IN
OUTPUT
LATCH
AND
THREE–STATE
BUFFERS
–
+
4–BIT
DAC
∑
V
(–)
REF
V
REF
16
DB3
DB2
DB1
DB0
(+)
4–BIT
FLASG
ADC
(4LSBs)
V
(–)
REF
INT
TIMING AND CONTROL CIRCUITRY
MODE
WR/RDY
CS
RD
PIN DESCRIPTION
PIN NO SYMBOL
DESCRIPTION
1
2
3
4
5
6
V
Analog input; range=GND≤V ≤V
IN DD
IN
DB0
3-state data output—Bit 0 (LSB)
3-state data output—Bit 1
3-state data output—Bit 2
3-state data output—Bit 3
WR-RD Mode
DB1
DB2
DB3
WR/RDY
WR: With CS Low, the conversion is started on the falling edge of WR. Approximately 800ns (the preset internal time
out, t ) after the WR rising edge, the result of the conversion will be strobed into the output latch, provided that RD
I
does not occur prior to this time out (see Figures 3a and 3b).
RD Mode
RDY: This is an open-drain output (no internal pull-up device). RDY will go Low after the falling edge of CS; RDY will
go 3-State when the result of the conversion is strobed into the output latch. It is used to simplify the interface to a
microprocessor system (see Figure 1).
7
8
Mode
RD
Mode: Mode selection input—it is internally tied to GND through a 30µA current source.
RD Mode: When mode is Low.
WR-RD Mode: When mode is High.
WR-RD Mode
With CS Low, the 3-State data outputs (DB0-DB7) will be activated when RD goes Low. RD can also be used to
increase the speed of the converter by reading data prior to the preset internal time out (T ~ 800ns). If this is done,
I
the data result transferred to output latch is latched after the falling edge of the RD (see Figures 3a and 3b).
RD Mode
With CS Low, the conversion will start with RD going Low; also, RD will enable the 3-State data outputs at the
completion of the conversion. RDY going 3-State and INT going Low indicate the completion of the conversion (see
Figure 1).
9
INT
WR-RD Mode
INT going Low indicates that the conversion is completed and the data result is in the output latch. INT will go
Low ~ 800ns (the preset internal time out, t ) after the rising edge of WR (see Figure 3a); or INT will go Low after
I
the falling edge of RD, if RD goes Low prior to the 800ns time out (see Figure 3b). INT is reset by the rising edge of
RD or CS (see Figures 3a and 3b).
569
August 31, 1994
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with
track/hold function
ADC0820
PIN DESCRIPTION (Continued)
PIN NO SYMBOL
DESCRIPTION
RD Mode
INT going Low indicates that the conversion is completed and the data result is in the output latch. INT is reset by
the rising edge of RD or CS (see Figure 1).
10
11
12
13
14
15
16
17
18
GND
Ground
V
REF
V
REF
(-)
The bottom of resistor ladder, voltage range: GND≤V
(-)≤V
(+)
REF
REF
(+)
The top of resistor ladder, voltage range: V
(-)≤V
(+)≤V
.
REF
REF
DD
CS
CS must be Low in order for the RD or WR to be recognized by the converter.
3-State data output—Bit 4
DB4
DB5
DB6
DB7
OFL
3-State data output—Bit 5
3-State data output—Bit 6
3-State data output—Bit 7 (MSB)
Overflow output—if the analog input is higher than the V
(+)- LSB, OFL will be low at the end of conversion. It can
REF
be used to cascade 2 or more devices to have more resolution (9, 10-bit). It is always active and never becomes
3-state.
19
20
NC
No connection
V
DD
Power supply voltage
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
V
V
Supply voltage
7
DD
Logic control inputs
-0.2 to V +0.2
V
DD
Voltage at other inputs and output
Storage temperature range
-0.2 to V +0.2
V
DD
T
STG
-65 to +150
°C
3
Maximum power dissipation
P
D
T =25°C(still-air)
A
N package
1690
1390
300
mW
mW
°C
D package
T
SOLD
Lead temperature (soldering, 10sec)
Operating ambient temperature range
ADC0820CNEN/CNED
T
A
T
≤T ≤T
MIN A MAX
0 to +70
°C
NOTES:
1. Absolute Maximum Ratings are those values beyond which the life of the device may be impaired.
2. All voltages are measured with respect to GND, unless otherwise specified.
3. Derate above 25°C at the following rates:
N package at 13.5mW/°C
D package at 11.1mW/°C
570
August 31, 1994
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with
track/hold function
ADC0820
DC ELECTRICAL CHARACTERISTICS
RD mode (Pin 7=0), V =5V, V
(+)=5V, and V
(-)=GND, unless otherwise specified. Limits apply from T
to T
.
DD
REF
REF
MIN
MAX
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
UNIT
Max
3
Typ
Resolution
8
8
8
±1
4
bits
LSB
kΩ
V
1
Unadjusted error
ADC0820C
R
Reference resistance
1
1.6
REF
REF
REF
IN
5
V
V
V
(+)
(-)
Input voltage
V
(-)
V
DD
REF
Input voltage
GND
V
REF
(+)
V
5
Input voltage
GND-0.1
V
DD
+0.1
V
CS=V
DD
Maximum analog input leakage current
V
IN
=V
DD
-3
3
µA
V
IN
=GND
Power supply sensitivity
Logical “1” input voltage
V
=5V±5%
±1/16
±1/4
LSB
V
DD
CS, WR, RD
2.0
3.5
V
DD
V
DD
V
V
V
V
=5.25V
=4.75V
IN(1)
DD
Mode
CS, WR, RD
Mode
GND
GND
0.8
1.5
1
Logical “0” input voltage
V
IN(0)
DD
V
=5V; CS, RD
IN(1)
I
I
Logical “1” input current
Logical “0” input current
V
=5V; WR
3
µA
µA
IN(1)
IN(1)
V
IN(1)
=5V; Mode
30
4.6
200
V
=0V; CS, RD, WR, Mode
-1
IN(0)
IN(0)
V
DD
=4.75V, I
=-360µA;
OUT
2.4
DB0-DB7, OFL, INT
=4.75V, I =-10µA
V
V
Logical “1” output voltage
V
OUT(1)
V
4.5
4.74
DD
OUT
DB0-DB7, OFL, INT
V
=4.75V, I =1.6mA;
DD
OUT
Logical “0” output voltage
3-state output current
0.2
0.4
3
V
OUT(0)
DB0-DB7, OFL, INT, RDY
V
=5V; DB0-DB7, RDY
OUT
I
µA
OZ
V
=0V; DB0-DB7, RDY
-3
6
OUT
V
=0V, DB0-DB7, OFL
INT
12
OUT
I
Output source current
mA
SOURCE
4.5
7
8
20
6
I
I
Output sink current
Supply current
Range
V
=5V; DB0-DB7, OFL, INT, RDY
CS=WR=RD=0
mA
mA
V
SINK
OUT
15
DD
V
4.5
5.5
DD
571
August 31, 1994
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with
track/hold function
ADC0820
AC ELECTRICAL CHARACTERISTICS
V
DD
= 5V, t = t = 20ns, V
= 5V, V
= 0V, and T = 25°C, unless otherwise specified.
R
F
REF(+)
REF(-)
A
4
LIMITS
SYMBOL
PARAMETER
Conversion time for RD mode
TEST CONDITIONS
UNIT
Max
3
Min
Typ
t
t
Mode=0, Figure 1
1.6
2.5
µs
CRD
Access time (delay from falling edge of
RD to output valid)
Mode=0, Figure 1
Mode=V , t =600ns, t =600ns;
t
+20
t
+50
ns
ACCO
CRD
CRD
DD WR
RD
t
Conversion time for WR-RD mode
1.52
50
µs
CWR-RD
Figures 3a and 3b
Min
600
600
ns
µs
ns
2
t
t
Write time
Max
Mode=V , Figures 3a and 3b
WR
DD
2
Read time
Min
Mode=V , Figures 3a and 3b
DD
RD
Mode=V , t <t ;
DD RD
I
190
280
320
120
150
1300
Access time (delay from falling edge of
RD t o output valid)
Figure 3b, C =15pF
t
ns
L
ACC1
ACC2
C =100pF
L
210
70
Access time (delay from falling edge of
RD t o output valid)
Mode=V , t >t ;
DD RD I
t
ns
ns
ns
Figure 3a, C =15pF
L
C =100pF
L
90
Mode=V
;
DD
t
t
Internal comparison time
800
I
Figures 2 and 3a, C =50pF
L
Three-state control (delay from rising
edge of RD to Hi-Z state)
, t
R =1kΩ, C =10pF
100
200
ns
1H 0H
L
L
Mode=V , C =50pF
DD
L
Delay from rising edge of WR to falling
edge of INT
t
t
t
>t ; Figure 3a
<t ; Figure 3b
I
t
I
ns
ns
INTL
RD
RD
I
t
+200
t
+290
RD
RD
Delay from rising edge of RD to rising
edge of INT
Figures 1, 3a, and 3b,
C =50pF
t
t
125
175
225
ns
ns
INTH
L
Delay from rising edge of WR to rising
edge of INT
Figure 2, C =50pF
270
INTHWR
L
t
t
Delay from CS to RDY
Figure 1, C =50pF, Mode=0
50
20
100
50
ns
ns
RDY
L
Delay from INT to output valid
Figure 2
ID
Mode=V , t <t ;
DD RD
I
t
Delay from RD to INT
200
290
ns
ns
RI
P
Figure 3b
Delay from end of conversion to next
conversion
2
t
Figures 1, 2, 3a, and 3b
500
SR
Slew rate, tracking
0.1
45
5
V/µs
pF
C
C
C
Analog input capacitance
Logic output capacitance
Logic input capacitance
VIN
OUT
IN
pF
5
pF
NOTES:
1. Unadjusted error includes offset, full-scale, and linearity errors.
2. Accuracy may degrade if t or t is shorter than the minimum value specified.
WR
RD
3. Typical values are at 25°C and represent most likely parametric norm.
4. Guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels.
5. V
and VIN must be applied after V has been turned on to prevent possibility of latching.
CC
REF
572
August 31, 1994
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with
track/hold function
ADC0820
3-STATE TEST CIRCUITS AND WAVEFORMS
t
1H
V
t
DD
R
V
CC
90%
50%
10%
RD
GND
RD
DATA
OUTPUT
CS
t
1H
1K
C
10pF
L
V
OH
90%
DATA
OUTPUTS
GND
t
R = 20ns
t
0H
V
V
CC
CC
t
R
V
DD
RD
90%
50%
10%
1k
GND
RD
DATA
OUTPUT
t
0H
CS
V
DD
DATA
OUTPUTS
C
L
10pF
10%
GND
MODE = LOW
CS
RD
t
P
RDY
(OUTPUT)
WITH
EXTERNAL
t
RDY
PULL–UP R, C
t
INT H
INT
t
CRD
DB0–DB7
OFL
VALID DATA
t
t
,
ACCO
1H 0H
Figure 1. RD Mode
573
August 31, 1994
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with
track/hold function
ADC0820
MODE = LOW
CS x RD = LOW
t
WR
WR
t
t
P
INT H WR
INT
t
I
t
ID
VALID DATA
DB0–DB7
Figure 2. Stand-Alone Mode
MODE = HIGH
CS
t
WR
WR (INPUT)
t
P
RD
t
RD
INT
t
INT
t
INT H
L
(T )
I
VALID
DATA
DB0–DB7
t
t
t
ACC2
1H, 0H
a. WR-RD Mode (t > t )
RD
I
CS
t
WR
WR
t
P
RD
t
RD
t
RI
INT
t
INT
L
t
INT H
(T )
I
VALID
DATA
DB0–DB7
t
ACC1
t
t
1H, 0H
b. WR-RD Mode (t < t )
RD
I
Figure 3. WR-RD Mode
574
August 31, 1994
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with
track/hold function
ADC0820
In the first cycle, one input switch and the inverter’s feedback switch
(Figure 4a) are closed. In this interval, C is charged to the
FUNCTIONAL DESCRIPTION
connected input (V1) less the inverter’s bias voltage (V ,
General Operation
S
approximately 1.6V). In the second cycle (Figure 4b), these two
switches are opened and the other (V2) input’s switch is closed. The
input capacitor now subtracts its stored voltage from the second
input and the difference is amplified by the inverter’s open loop gain.
The ADC0820 uses two 4-bit flash A/D converters to make an 8-bit
measurement (Block Diagram). Each flash ADC is made up of 15
comparators which compare the unknown input to a reference
ladder to get a 4-bit result. To take a full 8-bit reading, one flash
conversion is done to provide the 4 most significant data bits (via the
MS flash ADC). Driven by the 4 MSBs, an internal DAC recreates an
analog approximation of the input voltage. This analog signal is then
subtracted from the input, and the difference voltage is converted by
a second 4-bit flash ADC (the LS ADC), providing the 4 least
significant bits of the output data word.
The inverter’s input (V ) becomes
S’
C
VȀSȀ + VS ) (V2 – V1)
C ) CS
and the output will go High or Low depending on the sign of V’ -V .
S’
S
The actual circuitry used in the ADC0820 is a simple but important
expansion of the basic comparator described above. By adding a
second capacitor and another set of switches to the input (Figure 5),
the scheme can be expanded to make dual differential comparisons.
In this circuit, the feedback switch and one input switch on each
capacitor (Z switches) are closed in the zeroing cycle. A comparison
is then made by connecting the second input on each capacitor (S
switches) and opening all of the other switches. The change in
voltage at the inverter’s input, as a result of the change in charge on
each input capacitor, will now depend on both input signal
differences.
The internal DAC is actually a subsection of the MS flash converter.
This is accomplished by using the same resistor ladder for the A/D
as well as for generating the DAC signal. The DAC output is actually
the tap on the resistor ladder which most closely approximates the
analog input. In addition, the “sampled data” comparators used in
the ADC0820 provide the ability to compare the magnitudes of
several analog signals simultaneously, without using input summing
amplifiers. This is especially useful in the LS flash ADC, where the
signal to be converted is an analog difference.
The Sampled-Data Comparator
Each comparator in the ADC0820 consists of a CMOS inverter with
a capacitively-coupled input (Figure 4). Analog switches connect the
two comparator inputs to the input capacitor (C) and also connect
the inverter’s input and output. This device in effect now has one
differential input pair. A comparison requires two cycles, one for
zeroing the comparator, and another for making the comparison.
Architecture
In the ADC0820, 15 comparators are used in the MS and LS 4-bit
flash A/D converters. The MS (most significant) flash ADC also has
one additional comparator to detect input over-range. These two
sets of comparators operate alternately, with one group in its zeroing
cycle while the other is comparing.
V1
V1
C
C
V
A
O
V
A
V
O
S
V
S
C
S
V2
C
S
V2
• V = V
O
S
•
•
•
V ON C = V1 – V
B
C
• V ’ – V = (V2 – V1)
C
V
= SATRAY INPUT NODE CAPACITOR
= INVERTER INPUT BIAS VOLTAGE
S
S
S
C + C
S
–A
S
• V ’ =
O
[CV2 – CV1]
C + C
S
•
V ’ IS DEPENDENT ON V2–V1
O
a. Zeroing Phase
b. Compare Phase
Figure 4. Sampled Data Comparator
Z
S
Z
R LADDER (V1)
C1
C2
V
(V2)
IN
A
V
O
Z
S
V
C
S
ANALOG GND
(V3)
S
–A
V
=
=
[C1 (V2 – V1) + C2 (V4–V3)]
O
C1 + C2 + C
–A
S
S
1/2 LSB (V4)
∆Q
+
∆Q
C2]
[
C1
C1 + C2 + C
Figure 5. ADC0820 Comparator (From MS Flash ADC)
575
August 31, 1994
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with
track/hold function
ADC0820
To start a conversion in the WR-RD mode, the WR line is brought
Low. At this instant the MS comparators go from zeroing to
CS
comparison mode (Figure 8). When WR is returned High after at
least 600ns, the output from the first set of comparators (the first
flash) is decoded and latched. At this point the two 4-bit converters
RD
change modes and the LS (least significant) flash ADC enters its
compare cycle. No less than 600ns later, the RD line may be pulled
RDY
Low to latch the lower four data bits and finish the 8-bit conversion.
When RD goes Low, the flash A/Ds change state once again in
INT
preparation for the next conversion.
Figure 8 also outlines how the converter’s interface timing relates to
DB0–DB7
its analog input (V ). In WR-RD mode, V is measured while WR is
IN
IN
Low. In RD mode, sampling occurs during the first 800ns of RD.
Because of the input connections to the ADC0820’s LS and MS
a. RD Mode (Pin 7 is Low)
comparators, the converter has the ability to sample V at one
IN
instant, despite the fact that two separate 4-bit conversions are
being done. More specifically, when WR is Low the MS flash is in
CS
WR
compare mode (connected to V , and the LS flash is in zero mode
IN
(also connected to V ). Therefore both flash ADCs sample V at
IN
IN
the same time.
Digital Interface
RB
The ADC0820 has two basic interface modes which are selected by
strapping the Mode pin High or Low.
INT
RD Mode (Figure 6a)
With the Mode pin grounded, the converter is set to Read mode. In
this configuration, a complete conversion is done by pulling RD Low
until output data appears. An INT line is provided which goes Low at
the end of the conversion as well as a RDY output which can be
used to signal a processor that the converter is busy or can also
serve as a system Transfer Acknowledge signal.
DB0–DB7
b. WR-RD Mode (Pin 7 is High and t < t )
RD
I
When in RD mode, the comparator phases are internally triggered.
At the falling edge of RD, the MS flash converter goes from zero to
compare mode and the LS ADC’s comparators enter their zero
cycle. After 800ns, data from the MS flash is latched and the LS
flash ADC enters compare mode. Following another 800ns, the
lower four bits are recovered.
CS
WR
RB
WR Then RD Mode (Figures 6b and c)
INT
With the Mode pin tied High, the A/D will be set up for the WR-RD
mode. Here, a conversion is started with the WR input; however,
there are two options for reading the output data which relate to
interface timing. If an interrupt-driven scheme is desired, the user
can wait for INT to go Low
DB0–DB7
c. WR-RD Mode (Pin 7 is High and t > t )
RD
I
Figure 6.
576
August 31, 1994
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with
track/hold function
ADC0820
before reading the conversion result. INT will typically go Low 800ns
after WR’s rising edge. However, if a shorter conversion time is
desired, the processor need not wait for INT and can exercise a
Read after only 600ns. If this is done, INT will immediately go Low
and data will appear at the outputs.
This reference flexibility lets the input span not only be varied, but
also offset from zero. The voltage at V (-) sets the input level
REF
which produces a digital output of all zeroes. Though V is not itself
IN
differential, the reference design affords nearly differential-input
capability for most measurement applications. Figure 9 shows some
of the configurations that are possible.
Stand-Alone (Figure 7)
For stand-alone operation in WR-RD mode, CS and RD can be tied
Low and a conversion can be started with WR. Data will be valid
approximately 800ns following WR’s rising edge.
Input Current
Due to the unique conversion techniques employed by the
ADC0820, the analog input behaves somewhat differently than in
conventional devices. The A/D’s sampled data comparators take
varying amounts of input current depending on which cycle the
conversion is in.
Other Interface Considerations
In order to maintain conversion accuracy, WR has a maximum width
spec of 50µs. When the MS flash ADC’s sampled data comparators
are in comparison mode (WR is Low), the input capacitors (C,
Figure 5) must hold their charge. Switch leakage can cause errors if
the comparator is left in this phase for too long.
The equivalent input circuit of the ADC0820 is shown in Figure 10a.
When a conversion starts (WR Low, WR-RD mode), all input
switches close, connecting V to 31 1pF capacitors. Although the
IN
two 4-bit flash circuits are not both in their compare cycle at the
Since the MS flash ADC enters its zeroing phase at the end of a
conversion, a new conversion cannot be started until this phase is
same time, V still sees all input capacitors at once. This is
IN
because the MS flash converter is connected to the input during its
compare interval and the LS flash is connected to the input during its
zeroing phase. In other words, the LS ADC uses V as its
complete. The minimum spec for this time is 500ns (t in Figures 1,
P
2, 3a, and 3b).
IN
zero-phase input.
The input capacitors must charge to the input voltage through the on
resistance of the analog switches (about 5kΩ to 10kΩ). In addition,
about 12pF of input stray capacitance must also be charged. For
large source resistances, the analog input can be modeled as an
ANALOG CONSIDERATIONS
Reference and Input
The two V
inputs of the ADC0820 are fully differential and define
REF
RC network as shown in Figure 10b. As R increases, it will take
S
the zero- to full-scale input range of the A/D converter. This allows
the designer to easily vary the span of the analog input since this
longer for the input capacitance to charge.
range will be equivalent to the voltage difference between V (+)
IN
In RD mode, the input switches are closed for approximately 800ns
at the start of the conversion. In WR-RD mode, the time that the
switches are closed to allow this charging is the time that WR is
Low. Since other factors force this time to be at least 600ns, input
time constants of 100ns can be accommodated without special
consideration. Typical total input capacitance values of 45pF allow
and V (-). By reducing V
(V
=V
REF
(+)
IN
REF REF
-V
REF
(-)) to less than 5V, the sensitivity of the converter can be
increased (i.e., if V
=2V, then 1 LSB=7.8mV). The input/reference
REF
arrangement also facilitates ratiometric operation and, in many
cases, the chip power supply can be used for transducer power as
well as the V
source.
REF
R
to be 1.5kΩ without lengthening WR to give V more time to
IN
S
settle.
CS LOW
RD LOW
Input Filtering
It should be made clear that transients in the analog input signal,
WR
caused by charging current flowing into V , will not degrade the
IN
A/D’s performance in most cases. In effect, the ADC0820 does not
“look” at the input when these transients occur. The comparators’
outputs are not latched while WR is Low, so at least 600ns will be
provided to charge the ADC’s input capacitance. It is
INT
DB0–DB7
Figure 7. WR-RD Mode (Pin 7 is High)
Stand-Alone Operation
577
August 31, 1994
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with
track/hold function
ADC0820
WR
600ns
•
•
MS COMPARATORS ZERO
TO REFERENCE LADDER.
•
LS COMPARATORS OUTPUTS
ARE LATCHED AND
CAN BE READ
•
•
MS COMPARATORS COMPARE
TO THEIR REFERENCE
LADDER TAP. THE COMPARATOR
•
•
MS COMPARATORS OUT–
PUTS ARE LATCHED. THE
MS DAC IS SET. THE MS
COMPARATOR FLOATS.
LS COMPARATORS FLOAT
V
IN
V
• V .
LADDER TAP
•
MS COMPARATORS RE
TURN TO ZERO MODE.
IN
LS COMPARATORS COM–
PARE LSB SECTION OF REF–
ERENCE LADDER
LS COMPARATORS ZERO TO V
IN
THE COMPARATOR’S INPUT
CAPACTORS TRACK V
.
IN
Figure 8. Operating Sequence (WR-RD Mode)
IN+
IN+
VI (+)
N
VI (+)
N
IN+
VI (+)
N
GND
GND
VI (–)
N
GND
VI (–)
N
1.2k
1.2k
5V
REF (+)
REF(–)
5V
REF (+)
5V
REF (+)
REF(–)
2.5V
2.5V
REF(–)
VI (–)
N
• CURRENT PATH MUST
STILL EXIST FROM
V
(–) TO GROUND
IN
a. External Reference 2.5V Full-Scale
b. Power Supply as Reference
Figure 9. Analog Input Options
c. Input not Referred to GND
578
August 31, 1994
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with
track/hold function
ADC0820
R
ON
≈
12pF
1pF
R
R
ON
S
V
IN
350
R
S
TO LSB
R–LADDER
V
IN
1pF
C
S
12pF
31pF
15 LSB COMPARATORS
R
ON
R
ON
1pF
TO LSB
R–LADDER
1pF
b.
a.
Figure 10.
579
August 31, 1994
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with
track/hold function
ADC0820
therefore not necessary to filter out these transients by putting an
Input signals with slew rates typically below 100mV/µs can be
converted without error. However, because of the input time
external cap on the V terminal, if an input amplifier that can settle
IN
within 600ns is used to drive the input. The NE530 is a suitable op
amp for driving the input of the ADC0820.
constants, and charge injection through the opened comparator
input switches, faster signals may cause errors. Still, the ADC0820’s
loss in accuracy for a given increase in signal slope is far less than
what would be witnessed in a conventional successive
approximation device. An SAR type converter with a conversion
time as fast as 1µs would still not be able to measure a 5V, 1kHz
sine wave without the aid of an external sample-and-hold. The
ADC0820, with no such help, can typically measure 5V, 7kHz
waveforms.
Inherent Sample-Hold
Another benefit of the ADC0820’s input mechanism is its ability to
measure a variety of high-speed signals without the help of an
external sample-and-hold. In a conventional SAR type converter,
regardless of its speed, the input must remain at least 1/2LSB
stable throughout the conversion process if full accuracy is to be
maintained. Consequently, for many high-speed signals, this signal
must be externally sampled, and held stationary during the
conversion.
V
DD
INT
V
DD
+5V
RDY
CS
V
V
(+)
Sampled data comparators, by nature of their input switching,
already accomplish this function to a large degree (Section 1.2).
Although the conversion time for the ADC0820 is 1.5µs, the time
V
REF
IN
REF
0.1µF 47µF
RD
V
IN
DB7
DB0
MODE
(–)
through which V must be 1/2LSB stable is much smaller. Since
IN
V
REF
GND
the MS flash ADC uses V as its “compare” input and the LS ADC
IN
uses V as its “zero” input, the ADC0820 only “samples” V when
IN
IN
WR is Low. Even though the two flashes are not done
simultaneously, the analog signal is measured at one instant. The
Figure 11. 8-Bit Resolution Configuration
value of V approximately 100ns after the rising edge of WR (100ns
IN
due to internal logic propagation delay) will be the measured value.
25k
40k
–
+
V
(+4V
, 3kHz MAX)
+5V
IN
CC
CS
V
27k
IN
WR
RD
INT
12k
+5V
V
(+)
(–)
REF
+5V
V
V
DD
DB7
DB0
REF
0.1µF
47µF
GND
MODE
Figure 12. Telecom A/D Converter
580
August 31, 1994
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with
track/hold function
ADC0820
CS
CS
+5V
V
DD
WR
RD
WR
MODE
0.1µF
47µF
RD
D8
V
V
V
(+)
REF
REF
IN
DB7
DB0
V
IN
D0–D7
V
(–)
REF
GND
OFL
1k
5k
+5V
CS
V
DD
MODE
WR
1k
RD
V
V
(+)
REF
IN
DB7
DB0
V
(–)
REF
GND
OFL
Figure 13. 9-Bit Resolution Configuration
581
August 31, 1994
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