ADC0817CCN [TI]

ADC0816/ADC0817 8-Bit μP Compatible A/D Converters with16-Channel Multiplexer; ADC0816 / ADC0817的8位μP兼容A / D转换器with16通道多路复用器
ADC0817CCN
型号: ADC0817CCN
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

ADC0816/ADC0817 8-Bit μP Compatible A/D Converters with16-Channel Multiplexer
ADC0816 / ADC0817的8位μP兼容A / D转换器with16通道多路复用器

转换器 模数转换器 复用器 光电二极管
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ADC0816, ADC0817  
www.ti.com  
SNAS527C JUNE 1999REVISED MARCH 2013  
ADC0816/ADC0817 8-Bit μP Compatible A/D Converters  
with16-Channel Multiplexer  
Check for Samples: ADC0816, ADC0817  
1
FEATURES  
23  
Easy interface to all microprocessors  
DESCRIPTION  
The ADC0816, ADC0817 data acquisition component  
is a monolithic CMOS device with an 8-bit analog-to-  
Operates ratiometrically or with 5 VDC or  
analog span adjusted voltage reference  
digital  
converter,16-channel  
multiplexer  
and  
16-channel multiplexer with latched control  
logic  
microprocessor compatible control logic. The 8-bit  
A/D converter uses successive approximation as the  
conversion technique. The converter features a high  
impedance chopper stabilized comparator, a 256R  
Outputs meet TTL voltage level specifications  
0V to 5V analog input voltage range with  
single 5V supply  
voltage divider with analog switch tree and  
a
successive approximation register. The 16-channel  
multiplexer can directly access any one of 16-single-  
ended analog signals, and provides the logic for  
additional channel expansion. Signal conditioning of  
any analog input signal is eased by direct access to  
the multiplexer output, and to the input of the 8-bit  
A/D converter.  
No zero or full-scale adjust required  
Standard hermetic or molded 40-pin MDIP  
package  
Temperature range 40°C to +85°Cor 55°C to  
+125°C  
Latched TRI-STATE output  
The device eliminates the need for external zero and  
Direct access to “comparator in” and  
“multiplexer out” for signal conditioning  
full-scale  
adjustments.  
Easy  
interfacing  
to  
microprocessors is provided by the latched and  
decoded multiplexer address inputs and latched TTL  
TRI-STATE®outputs.  
ADC0816 equivalent to MM74C948  
ADC0817 equivalent to MM74C948-1  
The design of the ADC0816, ADC0817 has been  
optimized by incorporating the most desirable aspects  
of several A/D conversion techniques. The  
ADC0816,ADC0817 offers high speed, high  
KEY SPECIFICATIONS  
Resolution ........................8 Bits  
Total Unadjusted Error....±½ LSB and ±1  
Single Supply....................5 VDC  
Low Power........................15 mW  
Conversion Time..............100 µs  
accuracy,  
minimal  
temperature  
dependence,  
excellent long-term accuracy and repeatability, and  
consumes minima lpower. These features make this  
device ideally suited to applications from process and  
machine control to consumer and automotive  
applications. For similar performance in an 8-channel,  
28-pin, 8-bit A/D converter, see the ADC0808,  
ADC0809 data sheet. (See AN-258 for more  
information.)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
TRI-STATE is a registered trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 1999–2013, Texas Instruments Incorporated  
ADC0816, ADC0817  
SNAS527C JUNE 1999REVISED MARCH 2013  
www.ti.com  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
Block Diagram  
Connection Diagram  
Dual-In-Line Package  
See Package Number NJF0040A  
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(1) (2)  
Absolute Maximum Ratings  
(3)  
Supply Voltage (VCC  
)
6.5V  
Voltage at Any Pin  
0.3V to (VCC+0.3V)  
Except Control Inputs  
Voltage at Control Inputs  
0.3V to 15V  
(START, OE, CLOCK, ALE, EXPANSION CONTROL,  
ADD A, ADD B, ADD C, ADD D)  
Storage Temperature Range  
65°C to +150°C  
Package Dissipation at TA = 25°C  
Lead Temp. (Soldering, 10 seconds)  
Dual-In-Line Package (Plastic)  
Molded Chip Carrier Package  
875 mW  
260°C  
Vapor Phase (60seconds)  
215°C  
220°C  
400V  
Infrared (15 seconds)  
(4)  
ESD Susceptibility  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not  
apply when operating the device beyond its specified operating conditions.  
(2) All voltages are measured with respect to GND, unless otherwise specified.  
(3) A Zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC  
.
(4) Human body model, 100 pF discharged through a 1.5 kΩ resistor.  
(1)  
Operating Conditions  
Temperature Range  
(2)  
TMINTATMAX  
ADC0816CCN, ADC0817CCN  
40°CTA+85°C  
4.5 VDC to 6.0VDC  
0V to VCC  
(2)  
Range of VCC  
Voltage at Any Pin  
Except Control Inputs  
Voltage at Control Inputs  
0V to 15V  
(START,OE, CLOCK, ALE, EXPANSION CONTROL,  
ADD A, ADD B, ADD C, ADDD)  
(1) All voltages are measured with respect to GND, unless otherwise specified.  
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not  
apply when operating the device beyond its specified operating conditions.  
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Electrical Characteristics  
Converter Specifications: VCC = 5 VDC = VREF(+), VREF()= GND, VIN = VCOMPARATOR IN,TMIN TMAX and fCLK = 640 kHz unless  
otherwise stated.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
ADC0816  
Total Unadjusted Error  
25°C  
±½  
±¾  
LSB  
LSB  
(1)  
See Note  
TMIN to TMAX  
ADC0817  
Total Unadjusted Error  
0°C to 70°C  
±1  
LSB  
LSB  
kΩ  
VDC  
V
(1)  
See Note  
TMIN to TMAX  
±1¼  
Input Resistance  
From Ref(+)to Ref()  
1.0  
4.5  
(2)  
Analog Input Voltage Range  
Voltage, Top of Ladder  
V(+) or V()  
GND 0.1  
VCC + 0.1  
VCC+0.1  
VREF(+)  
Measured at Ref(+)  
VCC  
V
Voltage, Center of Ladder  
VCC/2 0.1  
VCC/2  
VCC/2 + 0.1  
VREF()  
Voltage, Bottom of Ladder  
Comparator Input Current  
Measured at Ref()  
0.1  
2  
0
V
(3)  
fc = 640 kHz,  
±0.5  
2
µA  
(1) Total unadjusted error includes offset, full-scale, and linearity errors. See Figure 3. None of these A/Ds requires a zero or full-scale  
adjust. However, if an all zero code is desired for an analog input other than 0.0V,or if a narrow full-scale span exists (for example: 0.5V  
to 4.5V full-scale)the reference voltages can be adjusted to achieve this. See Figure 13.  
(2) Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or  
one diode drop greater than the VCCsupply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog  
VIN does not exceed the supply voltage by more than 100 mV, the output code will be correct. To achieve an absolute0 VDC to 5 VDC  
input voltage range will therefore require a minimum supply voltage of 4.900 VDC over temperature variations, initial tolerance and  
loading.  
(3) Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock  
frequency and has little temperature dependence (Figure 6).  
4
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Electrical Characteristics  
Digital Levels and DC Specifications: ADC0816CCN, ADC0817CCN—4.75V VCC 5.25V, 40°C TA +85°C unless  
otherwise noted.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
ANALOG MULTIPLEXER  
(Any Selected Channel)  
TA = 25°C, RL= 10k  
TA = 85°C  
1.5  
3
6
9
kΩ  
kΩ  
kΩ  
Ω
RON  
Analog Multiplexer ON Resistance  
TA = 125°C  
ΔON Resistance Between Any 2  
Channels  
(Any Selected Channel)  
RL=10k  
75  
10  
ΔRON  
VCC= 5V, VIN= 5V,  
TA = 25°C  
IOFF+  
OFF Channel Leakage Current  
OFF Channel Leakage Current  
200  
1.0  
nA  
TMIN to TMAX  
VCC = 5V, VIN = 0,  
TA = 25°C  
μA  
IOFF()  
200  
1.0  
nA  
TMIN to TMax  
μA  
CONTROL INPUTS  
VIN(1)  
VIN(0)  
Logical “1”Input Voltage  
V
CC 1.5  
V
V
Logical “0”Input Voltage  
1.5  
1.0  
Logical “1”Input Current  
(The Control Inputs)  
IIN(1)  
IIN(0)  
VIN = 15V  
VIN = 0  
μA  
μA  
Logical “0”Input Current  
(The Control Inputs)  
1.0  
ICC  
Supply Current  
fCLK = 640 kHz  
0.3  
3.0  
mA  
DATA OUTPUTS AND EOC (INTERRUPT)  
IO = 360 μA, TA = 85°C  
IO = 300 μA, TA = 125°C  
VOUT(1)  
Logical “1”Output Voltage  
VCC 0.4  
V
VOUT(0)  
VOUT(0)  
Logical “0”Output Voltage  
IO = 1.6 mA  
IO = 1.2 mA  
VO = VCC  
VO = 0  
0.45  
0.45  
3.0  
V
V
Logical “0”Output Voltage EOC  
μA  
μA  
IOUT  
TRI-STATE Output Current  
3.0  
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Electrical Characteristics  
Timing Specifications:VCC = VREF(+) = 5V, VREF() = GND, tr = tf = 20 ns and TA = 25°C unless otherwise noted.  
Symbol  
tWS  
tWALE  
ts  
Parameter  
Conditions  
Min  
Typ  
100  
100  
25  
Max  
200  
200  
50  
Units  
ns  
(1)  
Minimum Start Pulse Width  
Minimum ALE Pulse Width  
Minimum Address Set-Up Time  
Minimum Address Hold Time  
(Figure 5)  
(Figure 5)  
(Figure 5)  
(Figure 5)  
ns  
ns  
TH  
25  
50  
ns  
Analog MUX Delay Time  
from ALE  
tD  
RS= OΩ (Figure 5)  
1
2.5  
μs  
tH1, tH0  
t1H, t0H  
tC  
OE Control to Q Logic State  
OE Control to Hi-Z  
Conversion Time  
CL= 50 pF, RL= 10k (Figure 8)  
CL= 10 pF, RL= 10k (Figure 8)  
125  
125  
100  
640  
250  
250  
ns  
ns  
(2)  
fc=640 kHz, (Figure 5)  
90  
10  
116  
μs  
fc  
Clock Frequency  
1280  
kHz  
Clock  
Periods  
tEOC  
CIN  
EOC Delay Time  
Input Capacitance  
(Figure 5)  
0
8 + 2μs  
15  
At Control Inputs  
10  
10  
pF  
TRI-STATE Output  
Capacitance  
(2)  
COUT  
At TRI-STATE Outputs  
15  
pF  
(1) If start pulse is asynchronous with converter clock or if fc > 640 kHz, the minimum start pulse width is 8clock periods plus 2 μs. For  
synchronous operation at fc 640 kHz take start high within 100 ns of clock going low.  
(2) The outputs of the data register are updated one clock cycle before the rising edge of EOC.  
Functional Description  
Multiplexer: The device contains a 16-channel single-ended analog signal multiplexer. A particular input channel  
is selected by using the address decoder. Table 1 shows the input states for the address line and the expansion  
control line to select any channel. The address is latched into the decoder on the low-to-high transition of the  
address latch enable signal.  
Table 1. Inputs States for the Address line  
Selected  
Address Line(1)  
Expansion  
AnalogChannel  
D
L
C
L
B
L
A
L
Control  
IN0  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
IN1  
L
L
L
H
L
IN2  
L
L
H
H
L
IN3  
L
L
H
L
IN4  
L
H
H
H
H
L
IN5  
L
L
H
L
IN6  
L
H
H
L
IN7  
L
H
L
IN8  
H
H
H
H
H
H
H
H
X
IN9  
IN10  
L
L
H
L
L
H
H
L
IN11  
L
H
L
IN12  
H
H
H
H
X
IN13  
L
H
L
IN14  
H
H
X
IN15  
H
X
All Channels OFF  
(1) X = don't care  
6
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Additional single-ended analog signals can be multiplexed to the A/D converter by disabling all the multiplexer  
inputs using the expansion control. The additional external signals are connected to the comparator input and the  
device ground. Additional signal conditioning (i.e., prescaling, sample and hold, instrumentation amplification,  
etc.) may also be added between the analog input signal and the comparator input.  
CONVERTER CHARACTERISTICS  
The Converter  
The heart of this single chip data acquisition system is its8-bit analog-to-digital converter. The converter is  
designed to give fast, accurate, and repeatable conversions over a wide range of temperatures. The converter is  
partitioned into 3 major sections: the 256R ladder network, the successive approximation register, and the  
comparator. The converter's digital outputs are positive true.  
The 256R ladder network approach Figure 1 was chosen over the conventional R/2R ladder because of its  
inherent monotonicity, which specifies no missing digital codes. Monotonicity is particularly important in closed  
loop feedback control systems. A non-monotonic relationship can cause oscillations that will be catastrophic for  
the system. Additionally, the 256R network does not cause load variations on the reference voltage.  
The bottom resistor and the top resistor of the ladder networking Figure 1 are not the same value as the  
remainder of the network. The difference in these resistors causes the output characteristic to be symmetrical  
with the zero and full-scale points of the transfer curve. The first output transition occurs when the analog signal  
has reached + ½ LSB and succeeding output transitions occur every 1 LSB later up to full-scale.  
Figure 1. Resistor Ladder and Switch Tree  
Figure 2. 3-Bit A/D Transfer Curve  
Figure 3. 3-Bit A/D Absolute Accuracy Curve  
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Figure 4. Typical Error Curve  
Timing Diagram  
Figure 5.  
The successive approximation register (SAR) performs 8 iterations to approximate the input voltage. For any  
SAR type converter, n-iterations are required for an n-bit converter. Figure 2 shows a typical example of a 3-bit  
converter. In the ADC0816,ADC0817, the approximation technique is extended to 8 bits using the 256Rnetwork.  
The A/D converter's successive approximation register (SAR)is reset on the positive edge of the start conversion  
(SC) pulse. The conversion is begun on the falling edge of the start conversion pulse. A conversion in process  
will be interrupted by receipt of a new start conversion pulse. Continuous conversion may be accomplished by  
tying the end-of-conversion(EOC) output to the SC input. If used in this mode, an external start conversion pulse  
should be applied after power up. End-of-conversion will go low between 0 and 8 clock pulses after the rising  
edge of start conversion.  
The most important section of the A/D converter is the comparator. It is this section which is responsible for the  
ultimate accuracy of the entire converter. It is also the comparator drift which has the greatest influence on the  
repeatability of the device. A chopper-stabilized comparator provides the most effective method of satisfying all  
the converter requirements.  
The chopper-stabilized comparator converts the DC input signal into an AC signal. This signal is then fed through  
a high gain AC amplifier and has the DC level restored. This technique limits the drift component of the amplifier  
since the drift is a DC component which is not passed by the AC amplifier. This makes the entire A/D converter  
extremely insensitive to temperature, long term drift and input offset errors.  
Figure 4 shows a typical error curve for the ADC0816 as measured using the procedures outlined in AN-179.  
8
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Typical Performance Characteristics  
Figure 6. Comparator IIN vs. VIN  
(VCC = VREF = 5V)  
Figure 7. Multiplexer RON vs. VIN  
(VCC = VREF = 5V)  
spacer  
TRI-STATE Test Circuits and Timing Diagrams  
Figure 8.  
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APPLICATION INFORMATION  
OPERATION  
Ratiometric Conversion  
The ADC0816, ADC0817 is designed as a complete Data Acquisition System (DAS) for ratiometric conversion  
systems. In ratiometric systems, the physical variable being measured is expressed as a percentage of full-scale  
which is not necessarily related to an absolute standard. The voltage input to the ADC0816 is expressed by the  
equation  
(1)  
Where:  
VIN = Input voltage into the ADC0816  
Vfs = Full-scale voltage  
VZ = Zero voltage  
DX = Data point being measured  
DMAX = Maximum data limit  
DMIN = Minimum data limit  
A good example of a ratiometric transducer is a potentiometer used as a position sensor. The position of the  
wiper is directly proportional to the output voltage which is a ratio of the full-scale voltage across it. Since the  
data is represented as a proportion of full-scale, reference requirements are greatly reduced, eliminating a large  
source of error and cost for many applications. A major advantage of the ADC0816, ADC0817 is that the input  
voltage range is equal to the supply range so the transducers can be connected directly across the supply and  
their outputs connected directly into the multiplexer inputs, (Figure 9).  
Ratiometric transducers such as potentiometers, strain gauges, thermistor bridges, pressure transducers, etc.,  
are suitable for measuring proportional relationships; however, many types of measurements must be referred to  
an absolute standard such as voltage or current. This means a system reference must be used which relates the  
full-scale voltage to the standard volt. For example, if VCC = VREF = 5.12V, then the full-scale range is divided into  
256 standard steps. The smallest standard step is 1 LSB which is then 20 mV.  
Resistor Ladder Limitations  
The voltages from the resistor ladder are compared to the selected input 8 times in a conversion. These voltages  
are coupled to the comparator via an analog switch tree which is referenced to the supply. The voltages at the  
top, center and bottom of the ladder must be controlled to maintain proper operation.  
The top of the ladder, Ref(+), should not be more positive than the supply, and the bottom of the ladder, Ref(),  
should not be more negative than ground. The center of the ladder voltage must also be near the center of the  
supply because the analog switch tree changes from N-channel switches to P-channel switches. These  
limitations are automatically satisfied in ratiometric systems and can be easily met in ground referenced systems.  
Figure 10 shows a ground referenced system with a separate supply and reference. In this system, the supply  
must be trimmed to match the reference voltage. For instance, if a5.12V reference is used, the supply should be  
adjusted to the same voltage within 0.1V.  
10  
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Figure 9. Ratiometric Conversion System  
The ADC0816 needs less than a milliamp of supply current so developing the supply from the reference is  
readily accomplished. In Figure 11 a ground references system is shown which generates the supply from the  
reference. The buffer shown can be an op amp of sufficient drive to supply the milliamp of supply current and the  
desired bus drive, or if a capacitive bus is driven by the outputs a large capacitor will supply the transient supply  
current as seen in Figure 12. The LM301 is overcompensated to insure stability when loaded by the 10 μF output  
capacitor.  
The top and bottom ladder voltages cannot exceed VCCand ground, respectively, but they can be symmetrically  
less than VCC and greater than ground. The center of the ladder voltage should always be near the center of the  
supply. The sensitivity of the converter can be increased, (i.e., size of the LSB steps decreased) by using a  
symmetrical reference system. In Figure 13, a2.5V reference is symmetrically centered about VCC/2 since the  
same current flows in identical resistors. This system with a 2.5V reference allows the LSB to be half the size of  
the LSB in a 5V reference system.  
Figure 10. Ground Referenced Conversion System Using Trimmed Supply  
Figure 11. Ground Referenced Conversion System with Reference Generating VCC Supply  
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Figure 12. Typical Reference and Supply Circuit  
Figure 13. Symmetrically Centered Reference  
Converter Equations  
The transition between adjacent codes N and N + 1 is given by:  
The center of an output code N is given by:  
(2)  
(3)  
(4)  
The output code N for an arbitrary input are the integers within the range:  
where: VIN = Voltage at comparator input  
VREF = Voltage at Ref(+)  
VREF = Voltage at Ref()  
VTUE = Total unadjusted error voltage(typically  
VREF(+) ÷512)  
12  
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Analog Comparator Inputs  
The dynamic comparator input current is caused by the periodic switching of on-chip stray capacitances These  
are connected alternately to the output of the resistor ladder/switch tree network and to the comparator input as  
part of the operation of the chopper stabilized comparator.  
The average value of the comparator input current varies directly with clock frequency and with VIN as shown in  
Figure 6.  
If no filter capacitors are used at the analog or comparator inputs and the signal source impedances are low, the  
comparator input current should not introduce converter errors, as the transient created by the capacitance  
discharge will die out before the comparator output is strobed.  
If input filter capacitors are desired for noise reduction and signal conditioning they will tend to average out the  
dynamic comparator input current. It will then take on the characteristics of a DC bias current whose effect can  
be predicted conventionally. See AN-258 for further discussion.  
Typical Application  
*Address latches needed for 8085 and SC/MP interfacing theADC0816, 17 to a microprocessor  
Microprocessor Interface Table  
PROCESSOR  
READ  
WRITE  
INTERRUPT(COMMENT)  
INTR (Thru RST Circuit)  
8080  
8085  
Z-80  
MEMR  
RD  
MEMW  
WR  
INTR (Thru RST Circuit)  
INT (Thru RST Circuit, Mode 0)  
SA (Thru Sense A)  
RD  
WR  
SC/MP  
6800  
NRDS  
NWDS  
VMA•φ2•R/W  
VMA•Q2•R/W  
IRQA or IRQB (Thru PIA)  
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REVISION HISTORY  
Changes from Revision B (March 2013) to Revision C  
Page  
Changed layout of National Data Sheet to TI format .......................................................................................................... 13  
14  
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PACKAGE OPTION ADDENDUM  
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1-Nov-2013  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(6)  
(3)  
(4/5)  
ADC0816CCN  
NRND  
ACTIVE  
PDIP  
PDIP  
NFJ  
40  
40  
9
TBD  
Call TI  
SN  
Call TI  
-40 to 85  
-40 to 85  
ADC0816CCN  
ADC0816CCN/NOPB  
NFJ  
9
Green (RoHS  
& no Sb/Br)  
Level-1-NA-UNLIM  
ADC0816CCN  
ADC0817CCN  
NRND  
PDIP  
PDIP  
NFJ  
NFJ  
40  
40  
9
9
TBD  
Call TI  
SN  
Call TI  
-40 to 85  
-40 to 85  
ADC0817CCN  
ADC0817CCN  
ADC0817CCN/NOPB  
ACTIVE  
Green (RoHS  
& no Sb/Br)  
Level-1-NA-UNLIM  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish  
value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
1-Nov-2013  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
MECHANICAL DATA  
N
F
J
0040A  
N40A (Rev E)  
www.ti.com  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and  
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale  
supplied at the time of order acknowledgment.  
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily  
performed.  
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or  
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information  
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Applications  
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www.ti.com/audio  
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Copyright © 2013, Texas Instruments Incorporated  

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