ADC0819 [NSC]
8-Bit Serial I/O A/D Converter with 19-Channel Multiplexer; 8位串行I / OA / D转换器，具有19通道多路复用器
| 型号： | ADC0819 |
| 厂家： | 
National Semiconductor |
| 描述： | 8-Bit Serial I/O A/D Converter with 19-Channel Multiplexer |
| 文件： | 总12页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 1994
ADC0819 8-Bit Serial I/O A/D Converter
with 19-Channel Multiplexer
General Description
Y
The ADC0819 is an 8-Bit successive approximation A/D
converter with simultaneous serial I/O. The serial input con-
trols an analog multiplexer which selects from 19 input
channels or an internal half scale test voltage.
Ratiometric or absolute voltage referencing.
Y
Y
Y
Y
Y
No zero or full-scale adjust required.
Internally addressable test voltage.
0V to 5V input range with single 5V power supply.
TTL/MOS input/output compatible.
An input sample-and-hold is implemented by a capacitive
reference ladder and sampled data comparator. This allows
the input signal to vary during the conversion cycle.
28-pin molded chip carrier or 28-pin molded DIP
Separate serial I/O and conversion clock inputs are provid-
ed to facilitate the interface to various microprocessors.
Key Specifications
Y
Resolution
8-Bits
g
1LSB
Y
g
Total unadjusted error
(/2LSB and
Features
Y
Y
Single supply
5V
DC
Separate asynchronous converter clock and serial data
I/O clock.
Y
Low Power
15 mW
Y
Conversion Time
16 ms
Y
19-Channel multiplexer with 5-Bit serial address logic.
Y
Built-in sample and hold function.
Connection Diagrams
Functional Diagram
Molded Chip Carrier (PCC) Package
TL/H/9287–1
Top View
Order Number ADC0819BCV, CCV
See NS Package Number V28A
Dual-In-Line Package
TL/H/9287–2
TL/H/9287–20
Top View
Order Number ADC0819BCN, CIN
See NS Package Number N28B
C
1995 National Semiconductor Corporation
TL/H/9287
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Lead Temperature (Soldering, 10 sec.)
Dual-In-Line Package (Plastic)
Surface Mount Package
Vapor Phase (60 sec.)
260 C
§
215 C
§
Supply Voltage (V
Voltage
)
CC
6.5V
Infrared (15 sec.)
220 C
§
2000V
ESD Susceptibility (Note 11)
b
a
g
Inputs and Outputs
0.3V to V
CC
0.3V
5mA
Input Current Per Pin (Note 3)
Total Package Input Current (Note 3)
Storage Temperature
Operating Ratings (Notes 1 & 2)
g
20mA
Supply Voltage (V
)
CC
4.5 V to 6.0 V
DC
DC
b
a
65 C to 150 C
§
§
875 mW
s
s
T
Temperature Range
T
T
MIN
A
MAX
e
Package Dissipation at T
25 C
§
A
s
s
s
s
b
b
a
a
a
ADC0819BCV, ADC0819CCV
ADC0819BCN
40 C
§
T
T
T
85 C
§
70 C
§
85 C
§
A
A
A
s
s
0 C
§
ADC0819CIN
40 C
§
Electrical Characteristics
The following specifications apply for V
CC
e
e
e
2.097 MHz unless otherwise specified. Boldface limits
2 CLK
5V, V
5V, w
REF
e
e
apply from T
to T
; all other limits T
MAX
T
J
25 C.
§
MIN
Parameter
CONVERTER AND MULTIPLEXER CHARACTERISTICS
A
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Typical
(Note 6)
Conditions
Units
e
(Note 4)
Maximum Total
V
5.00 V
DC
REF
Unadjusted Error
ADC0819BCV, BCN
ADC0819CCV, CIN
g
g
g
(2
g
1
(/2
1
LSB
LSB
Minimum Reference
Input Resistance
8
8
5
kX
kX
Maximum Reference
Input Resistance
11
11
a
a
0.05
Maximum Analog Input Range
Minimum Analog Input Range
On Channel Leakage Current
(Note 5)
(Note 9)
V
0.05
V
V
V
CC
CC
b
GND 0.05
b
GND 0.05
e
On Channel 5V
e
Off Channel 0V
400
1000
nA
nA
e
b
b
b
b
On Channel 0V
400
400
1000
1000
e
Off Channel 5V
(Note 9)
Off Channel Leakage Current
(Note 9)
On Channel 5V
e
nA
nA
e
Off Channel 0V
e
On Channel 0V
400
1000
e
Off Channel 5V
(Note 9)
e
Minimum V
TEST
Internal Test Voltage
V
V
,
(Note 10)
Counts
REF CC
CH 19 Selected
125
130
125
130
e
V ,
CC
Maximum V
TEST
Internal Test Voltage
V
(Note 10)
Counts
REF
CH 19 Selected
DIGITAL AND DC CHARACTERISTICS
e
e
V
IN(1)
Voltage (Min)
, Logical ‘‘1’’ Input
V
V
V
V
5.25V
4.75V
CC
2.0
0.8
2.5
2.0
0.8
2.5
V
V
V
, Logical ‘‘0’’ Input
IN(0)
Voltage (Max)
CC
e
I , Logical ‘‘1’’ Input
IN(1)
Current (Max)
5.0V
0V
0.005
IN
IN
mA
mA
e
b
I
, Logical ‘‘0’’ Input
0.005
IN(0)
Current (Max)
b
b
2.5
2.5
2
Electrical Characteristics (Continued)
e
e
e
2.097 MHz unless otherwise specified. Boldface limits
2 CLK
The following specifications apply for V
CC
5V, V
REF
5V, w
e
e
apply from T
to T
; all other limits T
MAX
T
J
25 C.
§
MIN
A
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Typical
(Note 6)
Parameter
Conditions
Units
DIGITAL AND DC CHARACTERISTICS (Continued)
e
4.75V
V , Logical ‘‘1’’
OUT(1)
Output Voltage (Min)
V
I
I
CC
OUT
OUT
eb
eb
360 mA
10 mA
2.4
4.5
2.4
4.5
V
V
e
5.25V
V , Logical ‘‘0’’
OUT(0)
Output Voltage (Max)
V
I
CC
0.4
0.4
V
e
1.6 mA
OUT
e
OUT
b
b
3
b
3
3
I
, TRI-STATE Output
V
V
0V
5V
0.01
0.01
3
mA
mA
OUT
Current (Max)
e
OUT
OUT
e
b
I
Current (Min)
, Output Source
SOURCE
V
0V
14
b
b
6.5
6.5
mA
e
I
I
I
, Output Sink Current (Min)
SINK
V
V
16
8.0
8.0
mA
mA
mA
OUT
CC
e
CS 1, V
, Supply Current (Max)
CC
Open
1
2.5
1
2.5
1
REF
e
REF
(Max)
V
5V
0.7
REF
AC CHARACTERISTICS
Tested
Limit
(Note 6) (Note 7)
Design
Limit
(Note 8)
Parameter
Conditions
Typical
Units
MHz
KHz
w
, w Clock Frequency
2 CLK
MIN
MAX
MIN
0.70
1.0
2.1
5.0
525
26
2
4.0
2.0
S
CLK
, Serial Data Clock
Frequency
MAX
1000
26
525
T , Conversion Process Time
MIN Not Including MUX
Addressing and
w
w
cycles
C
2
Analog Input
Sampling Times
MAX
32
32
t
, Access Time Delay From CS
Falling Edge to DO Data Valid
MIN
1
3
cycles
ACC
2
MAX
1
t
t
t
, Minimum Set-up Time of CS Falling
SET-UP
a
4/w
sec
ns
2CLK
Edge to S
Rising Edge
2 S
CLK
CLK
, CS Hold Time After the Falling
Edge of S
CLK
HCS
0
a
, Total CS Low Time
MIN
t
8/S
CLK
sec
sec
CS
set-up
a
MAX
t
(min) 26/w
CS
2CLK
t
t
t
t
t
, Minimum DI Hold Time from
HDI
0
0
ns
ns
ns
ns
ns
S
Rising Edge
CLK
e
e
, Minimum DO Hold Time from S
HDO
Falling Edge
R
C
30k,
100 pF
CLK
L
L
10
, Minimum DI Set-up Time to S
Rising Edge
SDI
CLK
200
180
90
400
250
150
e
e
, Maximum Delay From S
DDO CLK
R
30k,
100 pF
L
L
200
150
Falling Edge to DO Data Valid
C
e
e
, Maximum DO Hold Time,
(CS Rising edge to DO TRI-STATE)
R
3k,
100 pF
TRI
L
L
C
3
e
e e
t
f
e
20 ns, V 5V, unless
REF
Electrical Characteristics The following specifications apply for V
5V, t
CC
r
e
e
otherwise specified. Boldface limits apply from T
MIN
to T
; all other limits T
T
25 C.
§
MAX
A
J
Tested
Limit
Design
Limit
Typical
Parameter
Conditions
Units
(Note 6)
(Note 7)
(Note 8)
AC CHARACTERISTICS (Continued)
t
, Analog
After Address Is Latched
e
CS Low
CA
Sampling Time
a
3/S
CLK
1 ms
sec
ns
e
e
e
e
t
, Maximum DO
R
30 kX,
100 pf
30 kX,
100 pf
‘‘TRI-STATE’’ to ‘‘HIGH’’ State
‘‘LOW’’ to ‘‘HIGH’’ State
75
150
75
150
300
150
300
150
300
150
300
55
RDO
Rise Time
, Maximum DO
L
L
C
t
R
‘‘TRI-STATE’’ to ‘‘LOW’’ State
‘‘HIGH’’ to ‘‘LOW’’ State
FDO
Fall Time
, Maximum Input
L
L
ns
C
150
11
C
Analog Inputs, ANO–AN10 and V
IN
Capacitance
REF
pF
All Others
5
15
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to ground.
k
l
V
CC
g
) the maximum input current at any one pin is 5 mA. If the voltage at more than one pin exceeds
Note 3: Under over voltage conditions (V
0V and V
IN
.3V the total package current must be limited to 20 mA. For example the maximum number of pins that can be over driven at the maximum current level of
5 mA is four.
IN
a
V
CC
g
Note 4: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.
Note 5: Two on-chip diodes are tied to each analog input, which will forward-conduct for analog input voltages one diode drop below ground or one diode drop
greater than V
supply. Be careful during testing at low V
levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct, especially at
CC
CC
elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the
analog V does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 V to 5 V input voltage range will
DC
IN
therefore require a minimum supply voltage of 4.950 V
DC
over temperature variations, initial tolerance and loading.
DC
Note 6: Typicals are at 25 C and represent most likely parametric norm.
§
Note 7: Tested Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Design Limits are guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 9: Channel leakage current is measured after the channel selection.
e
Note 10: 1 count
V
/256.
REF
Note 11: Human body model; 100 pF discharged through a 1.5 kX resistor.
Test Circuits
D0 Except ‘‘TRI-STATE’’
Leakage Current
TL/H/9287–4
TL/H/9287–3
t
‘‘TRI-STATE’’
TRI
Timing Diagrams
D0 ‘‘TRI-STATE’’ Rise & Fall Times
TL/H/9287–6
TL/H/9287–5
4
Timing Diagrams (Continued)
D0 Low to High State
D0 High to Low State
TL/H/9287–7
TL/H/9287–8
Data Input and Output Timing
TL/H/9287–9
Timing with a continuous S
CLK
TL/H/9287–10
*Strobing CS High and Low will abort the present conversion and initiate a new serial I/O exchange.
Timing with a gated S
CLK
and CS Continuously Low
TL/H/9287–11
Using CS To TRI-STATE D0
TL/H/9287–12
Note: Strobing CS Low during this time interval will abort the conversion in process.
5
Timing Diagrams (Continued)
CS High During Conversion
TL/H/9287–13
CS Low During Conversion
TL/H/9287–14
Channel Addressing Table
TABLE I. ADC 0819 Channel Addressing
ANALOG
CHANNEL
SELECTED
MUX ADDRESS
A
A
6
A
5
A
4
A
3
A
2
A
1
A
0
7
0
0
0
0
0
X
X
X
CH0
CH1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
V
TEST
No Channel Select
No Channel Select
No Channel Select
No Channel Select
Logic Test Mode*
*Analog channel inputs CH0 thru CH4 are logic outputs
6
Functional Block Diagram
7
Functional Description
1.0 DIGITAL INTERFACE
The ADC0819 uses five input/output pins to implement the
serial interface. Taking chip select (CS) low enables the I/O
this mux address/sample cycle, data from the last conver-
sion is also clocked out on DO. Since D7 was clocked out
on the falling edge of CS only data bits D6–D0 remain to be
data lines (DO and DI) and the serial clock input (S
). The
CLK
result of the last conversion is transmitted by the A/D on the
DO line, while simultaneously the DI line receives the ad-
dress data that selects the mux channel for the next conver-
sion. The mux address is shifted in on the rising edge of
received. The following seven falling edges of S
this data on DO.
shift out
CLK
The 8th S
falling edge initiates the beginning of the A/D’s
CLK
actual conversion process which takes between 26 and 32
cycles (T ). During this time CS can go high to TRI-
S
and the conversion data is shifted out on the falling
cycles to complete the serial I/O.
CLK
edge. It takes eight S
w
2
C
CLK
STATE DO and disable the S
input or it can remain low.
CLK
A second clock (w ) controls the SAR during the conversion
2
process and must be continuously enabled.
If CS is held low a new I/O exchange will not start until the
conversion sequence has been completed, however once
the conversion ends serial I/O will immediately begin. Since
1.1 CONTINUOUS S
CLK
there is an ambiguity in the conversion time (T ) synchroniz-
C
ing the data exchange is impossible. Therefore CS should
With a continuous S input CS must be used to synchro-
nize the serial data exchange (see Figure 1). The ADC0819
CLK
go high before the 26th w clock has elasped and return low
2
recognizes a valid CS one to three w clock periods after
2
after the 32nd w to synchronize serial communication.
2
the actual falling edge of CS. This is implemented to ensure
noise immunity of the CS signal. Any spikes on CS less than
A conversion or I/O operation can be aborted at any time by
strobing CS. If CS is high or low less than one w clock it will
2
be ignored by the A/D. If the CS is strobed high or low
one w clock period will be ignored. CS must remain low
2
during the complete I/O exchange which takes eight S
CLK
between 1 to 3 w clocks the A/D may or may not respond.
2
cycles. Although CS is not immediately acknowledged for
the purpose of starting a new conversion, the falling edge of
CS immediately enables DO to output the MSB (D7) of the
previous conversion.
Therefore CS must be strobed high or low greater than 3 w
2
clocks to ensure recognition. If a conversion or I/O ex-
change is aborted while in process the consequent data
output will be erroneous until a complete conversion se-
quence has been implemented.
The first S
CLK
up time (t
rising edge will be acknowledged after a set-
) has elapsed from the falling edge of CS.
set-up
This and the following seven S
rising edges will shift in
1.2 DISCONTINUOUS S
CLK
CLK
thechanneladdressfortheanalogmultiplexer.Sincethereare
19 channels only five address bits are utilized. The first five
Another way to accomplish synchronous serial communica-
tion is to tie CS low continuously and disable S after its
8th falling edge (see Figure 2). S
CLK
must remain low for
S
CLK
S
CLK
cycles clock in the mux address, during the next three
cycles the analog input is selected and sampled. During
CLK
TL/H/9287–16
FIGURE 1
TL/H/9287–17
FIGURE 2
8
Functional Description (Continued)
at least 32 w clocks to ensure that the A/D has completed
eighth S falling edge. The hold mode is initiated with the
start of the conversion process. An acquisition window of
2
CLK
its conversion. If S
CLK
is enabled sooner, synchronizing to
a
1 msec is therefore available to allow the ladder
the data output on DO is not possible since an end of con-
version signal from the A/D is not available and the actual
conversion time is not known. With CS low during the con-
3t
S
CLK
capacitance to settle to the analog input voltage. Any
change in the analog voltage before or after the acquisition
window will not effect the A/D conversion result.
version time (32 w max) DO will go high or low after the
2
eighth falling edge of S
until the conversion is complet-
ed. Once the conversion is through DO will transmit the
CLK
In the most simple case, the ladder’s acquisition time is de-
termined by the R (3K) of the multiplexer switches and the
on
total ladder capacitance (90pf). These values yield an acqui-
sition time of about 2 msec for a full scale reading. There-
fore the analog input must be stable for at least 2 msec
MSB. The rest of the data will be shifted out once S
enabled as discussed previously.
is
CLK
If CS goes high during the conversion sequence DO is tri-
stated, and the result is not affected so long as CS remains
high until the end of the conversion.
before and 1 msec after the eighth S
falling edge to
CLK
ensure a proper conversion. External input source resist-
ance and capacitance will lengthen the acquisition time and
should be accounted for.
1.2 MULTIPLEXER ADDRESSING
The five bit mux address is shifted, MSB first, into DI. Input
data corresponds to the channel selected as shown in table
1. Care should be taken not to send an address greater than
or equal to twenty four (11XXX) as this puts the A/D in a
digital testing mode. In this mode the analog inputs CH0
thru CH4 become digital outputs, for our use in production
testing.
Other conventional sample and hold error specifications are
included in the error and timing specs of the A/D. The hold
step and gain error sample/hold specs are taken into ac-
count in the ADC0819’s total unadjusted error, while the
hold settling time is included in the A/D’s max conversion
time of 32 w clock periods. The hold droop rate can be
2
thought of as being zero since an unlimited amount of time
can pass between a conversion and the reading of data.
However, once the data is read it is lost and another conver-
sion is started.
2.0 ANALOG INPUT
2.1 THE INPUT SAMPLE AND HOLD
The ADC0819’s sample/hold capacitor is implemented in its
capacitive ladder structure. After the channel address is re-
ceived, the ladder is switched to sample the proper analog
input. This sampling mode is maintained for 1 msec after the
Typical Applications
ADC0819-INS8048 INTERFACE
TL/H/9287–18
9
ADC0819 FUNCTIONAL CIRCUIT
TL/H/9287–19
Ordering Information
a
0 C to 70 C
b
a
40 C to 85 C
Temperature Range
§
ADC0819BCN
§
§
§
g
Total Unadjusted
Error
(/2 LSB
ADC0819BCV
ADC0819CCV
V28A
g
1 LSB
ADC0819CIN
N28B
Package Outline
N28B
10
Physical Dimensions inches (millimeters)
Molded Dual-In-Line Package (N)
Order Number ADC0819BCN or ADC0819CIN
NS Package Number N28B
11
Physical Dimensions inches (millimeters) (Continued)
Molded Chip Carrier (V)
Order Number ADC0819BCV, CCV
NS Package Number V28A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
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Europe
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Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
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Fax:
(
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@
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a
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(
(
(
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