74LVC16374ADGVRG4 [TI]
16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs;
| 型号： | 74LVC16374ADGVRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs |
| 文件： | 总17页 (文件大小：469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC16374A
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS728A–OCTOBER 2003–REVISED OCTOBER 2005
FEATURES
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
•
•
•
•
•
Member of the Texas Instruments Widebus™
Family
1
48 1CLK
47 1D1
1OE
1Q1
1Q2
GND
1Q3
1Q4
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
2
46
3
1D2
Typical VOHV (Output VOH Undershoot) >2 V at
VCC = 3.3 V, TA = 25°C
4
45 GND
44 1D3
43 1D4
5
Ioff Supports Partial-Power-Down Mode
Operation
6
7
42
41
40
39
V
CC
V
CC
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input and Output Voltages With
8
1D5
1D6
GND
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
9
3.3-V VCC
)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
•
•
Latch-Up Performance Exceeds 250 mA Per
JESD 17
38 1D7
37 1D8
36 2D1
ESD Protection Exceeds JESD 22
35
34
33
32
31
30
29
28
27
26
25
2D2
GND
2D3
2D4
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
V
CC
V
CC
This 16-bit edge-triggered D-type flip-flop is designed
for 1.65-V to 3.6-V VCC operation.
2D5
2D6
GND
2D7
2D8
2CLK
2Q5
2Q6
GND
2Q7
2Q8
2OE
The SN74LVC16374A is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. The device can be
used as two 8-bit flip-flops or one 16-bit flip-flop. On
the positive transition of the clock (CLK) input, the Q
outputs of the flip-flop take on the logic levels set up
at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74LVC16374AGRDR
SN74LVC16374AZRDR
SN74LVC16374ADL
TOP-SIDE MARKING
FBGA – GRD
Tape and reel
LD374A
FBGA – ZRD (Pb-free)
Tube
SSOP – DL
LVC16374A
LVC16374A
LD374A
Tape and reel
SN74LVC16374ADLR
SN74LVC16374ADGGR
74LVC16374ADGGRG4
SN74LVC16374ADGVR
74LVC16374ADGVRE4
SN74LVC16374AGQLR
SN74LVC16374AZQLR
–40°C to 85°C
TSSOP – DGG
TVSOP – DGV
Tape and reel
Tape and reel
Tape and reel
VFBGA – GQL
LD374A
VFBGA – ZQL (Pb-free)
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC16374A
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS728A–OCTOBER 2003–REVISED OCTOBER 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
GQL OR ZQL PACKAGE
TERMINAL ASSIGNMENTS(1)
(TOP VIEW)
(56-Ball GQL/ZQL Package)
1 2 3 4 5 6
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
1OE
1Q2
1Q4
1Q6
1Q8
2Q1
2Q3
2Q5
2Q7
2OE
NC
NC
NC
NC
1CLK
1D2
1D4
1D6
1D8
2D1
2D3
2D5
2D7
2CLK
1Q1
1Q3
1Q5
1Q7
2Q2
2Q4
2Q6
2Q8
NC
GND
VCC
GND
GND
VCC
GND
1D1
1D3
1D5
1D7
2D2
2D4
2D6
2D8
NC
G
H
J
GND
VCC
GND
NC
GND
VCC
GND
NC
K
xxx
blk
blk
K
(1) NC – No internal connection
GRD OR ZRD PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS(1)
(54-Ball GRD/ZRD Package)
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1Q1
1Q3
1Q5
1Q7
2Q1
2Q3
2Q5
2Q7
2Q8
NC
1OE
NC
1CLK
NC
NC
1D1
1D3
1D5
1D7
2D1
2D3
2D5
2D7
2D8
A
B
C
D
1Q2
1Q4
1Q6
1Q8
2Q2
2Q4
2Q6
NC
1D2
1D4
1D6
1D8
2D2
2D4
2D6
NC
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
E
F
G
H
J
G
H
J
NC
2OE
2CLK
xxx
blk
blk
(1) NC – No internal connection
2
SN74LVC16374A
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS728A–OCTOBER 2003–REVISED OCTOBER 2005
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
H
L
L
↑
H or L
X
L
X
X
Q0
Z
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1
24
2OE
1OE
25
48
2CLK
1CLK
C1
1D
C1
1D
2
13
2Q1
1Q1
47
36
2D1
1D1
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DGG, DGV, and DL packages.
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
6.5
V
VO
VO
IIK
6.5
V
VCC + 0.5
–50
V
Input clamp current
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through each VCC or GND
±50
±100
70
DGG package
DGV package
58
θJA
Package thermal impedance(4)
DL package
63
°C/W
GQL/ZQL package
GRD/ZRD package
42
36
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
3
SN74LVC16374A
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS728A–OCTOBER 2003–REVISED OCTOBER 2005
Recommended Operating Conditions(1)
MIN
MAX UNIT
Operating
1.65
3.6
V
VCC
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.5
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
5.5
VCC
5.5
–4
VI
Input voltage
0
0
0
V
V
High or low state
3-state
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
–8
IOH
High-level output current
Low-level output current
mA
mA
–12
–24
4
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
8
IOL
12
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
TA
–40
85
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
SN74LVC16374A
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS728A–OCTOBER 2003–REVISED OCTOBER 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
1.65 V
2.3 V
MIN TYP(1)
VCC – 0.2
MAX
UNIT
IOH = –100 µA
IOH = –4 mA
IOH = –8 mA
1.2
1.7
2.2
2.4
2.2
VOH
V
2.7 V
IOH = –12 mA
3 V
IOH = –24 mA
IOL = 100 µA
3 V
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.7
IOL = 4 mA
VOL
IOL = 8 mA
V
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
3 V
0.55
±5
II
VI = 0 to 5.5 V
VI or VO = 5.5 V
VO = 0 to 5.5 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V(2)
3.6 V
µA
µA
µA
Ioff
IOZ
0
±10
±10
20
3.6 V
ICC
IO = 0
3.6 V
µA
20
∆ICC
Ci
One input at VCC – 0.6 V,
VI = VCC or GND
Other inputs at VCC or GND
2.7 V to 3.6 V
3.3 V
500
µA
pF
pF
5
Co
VO = VCC or GND
3.3 V
6.5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This applies in the disabled state only.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
150
MIN
MAX
150
MIN
MAX
150
MIN
MAX
150
fclock
tw
Clock frequency
MHz
ns
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
3.3
2.4
0.8
3.3
1.6
1
3.3
1.9
1.1
3.3
1.9
1.9
tsu
th
ns
ns
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
150
1
MAX
MIN
150
1
MAX
MIN
150
1
MAX
MIN
150
1.5
MAX
fmax
tpd
MHz
ns
CLK
OE
Q
Q
Q
6.5
6.7
4.3
4.7
5
4.9
5.3
6.1
4.5
4.6
5.5
1
ten
1
1
1
1.5
ns
tdis
OE
1
10.7
1
1
1.5
ns
tsk(o)
ns
5
SN74LVC16374A
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS728A–OCTOBER 2003–REVISED OCTOBER 2005
Operating Characteristics
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
47
TYP
52
TYP
58
Outputs enabled
Outputs disabled
Power dissipation capacitance
per flip-flop
Cpd
f = 10 MHz
pF
21
23
24
6
SN74LVC16374A
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS728A–OCTOBER 2003–REVISED OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
Open
PLH PHL
C
L
t
t
/t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUT
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
V
V
2.7 V
2.7 V
V
V
1.5 V
1.5 V
/2
V
V
6 V
6 V
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
30 pF
30 pF
50 pF
50 pF
CC
CC
CC
/2
CC
CC
CC
3.3 V ± 0.3 V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
V
M
V
M
Input
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
I
I
Output
Control
V
M
V
M
V
M
V
M
Input
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
S1 at V
LOAD
(see Note B)
V
V
/2
LOAD
V
OH
V
V
V
V
V
M
M
M
Output
V
V
+ V
∆
OL
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
− V
∆
OH
M
V
M
M
Output
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
74LVC16374ADGGRG4
74LVC16374ADGVRE4
SN74LVC16374ADGGR
SN74LVC16374ADGVR
SN74LVC16374ADL
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
48
48
48
48
48
48
48
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TSSOP
TVSOP
SSOP
SSOP
SSOP
SSOP
DGV
DGG
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC16374ADLG4
SN74LVC16374ADLR
SN74LVC16374ADLRG4
SN74LVC16374AGQLR
DL
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
GQL
1000
TBD
SNPB
Level-1-240C-UNLIM
Level-1-240C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
SN74LVC16374AGRDR
SN74LVC16374AZQLR
SN74LVC16374AZRDR
ACTIVE
ACTIVE
ACTIVE
BGA MI
CROSTA
R JUNI
OR
GRD
ZQL
ZRD
54
56
54
1000
TBD
SNPB
BGA MI
CROSTA
R JUNI
OR
1000 Green (RoHS &
no Sb/Br)
SNAGCU
SNAGCU
BGA MI
CROSTA
R JUNI
OR
1000 Green (RoHS &
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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