74LVC16374APA [IDT]

Bus Driver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, TSSOP-48;


型号：	74LVC16374APA
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Bus Driver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, TSSOP-48 驱动光电二极管逻辑集成电路触发器
文件：	总6页 (文件大小：430K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVC16374A

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP

INDUSTRIALTEMPERATURERANGE

3.3V CMOS 16-BIT

EDGE-TRIGGERED D-TYPE

IDT74LVC16374A

FLIP-FLOP WITH 3-STATE OUTPUTS,

5 VOLT TOLERANT I/O

DESCRIPTION:

FEATURES:

The LVC16374A 16-bit edge-triggered D-type flip-flop is built using

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

advanced dual metal CMOS technology. This high-speed, low-power

storage. The OutputEnable (OE)andclock(CLK)controls are organized

to operate this device as two 8-bit registers or one 16-bit register with

commonclock. Flow-throughorganizationofsignalpins simplifies layout.

Allinputs are designedwithhysteresis forimprovednoise margin.

Allpins oftheLVC16374Acanbedrivenfromeither3.3Vor5Vdevices.

This feature allows the use of this device as a translator in a mixed 3.3V/

5Vsupplysystem.

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4μ W typ. static)

• All inputs, outputs, and I/O are 5V tolerant

• Supports hot insertion

• Available in SSOP, TSSOP, and TVSOP packages

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

The LVC16374A has been designed with a ±24mA output driver. This

driver is capable of driving a moderate to heavy load while maintaining

speedperformance.

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

FUNCTIONALBLOCKDIAGRAM

2OE

1OE

2CLK

1CLK

2D1

1D1

2Q1

1Q1

TO SEVEN OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

OCTOBER 2008

DSC-4752/5

IDT74LVC16374A

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Terminal Voltage with Respect to GND

Storage Temperature

Max

Unit

–0.5 to +6.5

–65 to +150

–50 to +50

–50

1CLK

1D1

1OE

1Q1

1Q2

° C

IOUT

DC Output Current

IIK

IOK

Continuous Clamp Current,

VI < 0 or VO < 0

1D2

ICC

ISS

Continuous Current through each

VCC or GND

±100

GND

1D3

1D4

V^CC

1D5

1D6

GND

1Q3

1Q4

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

V^CC

1Q5

1Q6

CAPACITANCE (TA = +25°C, F = 1.0MHz)

GND

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

1D7

1D8

2D1

1Q7

1Q8

2Q1

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

4.5

COUT

CI/O

6.5

NOTE:

1. As applicable to the device type.

2D2

2Q2

GND

PINDESCRIPTION

Pin Names

2D3

2D4

2Q3

2Q4

VCC

2Q5

2Q6

GND

2Q7

2Q8

2OE

Description

xDx

xCLK

xOE

Data Inputs

VCC

2D5

Clock Inputs

3-State Output Enable Inputs (Active LOW)

3-State Outputs

xQx

2D6

GND

2D7

(1)

FUNCTIONTABLE(EACHFLIP-FLOP)

Inputs

Outputs

xQx

2D8

2CLK

xDx

xCLK

xOE

↑

SSOP/ TSSOP/ TVSOP

TOP VIEW

↑

(2)

NOTES:

1. H = HIGH Voltage Level

X = Don’t Care

L = LOW Voltage Level

Z = High-Impedance

2. Output level before the indicated steady-state input conditions were established.

IDT74LVC16374A

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP

INDUSTRIALTEMPERATURERANGE

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

OperatingCondition:TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

Input Leakage Current

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

VCC = 3.6V

VI = 0 to 5.5V

—

µA

µ A

IOZH

IOZL

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

IOFF

VIK

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

—

µ A

VCC = 2.3V, IIN = –18mA

–0.7

–1.2

Input Hysteresis

VCC = 3.3V

VCC = 3.6V

—

100

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VIN = GND or VCC

(2)

3.6 ≤ VIN ≤ 5.5V

—

ΔICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

500

µ A

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

VCC– 0.2

Max.

—

Unit

VOH

OutputHIGHVoltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC = 2.3V

VCC = 2.7V

VCC = 3V

—

1.7

—

2.2

—

2.4

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

2.2

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

—

IOL = 12mA

IOL = 24mA

—

VCC = 2.7V

VCC = 3V

—

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

IDT74LVC16374A

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP

INDUSTRIALTEMPERATURERANGE

OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C

Symbol

Parameter

Test Conditions

Typical

Unit

CPD

PowerDissipationCapacitanceperFlip-FlopOutputsenabled

PowerDissipationCapacitanceperFlip-FlopOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.7V

Max.

VCC = 3.3V ± 0.3V

Symbol

fMAX

tPLH

tPHL

tPZH

tPZL

tPHZ

tPLZ

tSU

Parameter

Min.

150

—

Min.

150

1.5

Max.

—

Unit

—

MHz

PropagationDelay

4.9

4.5

xCLK to xQx

OutputEnableTime

—

5.3

6.1

1.5

4.6

5.5

xOE to xQx

OutputDisableTime

xOE to xQx

Set-up Time HIGH or LOW, xDx to xCLK

Hold Time HIGH or LOW, xDx after xCLK

xCLK Pulse Width HIGH or LOW

1.9

1.1

3.3

—

1.9

1.1

3.3

—

(2)

tSK(o)

OutputSkew

—

500

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVC16374A

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

Symbol VCC⁽¹⁾=3.3V±0.3V VCC⁽¹⁾=2.7V VCC⁽²⁾=2.5V±0.2V Unit

tPHL

VLOAD

VIH

2 x Vcc

Vcc

tPLH

VOH

VOL

OUTPUT

2.7

1.5

300

2.7

1.5

300

Vcc / 2

150

tPHL

tPLH

VLZ

VHZ

VIH

OPPOSITE PHASE

INPUT TRANSITION

150

LVC Link

VLOAD

Open

GND

Propagation Delay

VCC

DISABLE

ENABLE

VIH

500Ω

CONTROL

INPUT

VIN

VOUT

(1, 2)

Pulse

tPZL

tPLZ

D.U.T.

Generator

VLOAD/2

V^OL+VLZ

VOL

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

500Ω

tPHZ

tPZH

VOH

VOH-VHZ

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

LVC Link

Test Circuit for All Outputs

LVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

VIH

SWITCHPOSITION

DATA

INPUT

Test

Switch

V^LOAD

GND

Open

t^SU

VIH

TIMING

INPUT

Open Drain

Disable Low

Enable Low

tREM

VIH

ASYNCHRONOUS

CONTROL

Disable High

Enable High

VIH

SYNCHRONOUS

CONTROL

All Other Tests

tSU

LVC Link

VIH

Set-up, Hold, and Release Times

INPUT

tPLH1

t^PHL1

V^OH

LOW-HIGH-LOW

VOL

PULSE

OUTPUT 1

tSK (x)

VOH

VOL

HIGH-LOW-HIGH

PULSE

OUTPUT 2

LVC Link

tPLH2

tPHL2

Pulse Width

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVC16374A

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

Device Type Package

XXXX

LVC

Bus-Hold

Family

Temp. Range

Shrink Small Outline Package

SSOP - Green

Thin Shrink Small Outline Package

PVG

TSSOP - Green

Thin Very Small Outline Package - Green

PAG

PFG

16-Bit Edge-Triggered D-Type Flip-Flop

with 3-State Outputs, 5 Volt Tolerant I/O

374A

Double-Density, 24mA

Blank

No Bus-hold

-40°C to +85°C

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for SALES:

800-345-7015 or 408-284-8200

fax: 408-284-2775

for Tech Support:

logichelp@idt.com

www.idt.com

74LVC16374APA [IDT]

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