74FCT2373CTSOCTE4 [TI]
8-Bit Latches;
| 型号： | 74FCT2373CTSOCTE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-Bit Latches |
| 文件： | 总14页 (文件大小：847K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY74FCT2373T
8-BIT LATCH
WITH 3-STATE OUTPUTS
SCCS039B – SEPTEMBER 1994 – REVISED OCTOBER 2001
Q OR SO PACKAGE
(TOP VIEW)
Function and Pinout Compatible With the
Fastest Bipolar Logic
25-Ω Output Series Resistors Reduce
Transmission-Line Reflection Noise
OE
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
O
O
0
7
Reduced V
Equivalent FCT Functions
(Typically = 3.3 V) Version of
D
0
D
D
OH
7
6
D
1
O
1
O
O
D
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
6
5
O
2
D
2
5
4
D
D
3
I
Supports Partial-Power-Down Mode
off
O
3
GND
O
Operation
4
LE
Matched Rise and Fall Times
3-State Outputs
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Fully Compatible With TTL Input and
Output Logic Levels
12-mA Output Sink Current
15-mA Output Source Current
description
The CY74FCT2373T is an 8-bit, high-speed CMOS, TTL-compatible buffered latch with 3-state outputs that is
ideal for driving high-capacitance loads, such as memory and address buffers. On-chip 25-Ω termination
resistors at the outputs reduce system noise caused by reflections. The CY74FCT2373T can replace the
CY74FCT373T to reduce noise in an existing design.
When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the
required setup times are latched when LE transitions from high to low. Data appears on the bus when the
output-enable (OE) input is low. When OE is high, the bus output is in the high-impedance state. In this mode,
data can be entered into the latches.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QSOP – Q
SOIC – SO
Tape and reel
Tube
4.7
4.7
4.7
5.2
8
CY74FCT2373CTQCT
CY74FCT2373CTSOC
CY74FCT2373CTSOCT
CY74FCT2373ATQCT
CY74FCT2373TQCT
FCT2373C
FCT2373C
–40°C to 85°C
Tape and reel
Tape and reel
Tape and reel
QSOP – Q
QSOP – Q
FCT2373A
FCT2373
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY74FCT2373T
8-BIT LATCH
WITH 3-STATE OUTPUTS
SCCS039B – SEPTEMBER 1994 – REVISED OCTOBER 2001
FUNCTION TABLE
INPUTS
OUTPUT
O
OE
LE
H
H
L
D
H
L
L
L
H
L
L
X
X
Q
0
H
X
Z
H = High logic level, L = Low logic level,
X = Don’t care, Z = High-impedance
state, Q = Previous state of flip flops
0
(Q
)
0–1
logic diagram
1
OE
LE
11
CP
D
2
Q
O
0
3
D
0
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, θ (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W
JA
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Ambient temperature range with power applied, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.75
2
5
5.25
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
V
IH
0.8
–15
12
V
IL
I
I
mA
mA
°C
OH
OL
T
A
–40
85
NOTE 2: All unused inputs of the device must be held at V
or GND to ensure proper device operation.
CC
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY74FCT2373T
8-BIT LATCH
WITH 3-STATE OUTPUTS
SCCS039B – SEPTEMBER 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
2.4
20
TYP
MAX
UNIT
V
V
V
V
V
V
V
V
= 4.75 V,
= 4.75 V,
= 4.75 V,
= 4.75 V,
I
I
I
I
= –18 mA
–0.7
3.3
0.3
28
–1.2
IK
CC
CC
CC
CC
IN
= –15 mA
= 12 mA
= 12 mA
V
OH
OL
OH
OL
OL
0.55
40
V
R
Ω
OUT
hys
V
All inputs
0.2
V
I
I
I
I
I
I
I
I
V
V
V
V
V
V
V
V
V
V
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 0 V,
V
V
V
V
V
V
V
V
= V
CC
5
±1
µA
µA
µA
µA
µA
mA
µA
mA
mA
I
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
IN
IN
IN
= 2.7 V
= 0.5 V
IH
±1
IL
= 2.7 V
= 0.5 V
= 0 V
10
OZH
OZL
OUT
OUT
OUT
OUT
–10
–225
±1
‡
–60
–120
OS
= 4.5 V
off
= 5.25 V,
≤ 0.2 V,
V ≥ V
IN CC
– 0.2 V
0.1
0.5
0.2
2
CC
IN
§
∆I
= 5.25 V, V = 3.4 V , f = 0, Outputs open
IN
CC
1
= 5.25 V, One input switching at 50% duty cycle, Outputs open,
– 0.2 V
mA/
MHz
¶
I
0.06
0.12
CCD
OE = GND, V ≤ 0.2 V or V ≥ V
IN IN CC
V
V
≤ 0.2 V or
One input switching
IN
IN
0.7
1
1.4
2.4
≥ V
CC
– 0.2 V
at f = 10 MHz
1
V
= 5.25 V,
CC
at 50% duty cycle
Eight bits switching
V
IN
= 3.4 V or GND
Outputs open,
OE = GND,
LE = V
CC
#
I
C
mA
V
IN
V
IN
≤ 0.2 V or
||
||
1.3
2.6
≥ V
– 0.2 V
at f = 2.5 MHz
1
at 50% duty cycle
CC
V
IN
= 3.4 V or GND
3.3
6
10.6
C
C
10
12
pF
pF
i
8
o
†
‡
Typical values are at V
CC
= 5 V, T = 25°C.
A
Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus
and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise,
prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In
any sequence of parameter tests, I
tests should be performed last.
OS
§
¶
#
Per TTL-driven input (V = 3.4 V); all other inputs at V
or GND
IN CC
This parameter is derived for use in total power-supply calculations.
= I + ∆I × D × N + I (f /2 + f × N )
I
C
CC
CC CCD 0
H
T
1
1
Where:
I
I
∆I
D
N
= Total supply current
= Power-supply current with CMOS input levels
C
CC
CC
H
T
= Power-supply current for a TTL high input (V = 3.4 V)
IN
= Duty cycle for TTL inputs high
= Number of TTL inputs at D
H
I
f
f
= Dynamic current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
CCD
0
1
N
= Number of inputs changing at f
1
1
All currents are in milliamperes and all frequencies are in megahertz.
||
Values for these conditions are examples of the I
CC
formula.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY74FCT2373T
8-BIT LATCH
WITH 3-STATE OUTPUTS
SCCS039B – SEPTEMBER 1994 – REVISED OCTOBER 2001
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
CY74FCT2373T CY74FCT2373AT CY74FCT2373CT
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, D to LE
Hold time, D to LE
6
5
5
ns
ns
ns
High to low
High to low
2
2
2
1.5
1.5
1.5
switching characteristics over operating free-air temperature range (see Figure 1)
CY74FCT2373T CY74FCT2373AT CY74FCT2373CT
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
1.5
1.5
2
MAX
8
MIN
1.5
1.5
2
MAX
5.2
5.2
8.5
8.5
6.5
6.5
5.5
5.5
MIN
1.5
1.5
2
MAX
4.7
4.7
5.5
5.5
5.5
5.5
5
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
O
O
O
O
8
13
13
11
11
7
LE
ns
2
2
2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
OE
OE
ns
7
5
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY74FCT2373T
8-BIT LATCH
WITH 3-STATE OUTPUTS
SCCS039B – SEPTEMBER 1994 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
7 V
Open
GND
S1
500 Ω
From Output
Under Test
From Output
Under Test
Test
Point
TEST
S1
t
/t
Open
7 V
PLH PHL
t /t
C
= 50 pF
C
= 50 pF
L
L
500 Ω
500 Ω
PLZ PZL
/t
(see Note A)
(see Note A)
t
Open
PHZ PZH
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0 V
1.5 V
Timing Input
Data Input
t
w
t
h
t
3 V
su
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
t
t
t
PLH
PHL
PLH
PZL
PZH
PLZ
≈3.5 V
V
Output
Waveform 1
(see Note B)
OH
In-Phase
Output
1.5 V
1.5 V
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
OL
V
OL
t
t
PHL
PHZ
V
V
V
OH
OH
Output
Waveform 2
(see Note B)
Out-of-Phase
Output
– 0.3 V
OH
1.5 V
1.5 V
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
74FCT2373CTSOCTE4
74FCT2373CTSOCTG4
CY74FCT2373CTSOC
ACTIVE
SOIC
SOIC
SOIC
DW
20
20
20
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
-40 to 85
ACTIVE
ACTIVE
DW
DW
25
2500
2500
2500
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
FCT2373C
CY74FCT2573ATQCT
CY74FCT2573ATQCTG4
CY74FCT2573CTQCT
CY74FCT2573CTSOC
CY74FCT2573CTSOCE4
CY74FCT2573CTSOCG4
CY74FCT2573CTSOCT
CY74FCT2573TSOC
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DBQ
DBQ
DBQ
DW
20
20
20
20
20
20
20
20
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
FCT2573A
FCT2573A
FCT2573C
FCT2573C
FCT2573C
FCT2573C
FCT2573C
FCT2573
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
DW
25
Green (RoHS
& no Sb/Br)
DW
25
Green (RoHS
& no Sb/Br)
DW
2000
25
Green (RoHS
& no Sb/Br)
DW
Green (RoHS
& no Sb/Br)
CY74FCT2573TSOCT
DW
2000
Green (RoHS
& no Sb/Br)
FCT2573
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CY74FCT2573ATQCT
CY74FCT2573CTQCT
CY74FCT2573CTSOCT
CY74FCT2573TSOCT
SSOP
SSOP
SOIC
SOIC
DBQ
DBQ
DW
20
20
20
20
2500
2500
2000
2000
330.0
330.0
330.0
330.0
16.4
16.4
24.4
24.4
6.5
6.5
9.0
9.0
2.1
2.1
2.7
2.7
8.0
8.0
16.0
16.0
24.0
24.0
Q1
Q1
Q1
Q1
10.8
10.8
13.0
13.0
12.0
12.0
DW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CY74FCT2573ATQCT
CY74FCT2573CTQCT
CY74FCT2573CTSOCT
CY74FCT2573TSOCT
SSOP
SSOP
SOIC
SOIC
DBQ
DBQ
DW
20
20
20
20
2500
2500
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
38.0
45.0
45.0
DW
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
18X 1.27
20
1
13.0
12.6
NOTE 3
2X
11.43
10
11
0.51
0.31
20X
2.65 MAX
7.6
7.4
B
0.25
C A B
NOTE 4
0.33
0.10
TYP
0.25
SEE DETAIL A
GAGE PLANE
0 - 8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
10
11
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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相关型号：
74FCT2373CTSOCTG4
Octal D-Type Transparent Latches with 3-State Outputs and Series Damping Resistors 20-SOIC -40 to 85
TI
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