74CBTLV3383DBQRG4 [TI]
CBTLV/3B SERIES, 5-BIT EXCHANGER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, QSOP-24;
| 型号： | 74CBTLV3383DBQRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CBTLV/3B SERIES, 5-BIT EXCHANGER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, QSOP-24 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总16页 (文件大小：696K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢉ ꢊꢉ
ꢇ ꢋꢌꢍꢈꢋ ꢇꢆꢎꢏ ꢐ ꢑ ꢒ ꢍꢅꢓ ꢆ ꢔ ꢐꢆ ꢅꢕꢀ ꢍꢐꢖꢄ ꢗꢎꢁꢏ ꢐ ꢀ ꢌꢓ ꢆꢄ ꢗ
SCDS047G − MARCH 1998 − REVISED OCTOBER 2003
DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
5-Ω Switch Connection Between Two Ports
Rail-to-Rail Switching on Data I/O Ports
1
24
23
22
21
20
19
18
17
16
15
14
13
I
Supports Partial-Power-Down Mode
BE
1B1
1A1
1A2
1B2
2B1
2A1
2A2
2B2
3B1
3A1
GND
V
CC
off
2
Operation
5B2
5A2
5A1
5B1
4B2
4A2
4A1
4B1
3B2
3A2
BX
3
Latch-Up Performance Exceeds 250 mA Per
JESD 17
4
5
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
6
7
8
9
description/ordering information
10
11
12
The SN74CBTLV3383 provides ten bits of
high-speed bus switching or exchanging. The low
on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
The device operates as a 10-bit bus switch or as a 5-bit bus exchanger, which provides swapping of the A and
B pairs of signals. The bus-exchange function is selected when BX is high, and BE is low.
This device is fully specified for partial-power-down applications using I . The I feature ensures that
off
off
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QSOP − DBQ
SOIC − DW
Tape and reel
Tube
SN74CBTLV3383DBQR
SN74CBTLV3383DW
SN74CBTLV3383DWR
SN74CBTLV3383PWR
SN74CBTLV3383DGVR
CL383
CBTLV3383
−40°C to 85°C
Tape and reel
Tape and reel
Tape and reel
TSSOP − PW
TVSOP − DGV
CL383
CL383
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
INPUTS/OUTPUTS
BE
BX
L
1A1−5A1
1B1−5B1
1B2−5B2
Z
1A2−5A2
1B2−5B2
1B1−5B1
Z
L
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈꢉ ꢉ ꢊꢉ
ꢇ ꢋꢌꢍꢈ ꢋꢇꢆꢎ ꢏꢐ ꢑ ꢒ ꢍꢅꢓ ꢆ ꢔꢐ ꢆ ꢅꢕ ꢀꢍꢐ ꢖ ꢄꢗꢎ ꢁꢏ ꢐ ꢀꢌ ꢓ ꢆꢄ ꢗ
SCDS047G − MARCH 1998 − REVISED OCTOBER 2003
logic diagram (positive logic)
3
2
1A1
1B1
SW
SW
SW
4
5
1A2
1B2
5B1
SW
SW
21
20
5A1
SW
SW
22
23
5A2
5B2
SW
1
BE
13
BX
simplified schematic, each FET switch
A
B
(OE)
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢇ ꢋꢌꢍꢈꢋ ꢇꢆꢎꢏ ꢐ ꢑ ꢒ ꢍꢅꢓ ꢆ ꢔ ꢐꢆ ꢅꢕꢀ ꢍꢐꢖꢄ ꢗꢎꢁꢏ ꢐ ꢀ ꢌꢓ ꢆꢄ ꢗ
SCDS047G − MARCH 1998 − REVISED OCTOBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK I/O
Package thermal impedance, θ (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
2.3
1.7
2
MAX
UNIT
V
V
Supply voltage
3.6
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
High-level control input voltage
V
IH
0.7
0.8
85
V
IL
Low-level control input voltage
Operating free-air temperature
V
T
A
−40
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
I = −18 mA
MIN TYP
MAX
−1.2
1
UNIT
V
V
V
V
V
V
V
= 3 V,
IK
CC
CC
CC
CC
CC
I
I
I
I
= 3.6 V,
= 0,
V = V
I CC
or GND
µA
µA
µA
µA
pF
I
V or V = 0 to 3.6 V
10
off
I
O
= 3.6 V,
= 3.6 V,
I
O
= 0,
V = V
I CC
or GND
10
CC
§
∆I
CC
Control inputs
One input at 3 V,
Other inputs at V
CC
or GND
300
C
C
Control inputs V = 3 V or 0
3.5
13.5
5
i
I
V
O
= 3 V or 0,
BE = V
CC
pF
io(OFF)
I = 64 mA
8
8
I
V = 0
I
V
CC
= 2.3 V,
I = 24 mA
I
5
TYP at V
CC
= 2.5 V
V = 1.7 V,
I
I = 15 mA
I
27
5
40
7
¶
on
Ω
r
I = 64 mA
I
V = 0
I
V
CC
= 3 V
I = 24 mA
I
5
7
V = 2.4 V,
I
I = 15 mA
I
10
15
‡
§
¶
All typical values are at V
This is the increase in supply current for each input that is at the specified voltage level, rather than V
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
= 3.3 V (unless otherwise noted), T = 25°C.
A
CC
or GND.
CC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈꢉ ꢉ ꢊꢉ
ꢇ ꢋꢌꢍꢈ ꢋꢇꢆꢎ ꢏꢐ ꢑ ꢒ ꢍꢅꢓ ꢆ ꢔꢐ ꢆ ꢅꢕ ꢀꢍꢐ ꢖ ꢄꢗꢎ ꢁꢏ ꢐ ꢀꢌ ꢓ ꢆꢄ ꢗ
SCDS047G − MARCH 1998 − REVISED OCTOBER 2003
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 2.5 V
V
= 3.3 V
CC
0.2 V
CC
0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN MAX
†
t
t
t
t
A or B
BX
B or A
A or B
A or B
A or B
0.15
5.8
5.3
6
0.25
4.7
4.7
6
ns
ns
ns
ns
pd
pd
en
1.5
1.5
1
1.5
1.5
1
BE
BE
dis
†
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCDS047G − MARCH 1998 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
S1
S1
t
/t
Open
Open
R
PLH PHL
L
From Output
Under Test
t
/t
2 × V
CC
GND
PLZ PZL
GND
t
/t
PHZ PZH
C
L
R
L
(see Note A)
C
V
∆
R
V
CC
L
L
2.5 V 0.2 V
3.3 V 0.3 V
500 Ω
500 Ω
0.15 V
0.3 V
30 pF
50 pF
LOAD CIRCUIT
V
CC
Timing Input
V
CC
/2
0 V
t
w
t
t
h
su
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
V
CC
/2
V
CC
/2
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
V
CC
/2
V
CC
/2
V
CC
/2
V
/2
Input
CC
0 V
V
0 V
t
t
t
PHL
t
t
PLH
PZL
PLZ
+ V
Output
Waveform 1
V
V
OH
CC
V
V
/2
/2
V
CC
/2
V
CC
/2
/2
Output
CC
S1 at 2 × V
(see Note B)
CC
V
OL
∆
V
OL
OL
t
t
t
PHL
PLH
/2
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
OH
∆
V
CC
V
CC
CC
Output
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
are the same as t
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
74CBTLV3383DBQRE4
74CBTLV3383DBQRG4
74CBTLV3383DGVRE4
74CBTLV3383DGVRG4
74CBTLV3383DWRE4
74CBTLV3383DWRG4
74CBTLV3383PWRE4
74CBTLV3383PWRG4
SN74CBTLV3383DBQR
SN74CBTLV3383DGVR
SN74CBTLV3383DW
SN74CBTLV3383DWE4
SN74CBTLV3383DWG4
SN74CBTLV3383DWR
SN74CBTLV3383PW
SN74CBTLV3383PWE4
SN74CBTLV3383PWG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
TVSOP
TVSOP
SOIC
DBQ
DBQ
DGV
DGV
DW
DW
PW
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
2500
2500
2000
2000
2000
2000
2000
2000
2500
2000
25
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SOIC
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
SSOP
TVSOP
SOIC
Green (RoHS
& no Sb/Br)
PW
Green (RoHS
& no Sb/Br)
DBQ
DGV
DW
DW
DW
DW
PW
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SOIC
25
Green (RoHS
& no Sb/Br)
SOIC
25
Green (RoHS
& no Sb/Br)
SOIC
2000
60
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
PW
60
Green (RoHS
& no Sb/Br)
PW
60
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74CBTLV3383PWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74CBTLV3383DBQR
SSOP
DBQ
DGV
DW
24
24
24
24
2500
2000
2000
2000
330.0
330.0
330.0
330.0
16.4
12.4
24.4
16.4
6.5
6.9
9.0
5.6
2.1
1.6
2.7
1.6
8.0
8.0
16.0
12.0
24.0
16.0
Q1
Q1
Q1
Q1
SN74CBTLV3383DGVR TVSOP
SN74CBTLV3383DWR SOIC
SN74CBTLV3383PWR TSSOP
10.75 15.7
6.95 8.3
12.0
8.0
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74CBTLV3383DBQR
SN74CBTLV3383DGVR
SN74CBTLV3383DWR
SN74CBTLV3383PWR
SSOP
TVSOP
SOIC
DBQ
DGV
DW
24
24
24
24
2500
2000
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
35.0
45.0
38.0
TSSOP
PW
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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相关型号：
74CBTLV3384PW
CBTLV/3B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, 4.40 MM, PLASTIC, MO-153, SOT355-1, TSSOP-24
NXP
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