74ACTQ841SPCQR [TI]
ACT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDIP24, 0.300 INCH, SLIM, PLASTIC, DIP-24;
| 型号： | 74ACTQ841SPCQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ACT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDIP24, 0.300 INCH, SLIM, PLASTIC, DIP-24 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总10页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1993
54ACTQ/74ACTQ841 Quiet Series 10-Bit Transparent
Latch with TRI-STATE Outputs
É
General Description
Features
Y
Guaranteed simultaneous switching noise level and
dynamic threshold performance
The ’ACTQ841 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths or
buses carrying parity. The ’841 is a 10-bit transparent latch,
a 10-bit version of the ’373. The ’ACTQ841 utilizes NSC
Quiet Series technology to guarantee quiet output switching
and improved dynamic threshold performance, FACT Quiet
SeriesTM features GTOTM output control and undershoot
corrector in addition to a split ground bus for superior per-
formance.
Y
Y
Guaranteed pin-to-pin skew AC performance
Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
Improved latch-up immunity
Y
Y
Y
Y
Outputs source/sink 24 mA
’ACTQ841 has TTL-compatible inputs
Standard Military Drawing (SMD)
Ð ’ACTQ841: 5962-92200
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
TL/F/10688–1
TL/F/10688–2
TL/F/10688–3
Pin Names
D –D
Description
Data Inputs
Pin Assignment
for LCC
0
9
O –O
0
TRI-STATE Outputs
Output Enable
9
OE
LE
Latch Enable
TL/F/10688–4
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
FACT Quiet SeriesTM and GTOTM are trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/10688
RRD-B30M75/Printed in U. S. A.
Functional Description
The ’ACTQ841 consists of ten D-type latches with
TRI-STATE outputs. The flip-flops appear transparent to the
data when Latch Enable (LE) is HIGH. This allows asyn-
chronous operation, as the output transition follows the data
in transition.
Function Table
Inputs
LE
Internal
Q
Output
Function
OE
D
O
X
H
H
H
L
X
H
H
L
X
L
X
L
Z
Z
High Z
High Z
On the LE HIGH-to-LOW transition, the data that meets the
setup and hold time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH
the bus output is in the high impedance state.
H
X
L
H
Z
High Z
NC
L
Z
Latched
H
H
L
L
Transparent
Transparent
Latched
L
H
X
H
H
L
NC
NC
e
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
Z
High Impendance
e
NC
No Change
Logic Diagram
TL/F/10688–5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Rating (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (V
’ACTQ
)
CC
4.5V to 5.5V
b
a
0.5V to 7.0V
Supply Voltage (V
)
CC
Input Voltage (V )
I
0V to V
0V to V
CC
DC Input Diode Current (I
)
IK
Output Voltage (V
)
O
CC
e b
b
a
V
I
V
I
0.5V
a
20 mA
20 mA
Operating Temperature (T )
A
e
V
CC
0.5V
b
b
a
40 C to 85 C
74ACTQ
54ACTQ
§
55 C to 125 C
§
§
b
b
a
0.5V
DC Input Voltage (V )
I
0.5V to V
0.5V to V
CC
a
§
DC Output Diode Current (I
)
OK
Minimum Input Edge Rate DV/Dt
’ACTQ Devices
e b
b
a
V
V
0.5V
a
20 mA
20 mA
O
O
e
V
CC
0.5V
V
V
from 0.8V to 2.0V
@
IN
a
DC Output Voltage (V
DC Output Source
)
O
0.5V
50 mA
50 mA
CC
4.5V, 5.5V
125 mV/ns
CC
Note: All commercial packaging is not recommended for applications requir-
b
a
ing greater than 2000 temperature cycles from 40 C to 125 C.
§
§
g
g
or Sink Current (I
)
O
DC V
or Ground Current
CC
per Output Pin (I or I
CC
)
GND
)
b
a
65 C to 150 C
Storage Temperature (T
§
§
STG
DC Latch-Up Source
or Sink Current
g
300 mA
Junction Temperature (T )
J
CDIP
PDIP
175 C
§
140 C
§
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACTTM circuits outside databook specifications.
DC Electrical Characteristics for ’ACTQ Family Devices
74ACTQ
54ACTQ
74ACTQ
e
a
e
a
V
CC
(V)
T
A
55 C to 125 C
T
A
40 C to 85 C
e a
Symbol
Parameter
T
A
25 C
§
Units
Conditions
b
b
§
§
§
§
Typ
Guaranteed Limits
e
0.1V
V
V
V
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
IH
OUT
V
V
V
b
or V
CC
0.1V
e
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
OUT
0.1V
0.1V
IL
b
or V
CC
e b
OUT
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
I
50 mA
OH
e
*V
IN
V
IL
or V
IH
b
b
4.5
5.5
3.86
4.86
3.70
4.70
3.76
4.76
24 mA
24 mA
V
V
I
OH
e
e
V
OL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I
50 mA
OUT
*V
IN
V or V
IL IH
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
24 mA
24 mA
V
I
OL
e
I
I
Maximum Input
Leakage Current
V
V
, GND
CC
IN
I
g
g
g
g
g
5.5
5.5
0.1
0.5
1.0
1.0
5.0
mA
mA
e
Maximum TRI-STATE
Leakage Current
V
V
V , V
IL IH
OZ
I
g
10.0
e
V
, GND
CC
O
e
b
2.1V
I
I
I
Maximum I /Input
CC
5.5
5.5
5.5
0.6
1.6
50
1.5
75
mA
mA
mA
V
V
V
V
CC
CCT
OLD
OHD
I
e
²
Minimum Dynamic
Output Current
1.65V Max
e
3.85V Min
OLD
OHD
b
b
50
75
*All outputs loaded; thresholds on input associated with output under test.
²
Maximum test duration 2.0 ms, one output loaded at a time.
3
DC Electrical Characteristics for ’ACTQ Family Devices (Continued)
74ACTQ
54ACTQ
74ACTQ
e
e
T
A
V
CC
(V)
T
A
55 C to 125 C
e a
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
a
b a
40 C to 85 C
§
Guaranteed Limits
§
§
§
Typ
e
V
CC
I
Maximum Quiescent
Supply Current
V
IN
CC
5.5
5.0
5.0
5.0
5.0
8.0
1.5
160.0
80.0
mA
V
or GND (Note 1)
V
V
V
V
Quiet Output
Figures 2-12,13
(Notes 2, 3)
OLP
OLV
IHD
ILD
1.1
Maximum Dynamic V
OL
OL
Quiet Output
Minimum Dynamic V
Figures 2-12,13
(Notes 2, 3)
b
b
0.6
1.9
1.2
1.2
2.2
0.8
V
Minimum High Level
Dynamic Input Voltage
(Notes 2, 4)
V
Maximum Low Level
Dynamic Input Voltage
(Notes 2, 4)
V
²
Maximum test duration 2.0 ms, one output loaded at a time.
@ @
for 54ACTQ 25 C is identical to 74ACTQ 25 C.
§ §
Note 1: I
CC
Note 2: PDIP package.
@
Note 3: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output GND.
b
Note 4: Max number of data inputs (n) switching. (n
e
1) inputs switching 0V to 3V (’ACTQ). Input-under-test switching: 3V to threshold (V ), 0V to threshold
ILD
(V ), f
IHD
1 MHz.
AC Electrical Characteristics
74ACTQ
54ACTQ
e b
74ACTQ
e b
40 C
T
55 C
T
§
to 125 C
§
A
A
e a
A
V *
CC
(V)
T
25 C
§
50 pF
a
e
a
e
Symbol
Parameter
to 85 C
Units
§
50 pF
§
50 pF
e
C
L
C
C
L
L
Min
Typ
Max
Min
Max
Min
Max
t
t
,
,
Propagation Delay
to O
2.0
2.0
9.5
11.0
PLH
PHL
5.0
5.0
5.0
5.0
5.0
2.5
7.0
7.0
8.5
6.0
0.5
9.5
2.0
10.0
10.0
12.0
9.5
ns
ns
ns
ns
ns
D
n
n
t
t
Propagation Delay
LE to O
2.0
2.0
11.0
11.0
PLH
PHL
2.5
2.5
1.0
9.5
11.0
9.0
2.0
2.0
1.0
n
t
t
,
Output Enable Time
OE to O
1.5
1.5
11.0
13.0
PZH
PZL
n
t
t
,
Output Disable Time
OE to O
1.5
1.5
8.5
5.5
PHZ
PLZ
n
t
t
,
Output to Output
Skew** D to O
OSLH
OSHL
1.0
1.0
n
n
g
*Voltage Range 5.0 is 5.0V 0.5V.
**Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The
specification applies to any outputs switching in the same direction, either HIGH to LOW (t
tested.
) or LOW to HIGH (t
). Parameter guaranteed by design. Not
OSLH
OSHL
4
AC Operating Requirements
74ACTQ
54ACTQ
e b
74ACTQ
e b
40 C
T
55 C
T
A
§
to 125 C
§
A
e a
A
V *
CC
(V)
T
25 C
§
50 pF
a
e
a
Symbol
Parameter
to 85 C
Units
§
50 pF
§
e
C
L
e
50 pF
C
C
L
L
Typ
Guaranteed Minimum
t
t
t
Setup Time, HIGH or LOW
S
5.0
3.0
3.0
3.0
ns
D
n
to LE
Hold Time, HIGH or LOW
to LE
H
5.0
5.0
1.5
4.0
1.5
4.0
1.5
4.0
ns
ns
D
n
LE Pulse Width, HIGH
W
g
*Voltage Range 5.0 is 5.0V 0.5V.
Capacitance
Symbol
Parameter
Typ
Units
Conditions
e
OPEN
C
C
Input Capacitance
4.5
pF
pF
V
IN
CC
e
5.0V
Power Dissipation
Capacitance
V
PD
CC
85.0
5
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the noise
characteristics of FACT.
6. Set the word generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for AC
devices. Verify levels with a digital volt meter.
V /V
OLP OLV
and V
/V :
OHP OHV
Equipment:
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50X coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
#
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF, 500X.
Measure V
and V
OLV
on the quiet output during the
and V on the quiet out-
#
#
OLP
HL transition. Measure V
2. Deskew the word generator so that no two channels have
greater than 150 ps skew between them. This requires
that the oscilloscope be deskewed first. Swap out the
channels that have more than 150 ps of skew until all
channels being used are within 150 ps. It is important to
deskew the word generator channels before testing. This
will ensure that the outputs switch simultaneously.
OHP
put during the LH transition.
OHV
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
V
and V
:
IHD
ILD
3. Terminate all inputs and outputs to ensure proper loading
of the outputs and that the input levels are at the correct
voltage.
Monitor one of the switching outputs using a 50X coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
#
4. Set V
to 5.0V.
First increase the input LOW voltage level, V , until the
IL
output begins to oscillate. Oscillation is defined as noise
#
#
#
CC
5. Set the word generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and affect the results of the measurement.
on the output LOW level that exceeds V limits, or on
IL
output HIGH levels that exceed V limits. The input
IH
LOW voltage level at which oscillation occurs is defined
as V
.
ILD
Next increase the input HIGH voltage level on the word
generator, V until the output begins to oscillate. Oscilla-
IH
tion is defined as noise on the output LOW level that
exceeds V limits, or on output HIGH levels that exceed
IL
V
limits. The input HIGH voltage level at which oscilla-
.
IH
tion occurs is defined as V
IHD
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
TL/F/10688–6
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note A: V
and V
are measured with respect to ground reference.
OLP
OHV
e
Note B: Input pulses have the following characteristics:
k
150 ps.
f
1 MHz,
e
e
3 ns, skew
t
r
3 ns, t
f
TL/F/10688–7
FIGURE 2. Simultaneous Switching Test Circuit
6
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74ACTQ 841
P
C
QR
Temperature Range Family
Special Variations
e
e
e
e
74ACTQ
54ACTQ
Commercial TTL-Compatible
Military TTL-Compatible
X
QR
Device shipped in 13 reels
×
Commercial grade device with burn-
in
Device Type
e
QB
Military grade device with
environmental and burn-in
processing shipped in tubes
Package Code
e
SD Slim Ceramic DIP
SP Slim Plastic DIP
e
Temperature Range
e
e
e
F
L
S
Flatpak
Leadless Ceramic Chip Carrier (LCC)
Small Outline (SOIC)
e
e
b a
C
M
Commercial ( 40 C to 85 C)
§
§
b a
Military ( 55 C to 125 C)
§
§
Physical Dimensions inches (millimeters)
28-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E28A
7
Physical Dimensions inches (millimeters) (Continued)
24-Lead Slim (0.300 Wide) Ceramic Dual-In-Line Package (SD)
×
NS Package Number J24F
24-Lead Small Outline Integrated Circuit (S)
NS Package Number M24B
8
Physical Dimensions inches (millimeters) (Continued)
24-Lead Slim (0.300 Wide) Plastic Dual-In-Line Package (SP)
×
NS Package Number N24C
9
Ý
Lit. 115190
Physical Dimensions inches (millimeters) (Continued)
24-Lead Ceramic Flatpak (F)
NS Package Number W24C
LIFE SUPPORT POLICY
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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