74ACTQ843SC [FAIRCHILD]
Quiet Seriesa⑩ 9-Bit Transparent Latch with 3-STATE Outputs; 安静Seriesa⑩ 9位透明锁存器带3态输出
| 型号： | 74ACTQ843SC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quiet Seriesa⑩ 9-Bit Transparent Latch with 3-STATE Outputs |
| 文件： | 总8页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1990
Revised December 1998
74ACTQ843
Quiet Series 9-Bit Transparent Latch
with 3-STATE Outputs
General Description
Features
■ Guaranteed simultaneous switching noise level and
The ACTQ843 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths. The
ACTQ843 utilizes Fairchild FACT Quiet Series technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control and undershoot corrector in
addition to a split ground bus for superior performance.
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Inputs and outputs on opposite sides of package for
easy interface with microprocessors
■ Improved latch-up immunity
■ Outputs source/sink 24 mA
■ ACTQ843 has TTL-compatible inputs
■ Functionally and pin-compatible to AMD’s AM29843
■ 3-STATE outputs for bus interfacing
Ordering Code:
Order Number Package Number
Package Description
74ACTQ843SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
74ACTQ843SPC
N24C
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment for DIP and SOIC
Pin Descriptions
Pin Names
Description
Data Inputs
D0–D8
O0–O8
OE
Data Outputs
Output Enable
Latch Enable
Clear
LE
CLR
PRE
Preset
FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010689.prf
www.fairchildsemi.com
Functional Description
The ACTQ843 consists of nine D-type latches with 3-
STATE outputs. The flip-flops appear transparent to the
data when Latch Enable (LE) is HIGH. This allows asyn-
chronous operation, as the output transition follows the
data in transition. On the LE HIGH-to-LOW transition, the
data that meets the setup times is latched. Data appears
on the bus when the Output Enable (OE) is LOW. When
OE is HIGH, the bus output is in the high impedance state.
In addition to the LE and OE pins, the ACTQ843 has a
Clear (CLR) pin and a Preset (PRE) pin. These pins are
ideal for parity bus interfacing in high performance sys-
tems. When CLR is LOW, the outputs are LOW if OE is
LOW. When CLR is HIGH, data can be entered into the
latch. When PRE is LOW, the outputs are HIGH if OE is
LOW. Preset overrides CLR.
Function Table
Inputs
Internal Outputs
Function
CLR PRE OE
LE
H
H
L
D
L
Q
L
O
Z
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
L
High Z
H
X
L
H
Z
High Z
NC
L
Z
Latched
H
H
L
L
Transparent
Transparent
Latched
L
H
X
X
X
X
X
X
H
H
NC
H
L
L
NC
H
L
X
X
X
L
Preset
H
L
L
L
Clear
L
L
H
H
Z
Preset
L
H
L
H
H
L
Clear/High Z
Preset/High Z
H
L
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Logic Diagram
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2
Junction Temperature (TJ)
PDIP
Absolute Maximum Ratings(Note 1)
140°C
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Recommended Operating
Conditions
−20 mA
+20 mA
VI = VCC + 0.5V
Supply Voltage (VCC
Input Voltage (VI)
)
4.5V to 5.5V
0V to VCC
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
DC Output Diode Current (I OK
)
Output Voltage (VO)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate ∆V/∆t
VIN from 0.8V to 2.0V
−40°C to +85°C
125 mV/ns
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
VCC @ 4.5V, 5.5V
or Sink Current (IO)
±50 mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
±50 mA
Storage Temperature (TSTG
DC Latch-Up Source
or Sink Current
)
−65°C to +150°C
± 300 mA
DC Electrical Characteristics
V
T
= +25°C
T = −40°C to +85°C
A
CC
A
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
V
V
V
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
V
= 0.1V
IH
OUT
1.5
2.0
0.8
0.8
4.4
5.4
or V − 0.1V
CC
Maximum LOW Level
Input Voltage
1.5
V
V
V
= 0.1V
IL
OUT
1.5
or V − 0.1V
CC
Minimum HIGH Level
Output Voltage
4.49
5.49
I
= −50 µA
OUT
OH
V
= V or V
IN
IL
IH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
I
I
I
= 24 mA
OH
OH
OUT
= 24 mA (Note 2)
= 50 µA
V
Maximum LOW Level
Output Voltage
0.001
0.001
OL
0.1
0.1
V
= V or V
IN
OL
OL
IL
IH
4.5
5.5
5.5
0.36
0.36
± 0.1
0.44
0.44
± 1.0
V
I
I
= 24 mA
= 24 mA (Note 2)
I
I
Maximum Input
µA
µA
V = V , GND
I CC
IN
Leakage Current
Maximum 3-STATE
Leakage Current
5.5
± 0.5
± 5.0
V = V , V
OZ
I
IL
IH
V
= V , GND
CC
O
I
I
I
I
Maximum I /Input
CC
5.5
5.5
5.5
5.5
0.6
1.5
75
mA
mA
mA
µA
V = V − 2.1V
CCT
OLD
OHD
CC
I
CC
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
V
V
V
= 1.65V Max
OLD
OHD
−75
80.0
= 3.85V Min
8.0
1.5
= V
CC
IN
or GND
V
V
V
V
Quiet Output
5.0
5.0
5.0
5.0
1.1
−0.6
1.9
V
V
V
V
Figure 1, Figure 2
(Note 4)(Note 5)
Figure 1, Figure 2
(Note 4)(Note 5)
(Note 4)(Note 6)
OLP
OLV
IHD
ILD
Maximum Dynamic V
Quiet Output
OL
−1.2
2.0
Minimum Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
1.2
0.8
(Note 4)(Note 6)
3
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DC Electrical Characteristics (Continued)
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: DIP package.
Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 6: Max number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V. Input-under-test switching:
3V to threshold (V ), 0V to threshold (V ), f = 1 MHz.
ILD
IHD
AC Electrical Characteristics
V
T
= +25°C
= 50 pF
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
(Note 7)
5.0
Units
ns
L
Min
Typ
Max
Min
Max
t
Propagation Delay
to O
2.5
6.2
9.5
2.0
2.0
2.0
2.0
2.0
10.0
10.0
10.0
10.0
11.0
PLH
D
n
n
t
Propagation Delay
to O
5.0
5.0
5.0
5.0
2.5
2.5
2.5
2.5
6.7
7.1
6.9
7.3
9.5
9.0
ns
PHL
D
n
n
t
Propagation Delay
LE to O
ns
PLH
n
t
Propagation Delay
LE to O
9.0
ns
PHL
n
t
Propagation Delay
PRE to O
10.0
ns
PLH
n
t
Propagation Delay
CLR to O
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
2.5
2.5
2.5
1.5
1.5
2.5
2.5
7.2
7.2
7.5
5.0
5.1
6.7
7.3
0.5
11.0
9.5
2.0
2.0
2.0
1.0
1.0
2.0
2.0
12.0
10.5
10.5
8.5
ns
ns
ns
ns
ns
ns
ns
ns
PHL
n
t
Output Enable Time
OE to O
PZH
n
t
Output Enable Time
OE to O
9.5
PZL
n
t
Output Disable Time
OE to O
8.0
PHZ
n
t
Output Disable Time
OE to O
8.0
8.5
PLZ
n
t
Propagation Delay
PRE to O
10.0
11.0
1.5
11.0
12.0
1.5
PHL
n
t
Propagation Delay
CLR to O
PLH
n
t
Output to Output Skew (Note 8)
D to O
n
OSLH
t
OSHL
Note 7: Voltage Range 5.0 is 5.0V ±0.5V.
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.
n
The specification applies to any outputs switching in the same direction, either HIGH to LOW (t
design. Not tested.
) or LOW to HIGH (t
). Parameter guaranteed by
OSLH
OSHL
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4
AC Operating Requirements
V
T
= +25°C
= 50 pF
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
(Note 9)
5.0
Units
ns
L
Typ
Guaranteed Minimum
t
t
Setup Time, HIGH or LOW
3.0
1.5
3.0
S
H
D
to LE
n
Hold Time, HIGH or LOW
to LE
5.0
1.5
ns
D
n
t
t
t
t
t
LE Pulse Width, HIGH
PRE Pulse Width, LOW
CLR Pulse Width, LOW
PRE Recovery Time
CLR Recovery Time
5.0
5.0
5.0
5.0
5.0
4.0
4.0
4.0
2.0
2.0
4.0
4.0
4.0
2.0
2.0
ns
ns
ns
ns
ns
W
W
W
rec
rec
Note 9: Voltage Range 5.0 is 5.0V ±0.5V.
Capacitance
Symbol
Parameter
Typ
4.5
52
Units
pF
Conditions
C
Input Capacitance
V
V
= OPEN
= 5.0V
IN
CC
CC
C
Power Dissipation Capacitance
pF
PD
5
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FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
VOLP/VOLV and VOHP/V OHV:
•
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
•
•
Measure VOLP and VOLV on the quiet output during the
Tektronics Model 7854 Oscilloscope
Procedure:
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
1. Verify Test Fixture Loading: Standard Load 50 pF,
case active and enable transition.
500Ω.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
VILD and VIHD
:
•
Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
•
First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD
.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
•
•
Next decrease the input HIGH voltage level on the, VIH
,
until the output begins to oscillate or steps out a min of 2
ns. Oscillation is defined as noise on the output LOW
level that exceeds VIL limits, or on output HIGH levels
that exceed VIH limits. The input HIGH voltage level at
which oscillation occurs is defined as VIHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note 10: V
and V
are measured with respect to ground reference.
OLP
OHV
Note 11: Input pulses have the following characteristics: f = 1 MHz,
= 3 ns, t = 3 ns, skew < 150 ps.
t
r
f
FIGURE 2. Simultaneous Switching Test Circuit
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6
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M24B
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Package Number N24C
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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