74AC11651 [TI]
OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS; 八路总线收发器和具备三态输出寄存器
| 型号： | 74AC11651 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS |
| 文件： | 总9页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS135 – MARCH 1990 – REVISED APRIL 1993
DW OR NT PACKAGE
(TOP VIEW)
•
Independent Registers and Enables for A
and B Buses
•
•
•
Multiplexed Real-Time and Stored Data
Inverting Data Paths
OEAB
A1
CLKAB
SAB
B1
1
2
3
4
5
6
7
8
9
28
27
26
25
Flow-Through Architecture Optimizes PCB
Layout
A2
A3
A4
GND
GND
GND
GND
B2
24 B3
•
•
•
•
Center-Pin V
Minimize High-Speed Switching Noise
and GND Configurations
CC
B4
23
22
21
V
V
CC
CC
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
20 B5
500-mA Typical Latch-Up Immunity at
125°C
A5 10
A6 11
19 B6
18 B7
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
A7 12
17 B8
A8 13
16 CLKBA
15 SBA
OEBA 14
description
These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and
OEBA) inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are
provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and
a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that
can be performed with the 74AC11651.
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when
all the other data sources to the two sets of bus lines are at high impedance, each set will remain at its last state.
The 74AC11651 is characterized for operation from –40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS135 – MARCH 1990 – REVISED APRIL 1993
1
14
OEAB OEBA
L
28
16
27
15
SBA
L
1
14
28
16
27
15
SBA
X
CLKAB CLKBA SAB
CLKAB CLKBA SAB
OEAB OEBA
L
X
X
X
H
H
X
X
L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
1
14
28
16
27
15
SBA
X
1
14
28
CLKAB CLKBA SAB
H or L H or L
16
27
15
SBA
H
CLKAB CLKBA SAB
OEAB OEBA
OEAB OEBA
X
L
L
H
X
H
X
↑
X
X
X
H
L
H
↑
X
X
X
↑
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS135 – MARCH 1990 – REVISED APRIL 1993
FUNCTION TABLE
DATA I/O
A1 THRU A8
INPUTS
CLKAB
OPERATION OR FUNCTION
OEAB
OEBA
CLKBA
SAB
X
SBA
X
B1 THRU B8
Input
L
L
H
H
H
H
X
L
H or L
H or L
Input
Input
Isolation
↑
↑
X
X
Input
Store A and B data
†
X
H
L
↑
H or L
X
X
Input
Unspecified
Output
Input
Store A, hold B
‡
X
↑
↑
X
Input
Store A in both registers
Hold A, store B
†
H or L
↑
X
X
Unspecified
Output
Output
Output
Input
‡
L
↑
X
↑
X
X
X
X
L
X
Input
Store B in both registers
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
L
L
Input
L
L
X
H or L
X
H
X
X
Output
Output
Output
H
H
H
H
X
H or L
X
H
Input
Stored A data to B bus and
stored B data to A bus
H
L
H or L
H or L
H
H
Output
Output
†
‡
The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.
When select control is low, clocks can occur simultaneously so long as allowances are made for propagation delays from A to B (B to A) plus
setup and hold times. When select control is high, clocks must be staggered in order to load both registers.
§
logic symbol
14
1
EN1 [BA]
EN2 [AB]
C4
OEBA
OEAB
16
CLKBA
15
28
27
SBA
CLKAB
SAB
G5
C6
G7
26
4D
5
2
B1
≥1
A1
1
1
5
6D
7
7
≥1
2
1
3
25
24
23
20
19
18
17
A2
A3
A4
A5
A6
A7
A8
B2
B3
B4
B5
B6
B7
B8
4
5
10
11
12
13
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS135 – MARCH 1990 – REVISED APRIL 1993
logic diagram (positive logic)
14
OEBA
1
OEAB
16
CLKBA
15
SBA
28
CLKAB
27
SAB
1 of 8
Channels
1D
C1
26
2
A1
B1
1D
C1
To 7 Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
O
O
CC
CC
or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS135 – MARCH 1990 – REVISED APRIL 1993
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage
3
2.1
5
5.5
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
V
High-level input voltage
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
V
V
0.9
1.35
1.65
V
IL
Low-level input voltage
= 4.5 V
= 5.5 V
V
V
Input voltage
0
0
V
V
V
I
CC
Output voltage
V
CC
–4
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
I
High-level output current
Low-level output current
= 4.5 V
= 5.5 V
= 3 V
–24
–24
12
mA
mA
OH
OL
I
= 4.5 V
= 5.5 V
24
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
ns/V
T
A
–40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
CC
MIN
2.9
TYP
MAX
3 V
4.5 V
5.5 V
3 V
2.9
4.4
I
I
= – 50 µA
4.4
OH
5.4
5.4
V
OH
= – 4 mA
2.58
3.94
4.94
2.48
3.8
V
OH
4.5 V
5.5 V
5.5 V
3 V
I
I
= – 24 mA
OH
4.8
†
= –75 mA
3.85
OH
0.1
0.1
0.1
0.1
I
= 50 µA
4.5 V
5.5 V
3 V
OL
0.1
0.1
V
OL
I
I
I
= 12 mA
= 24 mA
0.36
0.36
0.36
0.44
0.44
0.44
1.65
±1
V
OL
OL
OL
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
†
= 75 mA
I
I
I
Control inputs V = V
or GND
±0.1
±0.5
8
µA
µA
µA
pF
pF
I
I
CC
‡
A or B ports
V
= V or GND
CC
±5
OZ
CC
O
V = V
or GND,
or GND
I = 0
O
80
I
CC
CC
C
C
Control inputs V = V
4.5
10
i
I
A or B ports
V
= V or GND
CC
5 V
io
O
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter I includes the input leakage current.
OZ
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS135 – MARCH 1990 – REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 2)
= 3.3 V ± 0.3 V
CC
T
= 25°C
A
MIN
MAX
UNIT
MIN
0
MAX
f
t
t
t
Clock frequency
45
0
10
6.5
0
45
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, A or B before CLKAB↑ or CLKBA↑
Hold time, A or B after CLKAB↑ or CLKBA↑
10
6.5
0
w
ns
su
h
ns
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 2)
= 5 V ± 0.5 V
CC
T
= 25°C
A
MIN
MAX
UNIT
MIN
0
MAX
f
t
t
t
Clock frequency
90
0
5.5
4.5
0.5
90
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, A or B before CLKAB↑ or CLKBA↑
Hold time, A or B after CLKAB↑ or CLKBA↑
5.5
4.5
0.5
w
ns
su
h
ns
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
V
CC
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
45
TYP
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
45
3.2
4.3
4.6
5.4
3.8
4.8
3.4
5
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
3.2
4.3
4.6
5.4
3.8
4.8
3.4
5
7.7
9.5
12.1
14.6
15
14
16.1
17.2
19.2
15.3
17.1
14.6
17.1
16.9
21.3
9.2
A or B
B or A
A or B
A or B
A or B
A
9.8
CLKBA or CLKAB
ns
ns
ns
ns
ns
ns
ns
11.5
8.6
17.5
13.3
15.5
12.7
15.5
14.9
18.9
8.8
†
SBA or SAB
(A or B high)
10.2
8.1
†
SBA or SAB
(A or B low)
10.3
9.8
4.6
5.3
4.4
3.8
4.9
5.5
4.4
3.5
4.6
5.3
4.4
3.8
4.9
5.5
4.4
3.5
OEBA
OEBA
OEAB
OEAB
12.1
6.6
A
5.8
7.8
8.1
10.2
12.2
6.7
15.5
18.8
8.9
17.6
21.2
9.3
B
B
5.7
7.8
8
†
These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS135 – MARCH 1990 – REVISED APRIL 1993
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
V
CC
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
90
TYP
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
90
2.6
3.5
3.8
4.7
3.2
3.9
2.9
4.1
3.9
4.2
4.1
3.5
4.2
4.5
4.2
3.3
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
2.6
3.5
3.8
4.7
3.2
3.9
2.9
4.1
3.9
4.2
4.1
3.5
4.2
4.5
4.2
3.3
5.3
6.5
6.8
8.1
6
8
9.4
9.1
10.5
11.4
12.8
10.1
11.2
9.5
A or B
B or A
A or B
A or B
A or B
A
10
CLKBA or CLKAB
ns
ns
ns
ns
ns
ns
ns
11.5
8.8
†
SBA or SAB
(A or B high)
7
10.1
8.5
†
5.7
7.2
6.9
7.6
5.9
5.2
5.9
8
SBA or SAB
(A or B low)
10.3
9.8
11.4
11.1
12.5
8
OEBA
OEBA
OEAB
OEAB
11
7.6
A
6.8
7.1
10.4
11.4
7.8
11.8
12.9
8.2
B
6
B
5.1
6.9
7.2
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
UNIT
Outputs enabled
Outputs disabled
64
14
C
Power dissipation capacitance per transceiver
C
pF
pd
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS135 – MARCH 1990 – REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2×V
CC
Open
GND
TEST
S1
Open
2 × V
CC
GND
S1
t
t
t
/t
500 Ω
PLH PHL
From Output
Under Test
/t
PLZ PZL
/t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
t
w
LOAD CIRCUIT FOR OUTPUTS
V
CC
Input
50%
50%
0 V
V
CC
Timing Input
50%
VOLTAGE WAVEFORMS
PULSE DURATION
0 V
t
t
h
su
V
CC
V
CC
Data Input
50%
50%
Output
0 V
Control
(low-level
enabling)
50%
50%
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
0 V
t
t
PZL
PZH
t
PLZ
≈V
V
CC
CC
Input
(see Note B)
Output
Waveform 1
50%
50%
50%V
t
CC
20%V
80%V
CC
CC
0 V
S1 at 2 × V
(see Note C)
CC
V
OL
OH
t
PLH
PHZ
t
PHL
Output
Waveform 2
S1 at GND
V
V
OH
Output
(see Note D)
50%V
50%V
50%V
CC
CC
V
CC
(see Note C)
OL
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
For testing pulse duration: t = t = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low.
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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