74AC11652DW [TI]
OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS; 八路总线收发器和寄存器具有三态输出
| 型号： | 74AC11652DW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS |
| 文件： | 总9页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
DW PACKAGE
(TOP VIEW)
Independent Registers and Enables for A
and B Buses
Multiplexed Real-Time and Stored Data
Inverting Data Paths
OEAB
A1
CLKAB
SAB
B1
1
28
27
26
25
2
Flow-Through Architecture Optimizes PCB
Layout
A2
A3
3
B2
4
A4
5
24 B3
Center-Pin V
Minimize High-Speed Switching Noise
and GND Configurations
CC
GND
GND
GND
GND
A5
A6
A7
A8
B4
6
23
22
21
7
V
V
CC
CC
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
8
9
20 B5
500-mA Typical Latch-Up Immunity at
125°C
10
11
12
13
14
19 B6
18 B7
17 B8
description
16 CLKBA
15 SBA
The 74AC11652 consists of bus transceiver
circuits, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data
directly from the data bus or from the internal
OEBA
storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions.
The select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred.
A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four
fundamental bus-management functions that can be performed with the 74AC11652.
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when
all other data sources to the two sets of bus lines are at high impedance, each set remains at its last state.
The 74AC11652 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
1
14
OEAB OEBA
L
28
16
27
15
SBA
L
1
14
28
16
27
15
SBA
X
CLKAB CLKBA SAB
CLKAB CLKBA SAB
OEAB OEBA
L
X
X
X
H
H
X
X
L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
1
14
28
16
27
15
SBA
X
1
14
28
16
27
15
SBA
H
CLKAB CLKBA SAB
CLKAB CLKBA SAB
OEAB OEBA
OEAB OEBA
X
L
L
H
X
H
X
↑
X
X
X
H
L
L
L
H
↑
X
X
X
↑
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
FUNCTION TABLE
DATA I/O
†
INPUTS
OPERATION OR FUNCTION
OEAB
OEBA
CLKBA
SAB
X
SBA
X
A1 THRU A8
Input
B1 THRU B8
Input
CLKAB
L
L
H
H
H
H
X
L
L
↑
L
↑
Isolation
X
X
Input
Input
Store A and B data
‡
X
H
L
↑
L
↑
X
X
Input
Unspecified
Output
Input
Store A, hold B
‡
X
↑
X
Input
Store A in both registers
Hold A, store B
‡
L
↑
↑
X
X
Unspecified
Output
Output
Output
Input
‡
X
L
↑
X
X
X
L
Input
Store B in both registers
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
L
X
X
X
L
X
L
X
X
L
Input
L
L
H
X
X
Input
H
H
H
H
Output
Output
H
Input
Stored A data to B bus and
stored B data to A bus
H
L
L
L
H
H
Output
Output
†
‡
The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are
always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs.
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
§
logic symbol
14
1
EN1 [BA]
EN2 [AB]
C4
OEBA
OEAB
16
CLKBA
15
28
27
SBA
CLKAB
SAB
G5
C6
G7
26
4D
5
2
B1
≥1
A1
1
1
5
6D
7
7
≥1
2
1
3
25
24
23
20
19
18
17
A2
A3
A4
A5
A6
A7
A8
B2
B3
B4
B5
B6
B7
B8
4
5
10
11
12
13
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
logic diagram (positive logic)
14
OEBA
1
OEAB
16
CLKBA
15
SBA
28
CLKAB
27
SAB
One of Eight
Channels
1D
C1
2
A1
26
B1
1D
C1
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 W
Storage temperature range, T
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage
3
2.1
5
5.5
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
V
High-level input voltage
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
V
V
0.9
1.35
1.65
V
IL
Low-level input voltage
= 4.5 V
= 5.5 V
V
V
Input voltage
0
0
V
V
V
I
CC
Output voltage
V
CC
–4
O
V
V
V
V
V
V
= 3 V
CC
CC
CC
CC
CC
CC
I
High-level output current
Low-level output current
= 4.5 V
= 5.5 V
= 3 V
–24
–24
12
24
24
5
mA
mA
OH
OL
I
= 4.5 V
= 5.5 V
Control pins
Data
0
0
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
10
85
T
A
–40
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
CC
MIN
2.9
TYP
MAX
3 V
4.5 V
5.5 V
3 V
2.9
4.4
I
I
= – 50 µA
4.4
OH
5.4
5.4
V
OH
= – 4 mA
2.58
3.94
4.94
2.48
3.8
V
OH
4.5 V
5.5 V
5.5 V
3 V
I
I
= – 24 mA
OH
4.8
†
= –75 mA
3.85
OH
0.1
0.1
0.1
0.1
I
= 50 µA
4.5 V
5.5 V
3 V
OL
0.1
0.1
V
OL
I
I
I
= 12 mA
= 24 mA
0.36
0.36
0.36
0.44
0.44
0.44
1.65
±1
V
OL
OL
OL
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
†
= 75 mA
I
I
I
Control inputs V = V
or GND
±0.1
±0.5
8
µA
µA
µA
pF
pF
I
I
CC
‡
A or B ports
V
= V or GND
CC
±5
OZ
CC
O
V = V
or GND,
or GND
I = 0
O
80
I
CC
CC
C
C
Control inputs V = V
4.5
12
i
I
A or B ports
V
= V or GND
CC
5 V
io
O
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter I includes the input leakage current.
OZ
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 2)
= 3.3 V ± 0.3 V
CC
T
= 25°C
A
MIN
MAX
UNIT
MIN
0
MAX
f
t
t
t
Clock frequency
65
0
7.7
6
65
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, A or B before CLKAB↑ or CLKBA↑
Hold time, A or B after CLKAB↑ or CLKBA↑
7.7
6
w
ns
su
h
1
1
ns
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 2)
= 5 V ± 0.5 V
CC
T
= 25°C
A
MIN
MAX
UNIT
MIN
0
MAX
f
t
t
t
Clock frequency
105
0
4.8
4.5
1
105
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, A or B before CLKAB↑ or CLKBA↑
Hold time, A or B after CLKAB↑ or CLKBA↑
4.8
4.5
1
w
ns
su
h
ns
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
V
CC
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
65
TYP
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
65
2.9
3.9
4.3
5.3
3.4
4.7
3.9
4.8
4.3
5.2
3.7
3.5
4.7
5.6
4
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
2.9
3.9
4.3
5.3
3.4
4.7
3.9
4.8
4.3
5.2
3.7
3.5
4.7
5.6
4
8.5
10.3
11.2
13.1
9.4
11.1
12.9
14.3
16.2
12
12.9
14.2
16.2
17.8
13.7
15.6
14.9
17.7
16.5
22
A or B
B or A
A or B
A or B
A or B
A
CLKBA or CLKAB
ns
ns
ns
ns
ns
ns
ns
†
SBA or SAB
(A or B high)
11.5
10.5
12.1
11.1
14.4
6.4
14.3
13.3
16.3
14.5
19.8
8.1
†
SBA or SAB
(A or B low)
OEBA
8.5
A
OEBA
OEAB
OEAB
6
7.8
8.2
11.6
14.8
6.6
15
16.9
21.9
8.6
B
19.9
8.2
B
3.5
6.1
7.7
3.5
8
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
V
CC
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
105
2.4
3.1
3.6
4.4
2.9
3.8
3.3
4
TYP
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
105
2.4
3.1
3.6
4.4
2.9
3.8
3.3
4
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
5.2
6
7.6
8.7
8.6
9.6
A or B
B or A
A or B
A or B
A or B
A
6.7
7.8
5.6
6.9
6.2
7.1
6.6
7.4
5.5
5
9.5
10.7
12
CLKBA or CLKAB
ns
ns
ns
ns
ns
ns
ns
10.8
8.1
9.1
SBA or SAB
(A or B high)
9.6
10.7
9.9
8.8
SBA or SAB
(A or B low)
9.9
10.9
10.9
12.2
7.6
3.3
4.2
3.6
3.3
4.1
4.6
3.9
3.4
9.6
3.3
4.2
3.6
3.3
4.1
4.6
3.9
3.4
OEBA
OEBA
OEAB
OEAB
10.9
7.2
A
6.7
7.1
7.2
7.9
5.6
5.2
10.1
11.1
7.3
11.3
12.3
7.6
B
B
6.8
7.2
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
UNIT
Outputs enabled
Outputs disabled
60
14
C
Power dissipation capacitance per transceiver
C
pF
pd
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
S1
t
/t
Open
PLH PHL
/t
500 Ω
From Output
Under Test
t
2 × V
CC
GND
PLZ PZL
/t
t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
V
CC
Timing Input
(see Note B)
50%
0 V
t
w
t
h
t
V
CC
su
V
CC
Input
50%
50%
50%
50%
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
V
V
CC
CC
Input
50%
50%
50%
50%
0 V
0 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
V
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
V
CC
20% V
S1 at 2 × V
(see Note B)
CC
CC
CC
V
V
OL
OL
t
PHZ
t
PLH
t
PHL
t
PZH
Output
Waveform 2
S1 at GND
V
OH
OH
0 V
Out-of-Phase
Output
80% V
50% V
50% V
CC
CC
CC
V
OL
(see Note B)
VOLTAGE WAVEFORMS
C includes probe and jig capacitance.
L
VOLTAGE WAVEFORMS
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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